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powerpc/align: Use #ifdef __BIG_ENDIAN__ #else for REG_BYTE
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / align.c
CommitLineData
1da177e4
LT		 1/* align.c - handle alignment exceptions for the Power PC.
2 *
3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
4 * Copyright (c) 1998-1999 TiVo, Inc.
5 * PowerPC 403GCX modifications.
6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
7 * PowerPC 403GCX/405GP modifications.
8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
9 * 64-bit and Power4 support
5daf9071
BH		 10 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
11 * <benh@kernel.crashing.org>
12 * Merge ppc32 and ppc64 implementations
1da177e4
LT		 13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <asm/processor.h>
23#include <asm/uaccess.h>
1da177e4
LT		 24#include <asm/cache.h>
25#include <asm/cputable.h>
80947e7c 26#include <asm/emulated_ops.h>
ae3a197e 27#include <asm/switch_to.h>
ddca156a 28#include <asm/disassemble.h>
1da177e4
LT		 29
30struct aligninfo {
31 unsigned char len;
32 unsigned char flags;
33};
34
1da177e4
LT		 35
36#define INVALID { 0, 0 }
37
fab5db97
PM		 38/* Bits in the flags field */
39#define LD 0 /* load */
40#define ST 1 /* store */
c6d4267e 41#define SE 2 /* sign-extend value, or FP ld/st as word */
fab5db97
PM		 42#define F 4 /* to/from fp regs */
43#define U 8 /* update index register */
44#define M 0x10 /* multiple load/store */
45#define SW 0x20 /* byte swap */
46#define S 0x40 /* single-precision fp or... */
47#define SX 0x40 /* ... byte count in XER */
5daf9071 48#define HARD 0x80 /* string, stwcx. */
26caeb2e
KG		 49#define E4 0x40 /* SPE endianness is word */
50#define E8 0x80 /* SPE endianness is double word */
cd6f37be 51#define SPLT 0x80 /* VSX SPLAT load */
1da177e4 52
fab5db97 53/* DSISR bits reported for a DCBZ instruction: */
1da177e4
LT		 54#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
55
56/*
57 * The PowerPC stores certain bits of the instruction that caused the
58 * alignment exception in the DSISR register. This array maps those
59 * bits to information about the operand length and what the
60 * instruction would do.
61 */
62static struct aligninfo aligninfo[128] = {
63 { 4, LD }, /* 00 0 0000: lwz / lwarx */
64 INVALID, /* 00 0 0001 */
65 { 4, ST }, /* 00 0 0010: stw */
66 INVALID, /* 00 0 0011 */
67 { 2, LD }, /* 00 0 0100: lhz */
68 { 2, LD+SE }, /* 00 0 0101: lha */
69 { 2, ST }, /* 00 0 0110: sth */
70 { 4, LD+M }, /* 00 0 0111: lmw */
5daf9071 71 { 4, LD+F+S }, /* 00 0 1000: lfs */
1da177e4 72 { 8, LD+F }, /* 00 0 1001: lfd */
5daf9071 73 { 4, ST+F+S }, /* 00 0 1010: stfs */
1da177e4 74 { 8, ST+F }, /* 00 0 1011: stfd */
f83319d7 75 { 16, LD }, /* 00 0 1100: lq */
5daf9071 76 { 8, LD }, /* 00 0 1101: ld/ldu/lwa */
1da177e4 77 INVALID, /* 00 0 1110 */
5daf9071 78 { 8, ST }, /* 00 0 1111: std/stdu */
1da177e4
LT		 79 { 4, LD+U }, /* 00 1 0000: lwzu */
80 INVALID, /* 00 1 0001 */
81 { 4, ST+U }, /* 00 1 0010: stwu */
82 INVALID, /* 00 1 0011 */
83 { 2, LD+U }, /* 00 1 0100: lhzu */
84 { 2, LD+SE+U }, /* 00 1 0101: lhau */
85 { 2, ST+U }, /* 00 1 0110: sthu */
86 { 4, ST+M }, /* 00 1 0111: stmw */
5daf9071 87 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
1da177e4 88 { 8, LD+F+U }, /* 00 1 1001: lfdu */
5daf9071 89 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
1da177e4 90 { 8, ST+F+U }, /* 00 1 1011: stfdu */
c6d4267e 91 { 16, LD+F }, /* 00 1 1100: lfdp */
1da177e4 92 INVALID, /* 00 1 1101 */
c6d4267e 93 { 16, ST+F }, /* 00 1 1110: stfdp */
1da177e4
LT		 94 INVALID, /* 00 1 1111 */
95 { 8, LD }, /* 01 0 0000: ldx */
96 INVALID, /* 01 0 0001 */
97 { 8, ST }, /* 01 0 0010: stdx */
98 INVALID, /* 01 0 0011 */
99 INVALID, /* 01 0 0100 */
100 { 4, LD+SE }, /* 01 0 0101: lwax */
101 INVALID, /* 01 0 0110 */
102 INVALID, /* 01 0 0111 */
5daf9071
BH		 103 { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
104 { 4, LD+M+HARD }, /* 01 0 1001: lswi */
105 { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
106 { 4, ST+M+HARD }, /* 01 0 1011: stswi */
1da177e4
LT		 107 INVALID, /* 01 0 1100 */
108 { 8, LD+U }, /* 01 0 1101: ldu */
109 INVALID, /* 01 0 1110 */
110 { 8, ST+U }, /* 01 0 1111: stdu */
111 { 8, LD+U }, /* 01 1 0000: ldux */
112 INVALID, /* 01 1 0001 */
113 { 8, ST+U }, /* 01 1 0010: stdux */
114 INVALID, /* 01 1 0011 */
115 INVALID, /* 01 1 0100 */
116 { 4, LD+SE+U }, /* 01 1 0101: lwaux */
117 INVALID, /* 01 1 0110 */
118 INVALID, /* 01 1 0111 */
119 INVALID, /* 01 1 1000 */
120 INVALID, /* 01 1 1001 */
121 INVALID, /* 01 1 1010 */
122 INVALID, /* 01 1 1011 */
123 INVALID, /* 01 1 1100 */
124 INVALID, /* 01 1 1101 */
125 INVALID, /* 01 1 1110 */
126 INVALID, /* 01 1 1111 */
127 INVALID, /* 10 0 0000 */
128 INVALID, /* 10 0 0001 */
5daf9071 129 INVALID, /* 10 0 0010: stwcx. */
1da177e4
LT		 130 INVALID, /* 10 0 0011 */
131 INVALID, /* 10 0 0100 */
132 INVALID, /* 10 0 0101 */
133 INVALID, /* 10 0 0110 */
134 INVALID, /* 10 0 0111 */
135 { 4, LD+SW }, /* 10 0 1000: lwbrx */
136 INVALID, /* 10 0 1001 */
137 { 4, ST+SW }, /* 10 0 1010: stwbrx */
138 INVALID, /* 10 0 1011 */
139 { 2, LD+SW }, /* 10 0 1100: lhbrx */
140 { 4, LD+SE }, /* 10 0 1101 lwa */
141 { 2, ST+SW }, /* 10 0 1110: sthbrx */
f83319d7 142 { 16, ST }, /* 10 0 1111: stq */
1da177e4
LT		 143 INVALID, /* 10 1 0000 */
144 INVALID, /* 10 1 0001 */
145 INVALID, /* 10 1 0010 */
146 INVALID, /* 10 1 0011 */
147 INVALID, /* 10 1 0100 */
148 INVALID, /* 10 1 0101 */
149 INVALID, /* 10 1 0110 */
150 INVALID, /* 10 1 0111 */
151 INVALID, /* 10 1 1000 */
152 INVALID, /* 10 1 1001 */
153 INVALID, /* 10 1 1010 */
154 INVALID, /* 10 1 1011 */
155 INVALID, /* 10 1 1100 */
156 INVALID, /* 10 1 1101 */
157 INVALID, /* 10 1 1110 */
5daf9071 158 { 0, ST+HARD }, /* 10 1 1111: dcbz */
1da177e4
LT		 159 { 4, LD }, /* 11 0 0000: lwzx */
160 INVALID, /* 11 0 0001 */
161 { 4, ST }, /* 11 0 0010: stwx */
162 INVALID, /* 11 0 0011 */
163 { 2, LD }, /* 11 0 0100: lhzx */
164 { 2, LD+SE }, /* 11 0 0101: lhax */
165 { 2, ST }, /* 11 0 0110: sthx */
166 INVALID, /* 11 0 0111 */
5daf9071 167 { 4, LD+F+S }, /* 11 0 1000: lfsx */
1da177e4 168 { 8, LD+F }, /* 11 0 1001: lfdx */
5daf9071 169 { 4, ST+F+S }, /* 11 0 1010: stfsx */
1da177e4 170 { 8, ST+F }, /* 11 0 1011: stfdx */
c6d4267e
PM		 171 { 16, LD+F }, /* 11 0 1100: lfdpx */
172 { 4, LD+F+SE }, /* 11 0 1101: lfiwax */
173 { 16, ST+F }, /* 11 0 1110: stfdpx */
174 { 4, ST+F }, /* 11 0 1111: stfiwx */
1da177e4
LT		 175 { 4, LD+U }, /* 11 1 0000: lwzux */
176 INVALID, /* 11 1 0001 */
177 { 4, ST+U }, /* 11 1 0010: stwux */
178 INVALID, /* 11 1 0011 */
179 { 2, LD+U }, /* 11 1 0100: lhzux */
180 { 2, LD+SE+U }, /* 11 1 0101: lhaux */
181 { 2, ST+U }, /* 11 1 0110: sthux */
182 INVALID, /* 11 1 0111 */
5daf9071 183 { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
1da177e4 184 { 8, LD+F+U }, /* 11 1 1001: lfdux */
5daf9071 185 { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
1da177e4
LT		 186 { 8, ST+F+U }, /* 11 1 1011: stfdux */
187 INVALID, /* 11 1 1100 */
545bba18 188 { 4, LD+F }, /* 11 1 1101: lfiwzx */
1da177e4
LT		 189 INVALID, /* 11 1 1110 */
190 INVALID, /* 11 1 1111 */
191};
192
5daf9071
BH		 193/*
194 * The dcbz (data cache block zero) instruction
195 * gives an alignment fault if used on non-cacheable
196 * memory. We handle the fault mainly for the
197 * case when we are running with the cache disabled
198 * for debugging.
199 */
200static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
201{
202 long __user *p;
203 int i, size;
204
205#ifdef __powerpc64__
206 size = ppc64_caches.dline_size;
207#else
208 size = L1_CACHE_BYTES;
209#endif
210 p = (long __user *) (regs->dar & -size);
211 if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
212 return -EFAULT;
213 for (i = 0; i < size / sizeof(long); ++i)
e4ee3891 214 if (__put_user_inatomic(0, p+i))
5daf9071
BH		 215 return -EFAULT;
216 return 1;
217}
218
219/*
220 * Emulate load & store multiple instructions
221 * On 64-bit machines, these instructions only affect/use the
222 * bottom 4 bytes of each register, and the loads clear the
223 * top 4 bytes of the affected register.
224 */
075f6311 225#ifdef __BIG_ENDIAN__
5daf9071
BH		 226#ifdef CONFIG_PPC64
227#define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
228#else
229#define REG_BYTE(rp, i) *((u8 *)(rp) + (i))
230#endif
a9650e9b 231#else
075f6311
TM		 232#define REG_BYTE(rp, i) (*(((u8 *)((rp) + ((i)>>2)) + ((i)&3))))
233#endif
5daf9071 234
fab5db97
PM		 235#define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz))
236
5daf9071
BH		 237static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
238 unsigned int reg, unsigned int nb,
fab5db97
PM		 239 unsigned int flags, unsigned int instr,
240 unsigned long swiz)
5daf9071
BH		 241{
242 unsigned long *rptr;
fab5db97
PM		 243 unsigned int nb0, i, bswiz;
244 unsigned long p;
5daf9071
BH		 245
246 /*
247 * We do not try to emulate 8 bytes multiple as they aren't really
248 * available in our operating environments and we don't try to
249 * emulate multiples operations in kernel land as they should never
250 * be used/generated there at least not on unaligned boundaries
251 */
252 if (unlikely((nb > 4) || !user_mode(regs)))
253 return 0;
254
255 /* lmw, stmw, lswi/x, stswi/x */
256 nb0 = 0;
257 if (flags & HARD) {
258 if (flags & SX) {
259 nb = regs->xer & 127;
260 if (nb == 0)
261 return 1;
262 } else {
fab5db97
PM		 263 unsigned long pc = regs->nip ^ (swiz & 4);
264
e4ee3891
BH		 265 if (__get_user_inatomic(instr,
266 (unsigned int __user *)pc))
5daf9071 267 return -EFAULT;
fab5db97
PM		 268 if (swiz == 0 && (flags & SW))
269 instr = cpu_to_le32(instr);
5daf9071
BH		 270 nb = (instr >> 11) & 0x1f;
271 if (nb == 0)
272 nb = 32;
1da177e4 273 }
5daf9071
BH		 274 if (nb + reg * 4 > 128) {
275 nb0 = nb + reg * 4 - 128;
276 nb = 128 - reg * 4;
277 }
075f6311
TM		 278#ifdef __LITTLE_ENDIAN__
279 /*
280 * String instructions are endian neutral but the code
281 * below is not. Force byte swapping on so that the
282 * effects of swizzling are undone in the load/store
283 * loops below.
284 */
285 flags ^= SW;
286#endif
5daf9071
BH		 287 } else {
288 /* lwm, stmw */
289 nb = (32 - reg) * 4;
1da177e4 290 }
5daf9071
BH		 291
292 if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
293 return -EFAULT; /* bad address */
294
295 rptr = &regs->gpr[reg];
fab5db97
PM		 296 p = (unsigned long) addr;
297 bswiz = (flags & SW)? 3: 0;
298
299 if (!(flags & ST)) {
5daf9071
BH		 300 /*
301 * This zeroes the top 4 bytes of the affected registers
302 * in 64-bit mode, and also zeroes out any remaining
303 * bytes of the last register for lsw*.
304 */
305 memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
306 if (nb0 > 0)
307 memset(&regs->gpr[0], 0,
308 ((nb0 + 3) / 4) * sizeof(unsigned long));
309
fab5db97 310 for (i = 0; i < nb; ++i, ++p)
e4ee3891
BH		 311 if (__get_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
312 SWIZ_PTR(p)))
5daf9071
BH		 313 return -EFAULT;
314 if (nb0 > 0) {
315 rptr = &regs->gpr[0];
316 addr += nb;
fab5db97 317 for (i = 0; i < nb0; ++i, ++p)
e4ee3891
BH		 318 if (__get_user_inatomic(REG_BYTE(rptr,
319 i ^ bswiz),
320 SWIZ_PTR(p)))
5daf9071
BH		 321 return -EFAULT;
322 }
323
324 } else {
fab5db97 325 for (i = 0; i < nb; ++i, ++p)
e4ee3891
BH		 326 if (__put_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
327 SWIZ_PTR(p)))
5daf9071
BH		 328 return -EFAULT;
329 if (nb0 > 0) {
330 rptr = &regs->gpr[0];
331 addr += nb;
fab5db97 332 for (i = 0; i < nb0; ++i, ++p)
e4ee3891
BH		 333 if (__put_user_inatomic(REG_BYTE(rptr,
334 i ^ bswiz),
335 SWIZ_PTR(p)))
5daf9071
BH		 336 return -EFAULT;
337 }
338 }
339 return 1;
1da177e4
LT		 340}
341
c6d4267e
PM		 342/*
343 * Emulate floating-point pair loads and stores.
344 * Only POWER6 has these instructions, and it does true little-endian,
345 * so we don't need the address swizzling.
346 */
b887ec62
MN		 347static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
348 unsigned int flags)
c6d4267e 349{
553631e2
MN		 350 char *ptr0 = (char *) &current->thread.TS_FPR(reg);
351 char *ptr1 = (char *) &current->thread.TS_FPR(reg+1);
352 int i, ret, sw = 0;
c6d4267e 353
c6d4267e
PM		 354 if (reg & 1)
355 return 0; /* invalid form: FRS/FRT must be even */
553631e2
MN		 356 if (flags & SW)
357 sw = 7;
358 ret = 0;
359 for (i = 0; i < 8; ++i) {
360 if (!(flags & ST)) {
361 ret |= __get_user(ptr0[i^sw], addr + i);
362 ret |= __get_user(ptr1[i^sw], addr + i + 8);
363 } else {
364 ret |= __put_user(ptr0[i^sw], addr + i);
365 ret |= __put_user(ptr1[i^sw], addr + i + 8);
c6d4267e
PM		 366 }
367 }
368 if (ret)
369 return -EFAULT;
370 return 1; /* exception handled and fixed up */
371}
372
f83319d7
AB		 373#ifdef CONFIG_PPC64
374static int emulate_lq_stq(struct pt_regs *regs, unsigned char __user *addr,
375 unsigned int reg, unsigned int flags)
376{
377 char *ptr0 = (char *)&regs->gpr[reg];
378 char *ptr1 = (char *)&regs->gpr[reg+1];
379 int i, ret, sw = 0;
380
381 if (reg & 1)
382 return 0; /* invalid form: GPR must be even */
383 if (flags & SW)
384 sw = 7;
385 ret = 0;
386 for (i = 0; i < 8; ++i) {
387 if (!(flags & ST)) {
388 ret |= __get_user(ptr0[i^sw], addr + i);
389 ret |= __get_user(ptr1[i^sw], addr + i + 8);
390 } else {
391 ret |= __put_user(ptr0[i^sw], addr + i);
392 ret |= __put_user(ptr1[i^sw], addr + i + 8);
393 }
394 }
395 if (ret)
396 return -EFAULT;
397 return 1; /* exception handled and fixed up */
398}
399#endif /* CONFIG_PPC64 */
400
26caeb2e
KG		 401#ifdef CONFIG_SPE
402
403static struct aligninfo spe_aligninfo[32] = {
404 { 8, LD+E8 }, /* 0 00 00: evldd[x] */
405 { 8, LD+E4 }, /* 0 00 01: evldw[x] */
406 { 8, LD }, /* 0 00 10: evldh[x] */
407 INVALID, /* 0 00 11 */
408 { 2, LD }, /* 0 01 00: evlhhesplat[x] */
409 INVALID, /* 0 01 01 */
410 { 2, LD }, /* 0 01 10: evlhhousplat[x] */
411 { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */
412 { 4, LD }, /* 0 10 00: evlwhe[x] */
413 INVALID, /* 0 10 01 */
414 { 4, LD }, /* 0 10 10: evlwhou[x] */
415 { 4, LD+SE }, /* 0 10 11: evlwhos[x] */
416 { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */
417 INVALID, /* 0 11 01 */
418 { 4, LD }, /* 0 11 10: evlwhsplat[x] */
419 INVALID, /* 0 11 11 */
420
421 { 8, ST+E8 }, /* 1 00 00: evstdd[x] */
422 { 8, ST+E4 }, /* 1 00 01: evstdw[x] */
423 { 8, ST }, /* 1 00 10: evstdh[x] */
424 INVALID, /* 1 00 11 */
425 INVALID, /* 1 01 00 */
426 INVALID, /* 1 01 01 */
427 INVALID, /* 1 01 10 */
428 INVALID, /* 1 01 11 */
429 { 4, ST }, /* 1 10 00: evstwhe[x] */
430 INVALID, /* 1 10 01 */
431 { 4, ST }, /* 1 10 10: evstwho[x] */
432 INVALID, /* 1 10 11 */
433 { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */
434 INVALID, /* 1 11 01 */
435 { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */
436 INVALID, /* 1 11 11 */
437};
438
439#define EVLDD 0x00
440#define EVLDW 0x01
441#define EVLDH 0x02
442#define EVLHHESPLAT 0x04
443#define EVLHHOUSPLAT 0x06
444#define EVLHHOSSPLAT 0x07
445#define EVLWHE 0x08
446#define EVLWHOU 0x0A
447#define EVLWHOS 0x0B
448#define EVLWWSPLAT 0x0C
449#define EVLWHSPLAT 0x0E
450#define EVSTDD 0x10
451#define EVSTDW 0x11
452#define EVSTDH 0x12
453#define EVSTWHE 0x18
454#define EVSTWHO 0x1A
455#define EVSTWWE 0x1C
456#define EVSTWWO 0x1E
457
458/*
459 * Emulate SPE loads and stores.
460 * Only Book-E has these instructions, and it does true little-endian,
461 * so we don't need the address swizzling.
462 */
463static int emulate_spe(struct pt_regs *regs, unsigned int reg,
464 unsigned int instr)
465{
f626190d 466 int ret;
26caeb2e
KG		 467 union {
468 u64 ll;
469 u32 w[2];
470 u16 h[4];
471 u8 v[8];
472 } data, temp;
473 unsigned char __user *p, *addr;
474 unsigned long *evr = &current->thread.evr[reg];
475 unsigned int nb, flags;
476
477 instr = (instr >> 1) & 0x1f;
478
479 /* DAR has the operand effective address */
480 addr = (unsigned char __user *)regs->dar;
481
482 nb = spe_aligninfo[instr].len;
483 flags = spe_aligninfo[instr].flags;
484
485 /* Verify the address of the operand */
486 if (unlikely(user_mode(regs) &&
487 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
488 addr, nb)))
489 return -EFAULT;
490
491 /* userland only */
492 if (unlikely(!user_mode(regs)))
493 return 0;
494
495 flush_spe_to_thread(current);
496
497 /* If we are loading, get the data from user space, else
498 * get it from register values
499 */
500 if (flags & ST) {
501 data.ll = 0;
502 switch (instr) {
503 case EVSTDD:
504 case EVSTDW:
505 case EVSTDH:
506 data.w[0] = *evr;
507 data.w[1] = regs->gpr[reg];
508 break;
509 case EVSTWHE:
510 data.h[2] = *evr >> 16;
511 data.h[3] = regs->gpr[reg] >> 16;
512 break;
513 case EVSTWHO:
514 data.h[2] = *evr & 0xffff;
515 data.h[3] = regs->gpr[reg] & 0xffff;
516 break;
517 case EVSTWWE:
518 data.w[1] = *evr;
519 break;
520 case EVSTWWO:
521 data.w[1] = regs->gpr[reg];
522 break;
523 default:
524 return -EINVAL;
525 }
526 } else {
527 temp.ll = data.ll = 0;
528 ret = 0;
529 p = addr;
530
531 switch (nb) {
532 case 8:
533 ret |= __get_user_inatomic(temp.v[0], p++);
534 ret |= __get_user_inatomic(temp.v[1], p++);
535 ret |= __get_user_inatomic(temp.v[2], p++);
536 ret |= __get_user_inatomic(temp.v[3], p++);
537 case 4:
538 ret |= __get_user_inatomic(temp.v[4], p++);
539 ret |= __get_user_inatomic(temp.v[5], p++);
540 case 2:
541 ret |= __get_user_inatomic(temp.v[6], p++);
542 ret |= __get_user_inatomic(temp.v[7], p++);
543 if (unlikely(ret))
544 return -EFAULT;
545 }
546
547 switch (instr) {
548 case EVLDD:
549 case EVLDW:
550 case EVLDH:
551 data.ll = temp.ll;
552 break;
553 case EVLHHESPLAT:
554 data.h[0] = temp.h[3];
555 data.h[2] = temp.h[3];
556 break;
557 case EVLHHOUSPLAT:
558 case EVLHHOSSPLAT:
559 data.h[1] = temp.h[3];
560 data.h[3] = temp.h[3];
561 break;
562 case EVLWHE:
563 data.h[0] = temp.h[2];
564 data.h[2] = temp.h[3];
565 break;
566 case EVLWHOU:
567 case EVLWHOS:
568 data.h[1] = temp.h[2];
569 data.h[3] = temp.h[3];
570 break;
571 case EVLWWSPLAT:
572 data.w[0] = temp.w[1];
573 data.w[1] = temp.w[1];
574 break;
575 case EVLWHSPLAT:
576 data.h[0] = temp.h[2];
577 data.h[1] = temp.h[2];
578 data.h[2] = temp.h[3];
579 data.h[3] = temp.h[3];
580 break;
581 default:
582 return -EINVAL;
583 }
584 }
585
586 if (flags & SW) {
587 switch (flags & 0xf0) {
588 case E8:
f626190d 589 data.ll = swab64(data.ll);
26caeb2e
KG		 590 break;
591 case E4:
f626190d
AB		 592 data.w[0] = swab32(data.w[0]);
593 data.w[1] = swab32(data.w[1]);
26caeb2e
KG		 594 break;
595 /* Its half word endian */
596 default:
f626190d
AB		 597 data.h[0] = swab16(data.h[0]);
598 data.h[1] = swab16(data.h[1]);
599 data.h[2] = swab16(data.h[2]);
600 data.h[3] = swab16(data.h[3]);
26caeb2e
KG		 601 break;
602 }
603 }
604
605 if (flags & SE) {
606 data.w[0] = (s16)data.h[1];
607 data.w[1] = (s16)data.h[3];
608 }
609
610 /* Store result to memory or update registers */
611 if (flags & ST) {
612 ret = 0;
613 p = addr;
614 switch (nb) {
615 case 8:
616 ret |= __put_user_inatomic(data.v[0], p++);
617 ret |= __put_user_inatomic(data.v[1], p++);
618 ret |= __put_user_inatomic(data.v[2], p++);
619 ret |= __put_user_inatomic(data.v[3], p++);
620 case 4:
621 ret |= __put_user_inatomic(data.v[4], p++);
622 ret |= __put_user_inatomic(data.v[5], p++);
623 case 2:
624 ret |= __put_user_inatomic(data.v[6], p++);
625 ret |= __put_user_inatomic(data.v[7], p++);
626 }
627 if (unlikely(ret))
628 return -EFAULT;
629 } else {
630 *evr = data.w[0];
631 regs->gpr[reg] = data.w[1];
632 }
633
634 return 1;
635}
636#endif /* CONFIG_SPE */
5daf9071 637
52055d07 638#ifdef CONFIG_VSX
cd6f37be
MN		 639/*
640 * Emulate VSX instructions...
641 */
642static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
643 unsigned int areg, struct pt_regs *regs,
bb7f20b1
NC		 644 unsigned int flags, unsigned int length,
645 unsigned int elsize)
cd6f37be 646{
26456dcf 647 char *ptr;
bb7f20b1 648 unsigned long *lptr;
78fbc824 649 int ret = 0;
bb7f20b1
NC		 650 int sw = 0;
651 int i, j;
cd6f37be 652
5c2e0823
AB		 653 /* userland only */
654 if (unlikely(!user_mode(regs)))
655 return 0;
656
cd6f37be
MN		 657 flush_vsx_to_thread(current);
658
26456dcf 659 if (reg < 32)
3ad26e5c 660 ptr = (char *) &current->thread.fp_state.fpr[reg][0];
26456dcf 661 else
de79f7b9 662 ptr = (char *) &current->thread.vr_state.vr[reg - 32];
26456dcf 663
bb7f20b1
NC		 664 lptr = (unsigned long *) ptr;
665
52055d07
AB		 666#ifdef __LITTLE_ENDIAN__
667 if (flags & SW) {
668 elsize = length;
669 sw = length-1;
670 } else {
671 /*
672 * The elements are BE ordered, even in LE mode, so process
673 * them in reverse order.
674 */
675 addr += length - elsize;
676
677 /* 8 byte memory accesses go in the top 8 bytes of the VR */
678 if (length == 8)
679 ptr += 8;
680 }
681#else
bb7f20b1
NC		 682 if (flags & SW)
683 sw = elsize-1;
52055d07 684#endif
bb7f20b1
NC		 685
686 for (j = 0; j < length; j += elsize) {
687 for (i = 0; i < elsize; ++i) {
688 if (flags & ST)
689 ret |= __put_user(ptr[i^sw], addr + i);
690 else
691 ret |= __get_user(ptr[i^sw], addr + i);
cd6f37be 692 }
bb7f20b1 693 ptr += elsize;
52055d07
AB		 694#ifdef __LITTLE_ENDIAN__
695 addr -= elsize;
696#else
bb7f20b1 697 addr += elsize;
52055d07 698#endif
cd6f37be 699 }
bb7f20b1 700
52055d07
AB		 701#ifdef __BIG_ENDIAN__
702#define VSX_HI 0
703#define VSX_LO 1
704#else
705#define VSX_HI 1
706#define VSX_LO 0
707#endif
708
bb7f20b1
NC		 709 if (!ret) {
710 if (flags & U)
711 regs->gpr[areg] = regs->dar;
712
713 /* Splat load copies the same data to top and bottom 8 bytes */
714 if (flags & SPLT)
52055d07
AB		 715 lptr[VSX_LO] = lptr[VSX_HI];
716 /* For 8 byte loads, zero the low 8 bytes */
bb7f20b1 717 else if (!(flags & ST) && (8 == length))
52055d07 718 lptr[VSX_LO] = 0;
bb7f20b1 719 } else
cd6f37be 720 return -EFAULT;
bb7f20b1 721
cd6f37be
MN		 722 return 1;
723}
724#endif
725
5daf9071
BH		 726/*
727 * Called on alignment exception. Attempts to fixup
728 *
729 * Return 1 on success
730 * Return 0 if unable to handle the interrupt
731 * Return -EFAULT if data address is bad
732 */
733
734int fix_alignment(struct pt_regs *regs)
1da177e4 735{
cd6f37be 736 unsigned int instr, nb, flags, instruction = 0;
5daf9071
BH		 737 unsigned int reg, areg;
738 unsigned int dsisr;
1da177e4 739 unsigned char __user *addr;
fab5db97 740 unsigned long p, swiz;
835e206a
AB		 741 int ret, i;
742 union data {
5daf9071 743 u64 ll;
1da177e4
LT		 744 double dd;
745 unsigned char v[8];
746 struct {
835e206a
AB		 747#ifdef __LITTLE_ENDIAN__
748 int low32;
749 unsigned hi32;
750#else
1da177e4
LT		 751 unsigned hi32;
752 int low32;
835e206a 753#endif
1da177e4
LT		 754 } x32;
755 struct {
835e206a
AB		 756#ifdef __LITTLE_ENDIAN__
757 short low16;
758 unsigned char hi48[6];
759#else
1da177e4
LT		 760 unsigned char hi48[6];
761 short low16;
835e206a 762#endif
1da177e4
LT		 763 } x16;
764 } data;
765
766 /*
5daf9071
BH		 767 * We require a complete register set, if not, then our assembly
768 * is broken
1da177e4 769 */
5daf9071 770 CHECK_FULL_REGS(regs);
1da177e4
LT		 771
772 dsisr = regs->dsisr;
773
5daf9071
BH		 774 /* Some processors don't provide us with a DSISR we can use here,
775 * let's make one up from the instruction
776 */
1da177e4 777 if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
fab5db97
PM		 778 unsigned long pc = regs->nip;
779
780 if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE))
781 pc ^= 4;
e4ee3891
BH		 782 if (unlikely(__get_user_inatomic(instr,
783 (unsigned int __user *)pc)))
5daf9071 784 return -EFAULT;
fab5db97
PM		 785 if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE))
786 instr = cpu_to_le32(instr);
787 dsisr = make_dsisr(instr);
cd6f37be 788 instruction = instr;
1da177e4
LT		 789 }
790
791 /* extract the operation and registers from the dsisr */
792 reg = (dsisr >> 5) & 0x1f; /* source/dest register */
793 areg = dsisr & 0x1f; /* register to update */
26caeb2e
KG		 794
795#ifdef CONFIG_SPE
80947e7c 796 if ((instr >> 26) == 0x4) {
eecff81d 797 PPC_WARN_ALIGNMENT(spe, regs);
26caeb2e 798 return emulate_spe(regs, reg, instr);
80947e7c 799 }
26caeb2e
KG		 800#endif
801
1da177e4
LT		 802 instr = (dsisr >> 10) & 0x7f;
803 instr |= (dsisr >> 13) & 0x60;
804
805 /* Lookup the operation in our table */
806 nb = aligninfo[instr].len;
807 flags = aligninfo[instr].flags;
808
230aef7a
AB		 809 /* ldbrx/stdbrx overlap lfs/stfs in the DSISR unfortunately */
810 if (IS_XFORM(instruction) && ((instruction >> 1) & 0x3ff) == 532) {
811 nb = 8;
812 flags = LD+SW;
813 } else if (IS_XFORM(instruction) &&
814 ((instruction >> 1) & 0x3ff) == 660) {
815 nb = 8;
816 flags = ST+SW;
817 }
818
fab5db97
PM		 819 /* Byteswap little endian loads and stores */
820 swiz = 0;
835e206a 821 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
fab5db97 822 flags ^= SW;
835e206a 823#ifdef __BIG_ENDIAN__
fab5db97
PM		 824 /*
825 * So-called "PowerPC little endian" mode works by
826 * swizzling addresses rather than by actually doing
827 * any byte-swapping. To emulate this, we XOR each
828 * byte address with 7. We also byte-swap, because
829 * the processor's address swizzling depends on the
830 * operand size (it xors the address with 7 for bytes,
831 * 6 for halfwords, 4 for words, 0 for doublewords) but
832 * we will xor with 7 and load/store each byte separately.
833 */
834 if (cpu_has_feature(CPU_FTR_PPC_LE))
835 swiz = 7;
835e206a 836#endif
fab5db97
PM		 837 }
838
1da177e4
LT		 839 /* DAR has the operand effective address */
840 addr = (unsigned char __user *)regs->dar;
841
cd6f37be
MN		 842#ifdef CONFIG_VSX
843 if ((instruction & 0xfc00003e) == 0x7c000018) {
bb7f20b1
NC		 844 unsigned int elsize;
845
846 /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
cd6f37be
MN		 847 reg |= (instruction & 0x1) << 5;
848 /* Simple inline decoder instead of a table */
bb7f20b1
NC		 849 /* VSX has only 8 and 16 byte memory accesses */
850 nb = 8;
cd6f37be
MN		 851 if (instruction & 0x200)
852 nb = 16;
bb7f20b1
NC		 853
854 /* Vector stores in little-endian mode swap individual
855 elements, so process them separately */
856 elsize = 4;
857 if (instruction & 0x80)
858 elsize = 8;
859
cd6f37be 860 flags = 0;
835e206a 861 if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE))
bb7f20b1 862 flags |= SW;
cd6f37be
MN		 863 if (instruction & 0x100)
864 flags |= ST;
865 if (instruction & 0x040)
866 flags |= U;
867 /* splat load needs a special decoder */
868 if ((instruction & 0x400) == 0){
869 flags |= SPLT;
870 nb = 8;
871 }
eecff81d 872 PPC_WARN_ALIGNMENT(vsx, regs);
bb7f20b1 873 return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
cd6f37be
MN		 874 }
875#endif
5daf9071
BH		 876 /* A size of 0 indicates an instruction we don't support, with
877 * the exception of DCBZ which is handled as a special case here
1da177e4 878 */
80947e7c 879 if (instr == DCBZ) {
eecff81d 880 PPC_WARN_ALIGNMENT(dcbz, regs);
5daf9071 881 return emulate_dcbz(regs, addr);
80947e7c 882 }
5daf9071
BH		 883 if (unlikely(nb == 0))
884 return 0;
885
886 /* Load/Store Multiple instructions are handled in their own
887 * function
888 */
80947e7c 889 if (flags & M) {
eecff81d 890 PPC_WARN_ALIGNMENT(multiple, regs);
fab5db97
PM		 891 return emulate_multiple(regs, addr, reg, nb,
892 flags, instr, swiz);
80947e7c 893 }
1da177e4
LT		 894
895 /* Verify the address of the operand */
5daf9071
BH		 896 if (unlikely(user_mode(regs) &&
897 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
898 addr, nb)))
899 return -EFAULT;
1da177e4
LT		 900
901 /* Force the fprs into the save area so we can reference them */
902 if (flags & F) {
5daf9071
BH		 903 /* userland only */
904 if (unlikely(!user_mode(regs)))
1da177e4
LT		 905 return 0;
906 flush_fp_to_thread(current);
907 }
5daf9071 908
6f791bef 909 if (nb == 16) {
f83319d7
AB		 910 if (flags & F) {
911 /* Special case for 16-byte FP loads and stores */
912 PPC_WARN_ALIGNMENT(fp_pair, regs);
913 return emulate_fp_pair(addr, reg, flags);
914 } else {
915#ifdef CONFIG_PPC64
916 /* Special case for 16-byte loads and stores */
917 PPC_WARN_ALIGNMENT(lq_stq, regs);
918 return emulate_lq_stq(regs, addr, reg, flags);
919#else
920 return 0;
921#endif
922 }
80947e7c
GU		 923 }
924
eecff81d 925 PPC_WARN_ALIGNMENT(unaligned, regs);
c6d4267e 926
5daf9071
BH		 927 /* If we are loading, get the data from user space, else
928 * get it from register values
929 */
fab5db97 930 if (!(flags & ST)) {
835e206a
AB		 931 unsigned int start = 0;
932
1da177e4 933 switch (nb) {
1da177e4 934 case 4:
835e206a
AB		 935 start = offsetof(union data, x32.low32);
936 break;
1da177e4 937 case 2:
835e206a
AB		 938 start = offsetof(union data, x16.low16);
939 break;
1da177e4 940 }
835e206a
AB		 941
942 data.ll = 0;
943 ret = 0;
944 p = (unsigned long)addr;
945
946 for (i = 0; i < nb; i++)
947 ret |= __get_user_inatomic(data.v[start + i],
948 SWIZ_PTR(p++));
949
950 if (unlikely(ret))
951 return -EFAULT;
952
fab5db97 953 } else if (flags & F) {
de79f7b9 954 data.ll = current->thread.TS_FPR(reg);
fab5db97
PM		 955 if (flags & S) {
956 /* Single-precision FP store requires conversion... */
957#ifdef CONFIG_PPC_FPU
958 preempt_disable();
959 enable_kernel_fp();
c3244964 960 cvt_df(&data.dd, (float *)&data.x32.low32);
dc4fbba1 961 disable_kernel_fp();
fab5db97
PM		 962 preempt_enable();
963#else
964 return 0;
965#endif
966 }
967 } else
5daf9071
BH		 968 data.ll = regs->gpr[reg];
969
fab5db97
PM		 970 if (flags & SW) {
971 switch (nb) {
972 case 8:
f626190d 973 data.ll = swab64(data.ll);
fab5db97
PM		 974 break;
975 case 4:
f626190d 976 data.x32.low32 = swab32(data.x32.low32);
fab5db97
PM		 977 break;
978 case 2:
f626190d 979 data.x16.low16 = swab16(data.x16.low16);
fab5db97
PM		 980 break;
981 }
982 }
983
984 /* Perform other misc operations like sign extension
5daf9071
BH		 985 * or floating point single precision conversion
986 */
fab5db97 987 switch (flags & ~(U|SW)) {
c6d4267e
PM		 988 case LD+SE: /* sign extending integer loads */
989 case LD+F+SE: /* sign extend for lfiwax */
1da177e4
LT		 990 if ( nb == 2 )
991 data.ll = data.x16.low16;
992 else /* nb must be 4 */
993 data.ll = data.x32.low32;
5daf9071 994 break;
5daf9071 995
fab5db97 996 /* Single-precision FP load requires conversion... */
5daf9071
BH		 997 case LD+F+S:
998#ifdef CONFIG_PPC_FPU
999 preempt_disable();
1000 enable_kernel_fp();
c3244964 1001 cvt_fd((float *)&data.x32.low32, &data.dd);
dc4fbba1 1002 disable_kernel_fp();
5daf9071
BH		 1003 preempt_enable();
1004#else
1005 return 0;
5daf9071
BH		 1006#endif
1007 break;
1da177e4 1008 }
5daf9071
BH		 1009
1010 /* Store result to memory or update registers */
1da177e4 1011 if (flags & ST) {
835e206a
AB		 1012 unsigned int start = 0;
1013
1da177e4 1014 switch (nb) {
1da177e4 1015 case 4:
835e206a
AB		 1016 start = offsetof(union data, x32.low32);
1017 break;
1da177e4 1018 case 2:
835e206a
AB		 1019 start = offsetof(union data, x16.low16);
1020 break;
1da177e4 1021 }
835e206a
AB		 1022
1023 ret = 0;
1024 p = (unsigned long)addr;
1025
1026 for (i = 0; i < nb; i++)
1027 ret |= __put_user_inatomic(data.v[start + i],
1028 SWIZ_PTR(p++));
1029
5daf9071 1030 if (unlikely(ret))
1da177e4 1031 return -EFAULT;
5daf9071 1032 } else if (flags & F)
de79f7b9 1033 current->thread.TS_FPR(reg) = data.ll;
5daf9071
BH		 1034 else
1035 regs->gpr[reg] = data.ll;
1036
1da177e4 1037 /* Update RA as needed */
5daf9071 1038 if (flags & U)
1da177e4 1039 regs->gpr[areg] = regs->dar;
1da177e4
LT		 1040
1041 return 1;
1042}
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