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Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * This program is used to generate definitions needed by | |
3 | * assembly language modules. | |
4 | * | |
5 | * We use the technique used in the OSF Mach kernel code: | |
6 | * generate asm statements containing #defines, | |
7 | * compile this file to assembler, and then extract the | |
8 | * #defines from the assembly-language output. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
ed1cd6de CL |
16 | #define GENERATING_ASM_OFFSETS /* asm/smp.h */ |
17 | ||
0d55303c | 18 | #include <linux/compat.h> |
14cf11af PM |
19 | #include <linux/signal.h> |
20 | #include <linux/sched.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/string.h> | |
24 | #include <linux/types.h> | |
14cf11af PM |
25 | #include <linux/mman.h> |
26 | #include <linux/mm.h> | |
543b9fd3 | 27 | #include <linux/suspend.h> |
ad7f7167 | 28 | #include <linux/hrtimer.h> |
d1dead5c | 29 | #ifdef CONFIG_PPC64 |
14cf11af PM |
30 | #include <linux/time.h> |
31 | #include <linux/hardirq.h> | |
d1dead5c | 32 | #endif |
d4d298fe | 33 | #include <linux/kbuild.h> |
d1dead5c | 34 | |
14cf11af PM |
35 | #include <asm/io.h> |
36 | #include <asm/page.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/processor.h> | |
14cf11af PM |
39 | #include <asm/cputable.h> |
40 | #include <asm/thread_info.h> | |
033ef338 | 41 | #include <asm/rtas.h> |
a7f290da | 42 | #include <asm/vdso_datapage.h> |
66feed61 | 43 | #include <asm/dbell.h> |
14cf11af PM |
44 | #ifdef CONFIG_PPC64 |
45 | #include <asm/paca.h> | |
46 | #include <asm/lppaca.h> | |
14cf11af | 47 | #include <asm/cache.h> |
11a27ad7 | 48 | #include <asm/mmu.h> |
f04da0bc | 49 | #include <asm/hvcall.h> |
19ccb76a | 50 | #include <asm/xics.h> |
14cf11af | 51 | #endif |
ed79ba9e BH |
52 | #ifdef CONFIG_PPC_POWERNV |
53 | #include <asm/opal.h> | |
54 | #endif | |
989044ee | 55 | #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST) |
366d4b9b | 56 | #include <linux/kvm_host.h> |
0604675f | 57 | #endif |
989044ee AG |
58 | #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S) |
59 | #include <asm/kvm_book3s.h> | |
5deb8e7a | 60 | #include <asm/kvm_ppc.h> |
db93f574 | 61 | #endif |
14cf11af | 62 | |
57e2a99f | 63 | #ifdef CONFIG_PPC32 |
fca622c5 KG |
64 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
65 | #include "head_booke.h" | |
66 | #endif | |
57e2a99f | 67 | #endif |
fca622c5 | 68 | |
55fd766b | 69 | #if defined(CONFIG_PPC_FSL_BOOK3E) |
19f5465e TP |
70 | #include "../mm/mmu_decl.h" |
71 | #endif | |
72 | ||
f86ef74e CL |
73 | #ifdef CONFIG_PPC_8xx |
74 | #include <asm/fixmap.h> | |
75 | #endif | |
76 | ||
10d4cf18 RG |
77 | #define STACK_PT_REGS_OFFSET(sym, val) \ |
78 | DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val)) | |
79 | ||
14cf11af PM |
80 | int main(void) |
81 | { | |
45465615 RG |
82 | OFFSET(THREAD, task_struct, thread); |
83 | OFFSET(MM, task_struct, mm); | |
c3ff2a51 CL |
84 | #ifdef CONFIG_STACKPROTECTOR |
85 | OFFSET(TASK_CANARY, task_struct, stack_canary); | |
06ec27ae CL |
86 | #ifdef CONFIG_PPC64 |
87 | OFFSET(PACA_CANARY, paca_struct, canary); | |
88 | #endif | |
c3ff2a51 | 89 | #endif |
45465615 | 90 | OFFSET(MMCONTEXTID, mm_struct, context.id); |
14cf11af | 91 | #ifdef CONFIG_PPC64 |
9c1e1052 PM |
92 | DEFINE(SIGSEGV, SIGSEGV); |
93 | DEFINE(NMI_MASK, NMI_MASK); | |
d1dead5c | 94 | #else |
45465615 | 95 | OFFSET(KSP_LIMIT, thread_struct, ksp_limit); |
0df977ea CL |
96 | #ifdef CONFIG_PPC_RTAS |
97 | OFFSET(RTAS_SP, thread_struct, rtas_sp); | |
98 | #endif | |
d1dead5c | 99 | #endif /* CONFIG_PPC64 */ |
8c1fc5ab | 100 | OFFSET(TASK_STACK, task_struct, stack); |
ed1cd6de | 101 | #ifdef CONFIG_SMP |
f7354cca | 102 | OFFSET(TASK_CPU, task_struct, cpu); |
ed1cd6de | 103 | #endif |
d1dead5c | 104 | |
85baa095 | 105 | #ifdef CONFIG_LIVEPATCH |
45465615 | 106 | OFFSET(TI_livepatch_sp, thread_info, livepatch_sp); |
85baa095 ME |
107 | #endif |
108 | ||
45465615 RG |
109 | OFFSET(KSP, thread_struct, ksp); |
110 | OFFSET(PT_REGS, thread_struct, regs); | |
1325a684 | 111 | #ifdef CONFIG_BOOKE |
45465615 | 112 | OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]); |
1325a684 | 113 | #endif |
45465615 | 114 | OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode); |
aa9a9516 | 115 | OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr); |
45465615 RG |
116 | OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area); |
117 | OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr); | |
118 | OFFSET(THREAD_LOAD_FP, thread_struct, load_fp); | |
14cf11af | 119 | #ifdef CONFIG_ALTIVEC |
aa9a9516 | 120 | OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr); |
45465615 RG |
121 | OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area); |
122 | OFFSET(THREAD_VRSAVE, thread_struct, vrsave); | |
123 | OFFSET(THREAD_USED_VR, thread_struct, used_vr); | |
124 | OFFSET(VRSTATE_VSCR, thread_vr_state, vscr); | |
125 | OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec); | |
14cf11af | 126 | #endif /* CONFIG_ALTIVEC */ |
c6e6771b | 127 | #ifdef CONFIG_VSX |
45465615 | 128 | OFFSET(THREAD_USED_VSR, thread_struct, used_vsr); |
c6e6771b | 129 | #endif /* CONFIG_VSX */ |
d1dead5c | 130 | #ifdef CONFIG_PPC64 |
45465615 | 131 | OFFSET(KSP_VSID, thread_struct, ksp_vsid); |
d1dead5c | 132 | #else /* CONFIG_PPC64 */ |
45465615 | 133 | OFFSET(PGDIR, thread_struct, pgdir); |
14cf11af | 134 | #ifdef CONFIG_SPE |
45465615 RG |
135 | OFFSET(THREAD_EVR0, thread_struct, evr[0]); |
136 | OFFSET(THREAD_ACC, thread_struct, acc); | |
137 | OFFSET(THREAD_SPEFSCR, thread_struct, spefscr); | |
138 | OFFSET(THREAD_USED_SPE, thread_struct, used_spe); | |
14cf11af | 139 | #endif /* CONFIG_SPE */ |
d1dead5c | 140 | #endif /* CONFIG_PPC64 */ |
13d543cd | 141 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
45465615 | 142 | OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0); |
13d543cd | 143 | #endif |
97e49255 | 144 | #ifdef CONFIG_KVM_BOOK3S_32_HANDLER |
45465615 | 145 | OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu); |
97e49255 | 146 | #endif |
ffe129ec | 147 | #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE) |
45465615 | 148 | OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu); |
d30f6e48 | 149 | #endif |
d1dead5c | 150 | |
8b3c34cf | 151 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
45465615 RG |
152 | OFFSET(PACATMSCRATCH, paca_struct, tm_scratch); |
153 | OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar); | |
154 | OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr); | |
155 | OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar); | |
156 | OFFSET(THREAD_TM_TAR, thread_struct, tm_tar); | |
157 | OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr); | |
158 | OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr); | |
159 | OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs); | |
aa9a9516 | 160 | OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr); |
45465615 | 161 | OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave); |
aa9a9516 | 162 | OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr); |
8b3c34cf MN |
163 | /* Local pt_regs on stack for Transactional Memory funcs. */ |
164 | DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD + | |
165 | sizeof(struct pt_regs) + 16); | |
166 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
2468dcf6 | 167 | |
45465615 RG |
168 | OFFSET(TI_FLAGS, thread_info, flags); |
169 | OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags); | |
170 | OFFSET(TI_PREEMPT, thread_info, preempt_count); | |
d1dead5c SR |
171 | |
172 | #ifdef CONFIG_PPC64 | |
45465615 RG |
173 | OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size); |
174 | OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size); | |
175 | OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page); | |
176 | OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size); | |
177 | OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size); | |
178 | OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page); | |
d1dead5c SR |
179 | /* paca */ |
180 | DEFINE(PACA_SIZE, sizeof(struct paca_struct)); | |
45465615 RG |
181 | OFFSET(PACAPACAINDEX, paca_struct, paca_index); |
182 | OFFSET(PACAPROCSTART, paca_struct, cpu_start); | |
183 | OFFSET(PACAKSAVE, paca_struct, kstack); | |
184 | OFFSET(PACACURRENT, paca_struct, __current); | |
c911d2e1 CL |
185 | DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) + |
186 | offsetof(struct task_struct, thread_info)); | |
45465615 | 187 | OFFSET(PACASAVEDMSR, paca_struct, saved_msr); |
45465615 RG |
188 | OFFSET(PACAR1, paca_struct, saved_r1); |
189 | OFFSET(PACATOC, paca_struct, kernel_toc); | |
190 | OFFSET(PACAKBASE, paca_struct, kernelbase); | |
191 | OFFSET(PACAKMSR, paca_struct, kernel_msr); | |
4e26bc4a | 192 | OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask); |
45465615 | 193 | OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened); |
ea678ac6 | 194 | OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled); |
c395465d | 195 | #ifdef CONFIG_PPC_BOOK3S |
45465615 | 196 | OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id); |
d0f13e3c | 197 | #ifdef CONFIG_PPC_MM_SLICES |
45465615 RG |
198 | OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize); |
199 | OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize); | |
4722476b | 200 | OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit); |
d0f13e3c | 201 | DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); |
91c60b5b | 202 | #endif /* CONFIG_PPC_MM_SLICES */ |
c395465d | 203 | #endif |
dce6670a BH |
204 | |
205 | #ifdef CONFIG_PPC_BOOK3E | |
45465615 RG |
206 | OFFSET(PACAPGD, paca_struct, pgd); |
207 | OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd); | |
208 | OFFSET(PACA_EXGEN, paca_struct, exgen); | |
209 | OFFSET(PACA_EXTLB, paca_struct, extlb); | |
210 | OFFSET(PACA_EXMC, paca_struct, exmc); | |
211 | OFFSET(PACA_EXCRIT, paca_struct, excrit); | |
212 | OFFSET(PACA_EXDBG, paca_struct, exdbg); | |
213 | OFFSET(PACA_MC_STACK, paca_struct, mc_kstack); | |
214 | OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack); | |
215 | OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack); | |
216 | OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr); | |
217 | ||
218 | OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next); | |
219 | OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max); | |
220 | OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first); | |
dce6670a BH |
221 | #endif /* CONFIG_PPC_BOOK3E */ |
222 | ||
4e003747 | 223 | #ifdef CONFIG_PPC_BOOK3S_64 |
45465615 RG |
224 | OFFSET(PACASLBCACHE, paca_struct, slb_cache); |
225 | OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr); | |
126b11b2 | 226 | OFFSET(PACASTABRR, paca_struct, stab_rr); |
45465615 | 227 | OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp); |
91c60b5b | 228 | #ifdef CONFIG_PPC_MM_SLICES |
45465615 | 229 | OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp); |
d0f13e3c | 230 | #else |
45465615 | 231 | OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp); |
d0f13e3c | 232 | #endif /* CONFIG_PPC_MM_SLICES */ |
45465615 RG |
233 | OFFSET(PACA_EXGEN, paca_struct, exgen); |
234 | OFFSET(PACA_EXMC, paca_struct, exmc); | |
235 | OFFSET(PACA_EXSLB, paca_struct, exslb); | |
a3d96f70 | 236 | OFFSET(PACA_EXNMI, paca_struct, exnmi); |
8e0b634b | 237 | #ifdef CONFIG_PPC_PSERIES |
45465615 | 238 | OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr); |
8e0b634b | 239 | #endif |
45465615 RG |
240 | OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr); |
241 | OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid); | |
242 | OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid); | |
243 | OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area); | |
244 | OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use); | |
8e0b634b NP |
245 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
246 | OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use); | |
247 | #endif | |
45465615 RG |
248 | OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx); |
249 | OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count); | |
250 | OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx); | |
4e003747 | 251 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
45465615 | 252 | OFFSET(PACAEMERGSP, paca_struct, emergency_sp); |
1e9b4507 | 253 | #ifdef CONFIG_PPC_BOOK3S_64 |
45465615 | 254 | OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp); |
b1ee8a3d | 255 | OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp); |
45465615 | 256 | OFFSET(PACA_IN_MCE, paca_struct, in_mce); |
c4f3b52c | 257 | OFFSET(PACA_IN_NMI, paca_struct, in_nmi); |
aa8a5e00 ME |
258 | OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area); |
259 | OFFSET(PACA_EXRFI, paca_struct, exrfi); | |
bdcb1aef | 260 | OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size); |
aa8a5e00 | 261 | |
45465615 RG |
262 | #endif |
263 | OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id); | |
264 | OFFSET(PACAKEXECSTATE, paca_struct, kexec_state); | |
265 | OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default); | |
266 | OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime); | |
267 | OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user); | |
b286cedd LT |
268 | OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime); |
269 | OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime); | |
45465615 RG |
270 | OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save); |
271 | OFFSET(PACA_NAPSTATELOST, paca_struct, nap_state_lost); | |
272 | OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso); | |
c223c903 CL |
273 | #else /* CONFIG_PPC64 */ |
274 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE | |
45465615 RG |
275 | OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime); |
276 | OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user); | |
b286cedd LT |
277 | OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime); |
278 | OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime); | |
c223c903 | 279 | #endif |
033ef338 | 280 | #endif /* CONFIG_PPC64 */ |
d1dead5c SR |
281 | |
282 | /* RTAS */ | |
45465615 RG |
283 | OFFSET(RTASBASE, rtas_t, base); |
284 | OFFSET(RTASENTRY, rtas_t, entry); | |
d1dead5c | 285 | |
14cf11af | 286 | /* Interrupt register frame */ |
91120cc8 | 287 | DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); |
14cf11af | 288 | DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); |
10d4cf18 RG |
289 | STACK_PT_REGS_OFFSET(GPR0, gpr[0]); |
290 | STACK_PT_REGS_OFFSET(GPR1, gpr[1]); | |
291 | STACK_PT_REGS_OFFSET(GPR2, gpr[2]); | |
292 | STACK_PT_REGS_OFFSET(GPR3, gpr[3]); | |
293 | STACK_PT_REGS_OFFSET(GPR4, gpr[4]); | |
294 | STACK_PT_REGS_OFFSET(GPR5, gpr[5]); | |
295 | STACK_PT_REGS_OFFSET(GPR6, gpr[6]); | |
296 | STACK_PT_REGS_OFFSET(GPR7, gpr[7]); | |
297 | STACK_PT_REGS_OFFSET(GPR8, gpr[8]); | |
298 | STACK_PT_REGS_OFFSET(GPR9, gpr[9]); | |
299 | STACK_PT_REGS_OFFSET(GPR10, gpr[10]); | |
300 | STACK_PT_REGS_OFFSET(GPR11, gpr[11]); | |
301 | STACK_PT_REGS_OFFSET(GPR12, gpr[12]); | |
302 | STACK_PT_REGS_OFFSET(GPR13, gpr[13]); | |
d1dead5c | 303 | #ifndef CONFIG_PPC64 |
10d4cf18 | 304 | STACK_PT_REGS_OFFSET(GPR14, gpr[14]); |
d1dead5c | 305 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
306 | /* |
307 | * Note: these symbols include _ because they overlap with special | |
308 | * register names | |
309 | */ | |
10d4cf18 RG |
310 | STACK_PT_REGS_OFFSET(_NIP, nip); |
311 | STACK_PT_REGS_OFFSET(_MSR, msr); | |
312 | STACK_PT_REGS_OFFSET(_CTR, ctr); | |
313 | STACK_PT_REGS_OFFSET(_LINK, link); | |
314 | STACK_PT_REGS_OFFSET(_CCR, ccr); | |
315 | STACK_PT_REGS_OFFSET(_XER, xer); | |
316 | STACK_PT_REGS_OFFSET(_DAR, dar); | |
317 | STACK_PT_REGS_OFFSET(_DSISR, dsisr); | |
318 | STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3); | |
319 | STACK_PT_REGS_OFFSET(RESULT, result); | |
320 | STACK_PT_REGS_OFFSET(_TRAP, trap); | |
d1dead5c | 321 | #ifndef CONFIG_PPC64 |
d1dead5c SR |
322 | /* |
323 | * The PowerPC 400-class & Book-E processors have neither the DAR | |
324 | * nor the DSISR SPRs. Hence, we overload them to hold the similar | |
325 | * DEAR and ESR SPRs for such processors. For critical interrupts | |
326 | * we use them to hold SRR0 and SRR1. | |
14cf11af | 327 | */ |
10d4cf18 RG |
328 | STACK_PT_REGS_OFFSET(_DEAR, dar); |
329 | STACK_PT_REGS_OFFSET(_ESR, dsisr); | |
d1dead5c | 330 | #else /* CONFIG_PPC64 */ |
10d4cf18 | 331 | STACK_PT_REGS_OFFSET(SOFTE, softe); |
4c2de74c | 332 | STACK_PT_REGS_OFFSET(_PPR, ppr); |
d1dead5c SR |
333 | #endif /* CONFIG_PPC64 */ |
334 | ||
57e2a99f | 335 | #if defined(CONFIG_PPC32) |
fca622c5 KG |
336 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
337 | DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE); | |
338 | DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); | |
339 | /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */ | |
340 | DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); | |
341 | DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1)); | |
342 | DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2)); | |
343 | DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3)); | |
344 | DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6)); | |
345 | DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7)); | |
346 | DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0)); | |
347 | DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1)); | |
348 | DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0)); | |
349 | DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1)); | |
350 | DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0)); | |
351 | DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1)); | |
352 | DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit)); | |
353 | #endif | |
57e2a99f | 354 | #endif |
d1dead5c SR |
355 | |
356 | #ifndef CONFIG_PPC64 | |
45465615 | 357 | OFFSET(MM_PGD, mm_struct, pgd); |
d1dead5c | 358 | #endif /* ! CONFIG_PPC64 */ |
14cf11af PM |
359 | |
360 | /* About the CPU features table */ | |
45465615 RG |
361 | OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features); |
362 | OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup); | |
363 | OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore); | |
14cf11af | 364 | |
45465615 RG |
365 | OFFSET(pbe_address, pbe, address); |
366 | OFFSET(pbe_orig_address, pbe, orig_address); | |
367 | OFFSET(pbe_next, pbe, next); | |
14cf11af | 368 | |
543b9fd3 | 369 | #ifndef CONFIG_PPC64 |
fd582ec8 | 370 | DEFINE(TASK_SIZE, TASK_SIZE); |
d1dead5c | 371 | DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); |
a7f290da | 372 | #endif /* ! CONFIG_PPC64 */ |
14cf11af | 373 | |
a7f290da | 374 | /* datapage offsets for use by vdso */ |
45465615 RG |
375 | OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp); |
376 | OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec); | |
377 | OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs); | |
378 | OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count); | |
379 | OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest); | |
380 | OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime); | |
381 | OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32); | |
382 | OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec); | |
383 | OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec); | |
384 | OFFSET(STAMP_XTIME, vdso_data, stamp_xtime); | |
385 | OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction); | |
386 | OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size); | |
387 | OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size); | |
388 | OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size); | |
389 | OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size); | |
a7f290da | 390 | #ifdef CONFIG_PPC64 |
45465615 RG |
391 | OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64); |
392 | OFFSET(TVAL64_TV_SEC, timeval, tv_sec); | |
393 | OFFSET(TVAL64_TV_USEC, timeval, tv_usec); | |
9afc5eee AB |
394 | OFFSET(TVAL32_TV_SEC, old_timeval32, tv_sec); |
395 | OFFSET(TVAL32_TV_USEC, old_timeval32, tv_usec); | |
45465615 RG |
396 | OFFSET(TSPC64_TV_SEC, timespec, tv_sec); |
397 | OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec); | |
9afc5eee AB |
398 | OFFSET(TSPC32_TV_SEC, old_timespec32, tv_sec); |
399 | OFFSET(TSPC32_TV_NSEC, old_timespec32, tv_nsec); | |
a7f290da | 400 | #else |
45465615 RG |
401 | OFFSET(TVAL32_TV_SEC, timeval, tv_sec); |
402 | OFFSET(TVAL32_TV_USEC, timeval, tv_usec); | |
403 | OFFSET(TSPC32_TV_SEC, timespec, tv_sec); | |
404 | OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec); | |
a7f290da BH |
405 | #endif |
406 | /* timeval/timezone offsets for use by vdso */ | |
45465615 RG |
407 | OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest); |
408 | OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime); | |
a7f290da BH |
409 | |
410 | /* Other bits used by the vdso */ | |
411 | DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); | |
412 | DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); | |
5c929885 SS |
413 | DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE); |
414 | DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE); | |
a7f290da | 415 | DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); |
151db1fc | 416 | DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); |
a7f290da | 417 | |
007d88d0 DW |
418 | #ifdef CONFIG_BUG |
419 | DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry)); | |
420 | #endif | |
16a15a30 | 421 | |
03dfee6d ME |
422 | #ifdef CONFIG_PPC_BOOK3S_64 |
423 | DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE))); | |
dd1842a2 | 424 | #else |
ee7a76da | 425 | DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE); |
dd1842a2 | 426 | #endif |
4ee7084e | 427 | DEFINE(PTE_SIZE, sizeof(pte_t)); |
bee86f14 | 428 | |
bbf45ba5 | 429 | #ifdef CONFIG_KVM |
45465615 RG |
430 | OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack); |
431 | OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid); | |
432 | OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid); | |
1143a706 | 433 | OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr); |
45465615 RG |
434 | OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave); |
435 | OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr); | |
de56a948 | 436 | #ifdef CONFIG_ALTIVEC |
45465615 | 437 | OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr); |
de56a948 | 438 | #endif |
173c520a SG |
439 | OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); |
440 | OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); | |
441 | OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); | |
e14e7a1e | 442 | #ifdef CONFIG_PPC_BOOK3S |
45465615 | 443 | OFFSET(VCPU_TAR, kvm_vcpu, arch.tar); |
e14e7a1e | 444 | #endif |
fd0944ba | 445 | OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); |
173c520a | 446 | OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); |
9975f5e3 | 447 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
45465615 RG |
448 | OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr); |
449 | OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0); | |
450 | OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1); | |
451 | OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0); | |
452 | OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1); | |
453 | OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2); | |
454 | OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3); | |
b6c295df PM |
455 | #endif |
456 | #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING | |
45465615 RG |
457 | OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry); |
458 | OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr); | |
459 | OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit); | |
460 | OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time); | |
461 | OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time); | |
462 | OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity); | |
463 | OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start); | |
464 | OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount); | |
465 | OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total); | |
466 | OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min); | |
467 | OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max); | |
468 | #endif | |
469 | OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3); | |
470 | OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4); | |
471 | OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5); | |
472 | OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6); | |
473 | OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7); | |
474 | OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid); | |
475 | OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1); | |
476 | OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared); | |
477 | OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr); | |
478 | OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr); | |
5deb8e7a | 479 | #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE) |
45465615 | 480 | OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian); |
5deb8e7a | 481 | #endif |
bbf45ba5 | 482 | |
45465615 RG |
483 | OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0); |
484 | OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1); | |
485 | OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2); | |
486 | OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3); | |
487 | OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4); | |
488 | OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6); | |
b5904972 | 489 | |
45465615 RG |
490 | OFFSET(VCPU_KVM, kvm_vcpu, kvm); |
491 | OFFSET(KVM_LPID, kvm, arch.lpid); | |
d30f6e48 | 492 | |
00c3a37c | 493 | /* book3s */ |
9975f5e3 | 494 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
45465615 RG |
495 | OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets); |
496 | OFFSET(KVM_SDR1, kvm, arch.sdr1); | |
497 | OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid); | |
498 | OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr); | |
499 | OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1); | |
500 | OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits); | |
501 | OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls); | |
502 | OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v); | |
503 | OFFSET(KVM_RADIX, kvm, arch.radix); | |
134764ed | 504 | OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled); |
45465615 RG |
505 | OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr); |
506 | OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar); | |
507 | OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr); | |
508 | OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty); | |
509 | OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst); | |
360cae31 | 510 | OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested); |
45465615 RG |
511 | OFFSET(VCPU_CPU, kvm_vcpu, cpu); |
512 | OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu); | |
de56a948 | 513 | #endif |
00c3a37c | 514 | #ifdef CONFIG_PPC_BOOK3S |
45465615 RG |
515 | OFFSET(VCPU_PURR, kvm_vcpu, arch.purr); |
516 | OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr); | |
517 | OFFSET(VCPU_IC, kvm_vcpu, arch.ic); | |
518 | OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr); | |
519 | OFFSET(VCPU_AMR, kvm_vcpu, arch.amr); | |
520 | OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor); | |
521 | OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr); | |
522 | OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl); | |
523 | OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr); | |
524 | OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx); | |
525 | OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr); | |
526 | OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx); | |
527 | OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr); | |
528 | OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags); | |
529 | OFFSET(VCPU_DEC, kvm_vcpu, arch.dec); | |
530 | OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires); | |
531 | OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions); | |
532 | OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded); | |
533 | OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded); | |
2267ea76 | 534 | OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending); |
57900694 | 535 | OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request); |
45465615 RG |
536 | OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr); |
537 | OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc); | |
538 | OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc); | |
539 | OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar); | |
540 | OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar); | |
541 | OFFSET(VCPU_SIER, kvm_vcpu, arch.sier); | |
542 | OFFSET(VCPU_SLB, kvm_vcpu, arch.slb); | |
543 | OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max); | |
544 | OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr); | |
545 | OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr); | |
546 | OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar); | |
547 | OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa); | |
548 | OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr); | |
549 | OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); | |
550 | OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap); | |
551 | OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar); | |
552 | OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr); | |
553 | OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr); | |
554 | OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb); | |
555 | OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr); | |
556 | OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr); | |
557 | OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr); | |
558 | OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr); | |
559 | OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr); | |
560 | OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr); | |
561 | OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop); | |
562 | OFFSET(VCPU_WORT, kvm_vcpu, arch.wort); | |
563 | OFFSET(VCPU_TID, kvm_vcpu, arch.tid); | |
564 | OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr); | |
769377f7 | 565 | OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr); |
45465615 RG |
566 | OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map); |
567 | OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest); | |
568 | OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads); | |
569 | OFFSET(VCORE_KVM, kvmppc_vcore, kvm); | |
570 | OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset); | |
57b8daa7 | 571 | OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied); |
45465615 RG |
572 | OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr); |
573 | OFFSET(VCORE_PCR, kvmppc_vcore, pcr); | |
574 | OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes); | |
575 | OFFSET(VCORE_VTB, kvmppc_vcore, vtb); | |
576 | OFFSET(VCPU_SLB_E, kvmppc_slb, orige); | |
577 | OFFSET(VCPU_SLB_V, kvmppc_slb, origv); | |
de56a948 | 578 | DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb)); |
7b490411 | 579 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
45465615 RG |
580 | OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar); |
581 | OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar); | |
582 | OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr); | |
4bb3c7a0 | 583 | OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr); |
45465615 RG |
584 | OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm); |
585 | OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr); | |
586 | OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr); | |
587 | OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm); | |
588 | OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm); | |
589 | OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm); | |
590 | OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm); | |
591 | OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm); | |
592 | OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm); | |
593 | OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm); | |
594 | OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm); | |
595 | OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm); | |
7b490411 | 596 | #endif |
3c42bf8a PM |
597 | |
598 | #ifdef CONFIG_PPC_BOOK3S_64 | |
7aa79938 | 599 | #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE |
45465615 | 600 | OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu); |
3c42bf8a | 601 | # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f)) |
de56a948 PM |
602 | #else |
603 | # define SVCPU_FIELD(x, f) | |
604 | #endif | |
3c42bf8a PM |
605 | # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f)) |
606 | #else /* 32-bit */ | |
607 | # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f)) | |
608 | # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f)) | |
609 | #endif | |
610 | ||
611 | SVCPU_FIELD(SVCPU_CR, cr); | |
612 | SVCPU_FIELD(SVCPU_XER, xer); | |
613 | SVCPU_FIELD(SVCPU_CTR, ctr); | |
614 | SVCPU_FIELD(SVCPU_LR, lr); | |
615 | SVCPU_FIELD(SVCPU_PC, pc); | |
616 | SVCPU_FIELD(SVCPU_R0, gpr[0]); | |
617 | SVCPU_FIELD(SVCPU_R1, gpr[1]); | |
618 | SVCPU_FIELD(SVCPU_R2, gpr[2]); | |
619 | SVCPU_FIELD(SVCPU_R3, gpr[3]); | |
620 | SVCPU_FIELD(SVCPU_R4, gpr[4]); | |
621 | SVCPU_FIELD(SVCPU_R5, gpr[5]); | |
622 | SVCPU_FIELD(SVCPU_R6, gpr[6]); | |
623 | SVCPU_FIELD(SVCPU_R7, gpr[7]); | |
624 | SVCPU_FIELD(SVCPU_R8, gpr[8]); | |
625 | SVCPU_FIELD(SVCPU_R9, gpr[9]); | |
626 | SVCPU_FIELD(SVCPU_R10, gpr[10]); | |
627 | SVCPU_FIELD(SVCPU_R11, gpr[11]); | |
628 | SVCPU_FIELD(SVCPU_R12, gpr[12]); | |
629 | SVCPU_FIELD(SVCPU_R13, gpr[13]); | |
630 | SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr); | |
631 | SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar); | |
632 | SVCPU_FIELD(SVCPU_LAST_INST, last_inst); | |
633 | SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1); | |
0604675f | 634 | #ifdef CONFIG_PPC_BOOK3S_32 |
3c42bf8a | 635 | SVCPU_FIELD(SVCPU_SR, sr); |
0604675f | 636 | #endif |
3c42bf8a PM |
637 | #ifdef CONFIG_PPC64 |
638 | SVCPU_FIELD(SVCPU_SLB, slb); | |
639 | SVCPU_FIELD(SVCPU_SLB_MAX, slb_max); | |
616dff86 | 640 | SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr); |
3c42bf8a PM |
641 | #endif |
642 | ||
643 | HSTATE_FIELD(HSTATE_HOST_R1, host_r1); | |
644 | HSTATE_FIELD(HSTATE_HOST_R2, host_r2); | |
de56a948 | 645 | HSTATE_FIELD(HSTATE_HOST_MSR, host_msr); |
3c42bf8a PM |
646 | HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler); |
647 | HSTATE_FIELD(HSTATE_SCRATCH0, scratch0); | |
648 | HSTATE_FIELD(HSTATE_SCRATCH1, scratch1); | |
36e7bb38 | 649 | HSTATE_FIELD(HSTATE_SCRATCH2, scratch2); |
3c42bf8a | 650 | HSTATE_FIELD(HSTATE_IN_GUEST, in_guest); |
02143947 | 651 | HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5); |
19ccb76a | 652 | HSTATE_FIELD(HSTATE_NAPPING, napping); |
3c42bf8a | 653 | |
9975f5e3 | 654 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
7657f408 PM |
655 | HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req); |
656 | HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state); | |
de56a948 | 657 | HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu); |
371fefd6 PM |
658 | HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore); |
659 | HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys); | |
5af50993 BH |
660 | HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys); |
661 | HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt); | |
54695c30 BH |
662 | HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr); |
663 | HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi); | |
e0b7ec05 | 664 | HSTATE_FIELD(HSTATE_PTID, ptid); |
c0101509 | 665 | HSTATE_FIELD(HSTATE_TID, tid); |
4bb3c7a0 | 666 | HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend); |
9a4fc4ea ME |
667 | HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]); |
668 | HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]); | |
669 | HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]); | |
670 | HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]); | |
671 | HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]); | |
672 | HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]); | |
673 | HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]); | |
674 | HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]); | |
675 | HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]); | |
676 | HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]); | |
677 | HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]); | |
678 | HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]); | |
679 | HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]); | |
de56a948 PM |
680 | HSTATE_FIELD(HSTATE_PURR, host_purr); |
681 | HSTATE_FIELD(HSTATE_SPURR, host_spurr); | |
682 | HSTATE_FIELD(HSTATE_DSCR, host_dscr); | |
683 | HSTATE_FIELD(HSTATE_DABR, dabr); | |
684 | HSTATE_FIELD(HSTATE_DECEXP, dec_expires); | |
b4deba5c | 685 | HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode); |
19ccb76a | 686 | DEFINE(IPI_PRIORITY, IPI_PRIORITY); |
45465615 RG |
687 | OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr); |
688 | OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar); | |
689 | OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar); | |
690 | OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap); | |
691 | OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped); | |
c0101509 PM |
692 | OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set); |
693 | OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore); | |
9975f5e3 | 694 | #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */ |
de56a948 | 695 | |
0acb9111 PM |
696 | #ifdef CONFIG_PPC_BOOK3S_64 |
697 | HSTATE_FIELD(HSTATE_CFAR, cfar); | |
4b8473c9 | 698 | HSTATE_FIELD(HSTATE_PPR, ppr); |
616dff86 | 699 | HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr); |
0acb9111 PM |
700 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
701 | ||
3c42bf8a | 702 | #else /* CONFIG_PPC_BOOK3S */ |
fd0944ba | 703 | OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr); |
173c520a SG |
704 | OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer); |
705 | OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link); | |
706 | OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr); | |
707 | OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip); | |
45465615 RG |
708 | OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9); |
709 | OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst); | |
710 | OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear); | |
711 | OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr); | |
712 | OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save); | |
00c3a37c | 713 | #endif /* CONFIG_PPC_BOOK3S */ |
3c42bf8a | 714 | #endif /* CONFIG_KVM */ |
d17051cb AG |
715 | |
716 | #ifdef CONFIG_KVM_GUEST | |
45465615 RG |
717 | OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1); |
718 | OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2); | |
719 | OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3); | |
720 | OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending); | |
721 | OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr); | |
722 | OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical); | |
723 | OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr); | |
d17051cb AG |
724 | #endif |
725 | ||
ca9153a3 IY |
726 | #ifdef CONFIG_44x |
727 | DEFINE(PGD_T_LOG2, PGD_T_LOG2); | |
728 | DEFINE(PTE_T_LOG2, PTE_T_LOG2); | |
729 | #endif | |
55fd766b | 730 | #ifdef CONFIG_PPC_FSL_BOOK3E |
78f62237 | 731 | DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); |
45465615 RG |
732 | OFFSET(TLBCAM_MAS0, tlbcam, MAS0); |
733 | OFFSET(TLBCAM_MAS1, tlbcam, MAS1); | |
734 | OFFSET(TLBCAM_MAS2, tlbcam, MAS2); | |
735 | OFFSET(TLBCAM_MAS3, tlbcam, MAS3); | |
736 | OFFSET(TLBCAM_MAS7, tlbcam, MAS7); | |
78f62237 | 737 | #endif |
bbf45ba5 | 738 | |
4cd35f67 | 739 | #if defined(CONFIG_KVM) && defined(CONFIG_SPE) |
45465615 RG |
740 | OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]); |
741 | OFFSET(VCPU_ACC, kvm_vcpu, arch.acc); | |
742 | OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr); | |
743 | OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr); | |
4cd35f67 SW |
744 | #endif |
745 | ||
d30f6e48 | 746 | #ifdef CONFIG_KVM_BOOKE_HV |
45465615 RG |
747 | OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4); |
748 | OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6); | |
d30f6e48 SW |
749 | #endif |
750 | ||
5af50993 BH |
751 | #ifdef CONFIG_KVM_XICS |
752 | DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu, | |
753 | arch.xive_saved_state)); | |
754 | DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu, | |
755 | arch.xive_cam_word)); | |
756 | DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed)); | |
9b9b13a6 BH |
757 | DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on)); |
758 | DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr)); | |
759 | DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr)); | |
5af50993 BH |
760 | #endif |
761 | ||
73e75b41 | 762 | #ifdef CONFIG_KVM_EXIT_TIMING |
45465615 RG |
763 | OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu); |
764 | OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl); | |
765 | OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu); | |
766 | OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl); | |
73e75b41 HB |
767 | #endif |
768 | ||
7cba160a | 769 | #ifdef CONFIG_PPC_POWERNV |
45465615 RG |
770 | OFFSET(PACA_CORE_IDLE_STATE_PTR, paca_struct, core_idle_state_ptr); |
771 | OFFSET(PACA_THREAD_IDLE_STATE, paca_struct, thread_idle_state); | |
772 | OFFSET(PACA_THREAD_MASK, paca_struct, thread_mask); | |
773 | OFFSET(PACA_SUBCORE_SIBLING_MASK, paca_struct, subcore_sibling_mask); | |
22c6663d | 774 | OFFSET(PACA_REQ_PSSCR, paca_struct, requested_psscr); |
7672691a | 775 | OFFSET(PACA_DONT_STOP, paca_struct, dont_stop); |
e1c1cfed GS |
776 | #define STOP_SPR(x, f) OFFSET(x, paca_struct, stop_sprs.f) |
777 | STOP_SPR(STOP_PID, pid); | |
778 | STOP_SPR(STOP_LDBAR, ldbar); | |
779 | STOP_SPR(STOP_FSCR, fscr); | |
780 | STOP_SPR(STOP_HFSCR, hfscr); | |
781 | STOP_SPR(STOP_MMCR1, mmcr1); | |
782 | STOP_SPR(STOP_MMCR2, mmcr2); | |
783 | STOP_SPR(STOP_MMCRA, mmcra); | |
7cba160a SP |
784 | #endif |
785 | ||
66feed61 | 786 | DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER); |
a9af97aa | 787 | DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE); |
66feed61 | 788 | |
f86ef74e | 789 | #ifdef CONFIG_PPC_8xx |
9f595fd8 | 790 | DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE)); |
f86ef74e CL |
791 | #endif |
792 | ||
14cf11af PM |
793 | return 0; |
794 | } |