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powerpc/powernv: Recover correct PACA on wakeup from a stop on P9 DD1
[mirror_ubuntu-artful-kernel.git] / arch / powerpc / kernel / asm-offsets.c
CommitLineData
14cf11af
PM		 1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
14cf11af
PM		 16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
14cf11af
PM		 22#include <linux/mman.h>
23#include <linux/mm.h>
543b9fd3 24#include <linux/suspend.h>
ad7f7167 25#include <linux/hrtimer.h>
d1dead5c 26#ifdef CONFIG_PPC64
14cf11af
PM		 27#include <linux/time.h>
28#include <linux/hardirq.h>
d1dead5c 29#endif
d4d298fe 30#include <linux/kbuild.h>
d1dead5c 31
14cf11af
PM		 32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
14cf11af
PM		 36#include <asm/cputable.h>
37#include <asm/thread_info.h>
033ef338 38#include <asm/rtas.h>
a7f290da 39#include <asm/vdso_datapage.h>
66feed61 40#include <asm/dbell.h>
14cf11af
PM		 41#ifdef CONFIG_PPC64
42#include <asm/paca.h>
43#include <asm/lppaca.h>
14cf11af 44#include <asm/cache.h>
14cf11af 45#include <asm/compat.h>
11a27ad7 46#include <asm/mmu.h>
f04da0bc 47#include <asm/hvcall.h>
19ccb76a 48#include <asm/xics.h>
14cf11af 49#endif
ed79ba9e
BH		 50#ifdef CONFIG_PPC_POWERNV
51#include <asm/opal.h>
52#endif
989044ee 53#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
366d4b9b 54#include <linux/kvm_host.h>
0604675f 55#endif
989044ee
AG		 56#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
57#include <asm/kvm_book3s.h>
5deb8e7a 58#include <asm/kvm_ppc.h>
db93f574 59#endif
14cf11af 60
57e2a99f 61#ifdef CONFIG_PPC32
fca622c5
KG		 62#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
63#include "head_booke.h"
64#endif
57e2a99f 65#endif
fca622c5 66
55fd766b 67#if defined(CONFIG_PPC_FSL_BOOK3E)
19f5465e
TP		 68#include "../mm/mmu_decl.h"
69#endif
70
f86ef74e
CL		 71#ifdef CONFIG_PPC_8xx
72#include <asm/fixmap.h>
73#endif
74
10d4cf18
RG		 75#define STACK_PT_REGS_OFFSET(sym, val) \
76 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
77
14cf11af
PM		 78int main(void)
79{
45465615
RG		 80 OFFSET(THREAD, task_struct, thread);
81 OFFSET(MM, task_struct, mm);
82 OFFSET(MMCONTEXTID, mm_struct, context.id);
14cf11af 83#ifdef CONFIG_PPC64
9c1e1052
PM		 84 DEFINE(SIGSEGV, SIGSEGV);
85 DEFINE(NMI_MASK, NMI_MASK);
45465615 86 OFFSET(TASKTHREADPPR, task_struct, thread.ppr);
d1dead5c 87#else
45465615 88 OFFSET(THREAD_INFO, task_struct, stack);
cbc9565e 89 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
45465615 90 OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
d1dead5c
SR		 91#endif /* CONFIG_PPC64 */
92
85baa095 93#ifdef CONFIG_LIVEPATCH
45465615 94 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
85baa095
ME		 95#endif
96
45465615
RG		 97 OFFSET(KSP, thread_struct, ksp);
98 OFFSET(PT_REGS, thread_struct, regs);
1325a684 99#ifdef CONFIG_BOOKE
45465615 100 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
1325a684 101#endif
45465615
RG		 102 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
103 OFFSET(THREAD_FPSTATE, thread_struct, fp_state);
104 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
105 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
106 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
14cf11af 107#ifdef CONFIG_ALTIVEC
45465615
RG		 108 OFFSET(THREAD_VRSTATE, thread_struct, vr_state);
109 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
110 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
111 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
112 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
113 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
14cf11af 114#endif /* CONFIG_ALTIVEC */
c6e6771b 115#ifdef CONFIG_VSX
45465615 116 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
c6e6771b 117#endif /* CONFIG_VSX */
d1dead5c 118#ifdef CONFIG_PPC64
45465615 119 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
d1dead5c 120#else /* CONFIG_PPC64 */
45465615 121 OFFSET(PGDIR, thread_struct, pgdir);
14cf11af 122#ifdef CONFIG_SPE
45465615
RG		 123 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
124 OFFSET(THREAD_ACC, thread_struct, acc);
125 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
126 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
14cf11af 127#endif /* CONFIG_SPE */
d1dead5c 128#endif /* CONFIG_PPC64 */
13d543cd 129#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
45465615 130 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
13d543cd 131#endif
97e49255 132#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
45465615 133 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
97e49255 134#endif
ffe129ec 135#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
45465615 136 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
d30f6e48 137#endif
d1dead5c 138
8b3c34cf 139#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
45465615
RG		 140 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
141 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
142 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
143 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
144 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
145 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
146 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
147 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
148 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state);
149 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
150 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state);
8b3c34cf
MN		 151 /* Local pt_regs on stack for Transactional Memory funcs. */
152 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
153 sizeof(struct pt_regs) + 16);
154#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2468dcf6 155
45465615
RG		 156 OFFSET(TI_FLAGS, thread_info, flags);
157 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
158 OFFSET(TI_PREEMPT, thread_info, preempt_count);
159 OFFSET(TI_TASK, thread_info, task);
160 OFFSET(TI_CPU, thread_info, cpu);
d1dead5c
SR		 161
162#ifdef CONFIG_PPC64
45465615
RG		 163 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
164 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
165 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
166 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
167 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
168 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
d1dead5c
SR		 169 /* paca */
170 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
45465615
RG		 171 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
172 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
173 OFFSET(PACAKSAVE, paca_struct, kstack);
174 OFFSET(PACACURRENT, paca_struct, __current);
175 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
176 OFFSET(PACASTABRR, paca_struct, stab_rr);
177 OFFSET(PACAR1, paca_struct, saved_r1);
178 OFFSET(PACATOC, paca_struct, kernel_toc);
179 OFFSET(PACAKBASE, paca_struct, kernelbase);
180 OFFSET(PACAKMSR, paca_struct, kernel_msr);
181 OFFSET(PACASOFTIRQEN, paca_struct, soft_enabled);
182 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
c395465d 183#ifdef CONFIG_PPC_BOOK3S
45465615 184 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
d0f13e3c 185#ifdef CONFIG_PPC_MM_SLICES
45465615
RG		 186 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
187 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
bb183221 188 DEFINE(PACA_ADDR_LIMIT, offsetof(struct paca_struct, addr_limit));
d0f13e3c 189 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
91c60b5b 190#endif /* CONFIG_PPC_MM_SLICES */
c395465d 191#endif
dce6670a
BH		 192
193#ifdef CONFIG_PPC_BOOK3E
45465615
RG		 194 OFFSET(PACAPGD, paca_struct, pgd);
195 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
196 OFFSET(PACA_EXGEN, paca_struct, exgen);
197 OFFSET(PACA_EXTLB, paca_struct, extlb);
198 OFFSET(PACA_EXMC, paca_struct, exmc);
199 OFFSET(PACA_EXCRIT, paca_struct, excrit);
200 OFFSET(PACA_EXDBG, paca_struct, exdbg);
201 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
202 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
203 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
204 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
205
206 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
207 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
208 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
dce6670a
BH		 209#endif /* CONFIG_PPC_BOOK3E */
210
91c60b5b 211#ifdef CONFIG_PPC_STD_MMU_64
45465615
RG		 212 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
213 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
214 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
91c60b5b 215#ifdef CONFIG_PPC_MM_SLICES
45465615 216 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
d0f13e3c 217#else
45465615 218 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
d0f13e3c 219#endif /* CONFIG_PPC_MM_SLICES */
45465615
RG		 220 OFFSET(PACA_EXGEN, paca_struct, exgen);
221 OFFSET(PACA_EXMC, paca_struct, exmc);
222 OFFSET(PACA_EXSLB, paca_struct, exslb);
223 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
224 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
225 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
226 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
227 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
228 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
229 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
230 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
231 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
91c60b5b 232#endif /* CONFIG_PPC_STD_MMU_64 */
45465615 233 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
1e9b4507 234#ifdef CONFIG_PPC_BOOK3S_64
45465615
RG		 235 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
236 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
237#endif
238 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
239 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
240 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
241 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
242 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
b286cedd
LT		 243 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
244 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
45465615
RG		 245 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
246 OFFSET(PACA_NAPSTATELOST, paca_struct, nap_state_lost);
247 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
c223c903
CL		 248#else /* CONFIG_PPC64 */
249#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
45465615
RG		 250 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
251 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
b286cedd
LT		 252 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
253 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
c223c903 254#endif
033ef338 255#endif /* CONFIG_PPC64 */
d1dead5c
SR		 256
257 /* RTAS */
45465615
RG		 258 OFFSET(RTASBASE, rtas_t, base);
259 OFFSET(RTASENTRY, rtas_t, entry);
d1dead5c 260
14cf11af 261 /* Interrupt register frame */
91120cc8 262 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
14cf11af 263 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
218d169c 264#ifdef CONFIG_PPC64
d1dead5c
SR		 265 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
266 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
267 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
268#endif /* CONFIG_PPC64 */
10d4cf18
RG		 269 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
270 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
271 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
272 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
273 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
274 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
275 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
276 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
277 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
278 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
279 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
280 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
281 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
282 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
d1dead5c 283#ifndef CONFIG_PPC64
10d4cf18 284 STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
d1dead5c 285#endif /* CONFIG_PPC64 */
14cf11af
PM		 286 /*
287 * Note: these symbols include _ because they overlap with special
288 * register names
289 */
10d4cf18
RG		 290 STACK_PT_REGS_OFFSET(_NIP, nip);
291 STACK_PT_REGS_OFFSET(_MSR, msr);
292 STACK_PT_REGS_OFFSET(_CTR, ctr);
293 STACK_PT_REGS_OFFSET(_LINK, link);
294 STACK_PT_REGS_OFFSET(_CCR, ccr);
295 STACK_PT_REGS_OFFSET(_XER, xer);
296 STACK_PT_REGS_OFFSET(_DAR, dar);
297 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
298 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
299 STACK_PT_REGS_OFFSET(RESULT, result);
300 STACK_PT_REGS_OFFSET(_TRAP, trap);
d1dead5c 301#ifndef CONFIG_PPC64
d1dead5c
SR		 302 /*
303 * The PowerPC 400-class & Book-E processors have neither the DAR
304 * nor the DSISR SPRs. Hence, we overload them to hold the similar
305 * DEAR and ESR SPRs for such processors. For critical interrupts
306 * we use them to hold SRR0 and SRR1.
14cf11af 307 */
10d4cf18
RG		 308 STACK_PT_REGS_OFFSET(_DEAR, dar);
309 STACK_PT_REGS_OFFSET(_ESR, dsisr);
d1dead5c 310#else /* CONFIG_PPC64 */
10d4cf18 311 STACK_PT_REGS_OFFSET(SOFTE, softe);
d1dead5c
SR		 312
313 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
314 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
315 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
316#endif /* CONFIG_PPC64 */
317
57e2a99f 318#if defined(CONFIG_PPC32)
fca622c5
KG		 319#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
320 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
321 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
322 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
323 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
324 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
325 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
326 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
327 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
328 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
329 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
330 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
331 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
332 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
333 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
334 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
335 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
336#endif
57e2a99f 337#endif
d1dead5c
SR		 338
339#ifndef CONFIG_PPC64
45465615 340 OFFSET(MM_PGD, mm_struct, pgd);
d1dead5c 341#endif /* ! CONFIG_PPC64 */
14cf11af
PM		 342
343 /* About the CPU features table */
45465615
RG		 344 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
345 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
346 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
14cf11af 347
45465615
RG		 348 OFFSET(pbe_address, pbe, address);
349 OFFSET(pbe_orig_address, pbe, orig_address);
350 OFFSET(pbe_next, pbe, next);
14cf11af 351
543b9fd3 352#ifndef CONFIG_PPC64
fd582ec8 353 DEFINE(TASK_SIZE, TASK_SIZE);
d1dead5c 354 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
a7f290da 355#endif /* ! CONFIG_PPC64 */
14cf11af 356
a7f290da 357 /* datapage offsets for use by vdso */
45465615
RG		 358 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
359 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
360 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
361 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
362 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
363 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
364 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
365 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
366 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
367 OFFSET(STAMP_XTIME, vdso_data, stamp_xtime);
368 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
369 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
370 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
371 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
372 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
a7f290da 373#ifdef CONFIG_PPC64
45465615
RG		 374 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
375 OFFSET(TVAL64_TV_SEC, timeval, tv_sec);
376 OFFSET(TVAL64_TV_USEC, timeval, tv_usec);
377 OFFSET(TVAL32_TV_SEC, compat_timeval, tv_sec);
378 OFFSET(TVAL32_TV_USEC, compat_timeval, tv_usec);
379 OFFSET(TSPC64_TV_SEC, timespec, tv_sec);
380 OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec);
381 OFFSET(TSPC32_TV_SEC, compat_timespec, tv_sec);
382 OFFSET(TSPC32_TV_NSEC, compat_timespec, tv_nsec);
a7f290da 383#else
45465615
RG		 384 OFFSET(TVAL32_TV_SEC, timeval, tv_sec);
385 OFFSET(TVAL32_TV_USEC, timeval, tv_usec);
386 OFFSET(TSPC32_TV_SEC, timespec, tv_sec);
387 OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec);
a7f290da
BH		 388#endif
389 /* timeval/timezone offsets for use by vdso */
45465615
RG		 390 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
391 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
a7f290da
BH		 392
393 /* Other bits used by the vdso */
394 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
395 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
396 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
151db1fc 397 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
a7f290da 398
007d88d0
DW		 399#ifdef CONFIG_BUG
400 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
401#endif
16a15a30 402
dd1842a2
AK		 403#ifdef MAX_PGD_TABLE_SIZE
404 DEFINE(PGD_TABLE_SIZE, MAX_PGD_TABLE_SIZE);
405#else
ee7a76da 406 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
dd1842a2 407#endif
4ee7084e 408 DEFINE(PTE_SIZE, sizeof(pte_t));
bee86f14 409
bbf45ba5 410#ifdef CONFIG_KVM
45465615
RG		 411 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
412 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
413 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
414 OFFSET(VCPU_GPRS, kvm_vcpu, arch.gpr);
415 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
416 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
de56a948 417#ifdef CONFIG_ALTIVEC
45465615 418 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
de56a948 419#endif
45465615
RG		 420 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
421 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
422 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
e14e7a1e 423#ifdef CONFIG_PPC_BOOK3S
45465615 424 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
e14e7a1e 425#endif
45465615
RG		 426 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
427 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
9975f5e3 428#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
45465615
RG		 429 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
430 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
431 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
432 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
433 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
434 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
435 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
b6c295df
PM		 436#endif
437#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
45465615
RG		 438 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
439 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
440 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
441 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
442 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
443 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
444 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
445 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
446 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
447 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
448 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
449#endif
450 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
451 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
452 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
453 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
454 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
455 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
456 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
457 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
458 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
459 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
5deb8e7a 460#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
45465615 461 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
5deb8e7a 462#endif
bbf45ba5 463
45465615
RG		 464 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
465 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
466 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
467 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
468 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
469 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
b5904972 470
45465615
RG		 471 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
472 OFFSET(KVM_LPID, kvm, arch.lpid);
d30f6e48 473
00c3a37c 474 /* book3s */
9975f5e3 475#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
45465615
RG		 476 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
477 OFFSET(KVM_SDR1, kvm, arch.sdr1);
478 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
479 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
480 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
481 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
482 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
483 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
484 OFFSET(KVM_RADIX, kvm, arch.radix);
485 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
486 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
487 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
488 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
489 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
490 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
491 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
de56a948 492#endif
00c3a37c 493#ifdef CONFIG_PPC_BOOK3S
45465615
RG		 494 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
495 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
496 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
497 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
498 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
499 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
500 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
501 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
502 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
503 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
504 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
505 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
506 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
507 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
508 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
509 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
510 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
511 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
512 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
513 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
514 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
515 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
516 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
517 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
518 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
519 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
520 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
521 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
522 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
523 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
524 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
525 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
526 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
527 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
528 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
529 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
530 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
531 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
532 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
533 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
534 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
535 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
536 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
537 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
538 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
539 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
540 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
541 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
542 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
543 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
544 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
545 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
546 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
547 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
548 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
549 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
550 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
551 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
552 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
de56a948 553 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
7b490411 554#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
45465615
RG		 555 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
556 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
557 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
558 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
559 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
560 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
561 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
562 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
563 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
564 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
565 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
566 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
567 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
568 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
569 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
7b490411 570#endif
3c42bf8a
PM		 571
572#ifdef CONFIG_PPC_BOOK3S_64
7aa79938 573#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
45465615 574 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
3c42bf8a 575# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
de56a948
PM		 576#else
577# define SVCPU_FIELD(x, f)
578#endif
3c42bf8a
PM		 579# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
580#else /* 32-bit */
581# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
582# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
583#endif
584
585 SVCPU_FIELD(SVCPU_CR, cr);
586 SVCPU_FIELD(SVCPU_XER, xer);
587 SVCPU_FIELD(SVCPU_CTR, ctr);
588 SVCPU_FIELD(SVCPU_LR, lr);
589 SVCPU_FIELD(SVCPU_PC, pc);
590 SVCPU_FIELD(SVCPU_R0, gpr[0]);
591 SVCPU_FIELD(SVCPU_R1, gpr[1]);
592 SVCPU_FIELD(SVCPU_R2, gpr[2]);
593 SVCPU_FIELD(SVCPU_R3, gpr[3]);
594 SVCPU_FIELD(SVCPU_R4, gpr[4]);
595 SVCPU_FIELD(SVCPU_R5, gpr[5]);
596 SVCPU_FIELD(SVCPU_R6, gpr[6]);
597 SVCPU_FIELD(SVCPU_R7, gpr[7]);
598 SVCPU_FIELD(SVCPU_R8, gpr[8]);
599 SVCPU_FIELD(SVCPU_R9, gpr[9]);
600 SVCPU_FIELD(SVCPU_R10, gpr[10]);
601 SVCPU_FIELD(SVCPU_R11, gpr[11]);
602 SVCPU_FIELD(SVCPU_R12, gpr[12]);
603 SVCPU_FIELD(SVCPU_R13, gpr[13]);
604 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
605 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
606 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
607 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0604675f 608#ifdef CONFIG_PPC_BOOK3S_32
3c42bf8a 609 SVCPU_FIELD(SVCPU_SR, sr);
0604675f 610#endif
3c42bf8a
PM		 611#ifdef CONFIG_PPC64
612 SVCPU_FIELD(SVCPU_SLB, slb);
613 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
616dff86 614 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
3c42bf8a
PM		 615#endif
616
617 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
618 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
de56a948 619 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
3c42bf8a
PM		 620 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
621 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
622 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
36e7bb38 623 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
3c42bf8a 624 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
02143947 625 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
19ccb76a 626 HSTATE_FIELD(HSTATE_NAPPING, napping);
3c42bf8a 627
9975f5e3 628#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
7657f408
PM		 629 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
630 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
de56a948 631 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
371fefd6
PM		 632 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
633 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
54695c30
BH		 634 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
635 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
e0b7ec05 636 HSTATE_FIELD(HSTATE_PTID, ptid);
9a4fc4ea
ME		 637 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
638 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
639 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
640 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
641 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
642 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
643 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
644 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
645 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
646 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
647 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
648 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
649 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
de56a948
PM		 650 HSTATE_FIELD(HSTATE_PURR, host_purr);
651 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
652 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
653 HSTATE_FIELD(HSTATE_DABR, dabr);
654 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
b4deba5c 655 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
19ccb76a 656 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
45465615
RG		 657 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
658 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
659 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
660 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
661 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
9975f5e3 662#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
de56a948 663
0acb9111
PM		 664#ifdef CONFIG_PPC_BOOK3S_64
665 HSTATE_FIELD(HSTATE_CFAR, cfar);
4b8473c9 666 HSTATE_FIELD(HSTATE_PPR, ppr);
616dff86 667 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
0acb9111
PM		 668#endif /* CONFIG_PPC_BOOK3S_64 */
669
3c42bf8a 670#else /* CONFIG_PPC_BOOK3S */
45465615
RG		 671 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
672 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
673 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
674 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
675 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
676 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
677 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
678 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
679 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
680 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
00c3a37c 681#endif /* CONFIG_PPC_BOOK3S */
3c42bf8a 682#endif /* CONFIG_KVM */
d17051cb
AG		 683
684#ifdef CONFIG_KVM_GUEST
45465615
RG		 685 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
686 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
687 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
688 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
689 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
690 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
691 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
d17051cb
AG		 692#endif
693
ca9153a3
IY		 694#ifdef CONFIG_44x
695 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
696 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
697#endif
55fd766b 698#ifdef CONFIG_PPC_FSL_BOOK3E
78f62237 699 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
45465615
RG		 700 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
701 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
702 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
703 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
704 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
78f62237 705#endif
bbf45ba5 706
4cd35f67 707#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
45465615
RG		 708 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
709 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
710 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
711 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
4cd35f67
SW		 712#endif
713
d30f6e48 714#ifdef CONFIG_KVM_BOOKE_HV
45465615
RG		 715 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
716 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
d30f6e48
SW		 717#endif
718
73e75b41 719#ifdef CONFIG_KVM_EXIT_TIMING
45465615
RG		 720 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
721 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
722 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
723 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
73e75b41
HB		 724#endif
725
7cba160a 726#ifdef CONFIG_PPC_POWERNV
45465615
RG		 727 OFFSET(PACA_CORE_IDLE_STATE_PTR, paca_struct, core_idle_state_ptr);
728 OFFSET(PACA_THREAD_IDLE_STATE, paca_struct, thread_idle_state);
729 OFFSET(PACA_THREAD_MASK, paca_struct, thread_mask);
730 OFFSET(PACA_SUBCORE_SIBLING_MASK, paca_struct, subcore_sibling_mask);
17ed4c8f 731 OFFSET(PACA_SIBLING_PACA_PTRS, paca_struct, thread_sibling_pacas);
7cba160a
SP		 732#endif
733
66feed61
PM		 734 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
735
f86ef74e 736#ifdef CONFIG_PPC_8xx
9f595fd8 737 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
f86ef74e
CL		 738#endif
739
14cf11af
PM		 740 return 0;
741}
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