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treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152
[mirror_ubuntu-focal-kernel.git] / arch / powerpc / kernel / asm-offsets.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
14cf11af
PM		 2/*
3 * This program is used to generate definitions needed by
4 * assembly language modules.
5 *
6 * We use the technique used in the OSF Mach kernel code:
7 * generate asm statements containing #defines,
8 * compile this file to assembler, and then extract the
9 * #defines from the assembly-language output.
14cf11af
PM		 10 */
11
ed1cd6de
CL		 12#define GENERATING_ASM_OFFSETS /* asm/smp.h */
13
0d55303c 14#include <linux/compat.h>
14cf11af
PM		 15#include <linux/signal.h>
16#include <linux/sched.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20#include <linux/types.h>
14cf11af
PM		 21#include <linux/mman.h>
22#include <linux/mm.h>
543b9fd3 23#include <linux/suspend.h>
ad7f7167 24#include <linux/hrtimer.h>
d1dead5c 25#ifdef CONFIG_PPC64
14cf11af
PM		 26#include <linux/time.h>
27#include <linux/hardirq.h>
d1dead5c 28#endif
d4d298fe 29#include <linux/kbuild.h>
d1dead5c 30
14cf11af
PM		 31#include <asm/io.h>
32#include <asm/page.h>
33#include <asm/pgtable.h>
34#include <asm/processor.h>
14cf11af
PM		 35#include <asm/cputable.h>
36#include <asm/thread_info.h>
033ef338 37#include <asm/rtas.h>
a7f290da 38#include <asm/vdso_datapage.h>
66feed61 39#include <asm/dbell.h>
14cf11af
PM		 40#ifdef CONFIG_PPC64
41#include <asm/paca.h>
42#include <asm/lppaca.h>
14cf11af 43#include <asm/cache.h>
11a27ad7 44#include <asm/mmu.h>
f04da0bc 45#include <asm/hvcall.h>
19ccb76a 46#include <asm/xics.h>
14cf11af 47#endif
ed79ba9e
BH		 48#ifdef CONFIG_PPC_POWERNV
49#include <asm/opal.h>
50#endif
989044ee 51#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
366d4b9b 52#include <linux/kvm_host.h>
0604675f 53#endif
989044ee
AG		 54#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
55#include <asm/kvm_book3s.h>
5deb8e7a 56#include <asm/kvm_ppc.h>
db93f574 57#endif
14cf11af 58
57e2a99f 59#ifdef CONFIG_PPC32
fca622c5
KG		 60#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
61#include "head_booke.h"
62#endif
57e2a99f 63#endif
fca622c5 64
55fd766b 65#if defined(CONFIG_PPC_FSL_BOOK3E)
19f5465e
TP		 66#include "../mm/mmu_decl.h"
67#endif
68
f86ef74e
CL		 69#ifdef CONFIG_PPC_8xx
70#include <asm/fixmap.h>
71#endif
72
10d4cf18
RG		 73#define STACK_PT_REGS_OFFSET(sym, val) \
74 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
75
14cf11af
PM		 76int main(void)
77{
45465615
RG		 78 OFFSET(THREAD, task_struct, thread);
79 OFFSET(MM, task_struct, mm);
c3ff2a51
CL		 80#ifdef CONFIG_STACKPROTECTOR
81 OFFSET(TASK_CANARY, task_struct, stack_canary);
06ec27ae
CL		 82#ifdef CONFIG_PPC64
83 OFFSET(PACA_CANARY, paca_struct, canary);
84#endif
c3ff2a51 85#endif
45465615 86 OFFSET(MMCONTEXTID, mm_struct, context.id);
14cf11af 87#ifdef CONFIG_PPC64
9c1e1052
PM		 88 DEFINE(SIGSEGV, SIGSEGV);
89 DEFINE(NMI_MASK, NMI_MASK);
d1dead5c 90#else
45465615 91 OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
0df977ea
CL		 92#ifdef CONFIG_PPC_RTAS
93 OFFSET(RTAS_SP, thread_struct, rtas_sp);
94#endif
d1dead5c 95#endif /* CONFIG_PPC64 */
8c1fc5ab 96 OFFSET(TASK_STACK, task_struct, stack);
ed1cd6de 97#ifdef CONFIG_SMP
f7354cca 98 OFFSET(TASK_CPU, task_struct, cpu);
ed1cd6de 99#endif
d1dead5c 100
85baa095 101#ifdef CONFIG_LIVEPATCH
45465615 102 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
85baa095
ME		 103#endif
104
45465615
RG		 105 OFFSET(KSP, thread_struct, ksp);
106 OFFSET(PT_REGS, thread_struct, regs);
1325a684 107#ifdef CONFIG_BOOKE
45465615 108 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
1325a684 109#endif
45465615 110 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
aa9a9516 111 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
45465615
RG		 112 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
113 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
114 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
14cf11af 115#ifdef CONFIG_ALTIVEC
aa9a9516 116 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
45465615
RG		 117 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
118 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
119 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
120 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
121 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
14cf11af 122#endif /* CONFIG_ALTIVEC */
c6e6771b 123#ifdef CONFIG_VSX
45465615 124 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
c6e6771b 125#endif /* CONFIG_VSX */
d1dead5c 126#ifdef CONFIG_PPC64
45465615 127 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
d1dead5c 128#else /* CONFIG_PPC64 */
45465615 129 OFFSET(PGDIR, thread_struct, pgdir);
14cf11af 130#ifdef CONFIG_SPE
45465615
RG		 131 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
132 OFFSET(THREAD_ACC, thread_struct, acc);
133 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
134 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
14cf11af 135#endif /* CONFIG_SPE */
d1dead5c 136#endif /* CONFIG_PPC64 */
13d543cd 137#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
45465615 138 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
13d543cd 139#endif
97e49255 140#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
45465615 141 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
97e49255 142#endif
ffe129ec 143#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
45465615 144 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
d30f6e48 145#endif
a68c31fc
CL		 146#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
147 OFFSET(KUAP, thread_struct, kuap);
148#endif
d1dead5c 149
8b3c34cf 150#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
45465615
RG		 151 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
152 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
153 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
154 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
155 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
156 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
157 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
158 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
aa9a9516 159 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
45465615 160 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
aa9a9516 161 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
8b3c34cf
MN		 162 /* Local pt_regs on stack for Transactional Memory funcs. */
163 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
164 sizeof(struct pt_regs) + 16);
165#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2468dcf6 166
45465615
RG		 167 OFFSET(TI_FLAGS, thread_info, flags);
168 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
169 OFFSET(TI_PREEMPT, thread_info, preempt_count);
d1dead5c
SR		 170
171#ifdef CONFIG_PPC64
45465615
RG		 172 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
173 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
174 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
175 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
176 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
177 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
d1dead5c
SR		 178 /* paca */
179 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
45465615
RG		 180 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
181 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
182 OFFSET(PACAKSAVE, paca_struct, kstack);
183 OFFSET(PACACURRENT, paca_struct, __current);
c911d2e1
CL		 184 DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
185 offsetof(struct task_struct, thread_info));
45465615 186 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
45465615
RG		 187 OFFSET(PACAR1, paca_struct, saved_r1);
188 OFFSET(PACATOC, paca_struct, kernel_toc);
189 OFFSET(PACAKBASE, paca_struct, kernelbase);
190 OFFSET(PACAKMSR, paca_struct, kernel_msr);
4e26bc4a 191 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
45465615 192 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
ea678ac6 193 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
c395465d 194#ifdef CONFIG_PPC_BOOK3S
45465615 195 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
d0f13e3c 196#ifdef CONFIG_PPC_MM_SLICES
45465615
RG		 197 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
198 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
4722476b 199 OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit);
d0f13e3c 200 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
91c60b5b 201#endif /* CONFIG_PPC_MM_SLICES */
c395465d 202#endif
dce6670a
BH		 203
204#ifdef CONFIG_PPC_BOOK3E
45465615
RG		 205 OFFSET(PACAPGD, paca_struct, pgd);
206 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
207 OFFSET(PACA_EXGEN, paca_struct, exgen);
208 OFFSET(PACA_EXTLB, paca_struct, extlb);
209 OFFSET(PACA_EXMC, paca_struct, exmc);
210 OFFSET(PACA_EXCRIT, paca_struct, excrit);
211 OFFSET(PACA_EXDBG, paca_struct, exdbg);
212 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
213 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
214 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
215 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
216
217 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
218 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
219 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
dce6670a
BH		 220#endif /* CONFIG_PPC_BOOK3E */
221
4e003747 222#ifdef CONFIG_PPC_BOOK3S_64
45465615
RG		 223 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
224 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
126b11b2 225 OFFSET(PACASTABRR, paca_struct, stab_rr);
45465615 226 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
91c60b5b 227#ifdef CONFIG_PPC_MM_SLICES
45465615 228 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
d0f13e3c 229#else
45465615 230 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
d0f13e3c 231#endif /* CONFIG_PPC_MM_SLICES */
45465615
RG		 232 OFFSET(PACA_EXGEN, paca_struct, exgen);
233 OFFSET(PACA_EXMC, paca_struct, exmc);
234 OFFSET(PACA_EXSLB, paca_struct, exslb);
a3d96f70 235 OFFSET(PACA_EXNMI, paca_struct, exnmi);
8e0b634b 236#ifdef CONFIG_PPC_PSERIES
45465615 237 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
8e0b634b 238#endif
45465615
RG		 239 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
240 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
241 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
242 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
243 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
8e0b634b
NP		 244#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
245 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
246#endif
45465615
RG		 247 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
248 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
249 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
4e003747 250#endif /* CONFIG_PPC_BOOK3S_64 */
45465615 251 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
1e9b4507 252#ifdef CONFIG_PPC_BOOK3S_64
45465615 253 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
b1ee8a3d 254 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
45465615 255 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
c4f3b52c 256 OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
aa8a5e00
ME		 257 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
258 OFFSET(PACA_EXRFI, paca_struct, exrfi);
bdcb1aef 259 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
aa8a5e00 260
45465615
RG		 261#endif
262 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
263 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
264 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
265 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
266 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
b286cedd
LT		 267 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
268 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
45465615 269 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
45465615 270 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
c223c903
CL		 271#else /* CONFIG_PPC64 */
272#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
45465615
RG		 273 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
274 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
b286cedd
LT		 275 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
276 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
c223c903 277#endif
033ef338 278#endif /* CONFIG_PPC64 */
d1dead5c
SR		 279
280 /* RTAS */
45465615
RG		 281 OFFSET(RTASBASE, rtas_t, base);
282 OFFSET(RTASENTRY, rtas_t, entry);
d1dead5c 283
14cf11af 284 /* Interrupt register frame */
91120cc8 285 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
14cf11af 286 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
10d4cf18
RG		 287 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
288 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
289 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
290 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
291 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
292 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
293 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
294 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
295 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
296 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
297 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
298 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
299 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
300 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
d1dead5c 301#ifndef CONFIG_PPC64
10d4cf18 302 STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
d1dead5c 303#endif /* CONFIG_PPC64 */
14cf11af
PM		 304 /*
305 * Note: these symbols include _ because they overlap with special
306 * register names
307 */
10d4cf18
RG		 308 STACK_PT_REGS_OFFSET(_NIP, nip);
309 STACK_PT_REGS_OFFSET(_MSR, msr);
310 STACK_PT_REGS_OFFSET(_CTR, ctr);
311 STACK_PT_REGS_OFFSET(_LINK, link);
312 STACK_PT_REGS_OFFSET(_CCR, ccr);
313 STACK_PT_REGS_OFFSET(_XER, xer);
314 STACK_PT_REGS_OFFSET(_DAR, dar);
315 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
316 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
317 STACK_PT_REGS_OFFSET(RESULT, result);
318 STACK_PT_REGS_OFFSET(_TRAP, trap);
d1dead5c 319#ifndef CONFIG_PPC64
d1dead5c
SR		 320 /*
321 * The PowerPC 400-class & Book-E processors have neither the DAR
322 * nor the DSISR SPRs. Hence, we overload them to hold the similar
323 * DEAR and ESR SPRs for such processors. For critical interrupts
324 * we use them to hold SRR0 and SRR1.
14cf11af 325 */
10d4cf18
RG		 326 STACK_PT_REGS_OFFSET(_DEAR, dar);
327 STACK_PT_REGS_OFFSET(_ESR, dsisr);
d1dead5c 328#else /* CONFIG_PPC64 */
10d4cf18 329 STACK_PT_REGS_OFFSET(SOFTE, softe);
4c2de74c 330 STACK_PT_REGS_OFFSET(_PPR, ppr);
d1dead5c
SR		 331#endif /* CONFIG_PPC64 */
332
de78a9c4
CL		 333#ifdef CONFIG_PPC_KUAP
334 STACK_PT_REGS_OFFSET(STACK_REGS_KUAP, kuap);
335#endif
336
57e2a99f 337#if defined(CONFIG_PPC32)
fca622c5
KG		 338#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
339 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
340 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
341 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
342 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
343 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
344 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
345 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
346 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
347 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
348 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
349 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
350 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
351 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
352 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
353 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
354 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
355#endif
57e2a99f 356#endif
d1dead5c
SR		 357
358#ifndef CONFIG_PPC64
45465615 359 OFFSET(MM_PGD, mm_struct, pgd);
d1dead5c 360#endif /* ! CONFIG_PPC64 */
14cf11af
PM		 361
362 /* About the CPU features table */
45465615
RG		 363 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
364 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
365 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
14cf11af 366
45465615
RG		 367 OFFSET(pbe_address, pbe, address);
368 OFFSET(pbe_orig_address, pbe, orig_address);
369 OFFSET(pbe_next, pbe, next);
14cf11af 370
543b9fd3 371#ifndef CONFIG_PPC64
fd582ec8 372 DEFINE(TASK_SIZE, TASK_SIZE);
d1dead5c 373 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
a7f290da 374#endif /* ! CONFIG_PPC64 */
14cf11af 375
a7f290da 376 /* datapage offsets for use by vdso */
45465615
RG		 377 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
378 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
379 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
380 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
381 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
382 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
383 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
384 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
385 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
386 OFFSET(STAMP_XTIME, vdso_data, stamp_xtime);
387 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
388 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
389 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
390 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
391 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
a7f290da 392#ifdef CONFIG_PPC64
45465615
RG		 393 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
394 OFFSET(TVAL64_TV_SEC, timeval, tv_sec);
395 OFFSET(TVAL64_TV_USEC, timeval, tv_usec);
9afc5eee
AB		 396 OFFSET(TVAL32_TV_SEC, old_timeval32, tv_sec);
397 OFFSET(TVAL32_TV_USEC, old_timeval32, tv_usec);
45465615
RG		 398 OFFSET(TSPC64_TV_SEC, timespec, tv_sec);
399 OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec);
9afc5eee
AB		 400 OFFSET(TSPC32_TV_SEC, old_timespec32, tv_sec);
401 OFFSET(TSPC32_TV_NSEC, old_timespec32, tv_nsec);
a7f290da 402#else
45465615
RG		 403 OFFSET(TVAL32_TV_SEC, timeval, tv_sec);
404 OFFSET(TVAL32_TV_USEC, timeval, tv_usec);
405 OFFSET(TSPC32_TV_SEC, timespec, tv_sec);
406 OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec);
a7f290da
BH		 407#endif
408 /* timeval/timezone offsets for use by vdso */
45465615
RG		 409 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
410 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
a7f290da
BH		 411
412 /* Other bits used by the vdso */
413 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
414 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
5c929885
SS		 415 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
416 DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE);
a7f290da 417 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
151db1fc 418 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
a7f290da 419
007d88d0
DW		 420#ifdef CONFIG_BUG
421 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
422#endif
16a15a30 423
03dfee6d
ME		 424#ifdef CONFIG_PPC_BOOK3S_64
425 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE)));
dd1842a2 426#else
ee7a76da 427 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
dd1842a2 428#endif
4ee7084e 429 DEFINE(PTE_SIZE, sizeof(pte_t));
bee86f14 430
bbf45ba5 431#ifdef CONFIG_KVM
45465615
RG		 432 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
433 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
434 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
1143a706 435 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
45465615
RG		 436 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
437 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
de56a948 438#ifdef CONFIG_ALTIVEC
45465615 439 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
de56a948 440#endif
173c520a
SG		 441 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
442 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
443 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
e14e7a1e 444#ifdef CONFIG_PPC_BOOK3S
45465615 445 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
e14e7a1e 446#endif
fd0944ba 447 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
173c520a 448 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
9975f5e3 449#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
45465615
RG		 450 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
451 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
452 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
453 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
454 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
455 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
456 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
b6c295df
PM		 457#endif
458#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
45465615
RG		 459 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
460 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
461 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
462 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
463 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
464 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
465 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
466 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
467 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
468 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
469 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
470#endif
471 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
472 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
473 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
474 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
475 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
476 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
477 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
478 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
479 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
480 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
5deb8e7a 481#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
45465615 482 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
5deb8e7a 483#endif
bbf45ba5 484
45465615
RG		 485 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
486 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
487 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
488 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
489 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
490 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
b5904972 491
45465615
RG		 492 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
493 OFFSET(KVM_LPID, kvm, arch.lpid);
d30f6e48 494
00c3a37c 495 /* book3s */
9975f5e3 496#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
45465615
RG		 497 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
498 OFFSET(KVM_SDR1, kvm, arch.sdr1);
499 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
500 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
501 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
502 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
503 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
504 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
505 OFFSET(KVM_RADIX, kvm, arch.radix);
134764ed 506 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled);
45465615
RG		 507 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
508 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
509 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
510 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
511 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
360cae31 512 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested);
45465615
RG		 513 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
514 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
de56a948 515#endif
00c3a37c 516#ifdef CONFIG_PPC_BOOK3S
45465615
RG		 517 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
518 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
519 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
520 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
521 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
522 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
523 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
524 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
525 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
526 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
527 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
528 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
529 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
530 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
531 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
532 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
533 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
534 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
535 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
2267ea76 536 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
57900694 537 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
45465615
RG		 538 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
539 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
540 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
541 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
542 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
543 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
544 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
545 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
546 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
547 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
548 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
549 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
550 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
551 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
552 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
553 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
554 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
555 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
556 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
557 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
558 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
559 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
560 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
561 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
562 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
563 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
564 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
565 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
566 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
769377f7 567 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
45465615
RG		 568 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
569 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
570 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
571 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
572 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
57b8daa7 573 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
45465615
RG		 574 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
575 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
576 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
577 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
578 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
579 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
de56a948 580 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
7b490411 581#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
45465615
RG		 582 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
583 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
584 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
4bb3c7a0 585 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
45465615
RG		 586 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
587 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
588 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
589 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
590 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
591 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
592 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
593 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
594 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
595 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
596 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
597 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
7b490411 598#endif
3c42bf8a
PM		 599
600#ifdef CONFIG_PPC_BOOK3S_64
7aa79938 601#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
45465615 602 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
3c42bf8a 603# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
de56a948
PM		 604#else
605# define SVCPU_FIELD(x, f)
606#endif
3c42bf8a
PM		 607# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
608#else /* 32-bit */
609# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
610# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
611#endif
612
613 SVCPU_FIELD(SVCPU_CR, cr);
614 SVCPU_FIELD(SVCPU_XER, xer);
615 SVCPU_FIELD(SVCPU_CTR, ctr);
616 SVCPU_FIELD(SVCPU_LR, lr);
617 SVCPU_FIELD(SVCPU_PC, pc);
618 SVCPU_FIELD(SVCPU_R0, gpr[0]);
619 SVCPU_FIELD(SVCPU_R1, gpr[1]);
620 SVCPU_FIELD(SVCPU_R2, gpr[2]);
621 SVCPU_FIELD(SVCPU_R3, gpr[3]);
622 SVCPU_FIELD(SVCPU_R4, gpr[4]);
623 SVCPU_FIELD(SVCPU_R5, gpr[5]);
624 SVCPU_FIELD(SVCPU_R6, gpr[6]);
625 SVCPU_FIELD(SVCPU_R7, gpr[7]);
626 SVCPU_FIELD(SVCPU_R8, gpr[8]);
627 SVCPU_FIELD(SVCPU_R9, gpr[9]);
628 SVCPU_FIELD(SVCPU_R10, gpr[10]);
629 SVCPU_FIELD(SVCPU_R11, gpr[11]);
630 SVCPU_FIELD(SVCPU_R12, gpr[12]);
631 SVCPU_FIELD(SVCPU_R13, gpr[13]);
632 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
633 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
634 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
635 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0604675f 636#ifdef CONFIG_PPC_BOOK3S_32
3c42bf8a 637 SVCPU_FIELD(SVCPU_SR, sr);
0604675f 638#endif
3c42bf8a
PM		 639#ifdef CONFIG_PPC64
640 SVCPU_FIELD(SVCPU_SLB, slb);
641 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
616dff86 642 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
3c42bf8a
PM		 643#endif
644
645 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
646 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
de56a948 647 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
3c42bf8a
PM		 648 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
649 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
650 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
36e7bb38 651 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
3c42bf8a 652 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
02143947 653 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
19ccb76a 654 HSTATE_FIELD(HSTATE_NAPPING, napping);
3c42bf8a 655
9975f5e3 656#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
7657f408
PM		 657 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
658 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
de56a948 659 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
371fefd6
PM		 660 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
661 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
5af50993
BH		 662 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
663 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
54695c30
BH		 664 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
665 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
e0b7ec05 666 HSTATE_FIELD(HSTATE_PTID, ptid);
c0101509 667 HSTATE_FIELD(HSTATE_TID, tid);
4bb3c7a0 668 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
9a4fc4ea
ME		 669 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
670 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
671 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
672 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
673 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
674 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
675 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
676 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
677 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
678 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
679 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
680 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
681 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
de56a948
PM		 682 HSTATE_FIELD(HSTATE_PURR, host_purr);
683 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
684 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
685 HSTATE_FIELD(HSTATE_DABR, dabr);
686 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
b4deba5c 687 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
19ccb76a 688 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
45465615
RG		 689 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
690 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
691 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
692 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
693 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
c0101509
PM		 694 OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set);
695 OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore);
9975f5e3 696#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
de56a948 697
0acb9111
PM		 698#ifdef CONFIG_PPC_BOOK3S_64
699 HSTATE_FIELD(HSTATE_CFAR, cfar);
4b8473c9 700 HSTATE_FIELD(HSTATE_PPR, ppr);
616dff86 701 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
0acb9111
PM		 702#endif /* CONFIG_PPC_BOOK3S_64 */
703
3c42bf8a 704#else /* CONFIG_PPC_BOOK3S */
fd0944ba 705 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
173c520a
SG		 706 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
707 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
708 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
709 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
45465615
RG		 710 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
711 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
712 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
713 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
714 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
00c3a37c 715#endif /* CONFIG_PPC_BOOK3S */
3c42bf8a 716#endif /* CONFIG_KVM */
d17051cb
AG		 717
718#ifdef CONFIG_KVM_GUEST
45465615
RG		 719 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
720 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
721 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
722 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
723 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
724 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
725 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
d17051cb
AG		 726#endif
727
ca9153a3
IY		 728#ifdef CONFIG_44x
729 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
730 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
731#endif
55fd766b 732#ifdef CONFIG_PPC_FSL_BOOK3E
78f62237 733 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
45465615
RG		 734 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
735 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
736 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
737 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
738 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
78f62237 739#endif
bbf45ba5 740
4cd35f67 741#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
45465615
RG		 742 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
743 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
744 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
745 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
4cd35f67
SW		 746#endif
747
d30f6e48 748#ifdef CONFIG_KVM_BOOKE_HV
45465615
RG		 749 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
750 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
d30f6e48
SW		 751#endif
752
5af50993
BH		 753#ifdef CONFIG_KVM_XICS
754 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
755 arch.xive_saved_state));
756 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
757 arch.xive_cam_word));
758 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
9b9b13a6
BH		 759 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
760 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
761 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
5af50993
BH		 762#endif
763
73e75b41 764#ifdef CONFIG_KVM_EXIT_TIMING
45465615
RG		 765 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
766 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
767 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
768 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
73e75b41
HB		 769#endif
770
66feed61 771 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
a9af97aa 772 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE);
66feed61 773
f86ef74e 774#ifdef CONFIG_PPC_8xx
9f595fd8 775 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
f86ef74e
CL		 776#endif
777
14cf11af
PM		 778 return 0;
779}
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