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Commit | Line | Data |
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14cf11af PM |
1 | /* |
2 | * This program is used to generate definitions needed by | |
3 | * assembly language modules. | |
4 | * | |
5 | * We use the technique used in the OSF Mach kernel code: | |
6 | * generate asm statements containing #defines, | |
7 | * compile this file to assembler, and then extract the | |
8 | * #defines from the assembly-language output. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
13 | * 2 of the License, or (at your option) any later version. | |
14 | */ | |
15 | ||
14cf11af PM |
16 | #include <linux/signal.h> |
17 | #include <linux/sched.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/errno.h> | |
20 | #include <linux/string.h> | |
21 | #include <linux/types.h> | |
14cf11af PM |
22 | #include <linux/mman.h> |
23 | #include <linux/mm.h> | |
543b9fd3 | 24 | #include <linux/suspend.h> |
ad7f7167 | 25 | #include <linux/hrtimer.h> |
d1dead5c | 26 | #ifdef CONFIG_PPC64 |
14cf11af PM |
27 | #include <linux/time.h> |
28 | #include <linux/hardirq.h> | |
d1dead5c | 29 | #endif |
d4d298fe | 30 | #include <linux/kbuild.h> |
d1dead5c | 31 | |
14cf11af PM |
32 | #include <asm/io.h> |
33 | #include <asm/page.h> | |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/processor.h> | |
14cf11af PM |
36 | #include <asm/cputable.h> |
37 | #include <asm/thread_info.h> | |
033ef338 | 38 | #include <asm/rtas.h> |
a7f290da | 39 | #include <asm/vdso_datapage.h> |
14cf11af PM |
40 | #ifdef CONFIG_PPC64 |
41 | #include <asm/paca.h> | |
42 | #include <asm/lppaca.h> | |
14cf11af | 43 | #include <asm/cache.h> |
14cf11af | 44 | #include <asm/compat.h> |
11a27ad7 | 45 | #include <asm/mmu.h> |
f04da0bc | 46 | #include <asm/hvcall.h> |
19ccb76a | 47 | #include <asm/xics.h> |
14cf11af | 48 | #endif |
ed79ba9e BH |
49 | #ifdef CONFIG_PPC_POWERNV |
50 | #include <asm/opal.h> | |
51 | #endif | |
989044ee | 52 | #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST) |
366d4b9b | 53 | #include <linux/kvm_host.h> |
0604675f | 54 | #endif |
989044ee AG |
55 | #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S) |
56 | #include <asm/kvm_book3s.h> | |
db93f574 | 57 | #endif |
14cf11af | 58 | |
57e2a99f | 59 | #ifdef CONFIG_PPC32 |
fca622c5 KG |
60 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
61 | #include "head_booke.h" | |
62 | #endif | |
57e2a99f | 63 | #endif |
fca622c5 | 64 | |
55fd766b | 65 | #if defined(CONFIG_PPC_FSL_BOOK3E) |
19f5465e TP |
66 | #include "../mm/mmu_decl.h" |
67 | #endif | |
68 | ||
14cf11af PM |
69 | int main(void) |
70 | { | |
d1dead5c SR |
71 | DEFINE(THREAD, offsetof(struct task_struct, thread)); |
72 | DEFINE(MM, offsetof(struct task_struct, mm)); | |
5e696617 | 73 | DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id)); |
14cf11af | 74 | #ifdef CONFIG_PPC64 |
d1dead5c | 75 | DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context)); |
9c1e1052 PM |
76 | DEFINE(SIGSEGV, SIGSEGV); |
77 | DEFINE(NMI_MASK, NMI_MASK); | |
efcac658 | 78 | DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr)); |
71433285 | 79 | DEFINE(THREAD_DSCR_INHERIT, offsetof(struct thread_struct, dscr_inherit)); |
92779245 | 80 | DEFINE(TASKTHREADPPR, offsetof(struct task_struct, thread.ppr)); |
d1dead5c | 81 | #else |
f7e4217b | 82 | DEFINE(THREAD_INFO, offsetof(struct task_struct, stack)); |
d1dead5c SR |
83 | #endif /* CONFIG_PPC64 */ |
84 | ||
14cf11af | 85 | DEFINE(KSP, offsetof(struct thread_struct, ksp)); |
85218827 | 86 | DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit)); |
14cf11af | 87 | DEFINE(PT_REGS, offsetof(struct thread_struct, regs)); |
1325a684 AK |
88 | #ifdef CONFIG_BOOKE |
89 | DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0])); | |
90 | #endif | |
14cf11af PM |
91 | DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode)); |
92 | DEFINE(THREAD_FPR0, offsetof(struct thread_struct, fpr[0])); | |
93 | DEFINE(THREAD_FPSCR, offsetof(struct thread_struct, fpscr)); | |
14cf11af PM |
94 | #ifdef CONFIG_ALTIVEC |
95 | DEFINE(THREAD_VR0, offsetof(struct thread_struct, vr[0])); | |
96 | DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave)); | |
97 | DEFINE(THREAD_VSCR, offsetof(struct thread_struct, vscr)); | |
98 | DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr)); | |
99 | #endif /* CONFIG_ALTIVEC */ | |
c6e6771b MN |
100 | #ifdef CONFIG_VSX |
101 | DEFINE(THREAD_VSR0, offsetof(struct thread_struct, fpr)); | |
102 | DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr)); | |
103 | #endif /* CONFIG_VSX */ | |
d1dead5c SR |
104 | #ifdef CONFIG_PPC64 |
105 | DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid)); | |
106 | #else /* CONFIG_PPC64 */ | |
107 | DEFINE(PGDIR, offsetof(struct thread_struct, pgdir)); | |
d1dead5c SR |
108 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
109 | DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0)); | |
d1dead5c | 110 | #endif |
14cf11af PM |
111 | #ifdef CONFIG_SPE |
112 | DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0])); | |
113 | DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc)); | |
114 | DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr)); | |
115 | DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe)); | |
116 | #endif /* CONFIG_SPE */ | |
d1dead5c | 117 | #endif /* CONFIG_PPC64 */ |
97e49255 AG |
118 | #ifdef CONFIG_KVM_BOOK3S_32_HANDLER |
119 | DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu)); | |
120 | #endif | |
d30f6e48 SW |
121 | #ifdef CONFIG_KVM_BOOKE_HV |
122 | DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, kvm_vcpu)); | |
123 | #endif | |
d1dead5c | 124 | |
2468dcf6 IM |
125 | #ifdef CONFIG_PPC_BOOK3S_64 |
126 | DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar)); | |
127 | #endif | |
8b3c34cf MN |
128 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
129 | DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar)); | |
130 | DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr)); | |
131 | DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar)); | |
132 | DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs)); | |
133 | DEFINE(THREAD_TRANSACT_VR0, offsetof(struct thread_struct, | |
134 | transact_vr[0])); | |
135 | DEFINE(THREAD_TRANSACT_VSCR, offsetof(struct thread_struct, | |
136 | transact_vscr)); | |
137 | DEFINE(THREAD_TRANSACT_VRSAVE, offsetof(struct thread_struct, | |
138 | transact_vrsave)); | |
139 | DEFINE(THREAD_TRANSACT_FPR0, offsetof(struct thread_struct, | |
140 | transact_fpr[0])); | |
141 | DEFINE(THREAD_TRANSACT_FPSCR, offsetof(struct thread_struct, | |
142 | transact_fpscr)); | |
143 | #ifdef CONFIG_VSX | |
144 | DEFINE(THREAD_TRANSACT_VSR0, offsetof(struct thread_struct, | |
145 | transact_fpr[0])); | |
146 | #endif | |
147 | /* Local pt_regs on stack for Transactional Memory funcs. */ | |
148 | DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD + | |
149 | sizeof(struct pt_regs) + 16); | |
150 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
2468dcf6 | 151 | |
d1dead5c | 152 | DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); |
f39224a8 | 153 | DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags)); |
d1dead5c | 154 | DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count)); |
d1dead5c | 155 | DEFINE(TI_TASK, offsetof(struct thread_info, task)); |
d1dead5c | 156 | DEFINE(TI_CPU, offsetof(struct thread_info, cpu)); |
d1dead5c SR |
157 | |
158 | #ifdef CONFIG_PPC64 | |
159 | DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size)); | |
160 | DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size)); | |
161 | DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page)); | |
162 | DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size)); | |
163 | DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size)); | |
164 | DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page)); | |
d1dead5c SR |
165 | /* paca */ |
166 | DEFINE(PACA_SIZE, sizeof(struct paca_struct)); | |
9e368f29 | 167 | DEFINE(PACA_LOCK_TOKEN, offsetof(struct paca_struct, lock_token)); |
d1dead5c SR |
168 | DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index)); |
169 | DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start)); | |
170 | DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack)); | |
171 | DEFINE(PACACURRENT, offsetof(struct paca_struct, __current)); | |
172 | DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr)); | |
d1dead5c SR |
173 | DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr)); |
174 | DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1)); | |
175 | DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc)); | |
1f6a93e4 PM |
176 | DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase)); |
177 | DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr)); | |
d04c56f7 | 178 | DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled)); |
7230c564 | 179 | DEFINE(PACAIRQHAPPENED, offsetof(struct paca_struct, irq_happened)); |
d1dead5c | 180 | DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id)); |
d0f13e3c BH |
181 | #ifdef CONFIG_PPC_MM_SLICES |
182 | DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct, | |
183 | context.low_slices_psize)); | |
184 | DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct, | |
185 | context.high_slices_psize)); | |
186 | DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def)); | |
91c60b5b | 187 | #endif /* CONFIG_PPC_MM_SLICES */ |
dce6670a BH |
188 | |
189 | #ifdef CONFIG_PPC_BOOK3E | |
190 | DEFINE(PACAPGD, offsetof(struct paca_struct, pgd)); | |
191 | DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd)); | |
192 | DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen)); | |
193 | DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb)); | |
194 | DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc)); | |
195 | DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit)); | |
196 | DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg)); | |
197 | DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack)); | |
198 | DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack)); | |
199 | DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack)); | |
200 | #endif /* CONFIG_PPC_BOOK3E */ | |
201 | ||
91c60b5b BH |
202 | #ifdef CONFIG_PPC_STD_MMU_64 |
203 | DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real)); | |
204 | DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr)); | |
205 | DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache)); | |
206 | DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr)); | |
207 | DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp)); | |
208 | #ifdef CONFIG_PPC_MM_SLICES | |
d0f13e3c BH |
209 | DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp)); |
210 | #else | |
211 | DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, context.sllp)); | |
d0f13e3c | 212 | #endif /* CONFIG_PPC_MM_SLICES */ |
d1dead5c SR |
213 | DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen)); |
214 | DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc)); | |
215 | DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb)); | |
3356bb9f | 216 | DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr)); |
2f6093c8 | 217 | DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr)); |
11a27ad7 MN |
218 | DEFINE(SLBSHADOW_STACKVSID, |
219 | offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid)); | |
220 | DEFINE(SLBSHADOW_STACKESID, | |
221 | offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid)); | |
cf9efce0 | 222 | DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area)); |
de56a948 | 223 | DEFINE(LPPACA_PMCINUSE, offsetof(struct lppaca, pmcregs_in_use)); |
cf9efce0 | 224 | DEFINE(LPPACA_DTLIDX, offsetof(struct lppaca, dtl_idx)); |
a8606e20 | 225 | DEFINE(LPPACA_YIELDCOUNT, offsetof(struct lppaca, yield_count)); |
cf9efce0 | 226 | DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx)); |
91c60b5b BH |
227 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
228 | DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp)); | |
229 | DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id)); | |
1fc711f7 | 230 | DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state)); |
cf9efce0 PM |
231 | DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime)); |
232 | DEFINE(PACA_STARTTIME_USER, offsetof(struct paca_struct, starttime_user)); | |
91c60b5b BH |
233 | DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time)); |
234 | DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time)); | |
91c60b5b | 235 | DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save)); |
2fde6d20 | 236 | DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost)); |
0127262c | 237 | DEFINE(PACA_SPRG3, offsetof(struct paca_struct, sprg3)); |
033ef338 | 238 | #endif /* CONFIG_PPC64 */ |
d1dead5c SR |
239 | |
240 | /* RTAS */ | |
241 | DEFINE(RTASBASE, offsetof(struct rtas_t, base)); | |
242 | DEFINE(RTASENTRY, offsetof(struct rtas_t, entry)); | |
d1dead5c | 243 | |
14cf11af | 244 | /* Interrupt register frame */ |
91120cc8 | 245 | DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE); |
14cf11af | 246 | DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs)); |
218d169c | 247 | #ifdef CONFIG_PPC64 |
d1dead5c SR |
248 | /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */ |
249 | DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); | |
250 | DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16); | |
57852a85 MK |
251 | |
252 | /* hcall statistics */ | |
253 | DEFINE(HCALL_STAT_SIZE, sizeof(struct hcall_stats)); | |
254 | DEFINE(HCALL_STAT_CALLS, offsetof(struct hcall_stats, num_calls)); | |
255 | DEFINE(HCALL_STAT_TB, offsetof(struct hcall_stats, tb_total)); | |
256 | DEFINE(HCALL_STAT_PURR, offsetof(struct hcall_stats, purr_total)); | |
d1dead5c | 257 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
258 | DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0])); |
259 | DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1])); | |
260 | DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2])); | |
261 | DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3])); | |
262 | DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4])); | |
263 | DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5])); | |
264 | DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6])); | |
265 | DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7])); | |
266 | DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8])); | |
267 | DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9])); | |
268 | DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10])); | |
269 | DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11])); | |
270 | DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12])); | |
271 | DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13])); | |
d1dead5c | 272 | #ifndef CONFIG_PPC64 |
14cf11af PM |
273 | DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14])); |
274 | DEFINE(GPR15, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[15])); | |
275 | DEFINE(GPR16, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[16])); | |
276 | DEFINE(GPR17, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[17])); | |
277 | DEFINE(GPR18, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[18])); | |
278 | DEFINE(GPR19, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[19])); | |
279 | DEFINE(GPR20, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[20])); | |
280 | DEFINE(GPR21, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[21])); | |
281 | DEFINE(GPR22, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[22])); | |
282 | DEFINE(GPR23, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[23])); | |
283 | DEFINE(GPR24, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[24])); | |
284 | DEFINE(GPR25, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[25])); | |
285 | DEFINE(GPR26, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[26])); | |
286 | DEFINE(GPR27, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[27])); | |
287 | DEFINE(GPR28, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[28])); | |
288 | DEFINE(GPR29, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[29])); | |
289 | DEFINE(GPR30, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[30])); | |
290 | DEFINE(GPR31, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[31])); | |
d1dead5c | 291 | #endif /* CONFIG_PPC64 */ |
14cf11af PM |
292 | /* |
293 | * Note: these symbols include _ because they overlap with special | |
294 | * register names | |
295 | */ | |
296 | DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip)); | |
297 | DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr)); | |
298 | DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr)); | |
299 | DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link)); | |
300 | DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr)); | |
14cf11af PM |
301 | DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer)); |
302 | DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); | |
303 | DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); | |
d1dead5c SR |
304 | DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3)); |
305 | DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result)); | |
d73e0c99 | 306 | DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap)); |
d1dead5c SR |
307 | #ifndef CONFIG_PPC64 |
308 | DEFINE(_MQ, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, mq)); | |
309 | /* | |
310 | * The PowerPC 400-class & Book-E processors have neither the DAR | |
311 | * nor the DSISR SPRs. Hence, we overload them to hold the similar | |
312 | * DEAR and ESR SPRs for such processors. For critical interrupts | |
313 | * we use them to hold SRR0 and SRR1. | |
14cf11af PM |
314 | */ |
315 | DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar)); | |
316 | DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr)); | |
d1dead5c | 317 | #else /* CONFIG_PPC64 */ |
d1dead5c SR |
318 | DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe)); |
319 | ||
320 | /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */ | |
321 | DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)); | |
322 | DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8); | |
323 | #endif /* CONFIG_PPC64 */ | |
324 | ||
57e2a99f | 325 | #if defined(CONFIG_PPC32) |
fca622c5 KG |
326 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
327 | DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE); | |
328 | DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); | |
329 | /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */ | |
330 | DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0)); | |
331 | DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1)); | |
332 | DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2)); | |
333 | DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3)); | |
334 | DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6)); | |
335 | DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7)); | |
336 | DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0)); | |
337 | DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1)); | |
338 | DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0)); | |
339 | DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1)); | |
340 | DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0)); | |
341 | DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1)); | |
342 | DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit)); | |
343 | #endif | |
57e2a99f | 344 | #endif |
14cf11af PM |
345 | DEFINE(CLONE_VM, CLONE_VM); |
346 | DEFINE(CLONE_UNTRACED, CLONE_UNTRACED); | |
d1dead5c SR |
347 | |
348 | #ifndef CONFIG_PPC64 | |
14cf11af | 349 | DEFINE(MM_PGD, offsetof(struct mm_struct, pgd)); |
d1dead5c | 350 | #endif /* ! CONFIG_PPC64 */ |
14cf11af PM |
351 | |
352 | /* About the CPU features table */ | |
14cf11af PM |
353 | DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features)); |
354 | DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup)); | |
f39b7a55 | 355 | DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore)); |
14cf11af | 356 | |
d1dead5c SR |
357 | DEFINE(pbe_address, offsetof(struct pbe, address)); |
358 | DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address)); | |
359 | DEFINE(pbe_next, offsetof(struct pbe, next)); | |
14cf11af | 360 | |
543b9fd3 | 361 | #ifndef CONFIG_PPC64 |
fd582ec8 | 362 | DEFINE(TASK_SIZE, TASK_SIZE); |
d1dead5c | 363 | DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28); |
a7f290da | 364 | #endif /* ! CONFIG_PPC64 */ |
14cf11af | 365 | |
a7f290da BH |
366 | /* datapage offsets for use by vdso */ |
367 | DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp)); | |
368 | DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec)); | |
369 | DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs)); | |
370 | DEFINE(CFG_STAMP_XSEC, offsetof(struct vdso_data, stamp_xsec)); | |
371 | DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count)); | |
372 | DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest)); | |
373 | DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime)); | |
374 | DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32)); | |
375 | DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec)); | |
376 | DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec)); | |
597bc5c0 | 377 | DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime)); |
8fd63a9e | 378 | DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction)); |
fbe48175 OJ |
379 | DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size)); |
380 | DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size)); | |
381 | DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size)); | |
382 | DEFINE(CFG_DCACHE_LOGBLOCKSZ, offsetof(struct vdso_data, dcache_log_block_size)); | |
a7f290da BH |
383 | #ifdef CONFIG_PPC64 |
384 | DEFINE(CFG_SYSCALL_MAP64, offsetof(struct vdso_data, syscall_map_64)); | |
14cf11af PM |
385 | DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec)); |
386 | DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec)); | |
387 | DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec)); | |
388 | DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec)); | |
0c37ec2a BH |
389 | DEFINE(TSPC64_TV_SEC, offsetof(struct timespec, tv_sec)); |
390 | DEFINE(TSPC64_TV_NSEC, offsetof(struct timespec, tv_nsec)); | |
a7f290da BH |
391 | DEFINE(TSPC32_TV_SEC, offsetof(struct compat_timespec, tv_sec)); |
392 | DEFINE(TSPC32_TV_NSEC, offsetof(struct compat_timespec, tv_nsec)); | |
393 | #else | |
394 | DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec)); | |
395 | DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec)); | |
0c37ec2a BH |
396 | DEFINE(TSPC32_TV_SEC, offsetof(struct timespec, tv_sec)); |
397 | DEFINE(TSPC32_TV_NSEC, offsetof(struct timespec, tv_nsec)); | |
a7f290da BH |
398 | #endif |
399 | /* timeval/timezone offsets for use by vdso */ | |
14cf11af PM |
400 | DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest)); |
401 | DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime)); | |
a7f290da BH |
402 | |
403 | /* Other bits used by the vdso */ | |
404 | DEFINE(CLOCK_REALTIME, CLOCK_REALTIME); | |
405 | DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC); | |
406 | DEFINE(NSEC_PER_SEC, NSEC_PER_SEC); | |
151db1fc | 407 | DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC); |
a7f290da | 408 | |
007d88d0 DW |
409 | #ifdef CONFIG_BUG |
410 | DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry)); | |
411 | #endif | |
16a15a30 | 412 | |
ee7a76da | 413 | DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE); |
4ee7084e | 414 | DEFINE(PTE_SIZE, sizeof(pte_t)); |
bee86f14 | 415 | |
bbf45ba5 | 416 | #ifdef CONFIG_KVM |
bbf45ba5 HB |
417 | DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack)); |
418 | DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid)); | |
d30f6e48 | 419 | DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid)); |
bbf45ba5 | 420 | DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr)); |
eab17672 | 421 | DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave)); |
de56a948 PM |
422 | DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fpr)); |
423 | DEFINE(VCPU_FPSCR, offsetof(struct kvm_vcpu, arch.fpscr)); | |
424 | #ifdef CONFIG_ALTIVEC | |
425 | DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr)); | |
426 | DEFINE(VCPU_VSCR, offsetof(struct kvm_vcpu, arch.vscr)); | |
427 | #endif | |
428 | #ifdef CONFIG_VSX | |
429 | DEFINE(VCPU_VSRS, offsetof(struct kvm_vcpu, arch.vsr)); | |
430 | #endif | |
431 | DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer)); | |
432 | DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr)); | |
433 | DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr)); | |
434 | DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr)); | |
435 | DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc)); | |
436 | #ifdef CONFIG_KVM_BOOK3S_64_HV | |
437 | DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.shregs.msr)); | |
438 | DEFINE(VCPU_SRR0, offsetof(struct kvm_vcpu, arch.shregs.srr0)); | |
439 | DEFINE(VCPU_SRR1, offsetof(struct kvm_vcpu, arch.shregs.srr1)); | |
440 | DEFINE(VCPU_SPRG0, offsetof(struct kvm_vcpu, arch.shregs.sprg0)); | |
441 | DEFINE(VCPU_SPRG1, offsetof(struct kvm_vcpu, arch.shregs.sprg1)); | |
442 | DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2)); | |
443 | DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3)); | |
444 | #endif | |
b5904972 SW |
445 | DEFINE(VCPU_SHARED_SPRG4, offsetof(struct kvm_vcpu_arch_shared, sprg4)); |
446 | DEFINE(VCPU_SHARED_SPRG5, offsetof(struct kvm_vcpu_arch_shared, sprg5)); | |
447 | DEFINE(VCPU_SHARED_SPRG6, offsetof(struct kvm_vcpu_arch_shared, sprg6)); | |
448 | DEFINE(VCPU_SHARED_SPRG7, offsetof(struct kvm_vcpu_arch_shared, sprg7)); | |
49dd2c49 | 449 | DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid)); |
dd9ebf1f | 450 | DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1)); |
96bc451a | 451 | DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared)); |
666e7252 | 452 | DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr)); |
ecee273f | 453 | DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr)); |
bbf45ba5 | 454 | |
b5904972 SW |
455 | DEFINE(VCPU_SHARED_MAS0, offsetof(struct kvm_vcpu_arch_shared, mas0)); |
456 | DEFINE(VCPU_SHARED_MAS1, offsetof(struct kvm_vcpu_arch_shared, mas1)); | |
457 | DEFINE(VCPU_SHARED_MAS2, offsetof(struct kvm_vcpu_arch_shared, mas2)); | |
458 | DEFINE(VCPU_SHARED_MAS7_3, offsetof(struct kvm_vcpu_arch_shared, mas7_3)); | |
459 | DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, mas4)); | |
460 | DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, mas6)); | |
461 | ||
d30f6e48 SW |
462 | DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm)); |
463 | DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid)); | |
464 | ||
00c3a37c | 465 | /* book3s */ |
de56a948 | 466 | #ifdef CONFIG_KVM_BOOK3S_64_HV |
de56a948 PM |
467 | DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1)); |
468 | DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid)); | |
469 | DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr)); | |
470 | DEFINE(KVM_HOST_SDR1, offsetof(struct kvm, arch.host_sdr1)); | |
471 | DEFINE(KVM_TLBIE_LOCK, offsetof(struct kvm, arch.tlbie_lock)); | |
1b400ba0 | 472 | DEFINE(KVM_NEED_FLUSH, offsetof(struct kvm, arch.need_tlb_flush.bits)); |
aa04b4cc PM |
473 | DEFINE(KVM_LPCR, offsetof(struct kvm, arch.lpcr)); |
474 | DEFINE(KVM_RMOR, offsetof(struct kvm, arch.rmor)); | |
697d3899 | 475 | DEFINE(KVM_VRMA_SLB_V, offsetof(struct kvm, arch.vrma_slb_v)); |
de56a948 PM |
476 | DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr)); |
477 | DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar)); | |
7657f408 | 478 | DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr)); |
de56a948 | 479 | #endif |
00c3a37c | 480 | #ifdef CONFIG_PPC_BOOK3S |
de56a948 | 481 | DEFINE(VCPU_VCPUID, offsetof(struct kvm_vcpu, vcpu_id)); |
de56a948 PM |
482 | DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr)); |
483 | DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr)); | |
484 | DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr)); | |
485 | DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr)); | |
486 | DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor)); | |
487 | DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl)); | |
488 | DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr)); | |
62908905 | 489 | DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags)); |
de56a948 PM |
490 | DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec)); |
491 | DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires)); | |
aa04b4cc | 492 | DEFINE(VCPU_PENDING_EXC, offsetof(struct kvm_vcpu, arch.pending_exceptions)); |
19ccb76a PM |
493 | DEFINE(VCPU_CEDED, offsetof(struct kvm_vcpu, arch.ceded)); |
494 | DEFINE(VCPU_PRODDED, offsetof(struct kvm_vcpu, arch.prodded)); | |
de56a948 PM |
495 | DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr)); |
496 | DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc)); | |
497 | DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb)); | |
498 | DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max)); | |
499 | DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr)); | |
de56a948 PM |
500 | DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr)); |
501 | DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar)); | |
502 | DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst)); | |
503 | DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap)); | |
371fefd6 | 504 | DEFINE(VCPU_PTID, offsetof(struct kvm_vcpu, arch.ptid)); |
0acb9111 | 505 | DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar)); |
371fefd6 PM |
506 | DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_count)); |
507 | DEFINE(VCORE_NAP_COUNT, offsetof(struct kvmppc_vcore, nap_count)); | |
508 | DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest)); | |
19ccb76a | 509 | DEFINE(VCORE_NAPPING_THREADS, offsetof(struct kvmppc_vcore, napping_threads)); |
de56a948 PM |
510 | DEFINE(VCPU_SVCPU, offsetof(struct kvmppc_vcpu_book3s, shadow_vcpu) - |
511 | offsetof(struct kvmppc_vcpu_book3s, vcpu)); | |
512 | DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige)); | |
513 | DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv)); | |
514 | DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb)); | |
3c42bf8a PM |
515 | |
516 | #ifdef CONFIG_PPC_BOOK3S_64 | |
de56a948 | 517 | #ifdef CONFIG_KVM_BOOK3S_PR |
3c42bf8a | 518 | # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f)) |
de56a948 PM |
519 | #else |
520 | # define SVCPU_FIELD(x, f) | |
521 | #endif | |
3c42bf8a PM |
522 | # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f)) |
523 | #else /* 32-bit */ | |
524 | # define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f)) | |
525 | # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f)) | |
526 | #endif | |
527 | ||
528 | SVCPU_FIELD(SVCPU_CR, cr); | |
529 | SVCPU_FIELD(SVCPU_XER, xer); | |
530 | SVCPU_FIELD(SVCPU_CTR, ctr); | |
531 | SVCPU_FIELD(SVCPU_LR, lr); | |
532 | SVCPU_FIELD(SVCPU_PC, pc); | |
533 | SVCPU_FIELD(SVCPU_R0, gpr[0]); | |
534 | SVCPU_FIELD(SVCPU_R1, gpr[1]); | |
535 | SVCPU_FIELD(SVCPU_R2, gpr[2]); | |
536 | SVCPU_FIELD(SVCPU_R3, gpr[3]); | |
537 | SVCPU_FIELD(SVCPU_R4, gpr[4]); | |
538 | SVCPU_FIELD(SVCPU_R5, gpr[5]); | |
539 | SVCPU_FIELD(SVCPU_R6, gpr[6]); | |
540 | SVCPU_FIELD(SVCPU_R7, gpr[7]); | |
541 | SVCPU_FIELD(SVCPU_R8, gpr[8]); | |
542 | SVCPU_FIELD(SVCPU_R9, gpr[9]); | |
543 | SVCPU_FIELD(SVCPU_R10, gpr[10]); | |
544 | SVCPU_FIELD(SVCPU_R11, gpr[11]); | |
545 | SVCPU_FIELD(SVCPU_R12, gpr[12]); | |
546 | SVCPU_FIELD(SVCPU_R13, gpr[13]); | |
547 | SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr); | |
548 | SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar); | |
549 | SVCPU_FIELD(SVCPU_LAST_INST, last_inst); | |
550 | SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1); | |
0604675f | 551 | #ifdef CONFIG_PPC_BOOK3S_32 |
3c42bf8a | 552 | SVCPU_FIELD(SVCPU_SR, sr); |
0604675f | 553 | #endif |
3c42bf8a PM |
554 | #ifdef CONFIG_PPC64 |
555 | SVCPU_FIELD(SVCPU_SLB, slb); | |
556 | SVCPU_FIELD(SVCPU_SLB_MAX, slb_max); | |
557 | #endif | |
558 | ||
559 | HSTATE_FIELD(HSTATE_HOST_R1, host_r1); | |
560 | HSTATE_FIELD(HSTATE_HOST_R2, host_r2); | |
de56a948 | 561 | HSTATE_FIELD(HSTATE_HOST_MSR, host_msr); |
3c42bf8a PM |
562 | HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler); |
563 | HSTATE_FIELD(HSTATE_SCRATCH0, scratch0); | |
564 | HSTATE_FIELD(HSTATE_SCRATCH1, scratch1); | |
565 | HSTATE_FIELD(HSTATE_IN_GUEST, in_guest); | |
02143947 | 566 | HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5); |
19ccb76a | 567 | HSTATE_FIELD(HSTATE_NAPPING, napping); |
3c42bf8a | 568 | |
de56a948 | 569 | #ifdef CONFIG_KVM_BOOK3S_64_HV |
7657f408 PM |
570 | HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req); |
571 | HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state); | |
de56a948 | 572 | HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu); |
371fefd6 PM |
573 | HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore); |
574 | HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys); | |
de56a948 PM |
575 | HSTATE_FIELD(HSTATE_MMCR, host_mmcr); |
576 | HSTATE_FIELD(HSTATE_PMC, host_pmc); | |
577 | HSTATE_FIELD(HSTATE_PURR, host_purr); | |
578 | HSTATE_FIELD(HSTATE_SPURR, host_spurr); | |
579 | HSTATE_FIELD(HSTATE_DSCR, host_dscr); | |
580 | HSTATE_FIELD(HSTATE_DABR, dabr); | |
581 | HSTATE_FIELD(HSTATE_DECEXP, dec_expires); | |
19ccb76a | 582 | DEFINE(IPI_PRIORITY, IPI_PRIORITY); |
de56a948 PM |
583 | #endif /* CONFIG_KVM_BOOK3S_64_HV */ |
584 | ||
0acb9111 PM |
585 | #ifdef CONFIG_PPC_BOOK3S_64 |
586 | HSTATE_FIELD(HSTATE_CFAR, cfar); | |
587 | #endif /* CONFIG_PPC_BOOK3S_64 */ | |
588 | ||
3c42bf8a | 589 | #else /* CONFIG_PPC_BOOK3S */ |
7e57cba0 AG |
590 | DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr)); |
591 | DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer)); | |
0604675f AG |
592 | DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr)); |
593 | DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr)); | |
594 | DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc)); | |
595 | DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst)); | |
596 | DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear)); | |
597 | DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr)); | |
00c3a37c | 598 | #endif /* CONFIG_PPC_BOOK3S */ |
3c42bf8a | 599 | #endif /* CONFIG_KVM */ |
d17051cb AG |
600 | |
601 | #ifdef CONFIG_KVM_GUEST | |
602 | DEFINE(KVM_MAGIC_SCRATCH1, offsetof(struct kvm_vcpu_arch_shared, | |
603 | scratch1)); | |
604 | DEFINE(KVM_MAGIC_SCRATCH2, offsetof(struct kvm_vcpu_arch_shared, | |
605 | scratch2)); | |
606 | DEFINE(KVM_MAGIC_SCRATCH3, offsetof(struct kvm_vcpu_arch_shared, | |
607 | scratch3)); | |
608 | DEFINE(KVM_MAGIC_INT, offsetof(struct kvm_vcpu_arch_shared, | |
609 | int_pending)); | |
610 | DEFINE(KVM_MAGIC_MSR, offsetof(struct kvm_vcpu_arch_shared, msr)); | |
611 | DEFINE(KVM_MAGIC_CRITICAL, offsetof(struct kvm_vcpu_arch_shared, | |
612 | critical)); | |
cbe487fa | 613 | DEFINE(KVM_MAGIC_SR, offsetof(struct kvm_vcpu_arch_shared, sr)); |
d17051cb AG |
614 | #endif |
615 | ||
ca9153a3 IY |
616 | #ifdef CONFIG_44x |
617 | DEFINE(PGD_T_LOG2, PGD_T_LOG2); | |
618 | DEFINE(PTE_T_LOG2, PTE_T_LOG2); | |
619 | #endif | |
55fd766b | 620 | #ifdef CONFIG_PPC_FSL_BOOK3E |
78f62237 KG |
621 | DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam)); |
622 | DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0)); | |
623 | DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1)); | |
624 | DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2)); | |
625 | DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3)); | |
626 | DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7)); | |
627 | #endif | |
bbf45ba5 | 628 | |
4cd35f67 SW |
629 | #if defined(CONFIG_KVM) && defined(CONFIG_SPE) |
630 | DEFINE(VCPU_EVR, offsetof(struct kvm_vcpu, arch.evr[0])); | |
631 | DEFINE(VCPU_ACC, offsetof(struct kvm_vcpu, arch.acc)); | |
632 | DEFINE(VCPU_SPEFSCR, offsetof(struct kvm_vcpu, arch.spefscr)); | |
633 | DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, arch.host_spefscr)); | |
634 | #endif | |
635 | ||
d30f6e48 SW |
636 | #ifdef CONFIG_KVM_BOOKE_HV |
637 | DEFINE(VCPU_HOST_MAS4, offsetof(struct kvm_vcpu, arch.host_mas4)); | |
638 | DEFINE(VCPU_HOST_MAS6, offsetof(struct kvm_vcpu, arch.host_mas6)); | |
639 | DEFINE(VCPU_EPLC, offsetof(struct kvm_vcpu, arch.eplc)); | |
640 | #endif | |
641 | ||
73e75b41 HB |
642 | #ifdef CONFIG_KVM_EXIT_TIMING |
643 | DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu, | |
644 | arch.timing_exit.tv32.tbu)); | |
645 | DEFINE(VCPU_TIMING_EXIT_TBL, offsetof(struct kvm_vcpu, | |
646 | arch.timing_exit.tv32.tbl)); | |
647 | DEFINE(VCPU_TIMING_LAST_ENTER_TBU, offsetof(struct kvm_vcpu, | |
648 | arch.timing_last_enter.tv32.tbu)); | |
649 | DEFINE(VCPU_TIMING_LAST_ENTER_TBL, offsetof(struct kvm_vcpu, | |
650 | arch.timing_last_enter.tv32.tbl)); | |
651 | #endif | |
652 | ||
ed79ba9e BH |
653 | #ifdef CONFIG_PPC_POWERNV |
654 | DEFINE(OPAL_MC_GPR3, offsetof(struct opal_machine_check_event, gpr3)); | |
655 | DEFINE(OPAL_MC_SRR0, offsetof(struct opal_machine_check_event, srr0)); | |
656 | DEFINE(OPAL_MC_SRR1, offsetof(struct opal_machine_check_event, srr1)); | |
657 | DEFINE(PACA_OPAL_MC_EVT, offsetof(struct paca_struct, opal_mc_evt)); | |
658 | #endif | |
659 | ||
14cf11af PM |
660 | return 0; |
661 | } |