]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - arch/powerpc/kernel/asm-offsets.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
powerpc/asm: Remove unused symbols in asm-offsets.c
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / asm-offsets.c
CommitLineData
14cf11af
PM		 1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
14cf11af
PM		 16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
14cf11af
PM		 22#include <linux/mman.h>
23#include <linux/mm.h>
543b9fd3 24#include <linux/suspend.h>
ad7f7167 25#include <linux/hrtimer.h>
d1dead5c 26#ifdef CONFIG_PPC64
14cf11af
PM		 27#include <linux/time.h>
28#include <linux/hardirq.h>
d1dead5c 29#endif
d4d298fe 30#include <linux/kbuild.h>
d1dead5c 31
14cf11af
PM		 32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
14cf11af
PM		 36#include <asm/cputable.h>
37#include <asm/thread_info.h>
033ef338 38#include <asm/rtas.h>
a7f290da 39#include <asm/vdso_datapage.h>
66feed61 40#include <asm/dbell.h>
14cf11af
PM		 41#ifdef CONFIG_PPC64
42#include <asm/paca.h>
43#include <asm/lppaca.h>
14cf11af 44#include <asm/cache.h>
14cf11af 45#include <asm/compat.h>
11a27ad7 46#include <asm/mmu.h>
f04da0bc 47#include <asm/hvcall.h>
19ccb76a 48#include <asm/xics.h>
14cf11af 49#endif
ed79ba9e
BH		 50#ifdef CONFIG_PPC_POWERNV
51#include <asm/opal.h>
52#endif
989044ee 53#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
366d4b9b 54#include <linux/kvm_host.h>
0604675f 55#endif
989044ee
AG		 56#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
57#include <asm/kvm_book3s.h>
5deb8e7a 58#include <asm/kvm_ppc.h>
db93f574 59#endif
14cf11af 60
57e2a99f 61#ifdef CONFIG_PPC32
fca622c5
KG		 62#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
63#include "head_booke.h"
64#endif
57e2a99f 65#endif
fca622c5 66
55fd766b 67#if defined(CONFIG_PPC_FSL_BOOK3E)
19f5465e
TP		 68#include "../mm/mmu_decl.h"
69#endif
70
14cf11af
PM		 71int main(void)
72{
d1dead5c
SR		 73 DEFINE(THREAD, offsetof(struct task_struct, thread));
74 DEFINE(MM, offsetof(struct task_struct, mm));
5e696617 75 DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
14cf11af 76#ifdef CONFIG_PPC64
9c1e1052
PM		 77 DEFINE(SIGSEGV, SIGSEGV);
78 DEFINE(NMI_MASK, NMI_MASK);
92779245 79 DEFINE(TASKTHREADPPR, offsetof(struct task_struct, thread.ppr));
d1dead5c 80#else
f7e4217b 81 DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
cbc9565e
BH		 82 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
83 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
d1dead5c
SR		 84#endif /* CONFIG_PPC64 */
85
85baa095
ME		 86#ifdef CONFIG_LIVEPATCH
87 DEFINE(TI_livepatch_sp, offsetof(struct thread_info, livepatch_sp));
88#endif
89
14cf11af 90 DEFINE(KSP, offsetof(struct thread_struct, ksp));
14cf11af 91 DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
1325a684
AK		 92#ifdef CONFIG_BOOKE
93 DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));
94#endif
14cf11af 95 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
de79f7b9 96 DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fp_state));
18461960 97 DEFINE(THREAD_FPSAVEAREA, offsetof(struct thread_struct, fp_save_area));
de79f7b9 98 DEFINE(FPSTATE_FPSCR, offsetof(struct thread_fp_state, fpscr));
70fe3d98 99 DEFINE(THREAD_LOAD_FP, offsetof(struct thread_struct, load_fp));
14cf11af 100#ifdef CONFIG_ALTIVEC
de79f7b9 101 DEFINE(THREAD_VRSTATE, offsetof(struct thread_struct, vr_state));
18461960 102 DEFINE(THREAD_VRSAVEAREA, offsetof(struct thread_struct, vr_save_area));
14cf11af 103 DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));
14cf11af 104 DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr));
de79f7b9 105 DEFINE(VRSTATE_VSCR, offsetof(struct thread_vr_state, vscr));
70fe3d98 106 DEFINE(THREAD_LOAD_VEC, offsetof(struct thread_struct, load_vec));
14cf11af 107#endif /* CONFIG_ALTIVEC */
c6e6771b 108#ifdef CONFIG_VSX
c6e6771b
MN		 109 DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr));
110#endif /* CONFIG_VSX */
d1dead5c
SR		 111#ifdef CONFIG_PPC64
112 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid));
113#else /* CONFIG_PPC64 */
114 DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
14cf11af
PM		 115#ifdef CONFIG_SPE
116 DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
117 DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc));
118 DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr));
119 DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe));
120#endif /* CONFIG_SPE */
d1dead5c 121#endif /* CONFIG_PPC64 */
13d543cd 122#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
51ae8d4a 123 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0));
13d543cd 124#endif
97e49255
AG		 125#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
126 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
127#endif
ffe129ec 128#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
d30f6e48
SW		 129 DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, kvm_vcpu));
130#endif
d1dead5c 131
8b3c34cf 132#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
afc07701 133 DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
8b3c34cf
MN		 134 DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
135 DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
136 DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
28e61cc4
MN		 137 DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
138 DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
139 DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
8b3c34cf 140 DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
de79f7b9
PM		 141 DEFINE(THREAD_TRANSACT_VRSTATE, offsetof(struct thread_struct,
142 transact_vr));
8b3c34cf
MN		 143 DEFINE(THREAD_TRANSACT_VRSAVE, offsetof(struct thread_struct,
144 transact_vrsave));
de79f7b9
PM		 145 DEFINE(THREAD_TRANSACT_FPSTATE, offsetof(struct thread_struct,
146 transact_fp));
8b3c34cf
MN		 147 /* Local pt_regs on stack for Transactional Memory funcs. */
148 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
149 sizeof(struct pt_regs) + 16);
150#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2468dcf6 151
d1dead5c 152 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
f39224a8 153 DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));
d1dead5c 154 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
d1dead5c 155 DEFINE(TI_TASK, offsetof(struct thread_info, task));
d1dead5c 156 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
d1dead5c
SR		 157
158#ifdef CONFIG_PPC64
159 DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size));
160 DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size));
161 DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page));
162 DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size));
163 DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size));
164 DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page));
d1dead5c
SR		 165 /* paca */
166 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
167 DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index));
168 DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start));
169 DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack));
170 DEFINE(PACACURRENT, offsetof(struct paca_struct, __current));
171 DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr));
d1dead5c
SR		 172 DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr));
173 DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1));
174 DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc));
1f6a93e4
PM		 175 DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase));
176 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
d04c56f7 177 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
7230c564 178 DEFINE(PACAIRQHAPPENED, offsetof(struct paca_struct, irq_happened));
c395465d 179#ifdef CONFIG_PPC_BOOK3S
2fc251a8 180 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, mm_ctx_id));
d0f13e3c
BH		 181#ifdef CONFIG_PPC_MM_SLICES
182 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
2fc251a8 183 mm_ctx_low_slices_psize));
d0f13e3c 184 DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct,
2fc251a8 185 mm_ctx_high_slices_psize));
d0f13e3c 186 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
91c60b5b 187#endif /* CONFIG_PPC_MM_SLICES */
c395465d 188#endif
dce6670a
BH		 189
190#ifdef CONFIG_PPC_BOOK3E
191 DEFINE(PACAPGD, offsetof(struct paca_struct, pgd));
192 DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd));
193 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
194 DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb));
195 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
196 DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit));
197 DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg));
198 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
199 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
200 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
28efc35f
SW		 201 DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr));
202
203 DEFINE(TCD_ESEL_NEXT,
204 offsetof(struct tlb_core_data, esel_next));
205 DEFINE(TCD_ESEL_MAX,
206 offsetof(struct tlb_core_data, esel_max));
207 DEFINE(TCD_ESEL_FIRST,
208 offsetof(struct tlb_core_data, esel_first));
dce6670a
BH		 209#endif /* CONFIG_PPC_BOOK3E */
210
91c60b5b 211#ifdef CONFIG_PPC_STD_MMU_64
91c60b5b
BH		 212 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
213 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
214 DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
215#ifdef CONFIG_PPC_MM_SLICES
d0f13e3c
BH		 216 DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp));
217#else
2fc251a8 218 DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, mm_ctx_sllp));
d0f13e3c 219#endif /* CONFIG_PPC_MM_SLICES */
d1dead5c
SR		 220 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
221 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
222 DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb));
3356bb9f 223 DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr));
2f6093c8 224 DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr));
11a27ad7
MN		 225 DEFINE(SLBSHADOW_STACKVSID,
226 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid));
227 DEFINE(SLBSHADOW_STACKESID,
228 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid));
cf9efce0 229 DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area));
de56a948 230 DEFINE(LPPACA_PMCINUSE, offsetof(struct lppaca, pmcregs_in_use));
cf9efce0 231 DEFINE(LPPACA_DTLIDX, offsetof(struct lppaca, dtl_idx));
a8606e20 232 DEFINE(LPPACA_YIELDCOUNT, offsetof(struct lppaca, yield_count));
cf9efce0 233 DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx));
91c60b5b
BH		 234#endif /* CONFIG_PPC_STD_MMU_64 */
235 DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
1e9b4507
MS		 236#ifdef CONFIG_PPC_BOOK3S_64
237 DEFINE(PACAMCEMERGSP, offsetof(struct paca_struct, mc_emergency_sp));
238 DEFINE(PACA_IN_MCE, offsetof(struct paca_struct, in_mce));
239#endif
91c60b5b 240 DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
1fc711f7 241 DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
1db36525 242 DEFINE(PACA_DSCR_DEFAULT, offsetof(struct paca_struct, dscr_default));
cf9efce0
PM		 243 DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime));
244 DEFINE(PACA_STARTTIME_USER, offsetof(struct paca_struct, starttime_user));
91c60b5b
BH		 245 DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
246 DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
91c60b5b 247 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
2fde6d20 248 DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
9d378dfa 249 DEFINE(PACA_SPRG_VDSO, offsetof(struct paca_struct, sprg_vdso));
033ef338 250#endif /* CONFIG_PPC64 */
d1dead5c
SR		 251
252 /* RTAS */
253 DEFINE(RTASBASE, offsetof(struct rtas_t, base));
254 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
d1dead5c 255
14cf11af 256 /* Interrupt register frame */
91120cc8 257 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
14cf11af 258 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
218d169c 259#ifdef CONFIG_PPC64
d1dead5c
SR		 260 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
261 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
262 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
263#endif /* CONFIG_PPC64 */
14cf11af
PM		 264 DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0]));
265 DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1]));
266 DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2]));
267 DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3]));
268 DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4]));
269 DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5]));
270 DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6]));
271 DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7]));
272 DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8]));
273 DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9]));
274 DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10]));
275 DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11]));
276 DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12]));
277 DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13]));
d1dead5c 278#ifndef CONFIG_PPC64
14cf11af 279 DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14]));
d1dead5c 280#endif /* CONFIG_PPC64 */
14cf11af
PM		 281 /*
282 * Note: these symbols include _ because they overlap with special
283 * register names
284 */
285 DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip));
286 DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr));
287 DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr));
288 DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link));
289 DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr));
14cf11af
PM		 290 DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer));
291 DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
292 DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c
SR		 293 DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3));
294 DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result));
d73e0c99 295 DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap));
d1dead5c 296#ifndef CONFIG_PPC64
d1dead5c
SR		 297 /*
298 * The PowerPC 400-class & Book-E processors have neither the DAR
299 * nor the DSISR SPRs. Hence, we overload them to hold the similar
300 * DEAR and ESR SPRs for such processors. For critical interrupts
301 * we use them to hold SRR0 and SRR1.
14cf11af
PM		 302 */
303 DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
304 DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c 305#else /* CONFIG_PPC64 */
d1dead5c
SR		 306 DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe));
307
308 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
309 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
310 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
311#endif /* CONFIG_PPC64 */
312
57e2a99f 313#if defined(CONFIG_PPC32)
fca622c5
KG		 314#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
315 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
316 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
317 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
318 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
319 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
320 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
321 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
322 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
323 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
324 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
325 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
326 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
327 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
328 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
329 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
330 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
331#endif
57e2a99f 332#endif
d1dead5c
SR		 333
334#ifndef CONFIG_PPC64
14cf11af 335 DEFINE(MM_PGD, offsetof(struct mm_struct, pgd));
d1dead5c 336#endif /* ! CONFIG_PPC64 */
14cf11af
PM		 337
338 /* About the CPU features table */
14cf11af
PM		 339 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
340 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
f39b7a55 341 DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
14cf11af 342
d1dead5c
SR		 343 DEFINE(pbe_address, offsetof(struct pbe, address));
344 DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address));
345 DEFINE(pbe_next, offsetof(struct pbe, next));
14cf11af 346
543b9fd3 347#ifndef CONFIG_PPC64
fd582ec8 348 DEFINE(TASK_SIZE, TASK_SIZE);
d1dead5c 349 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
a7f290da 350#endif /* ! CONFIG_PPC64 */
14cf11af 351
a7f290da
BH		 352 /* datapage offsets for use by vdso */
353 DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp));
354 DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec));
355 DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs));
a7f290da
BH		 356 DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count));
357 DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest));
358 DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
359 DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32));
360 DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
361 DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
597bc5c0 362 DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
8fd63a9e 363 DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
fbe48175
OJ		 364 DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
365 DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
366 DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
367 DEFINE(CFG_DCACHE_LOGBLOCKSZ, offsetof(struct vdso_data, dcache_log_block_size));
a7f290da
BH		 368#ifdef CONFIG_PPC64
369 DEFINE(CFG_SYSCALL_MAP64, offsetof(struct vdso_data, syscall_map_64));
14cf11af
PM		 370 DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec));
371 DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec));
372 DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec));
373 DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec));
0c37ec2a
BH		 374 DEFINE(TSPC64_TV_SEC, offsetof(struct timespec, tv_sec));
375 DEFINE(TSPC64_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 376 DEFINE(TSPC32_TV_SEC, offsetof(struct compat_timespec, tv_sec));
377 DEFINE(TSPC32_TV_NSEC, offsetof(struct compat_timespec, tv_nsec));
378#else
379 DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec));
380 DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec));
0c37ec2a
BH		 381 DEFINE(TSPC32_TV_SEC, offsetof(struct timespec, tv_sec));
382 DEFINE(TSPC32_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 383#endif
384 /* timeval/timezone offsets for use by vdso */
14cf11af
PM		 385 DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
386 DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
a7f290da
BH		 387
388 /* Other bits used by the vdso */
389 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
390 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
391 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
151db1fc 392 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
a7f290da 393
007d88d0
DW		 394#ifdef CONFIG_BUG
395 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
396#endif
16a15a30 397
dd1842a2
AK		 398#ifdef MAX_PGD_TABLE_SIZE
399 DEFINE(PGD_TABLE_SIZE, MAX_PGD_TABLE_SIZE);
400#else
ee7a76da 401 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
dd1842a2 402#endif
4ee7084e 403 DEFINE(PTE_SIZE, sizeof(pte_t));
bee86f14 404
bbf45ba5 405#ifdef CONFIG_KVM
bbf45ba5
HB		 406 DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack));
407 DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid));
d30f6e48 408 DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid));
bbf45ba5 409 DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr));
eab17672 410 DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave));
efff1912 411 DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fp.fpr));
de56a948 412#ifdef CONFIG_ALTIVEC
efff1912 413 DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr.vr));
de56a948
PM		 414#endif
415 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
416 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
417 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
e14e7a1e 418#ifdef CONFIG_PPC_BOOK3S
b005255e 419 DEFINE(VCPU_TAR, offsetof(struct kvm_vcpu, arch.tar));
e14e7a1e 420#endif
de56a948
PM		 421 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
422 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
9975f5e3 423#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
de56a948
PM		 424 DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.shregs.msr));
425 DEFINE(VCPU_SRR0, offsetof(struct kvm_vcpu, arch.shregs.srr0));
426 DEFINE(VCPU_SRR1, offsetof(struct kvm_vcpu, arch.shregs.srr1));
427 DEFINE(VCPU_SPRG0, offsetof(struct kvm_vcpu, arch.shregs.sprg0));
428 DEFINE(VCPU_SPRG1, offsetof(struct kvm_vcpu, arch.shregs.sprg1));
429 DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2));
430 DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3));
b6c295df
PM		 431#endif
432#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
433 DEFINE(VCPU_TB_RMENTRY, offsetof(struct kvm_vcpu, arch.rm_entry));
434 DEFINE(VCPU_TB_RMINTR, offsetof(struct kvm_vcpu, arch.rm_intr));
435 DEFINE(VCPU_TB_RMEXIT, offsetof(struct kvm_vcpu, arch.rm_exit));
436 DEFINE(VCPU_TB_GUEST, offsetof(struct kvm_vcpu, arch.guest_time));
437 DEFINE(VCPU_TB_CEDE, offsetof(struct kvm_vcpu, arch.cede_time));
438 DEFINE(VCPU_CUR_ACTIVITY, offsetof(struct kvm_vcpu, arch.cur_activity));
439 DEFINE(VCPU_ACTIVITY_START, offsetof(struct kvm_vcpu, arch.cur_tb_start));
440 DEFINE(TAS_SEQCOUNT, offsetof(struct kvmhv_tb_accumulator, seqcount));
441 DEFINE(TAS_TOTAL, offsetof(struct kvmhv_tb_accumulator, tb_total));
442 DEFINE(TAS_MIN, offsetof(struct kvmhv_tb_accumulator, tb_min));
443 DEFINE(TAS_MAX, offsetof(struct kvmhv_tb_accumulator, tb_max));
de56a948 444#endif
c8ae0ace 445 DEFINE(VCPU_SHARED_SPRG3, offsetof(struct kvm_vcpu_arch_shared, sprg3));
b5904972
SW		 446 DEFINE(VCPU_SHARED_SPRG4, offsetof(struct kvm_vcpu_arch_shared, sprg4));
447 DEFINE(VCPU_SHARED_SPRG5, offsetof(struct kvm_vcpu_arch_shared, sprg5));
448 DEFINE(VCPU_SHARED_SPRG6, offsetof(struct kvm_vcpu_arch_shared, sprg6));
449 DEFINE(VCPU_SHARED_SPRG7, offsetof(struct kvm_vcpu_arch_shared, sprg7));
49dd2c49 450 DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid));
dd9ebf1f 451 DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1));
96bc451a 452 DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared));
666e7252 453 DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
ecee273f 454 DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr));
5deb8e7a
AG		 455#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
456 DEFINE(VCPU_SHAREDBE, offsetof(struct kvm_vcpu, arch.shared_big_endian));
457#endif
bbf45ba5 458
b5904972
SW		 459 DEFINE(VCPU_SHARED_MAS0, offsetof(struct kvm_vcpu_arch_shared, mas0));
460 DEFINE(VCPU_SHARED_MAS1, offsetof(struct kvm_vcpu_arch_shared, mas1));
461 DEFINE(VCPU_SHARED_MAS2, offsetof(struct kvm_vcpu_arch_shared, mas2));
462 DEFINE(VCPU_SHARED_MAS7_3, offsetof(struct kvm_vcpu_arch_shared, mas7_3));
463 DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, mas4));
464 DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, mas6));
465
d30f6e48
SW		 466 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
467 DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
468
00c3a37c 469 /* book3s */
9975f5e3 470#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
de56a948
PM		 471 DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1));
472 DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid));
473 DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr));
474 DEFINE(KVM_HOST_SDR1, offsetof(struct kvm, arch.host_sdr1));
1b400ba0 475 DEFINE(KVM_NEED_FLUSH, offsetof(struct kvm, arch.need_tlb_flush.bits));
699a0ea0 476 DEFINE(KVM_ENABLED_HCALLS, offsetof(struct kvm, arch.enabled_hcalls));
697d3899 477 DEFINE(KVM_VRMA_SLB_V, offsetof(struct kvm, arch.vrma_slb_v));
de56a948
PM		 478 DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr));
479 DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
7657f408 480 DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr));
c35635ef 481 DEFINE(VCPU_VPA_DIRTY, offsetof(struct kvm_vcpu, arch.vpa.dirty));
4a157d61 482 DEFINE(VCPU_HEIR, offsetof(struct kvm_vcpu, arch.emul_inst));
ec257165
PM		 483 DEFINE(VCPU_CPU, offsetof(struct kvm_vcpu, cpu));
484 DEFINE(VCPU_THREAD_CPU, offsetof(struct kvm_vcpu, arch.thread_cpu));
de56a948 485#endif
00c3a37c 486#ifdef CONFIG_PPC_BOOK3S
de56a948
PM		 487 DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr));
488 DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr));
b005255e
MN		 489 DEFINE(VCPU_IC, offsetof(struct kvm_vcpu, arch.ic));
490 DEFINE(VCPU_VTB, offsetof(struct kvm_vcpu, arch.vtb));
de56a948
PM		 491 DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr));
492 DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr));
493 DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor));
b005255e 494 DEFINE(VCPU_IAMR, offsetof(struct kvm_vcpu, arch.iamr));
de56a948
PM		 495 DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl));
496 DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr));
8563bf52 497 DEFINE(VCPU_DABRX, offsetof(struct kvm_vcpu, arch.dabrx));
b005255e
MN		 498 DEFINE(VCPU_DAWR, offsetof(struct kvm_vcpu, arch.dawr));
499 DEFINE(VCPU_DAWRX, offsetof(struct kvm_vcpu, arch.dawrx));
500 DEFINE(VCPU_CIABR, offsetof(struct kvm_vcpu, arch.ciabr));
62908905 501 DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
de56a948
PM		 502 DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec));
503 DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires));
aa04b4cc 504 DEFINE(VCPU_PENDING_EXC, offsetof(struct kvm_vcpu, arch.pending_exceptions));
19ccb76a
PM		 505 DEFINE(VCPU_CEDED, offsetof(struct kvm_vcpu, arch.ceded));
506 DEFINE(VCPU_PRODDED, offsetof(struct kvm_vcpu, arch.prodded));
de56a948
PM		 507 DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr));
508 DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc));
b005255e 509 DEFINE(VCPU_SPMC, offsetof(struct kvm_vcpu, arch.spmc));
14941789
PM		 510 DEFINE(VCPU_SIAR, offsetof(struct kvm_vcpu, arch.siar));
511 DEFINE(VCPU_SDAR, offsetof(struct kvm_vcpu, arch.sdar));
b005255e 512 DEFINE(VCPU_SIER, offsetof(struct kvm_vcpu, arch.sier));
de56a948
PM		 513 DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb));
514 DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max));
515 DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr));
de56a948
PM		 516 DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr));
517 DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar));
e5ee5422 518 DEFINE(VCPU_INTR_MSR, offsetof(struct kvm_vcpu, arch.intr_msr));
de56a948
PM		 519 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
520 DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap));
0acb9111 521 DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar));
4b8473c9 522 DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr));
b005255e
MN		 523 DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr));
524 DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb));
b005255e
MN		 525 DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr));
526 DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr));
527 DEFINE(VCPU_BESCR, offsetof(struct kvm_vcpu, arch.bescr));
528 DEFINE(VCPU_CSIGR, offsetof(struct kvm_vcpu, arch.csigr));
529 DEFINE(VCPU_TACR, offsetof(struct kvm_vcpu, arch.tacr));
530 DEFINE(VCPU_TCSCR, offsetof(struct kvm_vcpu, arch.tcscr));
531 DEFINE(VCPU_ACOP, offsetof(struct kvm_vcpu, arch.acop));
532 DEFINE(VCPU_WORT, offsetof(struct kvm_vcpu, arch.wort));
7d6c40da 533 DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_map));
371fefd6 534 DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest));
19ccb76a 535 DEFINE(VCORE_NAPPING_THREADS, offsetof(struct kvmppc_vcore, napping_threads));
e0b7ec05 536 DEFINE(VCORE_KVM, offsetof(struct kvmppc_vcore, kvm));
93b0f4dc 537 DEFINE(VCORE_TB_OFFSET, offsetof(struct kvmppc_vcore, tb_offset));
a0144e2a 538 DEFINE(VCORE_LPCR, offsetof(struct kvmppc_vcore, lpcr));
388cc6e1 539 DEFINE(VCORE_PCR, offsetof(struct kvmppc_vcore, pcr));
b005255e 540 DEFINE(VCORE_DPDES, offsetof(struct kvmppc_vcore, dpdes));
de56a948
PM		 541 DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige));
542 DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv));
543 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
7b490411
MN		 544#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
545 DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar));
546 DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar));
547 DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr));
548 DEFINE(VCPU_GPR_TM, offsetof(struct kvm_vcpu, arch.gpr_tm));
549 DEFINE(VCPU_FPRS_TM, offsetof(struct kvm_vcpu, arch.fp_tm.fpr));
550 DEFINE(VCPU_VRS_TM, offsetof(struct kvm_vcpu, arch.vr_tm.vr));
551 DEFINE(VCPU_VRSAVE_TM, offsetof(struct kvm_vcpu, arch.vrsave_tm));
552 DEFINE(VCPU_CR_TM, offsetof(struct kvm_vcpu, arch.cr_tm));
553 DEFINE(VCPU_LR_TM, offsetof(struct kvm_vcpu, arch.lr_tm));
554 DEFINE(VCPU_CTR_TM, offsetof(struct kvm_vcpu, arch.ctr_tm));
555 DEFINE(VCPU_AMR_TM, offsetof(struct kvm_vcpu, arch.amr_tm));
556 DEFINE(VCPU_PPR_TM, offsetof(struct kvm_vcpu, arch.ppr_tm));
557 DEFINE(VCPU_DSCR_TM, offsetof(struct kvm_vcpu, arch.dscr_tm));
558 DEFINE(VCPU_TAR_TM, offsetof(struct kvm_vcpu, arch.tar_tm));
559#endif
3c42bf8a
PM		 560
561#ifdef CONFIG_PPC_BOOK3S_64
7aa79938 562#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
a2d56020 563 DEFINE(PACA_SVCPU, offsetof(struct paca_struct, shadow_vcpu));
3c42bf8a 564# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
de56a948
PM		 565#else
566# define SVCPU_FIELD(x, f)
567#endif
3c42bf8a
PM		 568# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
569#else /* 32-bit */
570# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
571# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
572#endif
573
574 SVCPU_FIELD(SVCPU_CR, cr);
575 SVCPU_FIELD(SVCPU_XER, xer);
576 SVCPU_FIELD(SVCPU_CTR, ctr);
577 SVCPU_FIELD(SVCPU_LR, lr);
578 SVCPU_FIELD(SVCPU_PC, pc);
579 SVCPU_FIELD(SVCPU_R0, gpr[0]);
580 SVCPU_FIELD(SVCPU_R1, gpr[1]);
581 SVCPU_FIELD(SVCPU_R2, gpr[2]);
582 SVCPU_FIELD(SVCPU_R3, gpr[3]);
583 SVCPU_FIELD(SVCPU_R4, gpr[4]);
584 SVCPU_FIELD(SVCPU_R5, gpr[5]);
585 SVCPU_FIELD(SVCPU_R6, gpr[6]);
586 SVCPU_FIELD(SVCPU_R7, gpr[7]);
587 SVCPU_FIELD(SVCPU_R8, gpr[8]);
588 SVCPU_FIELD(SVCPU_R9, gpr[9]);
589 SVCPU_FIELD(SVCPU_R10, gpr[10]);
590 SVCPU_FIELD(SVCPU_R11, gpr[11]);
591 SVCPU_FIELD(SVCPU_R12, gpr[12]);
592 SVCPU_FIELD(SVCPU_R13, gpr[13]);
593 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
594 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
595 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
596 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0604675f 597#ifdef CONFIG_PPC_BOOK3S_32
3c42bf8a 598 SVCPU_FIELD(SVCPU_SR, sr);
0604675f 599#endif
3c42bf8a
PM		 600#ifdef CONFIG_PPC64
601 SVCPU_FIELD(SVCPU_SLB, slb);
602 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
616dff86 603 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
3c42bf8a
PM		 604#endif
605
606 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
607 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
de56a948 608 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
3c42bf8a
PM		 609 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
610 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
611 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
36e7bb38 612 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
3c42bf8a 613 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
02143947 614 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
19ccb76a 615 HSTATE_FIELD(HSTATE_NAPPING, napping);
3c42bf8a 616
9975f5e3 617#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
7657f408
PM		 618 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
619 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
de56a948 620 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
371fefd6
PM		 621 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
622 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
54695c30
BH		 623 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
624 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
e0b7ec05 625 HSTATE_FIELD(HSTATE_PTID, ptid);
9a4fc4ea
ME		 626 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
627 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
628 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
629 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
630 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
631 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
632 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
633 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
634 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
635 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
636 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
637 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
638 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
de56a948
PM		 639 HSTATE_FIELD(HSTATE_PURR, host_purr);
640 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
641 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
642 HSTATE_FIELD(HSTATE_DABR, dabr);
643 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
b4deba5c 644 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
19ccb76a 645 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
b4deba5c
PM		 646 DEFINE(KVM_SPLIT_RPR, offsetof(struct kvm_split_mode, rpr));
647 DEFINE(KVM_SPLIT_PMMAR, offsetof(struct kvm_split_mode, pmmar));
648 DEFINE(KVM_SPLIT_LDBAR, offsetof(struct kvm_split_mode, ldbar));
b4deba5c
PM		 649 DEFINE(KVM_SPLIT_DO_NAP, offsetof(struct kvm_split_mode, do_nap));
650 DEFINE(KVM_SPLIT_NAPPED, offsetof(struct kvm_split_mode, napped));
9975f5e3 651#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
de56a948 652
0acb9111
PM		 653#ifdef CONFIG_PPC_BOOK3S_64
654 HSTATE_FIELD(HSTATE_CFAR, cfar);
4b8473c9 655 HSTATE_FIELD(HSTATE_PPR, ppr);
616dff86 656 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
0acb9111
PM		 657#endif /* CONFIG_PPC_BOOK3S_64 */
658
3c42bf8a 659#else /* CONFIG_PPC_BOOK3S */
7e57cba0
AG		 660 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
661 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
0604675f
AG		 662 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
663 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
664 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
99e99d19 665 DEFINE(VCPU_SPRG9, offsetof(struct kvm_vcpu, arch.sprg9));
0604675f
AG		 666 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
667 DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
668 DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
15b708be 669 DEFINE(VCPU_CRIT_SAVE, offsetof(struct kvm_vcpu, arch.crit_save));
00c3a37c 670#endif /* CONFIG_PPC_BOOK3S */
3c42bf8a 671#endif /* CONFIG_KVM */
d17051cb
AG		 672
673#ifdef CONFIG_KVM_GUEST
674 DEFINE(KVM_MAGIC_SCRATCH1, offsetof(struct kvm_vcpu_arch_shared,
675 scratch1));
676 DEFINE(KVM_MAGIC_SCRATCH2, offsetof(struct kvm_vcpu_arch_shared,
677 scratch2));
678 DEFINE(KVM_MAGIC_SCRATCH3, offsetof(struct kvm_vcpu_arch_shared,
679 scratch3));
680 DEFINE(KVM_MAGIC_INT, offsetof(struct kvm_vcpu_arch_shared,
681 int_pending));
682 DEFINE(KVM_MAGIC_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
683 DEFINE(KVM_MAGIC_CRITICAL, offsetof(struct kvm_vcpu_arch_shared,
684 critical));
cbe487fa 685 DEFINE(KVM_MAGIC_SR, offsetof(struct kvm_vcpu_arch_shared, sr));
d17051cb
AG		 686#endif
687
ca9153a3
IY		 688#ifdef CONFIG_44x
689 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
690 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
691#endif
55fd766b 692#ifdef CONFIG_PPC_FSL_BOOK3E
78f62237
KG		 693 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
694 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
695 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
696 DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
697 DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
698 DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
699#endif
bbf45ba5 700
4cd35f67
SW		 701#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
702 DEFINE(VCPU_EVR, offsetof(struct kvm_vcpu, arch.evr[0]));
703 DEFINE(VCPU_ACC, offsetof(struct kvm_vcpu, arch.acc));
704 DEFINE(VCPU_SPEFSCR, offsetof(struct kvm_vcpu, arch.spefscr));
705 DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, arch.host_spefscr));
706#endif
707
d30f6e48
SW		 708#ifdef CONFIG_KVM_BOOKE_HV
709 DEFINE(VCPU_HOST_MAS4, offsetof(struct kvm_vcpu, arch.host_mas4));
710 DEFINE(VCPU_HOST_MAS6, offsetof(struct kvm_vcpu, arch.host_mas6));
d30f6e48
SW		 711#endif
712
73e75b41
HB		 713#ifdef CONFIG_KVM_EXIT_TIMING
714 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
715 arch.timing_exit.tv32.tbu));
716 DEFINE(VCPU_TIMING_EXIT_TBL, offsetof(struct kvm_vcpu,
717 arch.timing_exit.tv32.tbl));
718 DEFINE(VCPU_TIMING_LAST_ENTER_TBU, offsetof(struct kvm_vcpu,
719 arch.timing_last_enter.tv32.tbu));
720 DEFINE(VCPU_TIMING_LAST_ENTER_TBL, offsetof(struct kvm_vcpu,
721 arch.timing_last_enter.tv32.tbl));
722#endif
723
7cba160a
SP		 724#ifdef CONFIG_PPC_POWERNV
725 DEFINE(PACA_CORE_IDLE_STATE_PTR,
726 offsetof(struct paca_struct, core_idle_state_ptr));
727 DEFINE(PACA_THREAD_IDLE_STATE,
728 offsetof(struct paca_struct, thread_idle_state));
729 DEFINE(PACA_THREAD_MASK,
730 offsetof(struct paca_struct, thread_mask));
77b54e9f
SP		 731 DEFINE(PACA_SUBCORE_SIBLING_MASK,
732 offsetof(struct paca_struct, subcore_sibling_mask));
7cba160a
SP		 733#endif
734
66feed61
PM		 735 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
736
14cf11af
PM		 737 return 0;
738}
ubuntu-zesty-kernel mirror