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[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / kernel / asm-offsets.c
CommitLineData
14cf11af
PM		 1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
14cf11af
PM		 16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
14cf11af
PM		 22#include <linux/mman.h>
23#include <linux/mm.h>
543b9fd3 24#include <linux/suspend.h>
ad7f7167 25#include <linux/hrtimer.h>
d1dead5c 26#ifdef CONFIG_PPC64
14cf11af
PM		 27#include <linux/time.h>
28#include <linux/hardirq.h>
d1dead5c 29#endif
d4d298fe 30#include <linux/kbuild.h>
d1dead5c 31
14cf11af
PM		 32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
14cf11af
PM		 36#include <asm/cputable.h>
37#include <asm/thread_info.h>
033ef338 38#include <asm/rtas.h>
a7f290da 39#include <asm/vdso_datapage.h>
66feed61 40#include <asm/dbell.h>
14cf11af
PM		 41#ifdef CONFIG_PPC64
42#include <asm/paca.h>
43#include <asm/lppaca.h>
14cf11af 44#include <asm/cache.h>
14cf11af 45#include <asm/compat.h>
11a27ad7 46#include <asm/mmu.h>
f04da0bc 47#include <asm/hvcall.h>
19ccb76a 48#include <asm/xics.h>
14cf11af 49#endif
ed79ba9e
BH		 50#ifdef CONFIG_PPC_POWERNV
51#include <asm/opal.h>
52#endif
989044ee 53#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
366d4b9b 54#include <linux/kvm_host.h>
0604675f 55#endif
989044ee
AG		 56#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
57#include <asm/kvm_book3s.h>
5deb8e7a 58#include <asm/kvm_ppc.h>
db93f574 59#endif
14cf11af 60
57e2a99f 61#ifdef CONFIG_PPC32
fca622c5
KG		 62#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
63#include "head_booke.h"
64#endif
57e2a99f 65#endif
fca622c5 66
55fd766b 67#if defined(CONFIG_PPC_FSL_BOOK3E)
19f5465e
TP		 68#include "../mm/mmu_decl.h"
69#endif
70
f86ef74e
CL		 71#ifdef CONFIG_PPC_8xx
72#include <asm/fixmap.h>
73#endif
74
10d4cf18
RG		 75#define STACK_PT_REGS_OFFSET(sym, val) \
76 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
77
14cf11af
PM		 78int main(void)
79{
45465615
RG		 80 OFFSET(THREAD, task_struct, thread);
81 OFFSET(MM, task_struct, mm);
82 OFFSET(MMCONTEXTID, mm_struct, context.id);
14cf11af 83#ifdef CONFIG_PPC64
9c1e1052
PM		 84 DEFINE(SIGSEGV, SIGSEGV);
85 DEFINE(NMI_MASK, NMI_MASK);
45465615 86 OFFSET(TASKTHREADPPR, task_struct, thread.ppr);
d1dead5c 87#else
45465615 88 OFFSET(THREAD_INFO, task_struct, stack);
cbc9565e 89 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
45465615 90 OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
d1dead5c
SR		 91#endif /* CONFIG_PPC64 */
92
85baa095 93#ifdef CONFIG_LIVEPATCH
45465615 94 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
85baa095
ME		 95#endif
96
45465615
RG		 97 OFFSET(KSP, thread_struct, ksp);
98 OFFSET(PT_REGS, thread_struct, regs);
1325a684 99#ifdef CONFIG_BOOKE
45465615 100 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
1325a684 101#endif
45465615 102 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
aa9a9516 103 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
45465615
RG		 104 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
105 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
106 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
14cf11af 107#ifdef CONFIG_ALTIVEC
aa9a9516 108 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
45465615
RG		 109 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
110 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
111 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
112 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
113 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
14cf11af 114#endif /* CONFIG_ALTIVEC */
c6e6771b 115#ifdef CONFIG_VSX
45465615 116 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
c6e6771b 117#endif /* CONFIG_VSX */
d1dead5c 118#ifdef CONFIG_PPC64
45465615 119 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
d1dead5c 120#else /* CONFIG_PPC64 */
45465615 121 OFFSET(PGDIR, thread_struct, pgdir);
14cf11af 122#ifdef CONFIG_SPE
45465615
RG		 123 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
124 OFFSET(THREAD_ACC, thread_struct, acc);
125 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
126 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
14cf11af 127#endif /* CONFIG_SPE */
d1dead5c 128#endif /* CONFIG_PPC64 */
13d543cd 129#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
45465615 130 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
13d543cd 131#endif
97e49255 132#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
45465615 133 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
97e49255 134#endif
ffe129ec 135#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
45465615 136 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
d30f6e48 137#endif
d1dead5c 138
8b3c34cf 139#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
45465615
RG		 140 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
141 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
142 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
143 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
144 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
145 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
146 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
147 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
aa9a9516 148 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
45465615 149 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
aa9a9516 150 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
8b3c34cf
MN		 151 /* Local pt_regs on stack for Transactional Memory funcs. */
152 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
153 sizeof(struct pt_regs) + 16);
154#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2468dcf6 155
45465615
RG		 156 OFFSET(TI_FLAGS, thread_info, flags);
157 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
158 OFFSET(TI_PREEMPT, thread_info, preempt_count);
159 OFFSET(TI_TASK, thread_info, task);
160 OFFSET(TI_CPU, thread_info, cpu);
d1dead5c
SR		 161
162#ifdef CONFIG_PPC64
45465615
RG		 163 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
164 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
165 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
166 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
167 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
168 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
d1dead5c
SR		 169 /* paca */
170 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
45465615
RG		 171 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
172 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
173 OFFSET(PACAKSAVE, paca_struct, kstack);
174 OFFSET(PACACURRENT, paca_struct, __current);
175 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
176 OFFSET(PACASTABRR, paca_struct, stab_rr);
177 OFFSET(PACAR1, paca_struct, saved_r1);
178 OFFSET(PACATOC, paca_struct, kernel_toc);
179 OFFSET(PACAKBASE, paca_struct, kernelbase);
180 OFFSET(PACAKMSR, paca_struct, kernel_msr);
181 OFFSET(PACASOFTIRQEN, paca_struct, soft_enabled);
182 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
c395465d 183#ifdef CONFIG_PPC_BOOK3S
45465615 184 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
d0f13e3c 185#ifdef CONFIG_PPC_MM_SLICES
45465615
RG		 186 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
187 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
bb183221 188 DEFINE(PACA_ADDR_LIMIT, offsetof(struct paca_struct, addr_limit));
d0f13e3c 189 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
91c60b5b 190#endif /* CONFIG_PPC_MM_SLICES */
c395465d 191#endif
dce6670a
BH		 192
193#ifdef CONFIG_PPC_BOOK3E
45465615
RG		 194 OFFSET(PACAPGD, paca_struct, pgd);
195 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
196 OFFSET(PACA_EXGEN, paca_struct, exgen);
197 OFFSET(PACA_EXTLB, paca_struct, extlb);
198 OFFSET(PACA_EXMC, paca_struct, exmc);
199 OFFSET(PACA_EXCRIT, paca_struct, excrit);
200 OFFSET(PACA_EXDBG, paca_struct, exdbg);
201 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
202 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
203 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
204 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
205
206 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
207 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
208 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
dce6670a
BH		 209#endif /* CONFIG_PPC_BOOK3E */
210
91c60b5b 211#ifdef CONFIG_PPC_STD_MMU_64
45465615
RG		 212 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
213 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
214 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
91c60b5b 215#ifdef CONFIG_PPC_MM_SLICES
45465615 216 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
d0f13e3c 217#else
45465615 218 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
d0f13e3c 219#endif /* CONFIG_PPC_MM_SLICES */
45465615
RG		 220 OFFSET(PACA_EXGEN, paca_struct, exgen);
221 OFFSET(PACA_EXMC, paca_struct, exmc);
222 OFFSET(PACA_EXSLB, paca_struct, exslb);
a3d96f70 223 OFFSET(PACA_EXNMI, paca_struct, exnmi);
45465615
RG		 224 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
225 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
226 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
227 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
228 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
229 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
230 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
231 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
232 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
91c60b5b 233#endif /* CONFIG_PPC_STD_MMU_64 */
45465615 234 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
1e9b4507 235#ifdef CONFIG_PPC_BOOK3S_64
45465615 236 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
b1ee8a3d 237 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
45465615 238 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
c4f3b52c 239 OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
45465615
RG		 240#endif
241 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
242 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
243 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
244 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
245 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
b286cedd
LT		 246 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
247 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
45465615
RG		 248 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
249 OFFSET(PACA_NAPSTATELOST, paca_struct, nap_state_lost);
250 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
c223c903
CL		 251#else /* CONFIG_PPC64 */
252#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
45465615
RG		 253 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
254 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
b286cedd
LT		 255 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
256 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
c223c903 257#endif
033ef338 258#endif /* CONFIG_PPC64 */
d1dead5c
SR		 259
260 /* RTAS */
45465615
RG		 261 OFFSET(RTASBASE, rtas_t, base);
262 OFFSET(RTASENTRY, rtas_t, entry);
d1dead5c 263
14cf11af 264 /* Interrupt register frame */
91120cc8 265 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
14cf11af 266 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
218d169c 267#ifdef CONFIG_PPC64
d1dead5c
SR		 268 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
269 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
270 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
271#endif /* CONFIG_PPC64 */
10d4cf18
RG		 272 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
273 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
274 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
275 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
276 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
277 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
278 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
279 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
280 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
281 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
282 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
283 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
284 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
285 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
d1dead5c 286#ifndef CONFIG_PPC64
10d4cf18 287 STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
d1dead5c 288#endif /* CONFIG_PPC64 */
14cf11af
PM		 289 /*
290 * Note: these symbols include _ because they overlap with special
291 * register names
292 */
10d4cf18
RG		 293 STACK_PT_REGS_OFFSET(_NIP, nip);
294 STACK_PT_REGS_OFFSET(_MSR, msr);
295 STACK_PT_REGS_OFFSET(_CTR, ctr);
296 STACK_PT_REGS_OFFSET(_LINK, link);
297 STACK_PT_REGS_OFFSET(_CCR, ccr);
298 STACK_PT_REGS_OFFSET(_XER, xer);
299 STACK_PT_REGS_OFFSET(_DAR, dar);
300 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
301 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
302 STACK_PT_REGS_OFFSET(RESULT, result);
303 STACK_PT_REGS_OFFSET(_TRAP, trap);
d1dead5c 304#ifndef CONFIG_PPC64
d1dead5c
SR		 305 /*
306 * The PowerPC 400-class & Book-E processors have neither the DAR
307 * nor the DSISR SPRs. Hence, we overload them to hold the similar
308 * DEAR and ESR SPRs for such processors. For critical interrupts
309 * we use them to hold SRR0 and SRR1.
14cf11af 310 */
10d4cf18
RG		 311 STACK_PT_REGS_OFFSET(_DEAR, dar);
312 STACK_PT_REGS_OFFSET(_ESR, dsisr);
d1dead5c 313#else /* CONFIG_PPC64 */
10d4cf18 314 STACK_PT_REGS_OFFSET(SOFTE, softe);
d1dead5c
SR		 315
316 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
317 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
318 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
319#endif /* CONFIG_PPC64 */
320
57e2a99f 321#if defined(CONFIG_PPC32)
fca622c5
KG		 322#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
323 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
324 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
325 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
326 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
327 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
328 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
329 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
330 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
331 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
332 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
333 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
334 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
335 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
336 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
337 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
338 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
339#endif
57e2a99f 340#endif
d1dead5c
SR		 341
342#ifndef CONFIG_PPC64
45465615 343 OFFSET(MM_PGD, mm_struct, pgd);
d1dead5c 344#endif /* ! CONFIG_PPC64 */
14cf11af
PM		 345
346 /* About the CPU features table */
45465615
RG		 347 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
348 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
349 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
14cf11af 350
45465615
RG		 351 OFFSET(pbe_address, pbe, address);
352 OFFSET(pbe_orig_address, pbe, orig_address);
353 OFFSET(pbe_next, pbe, next);
14cf11af 354
543b9fd3 355#ifndef CONFIG_PPC64
fd582ec8 356 DEFINE(TASK_SIZE, TASK_SIZE);
d1dead5c 357 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
a7f290da 358#endif /* ! CONFIG_PPC64 */
14cf11af 359
a7f290da 360 /* datapage offsets for use by vdso */
45465615
RG		 361 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
362 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
363 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
364 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
365 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
366 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
367 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
368 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
369 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
370 OFFSET(STAMP_XTIME, vdso_data, stamp_xtime);
371 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
372 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
373 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
374 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
375 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
a7f290da 376#ifdef CONFIG_PPC64
45465615
RG		 377 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
378 OFFSET(TVAL64_TV_SEC, timeval, tv_sec);
379 OFFSET(TVAL64_TV_USEC, timeval, tv_usec);
380 OFFSET(TVAL32_TV_SEC, compat_timeval, tv_sec);
381 OFFSET(TVAL32_TV_USEC, compat_timeval, tv_usec);
382 OFFSET(TSPC64_TV_SEC, timespec, tv_sec);
383 OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec);
384 OFFSET(TSPC32_TV_SEC, compat_timespec, tv_sec);
385 OFFSET(TSPC32_TV_NSEC, compat_timespec, tv_nsec);
a7f290da 386#else
45465615
RG		 387 OFFSET(TVAL32_TV_SEC, timeval, tv_sec);
388 OFFSET(TVAL32_TV_USEC, timeval, tv_usec);
389 OFFSET(TSPC32_TV_SEC, timespec, tv_sec);
390 OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec);
a7f290da
BH		 391#endif
392 /* timeval/timezone offsets for use by vdso */
45465615
RG		 393 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
394 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
a7f290da
BH		 395
396 /* Other bits used by the vdso */
397 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
398 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
399 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
151db1fc 400 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
a7f290da 401
007d88d0
DW		 402#ifdef CONFIG_BUG
403 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
404#endif
16a15a30 405
03dfee6d
ME		 406#ifdef CONFIG_PPC_BOOK3S_64
407 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE)));
dd1842a2 408#else
ee7a76da 409 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
dd1842a2 410#endif
4ee7084e 411 DEFINE(PTE_SIZE, sizeof(pte_t));
bee86f14 412
bbf45ba5 413#ifdef CONFIG_KVM
45465615
RG		 414 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
415 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
416 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
417 OFFSET(VCPU_GPRS, kvm_vcpu, arch.gpr);
418 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
419 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
de56a948 420#ifdef CONFIG_ALTIVEC
45465615 421 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
de56a948 422#endif
45465615
RG		 423 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
424 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
425 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
e14e7a1e 426#ifdef CONFIG_PPC_BOOK3S
45465615 427 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
e14e7a1e 428#endif
45465615
RG		 429 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
430 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
9975f5e3 431#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
45465615
RG		 432 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
433 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
434 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
435 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
436 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
437 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
438 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
b6c295df
PM		 439#endif
440#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
45465615
RG		 441 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
442 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
443 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
444 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
445 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
446 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
447 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
448 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
449 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
450 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
451 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
452#endif
453 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
454 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
455 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
456 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
457 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
458 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
459 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
460 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
461 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
462 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
5deb8e7a 463#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
45465615 464 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
5deb8e7a 465#endif
bbf45ba5 466
45465615
RG		 467 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
468 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
469 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
470 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
471 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
472 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
b5904972 473
45465615
RG		 474 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
475 OFFSET(KVM_LPID, kvm, arch.lpid);
d30f6e48 476
00c3a37c 477 /* book3s */
9975f5e3 478#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
45465615
RG		 479 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
480 OFFSET(KVM_SDR1, kvm, arch.sdr1);
481 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
482 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
483 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
484 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
485 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
486 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
487 OFFSET(KVM_RADIX, kvm, arch.radix);
134764ed 488 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled);
45465615
RG		 489 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
490 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
491 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
492 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
493 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
494 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
495 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
de56a948 496#endif
00c3a37c 497#ifdef CONFIG_PPC_BOOK3S
45465615
RG		 498 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
499 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
500 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
501 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
502 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
503 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
504 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
505 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
506 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
507 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
508 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
509 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
510 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
511 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
512 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
513 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
514 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
515 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
516 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
57900694 517 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
45465615
RG		 518 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
519 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
520 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
521 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
522 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
523 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
524 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
525 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
526 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
527 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
528 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
529 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
530 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
531 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
532 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
533 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
534 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
535 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
536 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
537 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
538 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
539 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
540 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
541 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
542 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
543 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
544 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
545 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
546 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
769377f7 547 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
45465615
RG		 548 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
549 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
550 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
551 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
552 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
553 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
554 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
555 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
556 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
557 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
558 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
de56a948 559 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
7b490411 560#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
45465615
RG		 561 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
562 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
563 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
564 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
565 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
566 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
567 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
568 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
569 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
570 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
571 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
572 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
573 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
574 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
575 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
7b490411 576#endif
3c42bf8a
PM		 577
578#ifdef CONFIG_PPC_BOOK3S_64
7aa79938 579#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
45465615 580 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
3c42bf8a 581# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
de56a948
PM		 582#else
583# define SVCPU_FIELD(x, f)
584#endif
3c42bf8a
PM		 585# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
586#else /* 32-bit */
587# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
588# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
589#endif
590
591 SVCPU_FIELD(SVCPU_CR, cr);
592 SVCPU_FIELD(SVCPU_XER, xer);
593 SVCPU_FIELD(SVCPU_CTR, ctr);
594 SVCPU_FIELD(SVCPU_LR, lr);
595 SVCPU_FIELD(SVCPU_PC, pc);
596 SVCPU_FIELD(SVCPU_R0, gpr[0]);
597 SVCPU_FIELD(SVCPU_R1, gpr[1]);
598 SVCPU_FIELD(SVCPU_R2, gpr[2]);
599 SVCPU_FIELD(SVCPU_R3, gpr[3]);
600 SVCPU_FIELD(SVCPU_R4, gpr[4]);
601 SVCPU_FIELD(SVCPU_R5, gpr[5]);
602 SVCPU_FIELD(SVCPU_R6, gpr[6]);
603 SVCPU_FIELD(SVCPU_R7, gpr[7]);
604 SVCPU_FIELD(SVCPU_R8, gpr[8]);
605 SVCPU_FIELD(SVCPU_R9, gpr[9]);
606 SVCPU_FIELD(SVCPU_R10, gpr[10]);
607 SVCPU_FIELD(SVCPU_R11, gpr[11]);
608 SVCPU_FIELD(SVCPU_R12, gpr[12]);
609 SVCPU_FIELD(SVCPU_R13, gpr[13]);
610 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
611 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
612 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
613 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0604675f 614#ifdef CONFIG_PPC_BOOK3S_32
3c42bf8a 615 SVCPU_FIELD(SVCPU_SR, sr);
0604675f 616#endif
3c42bf8a
PM		 617#ifdef CONFIG_PPC64
618 SVCPU_FIELD(SVCPU_SLB, slb);
619 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
616dff86 620 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
3c42bf8a
PM		 621#endif
622
623 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
624 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
de56a948 625 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
3c42bf8a
PM		 626 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
627 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
628 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
36e7bb38 629 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
3c42bf8a 630 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
02143947 631 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
19ccb76a 632 HSTATE_FIELD(HSTATE_NAPPING, napping);
3c42bf8a 633
9975f5e3 634#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
7657f408
PM		 635 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
636 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
de56a948 637 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
371fefd6
PM		 638 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
639 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
5af50993
BH		 640 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
641 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
54695c30
BH		 642 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
643 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
e0b7ec05 644 HSTATE_FIELD(HSTATE_PTID, ptid);
c0101509 645 HSTATE_FIELD(HSTATE_TID, tid);
9a4fc4ea
ME		 646 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
647 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
648 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
649 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
650 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
651 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
652 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
653 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
654 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
655 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
656 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
657 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
658 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
de56a948
PM		 659 HSTATE_FIELD(HSTATE_PURR, host_purr);
660 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
661 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
662 HSTATE_FIELD(HSTATE_DABR, dabr);
663 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
b4deba5c 664 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
19ccb76a 665 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
45465615
RG		 666 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
667 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
668 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
669 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
670 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
c0101509
PM		 671 OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set);
672 OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore);
9975f5e3 673#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
de56a948 674
0acb9111
PM		 675#ifdef CONFIG_PPC_BOOK3S_64
676 HSTATE_FIELD(HSTATE_CFAR, cfar);
4b8473c9 677 HSTATE_FIELD(HSTATE_PPR, ppr);
616dff86 678 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
0acb9111
PM		 679#endif /* CONFIG_PPC_BOOK3S_64 */
680
3c42bf8a 681#else /* CONFIG_PPC_BOOK3S */
45465615
RG		 682 OFFSET(VCPU_CR, kvm_vcpu, arch.cr);
683 OFFSET(VCPU_XER, kvm_vcpu, arch.xer);
684 OFFSET(VCPU_LR, kvm_vcpu, arch.lr);
685 OFFSET(VCPU_CTR, kvm_vcpu, arch.ctr);
686 OFFSET(VCPU_PC, kvm_vcpu, arch.pc);
687 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
688 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
689 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
690 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
691 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
00c3a37c 692#endif /* CONFIG_PPC_BOOK3S */
3c42bf8a 693#endif /* CONFIG_KVM */
d17051cb
AG		 694
695#ifdef CONFIG_KVM_GUEST
45465615
RG		 696 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
697 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
698 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
699 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
700 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
701 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
702 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
d17051cb
AG		 703#endif
704
ca9153a3
IY		 705#ifdef CONFIG_44x
706 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
707 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
708#endif
55fd766b 709#ifdef CONFIG_PPC_FSL_BOOK3E
78f62237 710 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
45465615
RG		 711 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
712 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
713 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
714 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
715 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
78f62237 716#endif
bbf45ba5 717
4cd35f67 718#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
45465615
RG		 719 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
720 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
721 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
722 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
4cd35f67
SW		 723#endif
724
d30f6e48 725#ifdef CONFIG_KVM_BOOKE_HV
45465615
RG		 726 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
727 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
d30f6e48
SW		 728#endif
729
5af50993
BH		 730#ifdef CONFIG_KVM_XICS
731 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
732 arch.xive_saved_state));
733 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
734 arch.xive_cam_word));
735 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
736#endif
737
73e75b41 738#ifdef CONFIG_KVM_EXIT_TIMING
45465615
RG		 739 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
740 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
741 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
742 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
73e75b41
HB		 743#endif
744
7cba160a 745#ifdef CONFIG_PPC_POWERNV
45465615
RG		 746 OFFSET(PACA_CORE_IDLE_STATE_PTR, paca_struct, core_idle_state_ptr);
747 OFFSET(PACA_THREAD_IDLE_STATE, paca_struct, thread_idle_state);
748 OFFSET(PACA_THREAD_MASK, paca_struct, thread_mask);
749 OFFSET(PACA_SUBCORE_SIBLING_MASK, paca_struct, subcore_sibling_mask);
17ed4c8f 750 OFFSET(PACA_SIBLING_PACA_PTRS, paca_struct, thread_sibling_pacas);
22c6663d 751 OFFSET(PACA_REQ_PSSCR, paca_struct, requested_psscr);
e1c1cfed
GS		 752#define STOP_SPR(x, f) OFFSET(x, paca_struct, stop_sprs.f)
753 STOP_SPR(STOP_PID, pid);
754 STOP_SPR(STOP_LDBAR, ldbar);
755 STOP_SPR(STOP_FSCR, fscr);
756 STOP_SPR(STOP_HFSCR, hfscr);
757 STOP_SPR(STOP_MMCR1, mmcr1);
758 STOP_SPR(STOP_MMCR2, mmcr2);
759 STOP_SPR(STOP_MMCRA, mmcra);
7cba160a
SP		 760#endif
761
66feed61 762 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
a9af97aa 763 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE);
66feed61 764
f86ef74e 765#ifdef CONFIG_PPC_8xx
9f595fd8 766 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
f86ef74e
CL		 767#endif
768
14cf11af
PM		 769 return 0;
770}
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