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KVM: PPC: Book3S PR: Expose TAR facility to guest
[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / asm-offsets.c
CommitLineData
14cf11af
PM		 1/*
2 * This program is used to generate definitions needed by
3 * assembly language modules.
4 *
5 * We use the technique used in the OSF Mach kernel code:
6 * generate asm statements containing #defines,
7 * compile this file to assembler, and then extract the
8 * #defines from the assembly-language output.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
14cf11af
PM		 16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/errno.h>
20#include <linux/string.h>
21#include <linux/types.h>
14cf11af
PM		 22#include <linux/mman.h>
23#include <linux/mm.h>
543b9fd3 24#include <linux/suspend.h>
ad7f7167 25#include <linux/hrtimer.h>
d1dead5c 26#ifdef CONFIG_PPC64
14cf11af
PM		 27#include <linux/time.h>
28#include <linux/hardirq.h>
d1dead5c 29#endif
d4d298fe 30#include <linux/kbuild.h>
d1dead5c 31
14cf11af
PM		 32#include <asm/io.h>
33#include <asm/page.h>
34#include <asm/pgtable.h>
35#include <asm/processor.h>
14cf11af
PM		 36#include <asm/cputable.h>
37#include <asm/thread_info.h>
033ef338 38#include <asm/rtas.h>
a7f290da 39#include <asm/vdso_datapage.h>
14cf11af
PM		 40#ifdef CONFIG_PPC64
41#include <asm/paca.h>
42#include <asm/lppaca.h>
14cf11af 43#include <asm/cache.h>
14cf11af 44#include <asm/compat.h>
11a27ad7 45#include <asm/mmu.h>
f04da0bc 46#include <asm/hvcall.h>
19ccb76a 47#include <asm/xics.h>
14cf11af 48#endif
ed79ba9e
BH		 49#ifdef CONFIG_PPC_POWERNV
50#include <asm/opal.h>
51#endif
989044ee 52#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
366d4b9b 53#include <linux/kvm_host.h>
0604675f 54#endif
989044ee
AG		 55#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
56#include <asm/kvm_book3s.h>
5deb8e7a 57#include <asm/kvm_ppc.h>
db93f574 58#endif
14cf11af 59
57e2a99f 60#ifdef CONFIG_PPC32
fca622c5
KG		 61#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
62#include "head_booke.h"
63#endif
57e2a99f 64#endif
fca622c5 65
55fd766b 66#if defined(CONFIG_PPC_FSL_BOOK3E)
19f5465e
TP		 67#include "../mm/mmu_decl.h"
68#endif
69
14cf11af
PM		 70int main(void)
71{
d1dead5c
SR		 72 DEFINE(THREAD, offsetof(struct task_struct, thread));
73 DEFINE(MM, offsetof(struct task_struct, mm));
5e696617 74 DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
14cf11af 75#ifdef CONFIG_PPC64
d1dead5c 76 DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
9c1e1052
PM		 77 DEFINE(SIGSEGV, SIGSEGV);
78 DEFINE(NMI_MASK, NMI_MASK);
efcac658 79 DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr));
71433285 80 DEFINE(THREAD_DSCR_INHERIT, offsetof(struct thread_struct, dscr_inherit));
92779245 81 DEFINE(TASKTHREADPPR, offsetof(struct task_struct, thread.ppr));
d1dead5c 82#else
f7e4217b 83 DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
cbc9565e
BH		 84 DEFINE(THREAD_INFO_GAP, _ALIGN_UP(sizeof(struct thread_info), 16));
85 DEFINE(KSP_LIMIT, offsetof(struct thread_struct, ksp_limit));
d1dead5c
SR		 86#endif /* CONFIG_PPC64 */
87
14cf11af 88 DEFINE(KSP, offsetof(struct thread_struct, ksp));
14cf11af 89 DEFINE(PT_REGS, offsetof(struct thread_struct, regs));
1325a684
AK		 90#ifdef CONFIG_BOOKE
91 DEFINE(THREAD_NORMSAVES, offsetof(struct thread_struct, normsave[0]));
92#endif
14cf11af 93 DEFINE(THREAD_FPEXC_MODE, offsetof(struct thread_struct, fpexc_mode));
de79f7b9 94 DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fp_state));
18461960 95 DEFINE(THREAD_FPSAVEAREA, offsetof(struct thread_struct, fp_save_area));
de79f7b9 96 DEFINE(FPSTATE_FPSCR, offsetof(struct thread_fp_state, fpscr));
14cf11af 97#ifdef CONFIG_ALTIVEC
de79f7b9 98 DEFINE(THREAD_VRSTATE, offsetof(struct thread_struct, vr_state));
18461960 99 DEFINE(THREAD_VRSAVEAREA, offsetof(struct thread_struct, vr_save_area));
14cf11af 100 DEFINE(THREAD_VRSAVE, offsetof(struct thread_struct, vrsave));
14cf11af 101 DEFINE(THREAD_USED_VR, offsetof(struct thread_struct, used_vr));
de79f7b9 102 DEFINE(VRSTATE_VSCR, offsetof(struct thread_vr_state, vscr));
14cf11af 103#endif /* CONFIG_ALTIVEC */
c6e6771b 104#ifdef CONFIG_VSX
c6e6771b
MN		 105 DEFINE(THREAD_USED_VSR, offsetof(struct thread_struct, used_vsr));
106#endif /* CONFIG_VSX */
d1dead5c
SR		 107#ifdef CONFIG_PPC64
108 DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid));
109#else /* CONFIG_PPC64 */
110 DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
14cf11af
PM		 111#ifdef CONFIG_SPE
112 DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
113 DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc));
114 DEFINE(THREAD_SPEFSCR, offsetof(struct thread_struct, spefscr));
115 DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe));
116#endif /* CONFIG_SPE */
d1dead5c 117#endif /* CONFIG_PPC64 */
13d543cd 118#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
51ae8d4a 119 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0));
13d543cd 120#endif
97e49255
AG		 121#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
122 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
123#endif
ffe129ec 124#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
d30f6e48
SW		 125 DEFINE(THREAD_KVM_VCPU, offsetof(struct thread_struct, kvm_vcpu));
126#endif
d1dead5c 127
2468dcf6
IM		 128#ifdef CONFIG_PPC_BOOK3S_64
129 DEFINE(THREAD_TAR, offsetof(struct thread_struct, tar));
9353374b
ME		 130 DEFINE(THREAD_BESCR, offsetof(struct thread_struct, bescr));
131 DEFINE(THREAD_EBBHR, offsetof(struct thread_struct, ebbhr));
132 DEFINE(THREAD_EBBRR, offsetof(struct thread_struct, ebbrr));
59affcd3
ME		 133 DEFINE(THREAD_SIAR, offsetof(struct thread_struct, siar));
134 DEFINE(THREAD_SDAR, offsetof(struct thread_struct, sdar));
135 DEFINE(THREAD_SIER, offsetof(struct thread_struct, sier));
136 DEFINE(THREAD_MMCR0, offsetof(struct thread_struct, mmcr0));
137 DEFINE(THREAD_MMCR2, offsetof(struct thread_struct, mmcr2));
2468dcf6 138#endif
8b3c34cf 139#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
afc07701 140 DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
8b3c34cf
MN		 141 DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
142 DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
143 DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
28e61cc4
MN		 144 DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
145 DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
146 DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
8b3c34cf 147 DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
de79f7b9
PM		 148 DEFINE(THREAD_TRANSACT_VRSTATE, offsetof(struct thread_struct,
149 transact_vr));
8b3c34cf
MN		 150 DEFINE(THREAD_TRANSACT_VRSAVE, offsetof(struct thread_struct,
151 transact_vrsave));
de79f7b9
PM		 152 DEFINE(THREAD_TRANSACT_FPSTATE, offsetof(struct thread_struct,
153 transact_fp));
8b3c34cf
MN		 154 /* Local pt_regs on stack for Transactional Memory funcs. */
155 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
156 sizeof(struct pt_regs) + 16);
157#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2468dcf6 158
d1dead5c 159 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
f39224a8 160 DEFINE(TI_LOCAL_FLAGS, offsetof(struct thread_info, local_flags));
d1dead5c 161 DEFINE(TI_PREEMPT, offsetof(struct thread_info, preempt_count));
d1dead5c 162 DEFINE(TI_TASK, offsetof(struct thread_info, task));
d1dead5c 163 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
d1dead5c
SR		 164
165#ifdef CONFIG_PPC64
166 DEFINE(DCACHEL1LINESIZE, offsetof(struct ppc64_caches, dline_size));
167 DEFINE(DCACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_dline_size));
168 DEFINE(DCACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, dlines_per_page));
169 DEFINE(ICACHEL1LINESIZE, offsetof(struct ppc64_caches, iline_size));
170 DEFINE(ICACHEL1LOGLINESIZE, offsetof(struct ppc64_caches, log_iline_size));
171 DEFINE(ICACHEL1LINESPERPAGE, offsetof(struct ppc64_caches, ilines_per_page));
d1dead5c
SR		 172 /* paca */
173 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
9e368f29 174 DEFINE(PACA_LOCK_TOKEN, offsetof(struct paca_struct, lock_token));
d1dead5c
SR		 175 DEFINE(PACAPACAINDEX, offsetof(struct paca_struct, paca_index));
176 DEFINE(PACAPROCSTART, offsetof(struct paca_struct, cpu_start));
177 DEFINE(PACAKSAVE, offsetof(struct paca_struct, kstack));
178 DEFINE(PACACURRENT, offsetof(struct paca_struct, __current));
179 DEFINE(PACASAVEDMSR, offsetof(struct paca_struct, saved_msr));
d1dead5c
SR		 180 DEFINE(PACASTABRR, offsetof(struct paca_struct, stab_rr));
181 DEFINE(PACAR1, offsetof(struct paca_struct, saved_r1));
182 DEFINE(PACATOC, offsetof(struct paca_struct, kernel_toc));
1f6a93e4
PM		 183 DEFINE(PACAKBASE, offsetof(struct paca_struct, kernelbase));
184 DEFINE(PACAKMSR, offsetof(struct paca_struct, kernel_msr));
d04c56f7 185 DEFINE(PACASOFTIRQEN, offsetof(struct paca_struct, soft_enabled));
7230c564 186 DEFINE(PACAIRQHAPPENED, offsetof(struct paca_struct, irq_happened));
d1dead5c 187 DEFINE(PACACONTEXTID, offsetof(struct paca_struct, context.id));
d0f13e3c
BH		 188#ifdef CONFIG_PPC_MM_SLICES
189 DEFINE(PACALOWSLICESPSIZE, offsetof(struct paca_struct,
190 context.low_slices_psize));
191 DEFINE(PACAHIGHSLICEPSIZE, offsetof(struct paca_struct,
192 context.high_slices_psize));
193 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
91c60b5b 194#endif /* CONFIG_PPC_MM_SLICES */
dce6670a
BH		 195
196#ifdef CONFIG_PPC_BOOK3E
197 DEFINE(PACAPGD, offsetof(struct paca_struct, pgd));
198 DEFINE(PACA_KERNELPGD, offsetof(struct paca_struct, kernel_pgd));
199 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
200 DEFINE(PACA_EXTLB, offsetof(struct paca_struct, extlb));
201 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
202 DEFINE(PACA_EXCRIT, offsetof(struct paca_struct, excrit));
203 DEFINE(PACA_EXDBG, offsetof(struct paca_struct, exdbg));
204 DEFINE(PACA_MC_STACK, offsetof(struct paca_struct, mc_kstack));
205 DEFINE(PACA_CRIT_STACK, offsetof(struct paca_struct, crit_kstack));
206 DEFINE(PACA_DBG_STACK, offsetof(struct paca_struct, dbg_kstack));
28efc35f
SW		 207 DEFINE(PACA_TCD_PTR, offsetof(struct paca_struct, tcd_ptr));
208
209 DEFINE(TCD_ESEL_NEXT,
210 offsetof(struct tlb_core_data, esel_next));
211 DEFINE(TCD_ESEL_MAX,
212 offsetof(struct tlb_core_data, esel_max));
213 DEFINE(TCD_ESEL_FIRST,
214 offsetof(struct tlb_core_data, esel_first));
215 DEFINE(TCD_LOCK, offsetof(struct tlb_core_data, lock));
dce6670a
BH		 216#endif /* CONFIG_PPC_BOOK3E */
217
91c60b5b
BH		 218#ifdef CONFIG_PPC_STD_MMU_64
219 DEFINE(PACASTABREAL, offsetof(struct paca_struct, stab_real));
220 DEFINE(PACASTABVIRT, offsetof(struct paca_struct, stab_addr));
221 DEFINE(PACASLBCACHE, offsetof(struct paca_struct, slb_cache));
222 DEFINE(PACASLBCACHEPTR, offsetof(struct paca_struct, slb_cache_ptr));
223 DEFINE(PACAVMALLOCSLLP, offsetof(struct paca_struct, vmalloc_sllp));
224#ifdef CONFIG_PPC_MM_SLICES
d0f13e3c
BH		 225 DEFINE(MMUPSIZESLLP, offsetof(struct mmu_psize_def, sllp));
226#else
227 DEFINE(PACACONTEXTSLLP, offsetof(struct paca_struct, context.sllp));
d0f13e3c 228#endif /* CONFIG_PPC_MM_SLICES */
d1dead5c
SR		 229 DEFINE(PACA_EXGEN, offsetof(struct paca_struct, exgen));
230 DEFINE(PACA_EXMC, offsetof(struct paca_struct, exmc));
231 DEFINE(PACA_EXSLB, offsetof(struct paca_struct, exslb));
3356bb9f 232 DEFINE(PACALPPACAPTR, offsetof(struct paca_struct, lppaca_ptr));
2f6093c8 233 DEFINE(PACA_SLBSHADOWPTR, offsetof(struct paca_struct, slb_shadow_ptr));
11a27ad7
MN		 234 DEFINE(SLBSHADOW_STACKVSID,
235 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid));
236 DEFINE(SLBSHADOW_STACKESID,
237 offsetof(struct slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid));
cf9efce0 238 DEFINE(SLBSHADOW_SAVEAREA, offsetof(struct slb_shadow, save_area));
de56a948 239 DEFINE(LPPACA_PMCINUSE, offsetof(struct lppaca, pmcregs_in_use));
cf9efce0 240 DEFINE(LPPACA_DTLIDX, offsetof(struct lppaca, dtl_idx));
a8606e20 241 DEFINE(LPPACA_YIELDCOUNT, offsetof(struct lppaca, yield_count));
cf9efce0 242 DEFINE(PACA_DTL_RIDX, offsetof(struct paca_struct, dtl_ridx));
91c60b5b
BH		 243#endif /* CONFIG_PPC_STD_MMU_64 */
244 DEFINE(PACAEMERGSP, offsetof(struct paca_struct, emergency_sp));
1e9b4507
MS		 245#ifdef CONFIG_PPC_BOOK3S_64
246 DEFINE(PACAMCEMERGSP, offsetof(struct paca_struct, mc_emergency_sp));
247 DEFINE(PACA_IN_MCE, offsetof(struct paca_struct, in_mce));
248#endif
91c60b5b 249 DEFINE(PACAHWCPUID, offsetof(struct paca_struct, hw_cpu_id));
1fc711f7 250 DEFINE(PACAKEXECSTATE, offsetof(struct paca_struct, kexec_state));
cf9efce0
PM		 251 DEFINE(PACA_STARTTIME, offsetof(struct paca_struct, starttime));
252 DEFINE(PACA_STARTTIME_USER, offsetof(struct paca_struct, starttime_user));
91c60b5b
BH		 253 DEFINE(PACA_USER_TIME, offsetof(struct paca_struct, user_time));
254 DEFINE(PACA_SYSTEM_TIME, offsetof(struct paca_struct, system_time));
91c60b5b 255 DEFINE(PACA_TRAP_SAVE, offsetof(struct paca_struct, trap_save));
2fde6d20 256 DEFINE(PACA_NAPSTATELOST, offsetof(struct paca_struct, nap_state_lost));
9d378dfa 257 DEFINE(PACA_SPRG_VDSO, offsetof(struct paca_struct, sprg_vdso));
033ef338 258#endif /* CONFIG_PPC64 */
d1dead5c
SR		 259
260 /* RTAS */
261 DEFINE(RTASBASE, offsetof(struct rtas_t, base));
262 DEFINE(RTASENTRY, offsetof(struct rtas_t, entry));
d1dead5c 263
14cf11af 264 /* Interrupt register frame */
91120cc8 265 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
14cf11af 266 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
218d169c 267#ifdef CONFIG_PPC64
d1dead5c
SR		 268 /* Create extra stack space for SRR0 and SRR1 when calling prom/rtas. */
269 DEFINE(PROM_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
270 DEFINE(RTAS_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs) + 16);
57852a85
MK		 271
272 /* hcall statistics */
273 DEFINE(HCALL_STAT_SIZE, sizeof(struct hcall_stats));
274 DEFINE(HCALL_STAT_CALLS, offsetof(struct hcall_stats, num_calls));
275 DEFINE(HCALL_STAT_TB, offsetof(struct hcall_stats, tb_total));
276 DEFINE(HCALL_STAT_PURR, offsetof(struct hcall_stats, purr_total));
d1dead5c 277#endif /* CONFIG_PPC64 */
14cf11af
PM		 278 DEFINE(GPR0, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[0]));
279 DEFINE(GPR1, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[1]));
280 DEFINE(GPR2, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[2]));
281 DEFINE(GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[3]));
282 DEFINE(GPR4, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[4]));
283 DEFINE(GPR5, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[5]));
284 DEFINE(GPR6, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[6]));
285 DEFINE(GPR7, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[7]));
286 DEFINE(GPR8, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[8]));
287 DEFINE(GPR9, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[9]));
288 DEFINE(GPR10, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[10]));
289 DEFINE(GPR11, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[11]));
290 DEFINE(GPR12, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[12]));
291 DEFINE(GPR13, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[13]));
d1dead5c 292#ifndef CONFIG_PPC64
14cf11af
PM		 293 DEFINE(GPR14, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[14]));
294 DEFINE(GPR15, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[15]));
295 DEFINE(GPR16, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[16]));
296 DEFINE(GPR17, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[17]));
297 DEFINE(GPR18, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[18]));
298 DEFINE(GPR19, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[19]));
299 DEFINE(GPR20, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[20]));
300 DEFINE(GPR21, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[21]));
301 DEFINE(GPR22, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[22]));
302 DEFINE(GPR23, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[23]));
303 DEFINE(GPR24, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[24]));
304 DEFINE(GPR25, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[25]));
305 DEFINE(GPR26, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[26]));
306 DEFINE(GPR27, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[27]));
307 DEFINE(GPR28, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[28]));
308 DEFINE(GPR29, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[29]));
309 DEFINE(GPR30, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[30]));
310 DEFINE(GPR31, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, gpr[31]));
d1dead5c 311#endif /* CONFIG_PPC64 */
14cf11af
PM		 312 /*
313 * Note: these symbols include _ because they overlap with special
314 * register names
315 */
316 DEFINE(_NIP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, nip));
317 DEFINE(_MSR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, msr));
318 DEFINE(_CTR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ctr));
319 DEFINE(_LINK, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, link));
320 DEFINE(_CCR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, ccr));
14cf11af
PM		 321 DEFINE(_XER, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, xer));
322 DEFINE(_DAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
323 DEFINE(_DSISR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c
SR		 324 DEFINE(ORIG_GPR3, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, orig_gpr3));
325 DEFINE(RESULT, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, result));
d73e0c99 326 DEFINE(_TRAP, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, trap));
d1dead5c
SR		 327#ifndef CONFIG_PPC64
328 DEFINE(_MQ, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, mq));
329 /*
330 * The PowerPC 400-class & Book-E processors have neither the DAR
331 * nor the DSISR SPRs. Hence, we overload them to hold the similar
332 * DEAR and ESR SPRs for such processors. For critical interrupts
333 * we use them to hold SRR0 and SRR1.
14cf11af
PM		 334 */
335 DEFINE(_DEAR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dar));
336 DEFINE(_ESR, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, dsisr));
d1dead5c 337#else /* CONFIG_PPC64 */
d1dead5c
SR		 338 DEFINE(SOFTE, STACK_FRAME_OVERHEAD+offsetof(struct pt_regs, softe));
339
340 /* These _only_ to be used with {PROM,RTAS}_FRAME_SIZE!!! */
341 DEFINE(_SRR0, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs));
342 DEFINE(_SRR1, STACK_FRAME_OVERHEAD+sizeof(struct pt_regs)+8);
343#endif /* CONFIG_PPC64 */
344
57e2a99f 345#if defined(CONFIG_PPC32)
fca622c5
KG		 346#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
347 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
348 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
349 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
350 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
351 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
352 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
353 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
354 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
355 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
356 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
357 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
358 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
359 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
360 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
361 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
362 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
363#endif
57e2a99f 364#endif
14cf11af
PM		 365 DEFINE(CLONE_VM, CLONE_VM);
366 DEFINE(CLONE_UNTRACED, CLONE_UNTRACED);
d1dead5c
SR		 367
368#ifndef CONFIG_PPC64
14cf11af 369 DEFINE(MM_PGD, offsetof(struct mm_struct, pgd));
d1dead5c 370#endif /* ! CONFIG_PPC64 */
14cf11af
PM		 371
372 /* About the CPU features table */
14cf11af
PM		 373 DEFINE(CPU_SPEC_FEATURES, offsetof(struct cpu_spec, cpu_features));
374 DEFINE(CPU_SPEC_SETUP, offsetof(struct cpu_spec, cpu_setup));
f39b7a55 375 DEFINE(CPU_SPEC_RESTORE, offsetof(struct cpu_spec, cpu_restore));
14cf11af 376
d1dead5c
SR		 377 DEFINE(pbe_address, offsetof(struct pbe, address));
378 DEFINE(pbe_orig_address, offsetof(struct pbe, orig_address));
379 DEFINE(pbe_next, offsetof(struct pbe, next));
14cf11af 380
543b9fd3 381#ifndef CONFIG_PPC64
fd582ec8 382 DEFINE(TASK_SIZE, TASK_SIZE);
d1dead5c 383 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
a7f290da 384#endif /* ! CONFIG_PPC64 */
14cf11af 385
a7f290da
BH		 386 /* datapage offsets for use by vdso */
387 DEFINE(CFG_TB_ORIG_STAMP, offsetof(struct vdso_data, tb_orig_stamp));
388 DEFINE(CFG_TB_TICKS_PER_SEC, offsetof(struct vdso_data, tb_ticks_per_sec));
389 DEFINE(CFG_TB_TO_XS, offsetof(struct vdso_data, tb_to_xs));
390 DEFINE(CFG_STAMP_XSEC, offsetof(struct vdso_data, stamp_xsec));
391 DEFINE(CFG_TB_UPDATE_COUNT, offsetof(struct vdso_data, tb_update_count));
392 DEFINE(CFG_TZ_MINUTEWEST, offsetof(struct vdso_data, tz_minuteswest));
393 DEFINE(CFG_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
394 DEFINE(CFG_SYSCALL_MAP32, offsetof(struct vdso_data, syscall_map_32));
395 DEFINE(WTOM_CLOCK_SEC, offsetof(struct vdso_data, wtom_clock_sec));
396 DEFINE(WTOM_CLOCK_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
597bc5c0 397 DEFINE(STAMP_XTIME, offsetof(struct vdso_data, stamp_xtime));
8fd63a9e 398 DEFINE(STAMP_SEC_FRAC, offsetof(struct vdso_data, stamp_sec_fraction));
fbe48175
OJ		 399 DEFINE(CFG_ICACHE_BLOCKSZ, offsetof(struct vdso_data, icache_block_size));
400 DEFINE(CFG_DCACHE_BLOCKSZ, offsetof(struct vdso_data, dcache_block_size));
401 DEFINE(CFG_ICACHE_LOGBLOCKSZ, offsetof(struct vdso_data, icache_log_block_size));
402 DEFINE(CFG_DCACHE_LOGBLOCKSZ, offsetof(struct vdso_data, dcache_log_block_size));
a7f290da
BH		 403#ifdef CONFIG_PPC64
404 DEFINE(CFG_SYSCALL_MAP64, offsetof(struct vdso_data, syscall_map_64));
14cf11af
PM		 405 DEFINE(TVAL64_TV_SEC, offsetof(struct timeval, tv_sec));
406 DEFINE(TVAL64_TV_USEC, offsetof(struct timeval, tv_usec));
407 DEFINE(TVAL32_TV_SEC, offsetof(struct compat_timeval, tv_sec));
408 DEFINE(TVAL32_TV_USEC, offsetof(struct compat_timeval, tv_usec));
0c37ec2a
BH		 409 DEFINE(TSPC64_TV_SEC, offsetof(struct timespec, tv_sec));
410 DEFINE(TSPC64_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 411 DEFINE(TSPC32_TV_SEC, offsetof(struct compat_timespec, tv_sec));
412 DEFINE(TSPC32_TV_NSEC, offsetof(struct compat_timespec, tv_nsec));
413#else
414 DEFINE(TVAL32_TV_SEC, offsetof(struct timeval, tv_sec));
415 DEFINE(TVAL32_TV_USEC, offsetof(struct timeval, tv_usec));
0c37ec2a
BH		 416 DEFINE(TSPC32_TV_SEC, offsetof(struct timespec, tv_sec));
417 DEFINE(TSPC32_TV_NSEC, offsetof(struct timespec, tv_nsec));
a7f290da
BH		 418#endif
419 /* timeval/timezone offsets for use by vdso */
14cf11af
PM		 420 DEFINE(TZONE_TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
421 DEFINE(TZONE_TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
a7f290da
BH		 422
423 /* Other bits used by the vdso */
424 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
425 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
426 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
151db1fc 427 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
a7f290da 428
007d88d0
DW		 429#ifdef CONFIG_BUG
430 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
431#endif
16a15a30 432
ee7a76da 433 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
4ee7084e 434 DEFINE(PTE_SIZE, sizeof(pte_t));
bee86f14 435
bbf45ba5 436#ifdef CONFIG_KVM
bbf45ba5
HB		 437 DEFINE(VCPU_HOST_STACK, offsetof(struct kvm_vcpu, arch.host_stack));
438 DEFINE(VCPU_HOST_PID, offsetof(struct kvm_vcpu, arch.host_pid));
d30f6e48 439 DEFINE(VCPU_GUEST_PID, offsetof(struct kvm_vcpu, arch.pid));
bbf45ba5 440 DEFINE(VCPU_GPRS, offsetof(struct kvm_vcpu, arch.gpr));
eab17672 441 DEFINE(VCPU_VRSAVE, offsetof(struct kvm_vcpu, arch.vrsave));
efff1912 442 DEFINE(VCPU_FPRS, offsetof(struct kvm_vcpu, arch.fp.fpr));
de56a948 443#ifdef CONFIG_ALTIVEC
efff1912 444 DEFINE(VCPU_VRS, offsetof(struct kvm_vcpu, arch.vr.vr));
de56a948
PM		 445#endif
446 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
447 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
448 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
e14e7a1e 449#ifdef CONFIG_PPC_BOOK3S
b005255e 450 DEFINE(VCPU_TAR, offsetof(struct kvm_vcpu, arch.tar));
e14e7a1e 451#endif
de56a948
PM		 452 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
453 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
9975f5e3 454#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
de56a948
PM		 455 DEFINE(VCPU_MSR, offsetof(struct kvm_vcpu, arch.shregs.msr));
456 DEFINE(VCPU_SRR0, offsetof(struct kvm_vcpu, arch.shregs.srr0));
457 DEFINE(VCPU_SRR1, offsetof(struct kvm_vcpu, arch.shregs.srr1));
458 DEFINE(VCPU_SPRG0, offsetof(struct kvm_vcpu, arch.shregs.sprg0));
459 DEFINE(VCPU_SPRG1, offsetof(struct kvm_vcpu, arch.shregs.sprg1));
460 DEFINE(VCPU_SPRG2, offsetof(struct kvm_vcpu, arch.shregs.sprg2));
461 DEFINE(VCPU_SPRG3, offsetof(struct kvm_vcpu, arch.shregs.sprg3));
462#endif
c8ae0ace 463 DEFINE(VCPU_SHARED_SPRG3, offsetof(struct kvm_vcpu_arch_shared, sprg3));
b5904972
SW		 464 DEFINE(VCPU_SHARED_SPRG4, offsetof(struct kvm_vcpu_arch_shared, sprg4));
465 DEFINE(VCPU_SHARED_SPRG5, offsetof(struct kvm_vcpu_arch_shared, sprg5));
466 DEFINE(VCPU_SHARED_SPRG6, offsetof(struct kvm_vcpu_arch_shared, sprg6));
467 DEFINE(VCPU_SHARED_SPRG7, offsetof(struct kvm_vcpu_arch_shared, sprg7));
49dd2c49 468 DEFINE(VCPU_SHADOW_PID, offsetof(struct kvm_vcpu, arch.shadow_pid));
dd9ebf1f 469 DEFINE(VCPU_SHADOW_PID1, offsetof(struct kvm_vcpu, arch.shadow_pid1));
96bc451a 470 DEFINE(VCPU_SHARED, offsetof(struct kvm_vcpu, arch.shared));
666e7252 471 DEFINE(VCPU_SHARED_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
ecee273f 472 DEFINE(VCPU_SHADOW_MSR, offsetof(struct kvm_vcpu, arch.shadow_msr));
5deb8e7a
AG		 473#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
474 DEFINE(VCPU_SHAREDBE, offsetof(struct kvm_vcpu, arch.shared_big_endian));
475#endif
bbf45ba5 476
b5904972
SW		 477 DEFINE(VCPU_SHARED_MAS0, offsetof(struct kvm_vcpu_arch_shared, mas0));
478 DEFINE(VCPU_SHARED_MAS1, offsetof(struct kvm_vcpu_arch_shared, mas1));
479 DEFINE(VCPU_SHARED_MAS2, offsetof(struct kvm_vcpu_arch_shared, mas2));
480 DEFINE(VCPU_SHARED_MAS7_3, offsetof(struct kvm_vcpu_arch_shared, mas7_3));
481 DEFINE(VCPU_SHARED_MAS4, offsetof(struct kvm_vcpu_arch_shared, mas4));
482 DEFINE(VCPU_SHARED_MAS6, offsetof(struct kvm_vcpu_arch_shared, mas6));
483
d30f6e48
SW		 484 DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
485 DEFINE(KVM_LPID, offsetof(struct kvm, arch.lpid));
486
00c3a37c 487 /* book3s */
9975f5e3 488#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
de56a948
PM		 489 DEFINE(KVM_SDR1, offsetof(struct kvm, arch.sdr1));
490 DEFINE(KVM_HOST_LPID, offsetof(struct kvm, arch.host_lpid));
491 DEFINE(KVM_HOST_LPCR, offsetof(struct kvm, arch.host_lpcr));
492 DEFINE(KVM_HOST_SDR1, offsetof(struct kvm, arch.host_sdr1));
493 DEFINE(KVM_TLBIE_LOCK, offsetof(struct kvm, arch.tlbie_lock));
1b400ba0 494 DEFINE(KVM_NEED_FLUSH, offsetof(struct kvm, arch.need_tlb_flush.bits));
aa04b4cc
PM		 495 DEFINE(KVM_LPCR, offsetof(struct kvm, arch.lpcr));
496 DEFINE(KVM_RMOR, offsetof(struct kvm, arch.rmor));
697d3899 497 DEFINE(KVM_VRMA_SLB_V, offsetof(struct kvm, arch.vrma_slb_v));
de56a948
PM		 498 DEFINE(VCPU_DSISR, offsetof(struct kvm_vcpu, arch.shregs.dsisr));
499 DEFINE(VCPU_DAR, offsetof(struct kvm_vcpu, arch.shregs.dar));
7657f408 500 DEFINE(VCPU_VPA, offsetof(struct kvm_vcpu, arch.vpa.pinned_addr));
c35635ef 501 DEFINE(VCPU_VPA_DIRTY, offsetof(struct kvm_vcpu, arch.vpa.dirty));
de56a948 502#endif
00c3a37c 503#ifdef CONFIG_PPC_BOOK3S
de56a948 504 DEFINE(VCPU_VCPUID, offsetof(struct kvm_vcpu, vcpu_id));
de56a948
PM		 505 DEFINE(VCPU_PURR, offsetof(struct kvm_vcpu, arch.purr));
506 DEFINE(VCPU_SPURR, offsetof(struct kvm_vcpu, arch.spurr));
b005255e
MN		 507 DEFINE(VCPU_IC, offsetof(struct kvm_vcpu, arch.ic));
508 DEFINE(VCPU_VTB, offsetof(struct kvm_vcpu, arch.vtb));
de56a948
PM		 509 DEFINE(VCPU_DSCR, offsetof(struct kvm_vcpu, arch.dscr));
510 DEFINE(VCPU_AMR, offsetof(struct kvm_vcpu, arch.amr));
511 DEFINE(VCPU_UAMOR, offsetof(struct kvm_vcpu, arch.uamor));
b005255e 512 DEFINE(VCPU_IAMR, offsetof(struct kvm_vcpu, arch.iamr));
de56a948
PM		 513 DEFINE(VCPU_CTRL, offsetof(struct kvm_vcpu, arch.ctrl));
514 DEFINE(VCPU_DABR, offsetof(struct kvm_vcpu, arch.dabr));
8563bf52 515 DEFINE(VCPU_DABRX, offsetof(struct kvm_vcpu, arch.dabrx));
b005255e
MN		 516 DEFINE(VCPU_DAWR, offsetof(struct kvm_vcpu, arch.dawr));
517 DEFINE(VCPU_DAWRX, offsetof(struct kvm_vcpu, arch.dawrx));
518 DEFINE(VCPU_CIABR, offsetof(struct kvm_vcpu, arch.ciabr));
62908905 519 DEFINE(VCPU_HFLAGS, offsetof(struct kvm_vcpu, arch.hflags));
de56a948
PM		 520 DEFINE(VCPU_DEC, offsetof(struct kvm_vcpu, arch.dec));
521 DEFINE(VCPU_DEC_EXPIRES, offsetof(struct kvm_vcpu, arch.dec_expires));
aa04b4cc 522 DEFINE(VCPU_PENDING_EXC, offsetof(struct kvm_vcpu, arch.pending_exceptions));
19ccb76a
PM		 523 DEFINE(VCPU_CEDED, offsetof(struct kvm_vcpu, arch.ceded));
524 DEFINE(VCPU_PRODDED, offsetof(struct kvm_vcpu, arch.prodded));
de56a948
PM		 525 DEFINE(VCPU_MMCR, offsetof(struct kvm_vcpu, arch.mmcr));
526 DEFINE(VCPU_PMC, offsetof(struct kvm_vcpu, arch.pmc));
b005255e 527 DEFINE(VCPU_SPMC, offsetof(struct kvm_vcpu, arch.spmc));
14941789
PM		 528 DEFINE(VCPU_SIAR, offsetof(struct kvm_vcpu, arch.siar));
529 DEFINE(VCPU_SDAR, offsetof(struct kvm_vcpu, arch.sdar));
b005255e 530 DEFINE(VCPU_SIER, offsetof(struct kvm_vcpu, arch.sier));
de56a948
PM		 531 DEFINE(VCPU_SLB, offsetof(struct kvm_vcpu, arch.slb));
532 DEFINE(VCPU_SLB_MAX, offsetof(struct kvm_vcpu, arch.slb_max));
533 DEFINE(VCPU_SLB_NR, offsetof(struct kvm_vcpu, arch.slb_nr));
de56a948
PM		 534 DEFINE(VCPU_FAULT_DSISR, offsetof(struct kvm_vcpu, arch.fault_dsisr));
535 DEFINE(VCPU_FAULT_DAR, offsetof(struct kvm_vcpu, arch.fault_dar));
e5ee5422 536 DEFINE(VCPU_INTR_MSR, offsetof(struct kvm_vcpu, arch.intr_msr));
de56a948
PM		 537 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
538 DEFINE(VCPU_TRAP, offsetof(struct kvm_vcpu, arch.trap));
0acb9111 539 DEFINE(VCPU_CFAR, offsetof(struct kvm_vcpu, arch.cfar));
4b8473c9 540 DEFINE(VCPU_PPR, offsetof(struct kvm_vcpu, arch.ppr));
b005255e 541 DEFINE(VCPU_FSCR, offsetof(struct kvm_vcpu, arch.fscr));
616dff86 542 DEFINE(VCPU_SHADOW_FSCR, offsetof(struct kvm_vcpu, arch.shadow_fscr));
b005255e 543 DEFINE(VCPU_PSPB, offsetof(struct kvm_vcpu, arch.pspb));
b005255e
MN		 544 DEFINE(VCPU_EBBHR, offsetof(struct kvm_vcpu, arch.ebbhr));
545 DEFINE(VCPU_EBBRR, offsetof(struct kvm_vcpu, arch.ebbrr));
546 DEFINE(VCPU_BESCR, offsetof(struct kvm_vcpu, arch.bescr));
547 DEFINE(VCPU_CSIGR, offsetof(struct kvm_vcpu, arch.csigr));
548 DEFINE(VCPU_TACR, offsetof(struct kvm_vcpu, arch.tacr));
549 DEFINE(VCPU_TCSCR, offsetof(struct kvm_vcpu, arch.tcscr));
550 DEFINE(VCPU_ACOP, offsetof(struct kvm_vcpu, arch.acop));
551 DEFINE(VCPU_WORT, offsetof(struct kvm_vcpu, arch.wort));
a2d56020 552 DEFINE(VCPU_SHADOW_SRR1, offsetof(struct kvm_vcpu, arch.shadow_srr1));
371fefd6
PM		 553 DEFINE(VCORE_ENTRY_EXIT, offsetof(struct kvmppc_vcore, entry_exit_count));
554 DEFINE(VCORE_NAP_COUNT, offsetof(struct kvmppc_vcore, nap_count));
555 DEFINE(VCORE_IN_GUEST, offsetof(struct kvmppc_vcore, in_guest));
19ccb76a 556 DEFINE(VCORE_NAPPING_THREADS, offsetof(struct kvmppc_vcore, napping_threads));
e0b7ec05 557 DEFINE(VCORE_KVM, offsetof(struct kvmppc_vcore, kvm));
93b0f4dc 558 DEFINE(VCORE_TB_OFFSET, offsetof(struct kvmppc_vcore, tb_offset));
a0144e2a 559 DEFINE(VCORE_LPCR, offsetof(struct kvmppc_vcore, lpcr));
388cc6e1 560 DEFINE(VCORE_PCR, offsetof(struct kvmppc_vcore, pcr));
b005255e 561 DEFINE(VCORE_DPDES, offsetof(struct kvmppc_vcore, dpdes));
de56a948
PM		 562 DEFINE(VCPU_SLB_E, offsetof(struct kvmppc_slb, orige));
563 DEFINE(VCPU_SLB_V, offsetof(struct kvmppc_slb, origv));
564 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
7b490411
MN		 565#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
566 DEFINE(VCPU_TFHAR, offsetof(struct kvm_vcpu, arch.tfhar));
567 DEFINE(VCPU_TFIAR, offsetof(struct kvm_vcpu, arch.tfiar));
568 DEFINE(VCPU_TEXASR, offsetof(struct kvm_vcpu, arch.texasr));
569 DEFINE(VCPU_GPR_TM, offsetof(struct kvm_vcpu, arch.gpr_tm));
570 DEFINE(VCPU_FPRS_TM, offsetof(struct kvm_vcpu, arch.fp_tm.fpr));
571 DEFINE(VCPU_VRS_TM, offsetof(struct kvm_vcpu, arch.vr_tm.vr));
572 DEFINE(VCPU_VRSAVE_TM, offsetof(struct kvm_vcpu, arch.vrsave_tm));
573 DEFINE(VCPU_CR_TM, offsetof(struct kvm_vcpu, arch.cr_tm));
574 DEFINE(VCPU_LR_TM, offsetof(struct kvm_vcpu, arch.lr_tm));
575 DEFINE(VCPU_CTR_TM, offsetof(struct kvm_vcpu, arch.ctr_tm));
576 DEFINE(VCPU_AMR_TM, offsetof(struct kvm_vcpu, arch.amr_tm));
577 DEFINE(VCPU_PPR_TM, offsetof(struct kvm_vcpu, arch.ppr_tm));
578 DEFINE(VCPU_DSCR_TM, offsetof(struct kvm_vcpu, arch.dscr_tm));
579 DEFINE(VCPU_TAR_TM, offsetof(struct kvm_vcpu, arch.tar_tm));
580#endif
3c42bf8a
PM		 581
582#ifdef CONFIG_PPC_BOOK3S_64
7aa79938 583#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
a2d56020 584 DEFINE(PACA_SVCPU, offsetof(struct paca_struct, shadow_vcpu));
3c42bf8a 585# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
de56a948
PM		 586#else
587# define SVCPU_FIELD(x, f)
588#endif
3c42bf8a
PM		 589# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
590#else /* 32-bit */
591# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
592# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
593#endif
594
595 SVCPU_FIELD(SVCPU_CR, cr);
596 SVCPU_FIELD(SVCPU_XER, xer);
597 SVCPU_FIELD(SVCPU_CTR, ctr);
598 SVCPU_FIELD(SVCPU_LR, lr);
599 SVCPU_FIELD(SVCPU_PC, pc);
600 SVCPU_FIELD(SVCPU_R0, gpr[0]);
601 SVCPU_FIELD(SVCPU_R1, gpr[1]);
602 SVCPU_FIELD(SVCPU_R2, gpr[2]);
603 SVCPU_FIELD(SVCPU_R3, gpr[3]);
604 SVCPU_FIELD(SVCPU_R4, gpr[4]);
605 SVCPU_FIELD(SVCPU_R5, gpr[5]);
606 SVCPU_FIELD(SVCPU_R6, gpr[6]);
607 SVCPU_FIELD(SVCPU_R7, gpr[7]);
608 SVCPU_FIELD(SVCPU_R8, gpr[8]);
609 SVCPU_FIELD(SVCPU_R9, gpr[9]);
610 SVCPU_FIELD(SVCPU_R10, gpr[10]);
611 SVCPU_FIELD(SVCPU_R11, gpr[11]);
612 SVCPU_FIELD(SVCPU_R12, gpr[12]);
613 SVCPU_FIELD(SVCPU_R13, gpr[13]);
614 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
615 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
616 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
617 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0604675f 618#ifdef CONFIG_PPC_BOOK3S_32
3c42bf8a 619 SVCPU_FIELD(SVCPU_SR, sr);
0604675f 620#endif
3c42bf8a
PM		 621#ifdef CONFIG_PPC64
622 SVCPU_FIELD(SVCPU_SLB, slb);
623 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
616dff86 624 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
3c42bf8a
PM		 625#endif
626
627 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
628 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
de56a948 629 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
3c42bf8a
PM		 630 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
631 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
632 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
36e7bb38 633 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
3c42bf8a 634 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
02143947 635 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
19ccb76a 636 HSTATE_FIELD(HSTATE_NAPPING, napping);
3c42bf8a 637
9975f5e3 638#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
7657f408
PM		 639 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
640 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
de56a948 641 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
371fefd6
PM		 642 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
643 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
54695c30
BH		 644 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
645 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
e0b7ec05 646 HSTATE_FIELD(HSTATE_PTID, ptid);
de56a948
PM		 647 HSTATE_FIELD(HSTATE_MMCR, host_mmcr);
648 HSTATE_FIELD(HSTATE_PMC, host_pmc);
649 HSTATE_FIELD(HSTATE_PURR, host_purr);
650 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
651 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
652 HSTATE_FIELD(HSTATE_DABR, dabr);
653 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
19ccb76a 654 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
9975f5e3 655#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
de56a948 656
0acb9111
PM		 657#ifdef CONFIG_PPC_BOOK3S_64
658 HSTATE_FIELD(HSTATE_CFAR, cfar);
4b8473c9 659 HSTATE_FIELD(HSTATE_PPR, ppr);
616dff86 660 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
0acb9111
PM		 661#endif /* CONFIG_PPC_BOOK3S_64 */
662
3c42bf8a 663#else /* CONFIG_PPC_BOOK3S */
7e57cba0
AG		 664 DEFINE(VCPU_CR, offsetof(struct kvm_vcpu, arch.cr));
665 DEFINE(VCPU_XER, offsetof(struct kvm_vcpu, arch.xer));
0604675f
AG		 666 DEFINE(VCPU_LR, offsetof(struct kvm_vcpu, arch.lr));
667 DEFINE(VCPU_CTR, offsetof(struct kvm_vcpu, arch.ctr));
668 DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.pc));
669 DEFINE(VCPU_LAST_INST, offsetof(struct kvm_vcpu, arch.last_inst));
670 DEFINE(VCPU_FAULT_DEAR, offsetof(struct kvm_vcpu, arch.fault_dear));
671 DEFINE(VCPU_FAULT_ESR, offsetof(struct kvm_vcpu, arch.fault_esr));
15b708be 672 DEFINE(VCPU_CRIT_SAVE, offsetof(struct kvm_vcpu, arch.crit_save));
00c3a37c 673#endif /* CONFIG_PPC_BOOK3S */
3c42bf8a 674#endif /* CONFIG_KVM */
d17051cb
AG		 675
676#ifdef CONFIG_KVM_GUEST
677 DEFINE(KVM_MAGIC_SCRATCH1, offsetof(struct kvm_vcpu_arch_shared,
678 scratch1));
679 DEFINE(KVM_MAGIC_SCRATCH2, offsetof(struct kvm_vcpu_arch_shared,
680 scratch2));
681 DEFINE(KVM_MAGIC_SCRATCH3, offsetof(struct kvm_vcpu_arch_shared,
682 scratch3));
683 DEFINE(KVM_MAGIC_INT, offsetof(struct kvm_vcpu_arch_shared,
684 int_pending));
685 DEFINE(KVM_MAGIC_MSR, offsetof(struct kvm_vcpu_arch_shared, msr));
686 DEFINE(KVM_MAGIC_CRITICAL, offsetof(struct kvm_vcpu_arch_shared,
687 critical));
cbe487fa 688 DEFINE(KVM_MAGIC_SR, offsetof(struct kvm_vcpu_arch_shared, sr));
d17051cb
AG		 689#endif
690
ca9153a3
IY		 691#ifdef CONFIG_44x
692 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
693 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
694#endif
55fd766b 695#ifdef CONFIG_PPC_FSL_BOOK3E
78f62237
KG		 696 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
697 DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
698 DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
699 DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
700 DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
701 DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
702#endif
bbf45ba5 703
4cd35f67
SW		 704#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
705 DEFINE(VCPU_EVR, offsetof(struct kvm_vcpu, arch.evr[0]));
706 DEFINE(VCPU_ACC, offsetof(struct kvm_vcpu, arch.acc));
707 DEFINE(VCPU_SPEFSCR, offsetof(struct kvm_vcpu, arch.spefscr));
708 DEFINE(VCPU_HOST_SPEFSCR, offsetof(struct kvm_vcpu, arch.host_spefscr));
709#endif
710
d30f6e48
SW		 711#ifdef CONFIG_KVM_BOOKE_HV
712 DEFINE(VCPU_HOST_MAS4, offsetof(struct kvm_vcpu, arch.host_mas4));
713 DEFINE(VCPU_HOST_MAS6, offsetof(struct kvm_vcpu, arch.host_mas6));
714 DEFINE(VCPU_EPLC, offsetof(struct kvm_vcpu, arch.eplc));
715#endif
716
73e75b41
HB		 717#ifdef CONFIG_KVM_EXIT_TIMING
718 DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
719 arch.timing_exit.tv32.tbu));
720 DEFINE(VCPU_TIMING_EXIT_TBL, offsetof(struct kvm_vcpu,
721 arch.timing_exit.tv32.tbl));
722 DEFINE(VCPU_TIMING_LAST_ENTER_TBU, offsetof(struct kvm_vcpu,
723 arch.timing_last_enter.tv32.tbu));
724 DEFINE(VCPU_TIMING_LAST_ENTER_TBL, offsetof(struct kvm_vcpu,
725 arch.timing_last_enter.tv32.tbl));
726#endif
727
ed79ba9e
BH		 728#ifdef CONFIG_PPC_POWERNV
729 DEFINE(OPAL_MC_GPR3, offsetof(struct opal_machine_check_event, gpr3));
730 DEFINE(OPAL_MC_SRR0, offsetof(struct opal_machine_check_event, srr0));
731 DEFINE(OPAL_MC_SRR1, offsetof(struct opal_machine_check_event, srr1));
732 DEFINE(PACA_OPAL_MC_EVT, offsetof(struct paca_struct, opal_mc_evt));
733#endif
734
14cf11af
PM		 735 return 0;
736}
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