projects / mirror_ubuntu-focal-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 84e3ad5b VB |
2 | /* |
| 3 | * This file contains low level CPU setup functions. | |
| 4 | * Valentine Barshak <vbarshak@ru.mvista.com> | |
| 5 | * MontaVista Software, Inc (c) 2007 | |
| 6 | * | |
| 464076a4 | 7 | * Based on cpu_setup_6xx code by |
| 84e3ad5b | 8 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> |
| 84e3ad5b VB |
9 | */ |
| 10 | ||
| 11 | #include <asm/processor.h> | |
| 12 | #include <asm/cputable.h> | |
| 13 | #include <asm/ppc_asm.h> | |
| 14 | ||
| 8112753b VB |
15 | _GLOBAL(__setup_cpu_440ep) |
| 16 | b __init_fpu_44x | |
| 17 | _GLOBAL(__setup_cpu_440epx) | |
| 340ffd26 VB |
18 | mflr r4 |
| 19 | bl __init_fpu_44x | |
| 20 | bl __plb_disable_wrp | |
| 47c0bd1a | 21 | bl __fixup_440A_mcheck |
| 340ffd26 VB |
22 | mtlr r4 |
| 23 | blr | |
| 24 | _GLOBAL(__setup_cpu_440grx) | |
| 9ac30c31 JB |
25 | mflr r4 |
| 26 | bl __plb_disable_wrp | |
| 27 | bl __fixup_440A_mcheck | |
| 28 | mtlr r4 | |
| 29 | blr | |
| 464076a4 | 30 | _GLOBAL(__setup_cpu_460ex) |
| 939e622c | 31 | _GLOBAL(__setup_cpu_460gt) |
| 6c712090 | 32 | _GLOBAL(__setup_cpu_460sx) |
| 6edc323d | 33 | _GLOBAL(__setup_cpu_apm821xx) |
| 6612d9b0 BH |
34 | mflr r4 |
| 35 | bl __init_fpu_44x | |
| 36 | bl __fixup_440A_mcheck | |
| 37 | mtlr r4 | |
| 38 | blr | |
| 39 | ||
| 640d17d6 | 40 | _GLOBAL(__setup_cpu_440x5) |
| 47c0bd1a BH |
41 | _GLOBAL(__setup_cpu_440gx) |
| 42 | _GLOBAL(__setup_cpu_440spe) | |
| 43 | b __fixup_440A_mcheck | |
| 340ffd26 | 44 | |
| 8112753b VB |
45 | /* enable APU between CPU and FPU */ |
| 46 | _GLOBAL(__init_fpu_44x) | |
| 47 | mfspr r3,SPRN_CCR0 | |
| 48 | /* Clear DAPUIB flag in CCR0 */ | |
| 49 | rlwinm r3,r3,0,12,10 | |
| 50 | mtspr SPRN_CCR0,r3 | |
| 51 | isync | |
| 52 | blr | |
| 53 | ||
| 340ffd26 VB |
54 | /* |
| 55 | * Workaround for the incorrect write to DDR SDRAM errata. | |
| 56 | * The write address can be corrupted during writes to | |
| 57 | * DDR SDRAM when write pipelining is enabled on PLB0. | |
| 58 | * Disable write pipelining here. | |
| 59 | */ | |
| 60 | #define DCRN_PLB4A0_ACR 0x81 | |
| 61 | ||
| 62 | _GLOBAL(__plb_disable_wrp) | |
| 63 | mfdcr r3,DCRN_PLB4A0_ACR | |
| 64 | /* clear WRP bit in PLB4A0_ACR */ | |
| 65 | rlwinm r3,r3,0,8,6 | |
| 66 | mtdcr DCRN_PLB4A0_ACR,r3 | |
| 67 | isync | |
| 68 | blr | |
| 69 |