[mirror_ubuntu-zesty-kernel.git] / arch / powerpc / kernel / cpu_setup_power.S

/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include <asm/book3s/64/mmu-hash.h>

/* Entry: r3 = crap, r4 = ptr to cputable entry
 *
 * Note that we can be called twice for pseudo-PVRs
 */
_GLOBAL(__setup_cpu_power7)
	mflr	r11
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	bl	__init_LPCR
	bl	__init_tlb_power7
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power7)
	mflr	r11
	mfmsr	r3
	rldicl.	r0,r3,4,63
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	bl	__init_LPCR
	bl	__init_tlb_power7
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power8
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr   r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power8
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power9
	bl	__init_PMU_HV
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr   r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	bl	__init_LPCR
	bl	__init_HFSCR
	bl	__init_tlb_power9
	bl	__init_PMU_HV
	mtlr	r11
	blr

__init_hvmode_206:
	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
	mfmsr	r3
	rldicl.	r0,r3,4,63
	bnelr
	ld	r5,CPU_SPEC_FEATURES(r4)
	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
	xor	r5,r5,r6
	std	r5,CPU_SPEC_FEATURES(r4)
	blr

__init_LPCR:
	/* Setup a sane LPCR:
	 *   Called with initial LPCR in R3
	 *
	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
	 *   PECE = 0b111
	 *   DPFD = 4
	 *   HDICE = 0
	 *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	 *   VRMASD = 0b10000 (L=1, LP=00)
	 *
	 * Other bits untouched for now
	 */
	li	r5,1
	rldimi	r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
	li	r5,4
	rldimi	r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	clrrdi	r3,r3,1		/* clear HDICE */
	li	r5,4
	rldimi	r3,r5, LPCR_VC_SH, 0
	li	r5,0x10
	rldimi	r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
	mtspr	SPRN_LPCR,r3
	isync
	blr

__init_FSCR:
	mfspr	r3,SPRN_FSCR
	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
	mtspr	SPRN_FSCR,r3
	blr

__init_HFSCR:
	mfspr	r3,SPRN_HFSCR
	ori	r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
	mtspr	SPRN_HFSCR,r3
	blr

/*
 * Clear the TLB using the specified IS form of tlbiel instruction
 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
 */
__init_tlb_power7:
	li	r6,POWER7_TLB_SETS
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

__init_tlb_power8:
	li	r6,POWER8_TLB_SETS
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

__init_tlb_power9:
	li	r6,POWER9_TLB_SETS_HASH
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

__init_PMU_HV:
	li	r5,0
	mtspr	SPRN_MMCRC,r5
	blr

__init_PMU_HV_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRH,r5
	blr

__init_PMU:
	li	r5,0
	mtspr	SPRN_MMCRA,r5
	mtspr	SPRN_MMCR0,r5
	mtspr	SPRN_MMCR1,r5
	mtspr	SPRN_MMCR2,r5
	blr

__init_PMU_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRS,r5
	blr
Commit	Line	Data
24cc67de BH	1	/*
	2	* This file contains low level CPU setup functions.
	3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*
	10	*/
	11
	12	#include <asm/processor.h>
	13	#include <asm/page.h>
	14	#include <asm/cputable.h>
	15	#include <asm/ppc_asm.h>
	16	#include <asm/asm-offsets.h>
	17	#include <asm/cache.h>
f64e8084	18	#include <asm/book3s/64/mmu-hash.h>
24cc67de BH	19
	20	/* Entry: r3 = crap, r4 = ptr to cputable entry
	21	*
	22	* Note that we can be called twice for pseudo-PVRs
	23	*/
	24	_GLOBAL(__setup_cpu_power7)
	25	mflr r11
	26	bl __init_hvmode_206
	27	mtlr r11
	28	beqlr
b144871c BH	29	li r0,0
b144871c BH	30	mtspr SPRN_LPID,r0
f7c32c24	31	mfspr r3,SPRN_LPCR
24cc67de	32	bl __init_LPCR
04407050	33	bl __init_tlb_power7
24cc67de BH	34	mtlr r11
	35	blr
	36
	37	_GLOBAL(__restore_cpu_power7)
	38	mflr r11
	39	mfmsr r3
	40	rldicl. r0,r3,4,63
	41	beqlr
b144871c BH	42	li r0,0
b144871c BH	43	mtspr SPRN_LPID,r0
f7c32c24	44	mfspr r3,SPRN_LPCR
24cc67de	45	bl __init_LPCR
04407050	46	bl __init_tlb_power7
aec937b1 MN	47	mtlr r11
	48	blr
	49
	50	_GLOBAL(__setup_cpu_power8)
	51	mflr r11
57d23167	52	bl __init_FSCR
240686c1	53	bl __init_PMU
393eb79a	54	bl __init_PMU_ISA207
aec937b1 MN	55	bl __init_hvmode_206
	56	mtlr r11
	57	beqlr
	58	li r0,0
	59	mtspr SPRN_LPID,r0
f7c32c24	60	mfspr r3,SPRN_LPCR
d4e58e59	61	ori r3, r3, LPCR_PECEDH
aec937b1	62	bl __init_LPCR
2a3563b0	63	bl __init_HFSCR
04407050	64	bl __init_tlb_power8
240686c1	65	bl __init_PMU_HV
393eb79a	66	bl __init_PMU_HV_ISA207
aec937b1 MN	67	mtlr r11
	68	blr
	69
	70	_GLOBAL(__restore_cpu_power8)
	71	mflr r11
57d23167	72	bl __init_FSCR
240686c1	73	bl __init_PMU
393eb79a	74	bl __init_PMU_ISA207
aec937b1 MN	75	mfmsr r3
aec937b1 MN	76	rldicl. r0,r3,4,63
8c2a3817	77	mtlr r11
aec937b1 MN	78	beqlr
	79	li r0,0
	80	mtspr SPRN_LPID,r0
f7c32c24	81	mfspr r3,SPRN_LPCR
d4e58e59	82	ori r3, r3, LPCR_PECEDH
aec937b1	83	bl __init_LPCR
2a3563b0	84	bl __init_HFSCR
04407050	85	bl __init_tlb_power8
240686c1	86	bl __init_PMU_HV
393eb79a	87	bl __init_PMU_HV_ISA207
24cc67de BH	88	mtlr r11
	89	blr
	90
c3ab300e MN	91	_GLOBAL(__setup_cpu_power9)
	92	mflr r11
	93	bl __init_FSCR
393eb79a	94	bl __init_PMU
c3ab300e MN	95	bl __init_hvmode_206
	96	mtlr r11
	97	beqlr
	98	li r0,0
	99	mtspr SPRN_LPID,r0
	100	mfspr r3,SPRN_LPCR
	101	ori r3, r3, LPCR_PECEDH
	102	bl __init_LPCR
	103	bl __init_HFSCR
	104	bl __init_tlb_power9
393eb79a	105	bl __init_PMU_HV
c3ab300e MN	106	mtlr r11
	107	blr
	108
	109	_GLOBAL(__restore_cpu_power9)
	110	mflr r11
	111	bl __init_FSCR
393eb79a	112	bl __init_PMU
c3ab300e MN	113	mfmsr r3
	114	rldicl. r0,r3,4,63
	115	mtlr r11
	116	beqlr
	117	li r0,0
	118	mtspr SPRN_LPID,r0
	119	mfspr r3,SPRN_LPCR
	120	ori r3, r3, LPCR_PECEDH
	121	bl __init_LPCR
	122	bl __init_HFSCR
	123	bl __init_tlb_power9
393eb79a	124	bl __init_PMU_HV
c3ab300e MN	125	mtlr r11
	126	blr
	127
24cc67de	128	__init_hvmode_206:
969391c5	129	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
24cc67de BH	130	mfmsr r3
	131	rldicl. r0,r3,4,63
	132	bnelr
	133	ld r5,CPU_SPEC_FEATURES(r4)
969391c5	134	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
24cc67de BH	135	xor r5,r5,r6
	136	std r5,CPU_SPEC_FEATURES(r4)
	137	blr
	138
	139	__init_LPCR:
	140	/* Setup a sane LPCR:
f7c32c24	141	* Called with initial LPCR in R3
24cc67de	142	*
a5d4f3ad	143	* LPES = 0b01 (HSRR0/1 used for 0x500)
24cc67de	144	* PECE = 0b111
895796a8	145	* DPFD = 4
923c53ca PM	146	* HDICE = 0
	147	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	148	* VRMASD = 0b10000 (L=1, LP=00)
24cc67de BH	149	*
	150	* Other bits untouched for now
	151	*/
923c53ca PM	152	li r5,1
923c53ca PM	153	rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
24cc67de	154	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
895796a8	155	li r5,4
923c53ca PM	156	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	157	clrrdi r3,r3,1 /* clear HDICE */
	158	li r5,4
	159	rldimi r3,r5, LPCR_VC_SH, 0
	160	li r5,0x10
	161	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
24cc67de BH	162	mtspr SPRN_LPCR,r3
	163	isync
	164	blr
b144871c	165
2468dcf6 IM	166	__init_FSCR:
2468dcf6 IM	167	mfspr r3,SPRN_FSCR
1ddf499e	168	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
2468dcf6 IM	169	mtspr SPRN_FSCR,r3
	170	blr
	171
2a3563b0 MN	172	__init_HFSCR:
2a3563b0 MN	173	mfspr r3,SPRN_HFSCR
53b56ca0	174	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
1ddf499e	175	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB
2a3563b0 MN	176	mtspr SPRN_HFSCR,r3
	177	blr
	178
04407050 MS	179	/*
	180	* Clear the TLB using the specified IS form of tlbiel instruction
	181	* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
04407050 MS	182	*/
04407050 MS	183	__init_tlb_power7:
15b1624b	184	li r6,POWER7_TLB_SETS
04407050	185	mtctr r6
45706bb5	186	li r7,0xc00 /* IS field = 0b11 */
04407050 MS	187	ptesync
	188	2: tlbiel r7
	189	addi r7,r7,0x1000
	190	bdnz 2b
	191	ptesync
	192	1: blr
	193
	194	__init_tlb_power8:
15b1624b	195	li r6,POWER8_TLB_SETS
b144871c	196	mtctr r6
45706bb5	197	li r7,0xc00 /* IS field = 0b11 */
b144871c BH	198	ptesync
	199	2: tlbiel r7
	200	addi r7,r7,0x1000
	201	bdnz 2b
	202	ptesync
	203	1: blr
240686c1	204
c3ab300e MN	205	__init_tlb_power9:
	206	li r6,POWER9_TLB_SETS_HASH
	207	mtctr r6
	208	li r7,0xc00 /* IS field = 0b11 */
	209	ptesync
	210	2: tlbiel r7
	211	addi r7,r7,0x1000
	212	bdnz 2b
	213	ptesync
	214	1: blr
	215
240686c1 ME	216	__init_PMU_HV:
	217	li r5,0
	218	mtspr SPRN_MMCRC,r5
393eb79a MS	219	blr
	220
	221	__init_PMU_HV_ISA207:
	222	li r5,0
240686c1 ME	223	mtspr SPRN_MMCRH,r5
	224	blr
	225
	226	__init_PMU:
	227	li r5,0
240686c1 ME	228	mtspr SPRN_MMCRA,r5
	229	mtspr SPRN_MMCR0,r5
	230	mtspr SPRN_MMCR1,r5
	231	mtspr SPRN_MMCR2,r5
	232	blr
393eb79a MS	233
	234	__init_PMU_ISA207:
	235	li r5,0
	236	mtspr SPRN_MMCRS,r5
	237	blr