[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / kernel / cpu_setup_power.S

/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 *
 */

#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>
#include <asm/book3s/64/mmu-hash.h>

/* Entry: r3 = crap, r4 = ptr to cputable entry
 *
 * Note that we can be called twice for pseudo-PVRs
 */
_GLOBAL(__setup_cpu_power7)
	mflr	r11
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
	bl	__init_LPCR_ISA206
	bl	__init_tlb_power7
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power7)
	mflr	r11
	mfmsr	r3
	rldicl.	r0,r3,4,63
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	li	r4,(LPCR_LPES1 >> LPCR_LPES_SH)
	bl	__init_LPCR_ISA206
	bl	__init_tlb_power7
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr	r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA206
	bl	__init_HFSCR
	bl	__init_tlb_power8
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power8)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_PMU_ISA207
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_LPID,r0
	mfspr   r3,SPRN_LPCR
	ori	r3, r3, LPCR_PECEDH
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA206
	bl	__init_HFSCR
	bl	__init_tlb_power8
	bl	__init_PMU_HV
	bl	__init_PMU_HV_ISA207
	mtlr	r11
	blr

_GLOBAL(__setup_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	bl	__init_hvmode_206
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_PSSCR,r0
	mtspr	SPRN_LPID,r0
	mtspr	SPRN_PID,r0
	mfspr	r3,SPRN_LPCR
	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE  | LPCR_HEIC)
	or	r3, r3, r4
	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
	andc	r3, r3, r4
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA300
	bl	__init_HFSCR
	bl	__init_tlb_power9
	bl	__init_PMU_HV
	mtlr	r11
	blr

_GLOBAL(__restore_cpu_power9)
	mflr	r11
	bl	__init_FSCR
	bl	__init_PMU
	mfmsr	r3
	rldicl.	r0,r3,4,63
	mtlr	r11
	beqlr
	li	r0,0
	mtspr	SPRN_PSSCR,r0
	mtspr	SPRN_LPID,r0
	mtspr	SPRN_PID,r0
	mfspr   r3,SPRN_LPCR
	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
	or	r3, r3, r4
	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
	andc	r3, r3, r4
	li	r4,0 /* LPES = 0 */
	bl	__init_LPCR_ISA300
	bl	__init_HFSCR
	bl	__init_tlb_power9
	bl	__init_PMU_HV
	mtlr	r11
	blr

__init_hvmode_206:
	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
	mfmsr	r3
	rldicl.	r0,r3,4,63
	bnelr
	ld	r5,CPU_SPEC_FEATURES(r4)
	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
	xor	r5,r5,r6
	std	r5,CPU_SPEC_FEATURES(r4)
	blr

__init_LPCR_ISA206:
	/* Setup a sane LPCR:
	 *   Called with initial LPCR in R3 and desired LPES 2-bit value in R4
	 *
	 *   LPES = 0b01 (HSRR0/1 used for 0x500)
	 *   PECE = 0b111
	 *   DPFD = 4
	 *   HDICE = 0
	 *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	 *   VRMASD = 0b10000 (L=1, LP=00)
	 *
	 * Other bits untouched for now
	 */
	li	r5,0x10
	rldimi	r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5

	/* POWER9 has no VRMASD */
__init_LPCR_ISA300:
	rldimi	r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
	ori	r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
	li	r5,4
	rldimi	r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	clrrdi	r3,r3,1		/* clear HDICE */
	li	r5,4
	rldimi	r3,r5, LPCR_VC_SH, 0
	mtspr	SPRN_LPCR,r3
	isync
	blr

__init_FSCR:
	mfspr	r3,SPRN_FSCR
	ori	r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
	mtspr	SPRN_FSCR,r3
	blr

__init_HFSCR:
	mfspr	r3,SPRN_HFSCR
	ori	r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
		      HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
	mtspr	SPRN_HFSCR,r3
	blr

/*
 * Clear the TLB using the specified IS form of tlbiel instruction
 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
 */
__init_tlb_power7:
	li	r6,POWER7_TLB_SETS
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

__init_tlb_power8:
	li	r6,POWER8_TLB_SETS
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	ptesync
2:	tlbiel	r7
	addi	r7,r7,0x1000
	bdnz	2b
	ptesync
1:	blr

/*
 * Flush the TLB in hash mode. Hash must flush with RIC=2 once for process
 * and one for partition scope to clear process and partition table entries.
 */
__init_tlb_power9:
	li	r6,POWER9_TLB_SETS_HASH - 1
	mtctr	r6
	li	r7,0xc00	/* IS field = 0b11 */
	li	r8,0
	ptesync
	PPC_TLBIEL(7, 8, 2, 1, 0)
	PPC_TLBIEL(7, 8, 2, 0, 0)
2:	addi	r7,r7,0x1000
	PPC_TLBIEL(7, 8, 0, 0, 0)
	bdnz	2b
	ptesync
1:	blr

__init_PMU_HV:
	li	r5,0
	mtspr	SPRN_MMCRC,r5
	blr

__init_PMU_HV_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRH,r5
	blr

__init_PMU:
	li	r5,0
	mtspr	SPRN_MMCRA,r5
	mtspr	SPRN_MMCR0,r5
	mtspr	SPRN_MMCR1,r5
	mtspr	SPRN_MMCR2,r5
	blr

__init_PMU_ISA207:
	li	r5,0
	mtspr	SPRN_MMCRS,r5
	blr
Commit	Line	Data
24cc67de BH	1	/*
	2	* This file contains low level CPU setup functions.
	3	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version
	8	* 2 of the License, or (at your option) any later version.
	9	*
	10	*/
	11
	12	#include <asm/processor.h>
	13	#include <asm/page.h>
	14	#include <asm/cputable.h>
	15	#include <asm/ppc_asm.h>
	16	#include <asm/asm-offsets.h>
	17	#include <asm/cache.h>
f64e8084	18	#include <asm/book3s/64/mmu-hash.h>
24cc67de BH	19
	20	/* Entry: r3 = crap, r4 = ptr to cputable entry
	21	*
	22	* Note that we can be called twice for pseudo-PVRs
	23	*/
	24	_GLOBAL(__setup_cpu_power7)
	25	mflr r11
	26	bl __init_hvmode_206
	27	mtlr r11
	28	beqlr
b144871c BH	29	li r0,0
b144871c BH	30	mtspr SPRN_LPID,r0
f7c32c24	31	mfspr r3,SPRN_LPCR
08a1e650	32	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
700b7ead	33	bl __init_LPCR_ISA206
04407050	34	bl __init_tlb_power7
24cc67de BH	35	mtlr r11
	36	blr
	37
	38	_GLOBAL(__restore_cpu_power7)
	39	mflr r11
	40	mfmsr r3
	41	rldicl. r0,r3,4,63
	42	beqlr
b144871c BH	43	li r0,0
b144871c BH	44	mtspr SPRN_LPID,r0
f7c32c24	45	mfspr r3,SPRN_LPCR
08a1e650	46	li r4,(LPCR_LPES1 >> LPCR_LPES_SH)
700b7ead	47	bl __init_LPCR_ISA206
04407050	48	bl __init_tlb_power7
aec937b1 MN	49	mtlr r11
	50	blr
	51
	52	_GLOBAL(__setup_cpu_power8)
	53	mflr r11
57d23167	54	bl __init_FSCR
240686c1	55	bl __init_PMU
393eb79a	56	bl __init_PMU_ISA207
aec937b1 MN	57	bl __init_hvmode_206
	58	mtlr r11
	59	beqlr
	60	li r0,0
	61	mtspr SPRN_LPID,r0
f7c32c24	62	mfspr r3,SPRN_LPCR
d4e58e59	63	ori r3, r3, LPCR_PECEDH
08a1e650	64	li r4,0 /* LPES = 0 */
700b7ead	65	bl __init_LPCR_ISA206
2a3563b0	66	bl __init_HFSCR
04407050	67	bl __init_tlb_power8
240686c1	68	bl __init_PMU_HV
393eb79a	69	bl __init_PMU_HV_ISA207
aec937b1 MN	70	mtlr r11
	71	blr
	72
	73	_GLOBAL(__restore_cpu_power8)
	74	mflr r11
57d23167	75	bl __init_FSCR
240686c1	76	bl __init_PMU
393eb79a	77	bl __init_PMU_ISA207
aec937b1 MN	78	mfmsr r3
aec937b1 MN	79	rldicl. r0,r3,4,63
8c2a3817	80	mtlr r11
aec937b1 MN	81	beqlr
	82	li r0,0
	83	mtspr SPRN_LPID,r0
f7c32c24	84	mfspr r3,SPRN_LPCR
d4e58e59	85	ori r3, r3, LPCR_PECEDH
08a1e650	86	li r4,0 /* LPES = 0 */
700b7ead	87	bl __init_LPCR_ISA206
2a3563b0	88	bl __init_HFSCR
04407050	89	bl __init_tlb_power8
240686c1	90	bl __init_PMU_HV
393eb79a	91	bl __init_PMU_HV_ISA207
24cc67de BH	92	mtlr r11
	93	blr
	94
c3ab300e MN	95	_GLOBAL(__setup_cpu_power9)
	96	mflr r11
	97	bl __init_FSCR
393eb79a	98	bl __init_PMU
c3ab300e MN	99	bl __init_hvmode_206
	100	mtlr r11
	101	beqlr
	102	li r0,0
378f96d3	103	mtspr SPRN_PSSCR,r0
c3ab300e	104	mtspr SPRN_LPID,r0
371b8044	105	mtspr SPRN_PID,r0
c3ab300e	106	mfspr r3,SPRN_LPCR
08a1e650	107	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
7a43906f	108	or r3, r3, r4
fda2d27d AK	109	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
fda2d27d AK	110	andc r3, r3, r4
8d1b48ef	111	li r4,0 /* LPES = 0 */
700b7ead	112	bl __init_LPCR_ISA300
c3ab300e MN	113	bl __init_HFSCR
c3ab300e MN	114	bl __init_tlb_power9
393eb79a	115	bl __init_PMU_HV
c3ab300e MN	116	mtlr r11
	117	blr
	118
	119	_GLOBAL(__restore_cpu_power9)
	120	mflr r11
	121	bl __init_FSCR
393eb79a	122	bl __init_PMU
c3ab300e MN	123	mfmsr r3
	124	rldicl. r0,r3,4,63
	125	mtlr r11
	126	beqlr
	127	li r0,0
378f96d3	128	mtspr SPRN_PSSCR,r0
c3ab300e	129	mtspr SPRN_LPID,r0
371b8044	130	mtspr SPRN_PID,r0
c3ab300e	131	mfspr r3,SPRN_LPCR
08a1e650	132	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH \| LPCR_PECE_HVEE \| LPCR_HVICE \| LPCR_HEIC)
7a43906f	133	or r3, r3, r4
fda2d27d AK	134	LOAD_REG_IMMEDIATE(r4, LPCR_UPRT \| LPCR_HR)
fda2d27d AK	135	andc r3, r3, r4
8d1b48ef	136	li r4,0 /* LPES = 0 */
700b7ead	137	bl __init_LPCR_ISA300
c3ab300e MN	138	bl __init_HFSCR
c3ab300e MN	139	bl __init_tlb_power9
393eb79a	140	bl __init_PMU_HV
c3ab300e MN	141	mtlr r11
	142	blr
	143
24cc67de	144	__init_hvmode_206:
969391c5	145	/* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
24cc67de BH	146	mfmsr r3
	147	rldicl. r0,r3,4,63
	148	bnelr
	149	ld r5,CPU_SPEC_FEATURES(r4)
969391c5	150	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
24cc67de BH	151	xor r5,r5,r6
	152	std r5,CPU_SPEC_FEATURES(r4)
	153	blr
	154
700b7ead	155	__init_LPCR_ISA206:
24cc67de	156	/* Setup a sane LPCR:
08a1e650	157	* Called with initial LPCR in R3 and desired LPES 2-bit value in R4
24cc67de	158	*
a5d4f3ad	159	* LPES = 0b01 (HSRR0/1 used for 0x500)
24cc67de	160	* PECE = 0b111
895796a8	161	* DPFD = 4
923c53ca PM	162	* HDICE = 0
	163	* VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
	164	* VRMASD = 0b10000 (L=1, LP=00)
24cc67de BH	165	*
	166	* Other bits untouched for now
	167	*/
700b7ead NP	168	li r5,0x10
	169	rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
	170
	171	/* POWER9 has no VRMASD */
	172	__init_LPCR_ISA300:
08a1e650	173	rldimi r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
24cc67de	174	ori r3,r3,(LPCR_PECE0\|LPCR_PECE1\|LPCR_PECE2)
895796a8	175	li r5,4
923c53ca PM	176	rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
	177	clrrdi r3,r3,1 /* clear HDICE */
	178	li r5,4
	179	rldimi r3,r5, LPCR_VC_SH, 0
24cc67de BH	180	mtspr SPRN_LPCR,r3
	181	isync
	182	blr
b144871c	183
2468dcf6 IM	184	__init_FSCR:
2468dcf6 IM	185	mfspr r3,SPRN_FSCR
1ddf499e	186	ori r3,r3,FSCR_TAR\|FSCR_DSCR\|FSCR_EBB
2468dcf6 IM	187	mtspr SPRN_FSCR,r3
	188	blr
	189
2a3563b0 MN	190	__init_HFSCR:
2a3563b0 MN	191	mfspr r3,SPRN_HFSCR
53b56ca0	192	ori r3,r3,HFSCR_TAR\|HFSCR_TM\|HFSCR_BHRB\|HFSCR_PM\|\
02ed21ae	193	HFSCR_DSCR\|HFSCR_VECVSX\|HFSCR_FP\|HFSCR_EBB\|HFSCR_MSGP
2a3563b0 MN	194	mtspr SPRN_HFSCR,r3
	195	blr
	196
04407050 MS	197	/*
	198	* Clear the TLB using the specified IS form of tlbiel instruction
	199	* (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
04407050 MS	200	*/
04407050 MS	201	__init_tlb_power7:
15b1624b	202	li r6,POWER7_TLB_SETS
04407050	203	mtctr r6
45706bb5	204	li r7,0xc00 /* IS field = 0b11 */
04407050 MS	205	ptesync
	206	2: tlbiel r7
	207	addi r7,r7,0x1000
	208	bdnz 2b
	209	ptesync
	210	1: blr
	211
	212	__init_tlb_power8:
15b1624b	213	li r6,POWER8_TLB_SETS
b144871c	214	mtctr r6
45706bb5	215	li r7,0xc00 /* IS field = 0b11 */
b144871c BH	216	ptesync
	217	2: tlbiel r7
	218	addi r7,r7,0x1000
	219	bdnz 2b
	220	ptesync
	221	1: blr
240686c1	222
41d0c2ec NP	223	/*
	224	* Flush the TLB in hash mode. Hash must flush with RIC=2 once for process
	225	* and one for partition scope to clear process and partition table entries.
	226	*/
c3ab300e	227	__init_tlb_power9:
41d0c2ec	228	li r6,POWER9_TLB_SETS_HASH - 1
c3ab300e MN	229	mtctr r6
c3ab300e MN	230	li r7,0xc00 /* IS field = 0b11 */
41d0c2ec	231	li r8,0
c3ab300e	232	ptesync
41d0c2ec NP	233	PPC_TLBIEL(7, 8, 2, 1, 0)
	234	PPC_TLBIEL(7, 8, 2, 0, 0)
	235	2: addi r7,r7,0x1000
	236	PPC_TLBIEL(7, 8, 0, 0, 0)
c3ab300e MN	237	bdnz 2b
	238	ptesync
	239	1: blr
	240
240686c1 ME	241	__init_PMU_HV:
	242	li r5,0
	243	mtspr SPRN_MMCRC,r5
393eb79a MS	244	blr
	245
	246	__init_PMU_HV_ISA207:
	247	li r5,0
240686c1 ME	248	mtspr SPRN_MMCRH,r5
	249	blr
	250
	251	__init_PMU:
	252	li r5,0
240686c1 ME	253	mtspr SPRN_MMCRA,r5
	254	mtspr SPRN_MMCR0,r5
	255	mtspr SPRN_MMCR1,r5
	256	mtspr SPRN_MMCR2,r5
	257	blr
393eb79a MS	258
	259	__init_PMU_ISA207:
	260	li r5,0
	261	mtspr SPRN_MMCRS,r5
	262	blr