[mirror_ubuntu-hirsute-kernel.git] / arch / powerpc / kernel / cpu_setup_ppc970.S

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * This file contains low level CPU setup functions.
 *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
 */

#include <asm/processor.h>
#include <asm/page.h>
#include <asm/cputable.h>
#include <asm/ppc_asm.h>
#include <asm/asm-offsets.h>
#include <asm/cache.h>

_GLOBAL(__cpu_preinit_ppc970)
	/* Do nothing if not running in HV mode */
	mfmsr	r0
	rldicl.	r0,r0,4,63
	beqlr

	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	 * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	 * HID5:DCBZ32_ill
	 */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	rldimi	r3,r0,2,61	/* clear bit 61 (lg_pg_en) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync
	mfspr	r3,SPRN_HID5
	rldimi	r3,r0,6,56	/* clear bits 56 & 57 (DCBZ*) */
	sync
	mtspr	SPRN_HID5,r3
	isync
	sync

	/* Setup some basic HID1 features */
	mfspr	r0,SPRN_HID1
	li	r3,0x1200		/* enable i-fetch cacheability */
	sldi	r3,r3,44		/* and prefetch */
	or	r0,r0,r3
	mtspr	SPRN_HID1,r0
	mtspr	SPRN_HID1,r0
	isync

	/* Clear HIOR */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0		/* Clear interrupt prefix */
	isync
	blr

/* Definitions for the table use to save CPU states */
#define CS_HID0		0
#define CS_HID1		8
#define	CS_HID4		16
#define CS_HID5		24
#define CS_SIZE		32

	.data
	.balign	L1_CACHE_BYTES,0
cpu_state_storage:
	.space	CS_SIZE
	.balign	L1_CACHE_BYTES,0
	.text


_GLOBAL(__setup_cpu_ppc970)
	/* Do nothing if not running in HV mode */
	mfmsr	r0
	rldicl.	r0,r0,4,63
	beq	no_hv_mode

	mfspr	r0,SPRN_HID0
	li	r11,5			/* clear DOZE and SLEEP */
	rldimi	r0,r11,52,8		/* set NAP and DPM */
	li	r11,0
	rldimi	r0,r11,32,31		/* clear EN_ATTN */
	b	load_hids		/* Jump to shared code */


_GLOBAL(__setup_cpu_ppc970MP)
	/* Do nothing if not running in HV mode */
	mfmsr	r0
	rldicl.	r0,r0,4,63
	beq	no_hv_mode

	mfspr	r0,SPRN_HID0
	li	r11,0x15		/* clear DOZE and SLEEP */
	rldimi	r0,r11,52,6		/* set DEEPNAP, NAP and DPM */
	li	r11,0
	rldimi	r0,r11,32,31		/* clear EN_ATTN */

load_hids:
	mtspr	SPRN_HID0,r0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	mfspr	r0,SPRN_HID0
	sync
	isync

	/* Try to set LPES = 01 in HID4 */
	mfspr	r0,SPRN_HID4
	clrldi	r0,r0,1			/* clear LPES0 */
	ori	r0,r0,HID4_LPES1	/* set LPES1 */
	sync
	mtspr	SPRN_HID4,r0
	isync

	/* Save away cpu state */
	LOAD_REG_ADDR(r5,cpu_state_storage)

	/* Save HID0,1,4 and 5 */
	mfspr	r3,SPRN_HID0
	std	r3,CS_HID0(r5)
	mfspr	r3,SPRN_HID1
	std	r3,CS_HID1(r5)
	mfspr	r4,SPRN_HID4
	std	r4,CS_HID4(r5)
	mfspr	r3,SPRN_HID5
	std	r3,CS_HID5(r5)

	/* See if we successfully set LPES1 to 1; if not we are in Apple mode */
	andi.	r4,r4,HID4_LPES1
	bnelr

no_hv_mode:
	/* Disable CPU_FTR_HVMODE and exit, since we don't have HV mode */
	ld	r5,CPU_SPEC_FEATURES(r4)
	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
	andc	r5,r5,r6
	std	r5,CPU_SPEC_FEATURES(r4)
	blr

/* Called with no MMU context (typically MSR:IR/DR off) to
 * restore CPU state as backed up by the previous
 * function. This does not include cache setting
 */
_GLOBAL(__restore_cpu_ppc970)
	/* Do nothing if not running in HV mode */
	mfmsr	r0
	rldicl.	r0,r0,4,63
	beqlr

	LOAD_REG_ADDR(r5,cpu_state_storage)
	/* Before accessing memory, we make sure rm_ci is clear */
	li	r0,0
	mfspr	r3,SPRN_HID4
	rldimi	r3,r0,40,23	/* clear bit 23 (rm_ci) */
	sync
	mtspr	SPRN_HID4,r3
	isync
	sync

	/* Clear interrupt prefix */
	li	r0,0
	sync
	mtspr	SPRN_HIOR,0
	isync

	/* Restore HID0 */
	ld	r3,CS_HID0(r5)
	sync
	isync
	mtspr	SPRN_HID0,r3
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	mfspr	r3,SPRN_HID0
	sync
	isync

	/* Restore HID1 */
	ld	r3,CS_HID1(r5)
	sync
	isync
	mtspr	SPRN_HID1,r3
	mtspr	SPRN_HID1,r3
	sync
	isync

	/* Restore HID4 */
	ld	r3,CS_HID4(r5)
	sync
	isync
	mtspr	SPRN_HID4,r3
	sync
	isync

	/* Restore HID5 */
	ld	r3,CS_HID5(r5)
	sync
	isync
	mtspr	SPRN_HID5,r3
	sync
	isync
	blr
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
	3	* This file contains low level CPU setup functions.
	4	* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
1da177e4 LT	5	*/
1da177e4 LT	6
1da177e4 LT	7	#include <asm/processor.h>
1da177e4 LT	8	#include <asm/page.h>
1da177e4 LT	9	#include <asm/cputable.h>
1da177e4 LT	10	#include <asm/ppc_asm.h>
0013a854	11	#include <asm/asm-offsets.h>
1da177e4 LT	12	#include <asm/cache.h>
1da177e4 LT	13
f39b7a55 OJ	14	_GLOBAL(__cpu_preinit_ppc970)
f39b7a55 OJ	15	/* Do nothing if not running in HV mode */
1da177e4 LT	16	mfmsr r0
	17	rldicl. r0,r0,4,63
	18	beqlr
	19
1da177e4 LT	20	/* Make sure HID4:rm_ci is off before MMU is turned off, that large
	21	* pages are enabled with HID4:61 and clear HID5:DCBZ_size and
	22	* HID5:DCBZ32_ill
	23	*/
	24	li r0,0
	25	mfspr r3,SPRN_HID4
	26	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
	27	rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
	28	sync
	29	mtspr SPRN_HID4,r3
	30	isync
	31	sync
	32	mfspr r3,SPRN_HID5
	33	rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ) /
	34	sync
	35	mtspr SPRN_HID5,r3
	36	isync
	37	sync
	38
	39	/* Setup some basic HID1 features */
	40	mfspr r0,SPRN_HID1
	41	li r3,0x1200 /* enable i-fetch cacheability */
	42	sldi r3,r3,44 /* and prefetch */
	43	or r0,r0,r3
	44	mtspr SPRN_HID1,r0
	45	mtspr SPRN_HID1,r0
	46	isync
	47
	48	/* Clear HIOR */
	49	li r0,0
	50	sync
	51	mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
	52	isync
	53	blr
	54
1da177e4 LT	55	/* Definitions for the table use to save CPU states */
	56	#define CS_HID0 0
	57	#define CS_HID1 8
	58	#define CS_HID4 16
	59	#define CS_HID5 24
	60	#define CS_SIZE 32
	61
	62	.data
	63	.balign L1_CACHE_BYTES,0
8882a4da	64	cpu_state_storage:
1da177e4 LT	65	.space CS_SIZE
	66	.balign L1_CACHE_BYTES,0
	67	.text
8882a4da	68
1da177e4	69
f39b7a55 OJ	70	_GLOBAL(__setup_cpu_ppc970)
f39b7a55 OJ	71	/* Do nothing if not running in HV mode */
6d7c4662 JX	72	mfmsr r0
6d7c4662 JX	73	rldicl. r0,r0,4,63
969391c5	74	beq no_hv_mode
f39b7a55 OJ	75
	76	mfspr r0,SPRN_HID0
	77	li r11,5 /* clear DOZE and SLEEP */
	78	rldimi r0,r11,52,8 /* set NAP and DPM */
ea0763a7 PM	79	li r11,0
ea0763a7 PM	80	rldimi r0,r11,32,31 /* clear EN_ATTN */
5b43d20a OJ	81	b load_hids /* Jump to shared code */
	82
	83
	84	_GLOBAL(__setup_cpu_ppc970MP)
	85	/* Do nothing if not running in HV mode */
	86	mfmsr r0
	87	rldicl. r0,r0,4,63
969391c5	88	beq no_hv_mode
5b43d20a OJ	89
	90	mfspr r0,SPRN_HID0
	91	li r11,0x15 /* clear DOZE and SLEEP */
	92	rldimi r0,r11,52,6 /* set DEEPNAP, NAP and DPM */
	93	li r11,0
	94	rldimi r0,r11,32,31 /* clear EN_ATTN */
	95
	96	load_hids:
f39b7a55 OJ	97	mtspr SPRN_HID0,r0
	98	mfspr r0,SPRN_HID0
	99	mfspr r0,SPRN_HID0
	100	mfspr r0,SPRN_HID0
	101	mfspr r0,SPRN_HID0
	102	mfspr r0,SPRN_HID0
	103	mfspr r0,SPRN_HID0
	104	sync
	105	isync
	106
969391c5 PM	107	/* Try to set LPES = 01 in HID4 */
	108	mfspr r0,SPRN_HID4
	109	clrldi r0,r0,1 /* clear LPES0 */
	110	ori r0,r0,HID4_LPES1 /* set LPES1 */
	111	sync
	112	mtspr SPRN_HID4,r0
	113	isync
	114
f39b7a55	115	/* Save away cpu state */
e31aa453	116	LOAD_REG_ADDR(r5,cpu_state_storage)
6d7c4662 JX	117
6d7c4662 JX	118	/* Save HID0,1,4 and 5 */
1da177e4 LT	119	mfspr r3,SPRN_HID0
	120	std r3,CS_HID0(r5)
	121	mfspr r3,SPRN_HID1
	122	std r3,CS_HID1(r5)
969391c5 PM	123	mfspr r4,SPRN_HID4
969391c5 PM	124	std r4,CS_HID4(r5)
1da177e4 LT	125	mfspr r3,SPRN_HID5
1da177e4 LT	126	std r3,CS_HID5(r5)
8882a4da	127
969391c5 PM	128	/* See if we successfully set LPES1 to 1; if not we are in Apple mode */
	129	andi. r4,r4,HID4_LPES1
	130	bnelr
	131
	132	no_hv_mode:
	133	/* Disable CPU_FTR_HVMODE and exit, since we don't have HV mode */
	134	ld r5,CPU_SPEC_FEATURES(r4)
	135	LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
	136	andc r5,r5,r6
	137	std r5,CPU_SPEC_FEATURES(r4)
1da177e4 LT	138	blr
	139
	140	/* Called with no MMU context (typically MSR:IR/DR off) to
	141	* restore CPU state as backed up by the previous
	142	* function. This does not include cache setting
	143	*/
f39b7a55 OJ	144	_GLOBAL(__restore_cpu_ppc970)
f39b7a55 OJ	145	/* Do nothing if not running in HV mode */
6d7c4662 JX	146	mfmsr r0
	147	rldicl. r0,r0,4,63
	148	beqlr
	149
e31aa453	150	LOAD_REG_ADDR(r5,cpu_state_storage)
6d7c4662	151	/* Before accessing memory, we make sure rm_ci is clear */
1da177e4 LT	152	li r0,0
	153	mfspr r3,SPRN_HID4
	154	rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
	155	sync
	156	mtspr SPRN_HID4,r3
	157	isync
	158	sync
	159
	160	/* Clear interrupt prefix */
	161	li r0,0
	162	sync
	163	mtspr SPRN_HIOR,0
	164	isync
	165
	166	/* Restore HID0 */
	167	ld r3,CS_HID0(r5)
	168	sync
	169	isync
	170	mtspr SPRN_HID0,r3
	171	mfspr r3,SPRN_HID0
	172	mfspr r3,SPRN_HID0
	173	mfspr r3,SPRN_HID0
	174	mfspr r3,SPRN_HID0
	175	mfspr r3,SPRN_HID0
	176	mfspr r3,SPRN_HID0
	177	sync
	178	isync
	179
	180	/* Restore HID1 */
	181	ld r3,CS_HID1(r5)
	182	sync
	183	isync
	184	mtspr SPRN_HID1,r3
	185	mtspr SPRN_HID1,r3
	186	sync
	187	isync
8882a4da	188
1da177e4 LT	189	/* Restore HID4 */
	190	ld r3,CS_HID4(r5)
	191	sync
	192	isync
	193	mtspr SPRN_HID4,r3
	194	sync
	195	isync
	196
	197	/* Restore HID5 */
	198	ld r3,CS_HID5(r5)
	199	sync
	200	isync
	201	mtspr SPRN_HID5,r3
	202	sync
	203	isync
1da177e4 LT	204	blr
1da177e4 LT	205