]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3c8c90ab LV |
2 | * Copyright IBM Corporation 2001, 2005, 2006 |
3 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
4 | * Copyright Linas Vepstas 2005, 2006 | |
cb3bc9d0 | 5 | * Copyright 2001-2012 IBM Corporation. |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
7f52a526 | 25 | #include <linux/debugfs.h> |
cb3bc9d0 | 26 | #include <linux/sched.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/list.h> | |
1da177e4 | 29 | #include <linux/pci.h> |
a3032ca9 | 30 | #include <linux/iommu.h> |
1da177e4 LT |
31 | #include <linux/proc_fs.h> |
32 | #include <linux/rbtree.h> | |
66f9af83 | 33 | #include <linux/reboot.h> |
1da177e4 LT |
34 | #include <linux/seq_file.h> |
35 | #include <linux/spinlock.h> | |
66b15db6 | 36 | #include <linux/export.h> |
acaa6176 SR |
37 | #include <linux/of.h> |
38 | ||
60063497 | 39 | #include <linux/atomic.h> |
1e54b938 | 40 | #include <asm/debug.h> |
1da177e4 | 41 | #include <asm/eeh.h> |
172ca926 | 42 | #include <asm/eeh_event.h> |
1da177e4 | 43 | #include <asm/io.h> |
212d16cd | 44 | #include <asm/iommu.h> |
1da177e4 | 45 | #include <asm/machdep.h> |
172ca926 | 46 | #include <asm/ppc-pci.h> |
1da177e4 | 47 | #include <asm/rtas.h> |
1da177e4 | 48 | |
1da177e4 LT |
49 | |
50 | /** Overview: | |
51 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
52 | * dealing with PCI bus errors that can't be dealt with within the | |
53 | * usual PCI framework, except by check-stopping the CPU. Systems | |
54 | * that are designed for high-availability/reliability cannot afford | |
55 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
56 | * An EEH-capable bridge operates by converting a detected error | |
57 | * into a "slot freeze", taking the PCI adapter off-line, making | |
58 | * the slot behave, from the OS'es point of view, as if the slot | |
59 | * were "empty": all reads return 0xff's and all writes are silently | |
60 | * ignored. EEH slot isolation events can be triggered by parity | |
61 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
62 | * which in turn might be caused by low voltage on the bus, dust, |
63 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
64 | * |
65 | * Note, however, that one of the leading causes of EEH slot | |
66 | * freeze events are buggy device drivers, buggy device microcode, | |
67 | * or buggy device hardware. This is because any attempt by the | |
68 | * device to bus-master data to a memory address that is not | |
69 | * assigned to the device will trigger a slot freeze. (The idea | |
70 | * is to prevent devices-gone-wild from corrupting system memory). | |
71 | * Buggy hardware/drivers will have a miserable time co-existing | |
72 | * with EEH. | |
73 | * | |
74 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 75 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
76 | * whether this is the case, and then take appropriate steps to |
77 | * reset the PCI slot, the PCI device, and then resume operations. | |
78 | * However, until that day, the checking is done here, with the | |
79 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
80 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
81 | * and sent out for processing. | |
82 | */ | |
83 | ||
5c1344e9 | 84 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
85 | * handler after a slot isolation event, it might be broken. |
86 | * This sets the threshold for how many read attempts we allow | |
87 | * before printing an error message. | |
1da177e4 | 88 | */ |
2fd30be8 | 89 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 90 | |
17213c3b | 91 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
fb48dc22 | 92 | #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000) |
9c547768 | 93 | |
d7bb8862 | 94 | /* |
8a5ad356 GS |
95 | * EEH probe mode support, which is part of the flags, |
96 | * is to support multiple platforms for EEH. Some platforms | |
97 | * like pSeries do PCI emunation based on device tree. | |
98 | * However, other platforms like powernv probe PCI devices | |
99 | * from hardware. The flag is used to distinguish that. | |
100 | * In addition, struct eeh_ops::probe would be invoked for | |
101 | * particular OF node or PCI device so that the corresponding | |
102 | * PE would be created there. | |
d7bb8862 | 103 | */ |
8a5ad356 GS |
104 | int eeh_subsystem_flags; |
105 | EXPORT_SYMBOL(eeh_subsystem_flags); | |
106 | ||
107 | /* Platform dependent EEH operations */ | |
108 | struct eeh_ops *eeh_ops = NULL; | |
d7bb8862 | 109 | |
fd761fd8 | 110 | /* Lock to avoid races due to multiple reports of an error */ |
4907581d | 111 | DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 112 | |
212d16cd GS |
113 | /* Lock to protect passed flags */ |
114 | static DEFINE_MUTEX(eeh_dev_mutex); | |
115 | ||
17213c3b LV |
116 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
117 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
118 | * can access it. | |
119 | */ | |
d99bb1db LV |
120 | #define EEH_PCI_REGS_LOG_LEN 4096 |
121 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
122 | ||
e575f8db GS |
123 | /* |
124 | * The struct is used to maintain the EEH global statistic | |
125 | * information. Besides, the EEH global statistics will be | |
126 | * exported to user space through procfs | |
127 | */ | |
128 | struct eeh_stats { | |
129 | u64 no_device; /* PCI device not found */ | |
130 | u64 no_dn; /* OF node not found */ | |
131 | u64 no_cfg_addr; /* Config address not found */ | |
132 | u64 ignored_check; /* EEH check skipped */ | |
133 | u64 total_mmio_ffs; /* Total EEH checks */ | |
134 | u64 false_positives; /* Unnecessary EEH checks */ | |
135 | u64 slot_resets; /* PE reset */ | |
136 | }; | |
137 | ||
138 | static struct eeh_stats eeh_stats; | |
1da177e4 | 139 | |
7684b40c LV |
140 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
141 | ||
7f52a526 GS |
142 | static int __init eeh_setup(char *str) |
143 | { | |
144 | if (!strcmp(str, "off")) | |
05b1721d | 145 | eeh_add_flag(EEH_FORCE_DISABLED); |
7f52a526 GS |
146 | |
147 | return 1; | |
148 | } | |
149 | __setup("eeh=", eeh_setup); | |
150 | ||
d99bb1db | 151 | /** |
cce4b2d2 | 152 | * eeh_gather_pci_data - Copy assorted PCI config space registers to buff |
f631acd3 | 153 | * @edev: device to report data for |
d99bb1db LV |
154 | * @buf: point to buffer in which to log |
155 | * @len: amount of room in buffer | |
156 | * | |
157 | * This routine captures assorted PCI configuration space data, | |
158 | * and puts them into a buffer for RTAS error logging. | |
159 | */ | |
f631acd3 | 160 | static size_t eeh_gather_pci_data(struct eeh_dev *edev, char * buf, size_t len) |
d99bb1db | 161 | { |
f631acd3 | 162 | struct device_node *dn = eeh_dev_to_of_node(edev); |
d99bb1db | 163 | u32 cfg; |
fcf9892b | 164 | int cap, i; |
d99bb1db LV |
165 | int n = 0; |
166 | ||
f631acd3 | 167 | n += scnprintf(buf+n, len-n, "%s\n", dn->full_name); |
2d86c385 | 168 | pr_warn("EEH: of node=%s\n", dn->full_name); |
fcf9892b | 169 | |
3780444c | 170 | eeh_ops->read_config(dn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b | 171 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
2d86c385 | 172 | pr_warn("EEH: PCI device/vendor: %08x\n", cfg); |
fcf9892b | 173 | |
3780444c | 174 | eeh_ops->read_config(dn, PCI_COMMAND, 4, &cfg); |
d99bb1db | 175 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); |
2d86c385 | 176 | pr_warn("EEH: PCI cmd/status register: %08x\n", cfg); |
fcf9892b | 177 | |
0b9369f4 | 178 | /* Gather bridge-specific registers */ |
2a18dfc6 | 179 | if (edev->mode & EEH_DEV_BRIDGE) { |
3780444c | 180 | eeh_ops->read_config(dn, PCI_SEC_STATUS, 2, &cfg); |
0b9369f4 | 181 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); |
2d86c385 | 182 | pr_warn("EEH: Bridge secondary status: %04x\n", cfg); |
0b9369f4 | 183 | |
3780444c | 184 | eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &cfg); |
0b9369f4 | 185 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); |
2d86c385 | 186 | pr_warn("EEH: Bridge control: %04x\n", cfg); |
0b9369f4 LV |
187 | } |
188 | ||
fcf9892b | 189 | /* Dump out the PCI-X command and status regs */ |
2a18dfc6 | 190 | cap = edev->pcix_cap; |
fcf9892b | 191 | if (cap) { |
3780444c | 192 | eeh_ops->read_config(dn, cap, 4, &cfg); |
fcf9892b | 193 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); |
2d86c385 | 194 | pr_warn("EEH: PCI-X cmd: %08x\n", cfg); |
fcf9892b | 195 | |
3780444c | 196 | eeh_ops->read_config(dn, cap+4, 4, &cfg); |
fcf9892b | 197 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); |
2d86c385 | 198 | pr_warn("EEH: PCI-X status: %08x\n", cfg); |
fcf9892b LV |
199 | } |
200 | ||
2a18dfc6 GS |
201 | /* If PCI-E capable, dump PCI-E cap 10 */ |
202 | cap = edev->pcie_cap; | |
203 | if (cap) { | |
fcf9892b | 204 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); |
2d86c385 | 205 | pr_warn("EEH: PCI-E capabilities and status follow:\n"); |
fcf9892b LV |
206 | |
207 | for (i=0; i<=8; i++) { | |
2a18dfc6 | 208 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); |
fcf9892b | 209 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); |
2d86c385 | 210 | pr_warn("EEH: PCI-E %02x: %08x\n", i, cfg); |
fcf9892b | 211 | } |
2a18dfc6 | 212 | } |
fcf9892b | 213 | |
2a18dfc6 GS |
214 | /* If AER capable, dump it */ |
215 | cap = edev->aer_cap; | |
216 | if (cap) { | |
217 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
218 | pr_warn("EEH: PCI-E AER capability register set follows:\n"); | |
219 | ||
220 | for (i=0; i<14; i++) { | |
221 | eeh_ops->read_config(dn, cap+4*i, 4, &cfg); | |
222 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
223 | pr_warn("EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
fcf9892b LV |
224 | } |
225 | } | |
0b9369f4 | 226 | |
d99bb1db LV |
227 | return n; |
228 | } | |
229 | ||
cb3bc9d0 GS |
230 | /** |
231 | * eeh_slot_error_detail - Generate combined log including driver log and error log | |
ff477966 | 232 | * @pe: EEH PE |
cb3bc9d0 GS |
233 | * @severity: temporary or permanent error log |
234 | * | |
235 | * This routine should be called to generate the combined log, which | |
236 | * is comprised of driver log and error log. The driver log is figured | |
237 | * out from the config space of the corresponding PCI device, while | |
238 | * the error log is fetched through platform dependent function call. | |
239 | */ | |
ff477966 | 240 | void eeh_slot_error_detail(struct eeh_pe *pe, int severity) |
d99bb1db LV |
241 | { |
242 | size_t loglen = 0; | |
9feed42e | 243 | struct eeh_dev *edev, *tmp; |
d99bb1db | 244 | |
c35ae179 GS |
245 | /* |
246 | * When the PHB is fenced or dead, it's pointless to collect | |
247 | * the data from PCI config space because it should return | |
248 | * 0xFF's. For ER, we still retrieve the data from the PCI | |
249 | * config space. | |
78954700 GS |
250 | * |
251 | * For pHyp, we have to enable IO for log retrieval. Otherwise, | |
252 | * 0xFF's is always returned from PCI config space. | |
c35ae179 | 253 | */ |
9e049375 | 254 | if (!(pe->type & EEH_PE_PHB)) { |
dc561fb9 | 255 | if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG)) |
78954700 | 256 | eeh_pci_enable(pe, EEH_OPT_THAW_MMIO); |
c35ae179 GS |
257 | eeh_ops->configure_bridge(pe); |
258 | eeh_pe_restore_bars(pe); | |
259 | ||
260 | pci_regs_buf[0] = 0; | |
9feed42e | 261 | eeh_pe_for_each_dev(pe, edev, tmp) { |
c35ae179 GS |
262 | loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen, |
263 | EEH_PCI_REGS_LOG_LEN - loglen); | |
264 | } | |
265 | } | |
ff477966 GS |
266 | |
267 | eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); | |
d99bb1db LV |
268 | } |
269 | ||
1da177e4 | 270 | /** |
cb3bc9d0 GS |
271 | * eeh_token_to_phys - Convert EEH address token to phys address |
272 | * @token: I/O token, should be address in the form 0xA.... | |
273 | * | |
274 | * This routine should be called to convert virtual I/O address | |
275 | * to physical one. | |
1da177e4 LT |
276 | */ |
277 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
278 | { | |
279 | pte_t *ptep; | |
280 | unsigned long pa; | |
12bc9f6f | 281 | int hugepage_shift; |
1da177e4 | 282 | |
12bc9f6f AK |
283 | /* |
284 | * We won't find hugepages here, iomem | |
285 | */ | |
286 | ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift); | |
1da177e4 LT |
287 | if (!ptep) |
288 | return token; | |
12bc9f6f | 289 | WARN_ON(hugepage_shift); |
1da177e4 LT |
290 | pa = pte_pfn(*ptep) << PAGE_SHIFT; |
291 | ||
292 | return pa | (token & (PAGE_SIZE-1)); | |
293 | } | |
294 | ||
b95cd2cd GS |
295 | /* |
296 | * On PowerNV platform, we might already have fenced PHB there. | |
297 | * For that case, it's meaningless to recover frozen PE. Intead, | |
298 | * We have to handle fenced PHB firstly. | |
299 | */ | |
300 | static int eeh_phb_check_failure(struct eeh_pe *pe) | |
301 | { | |
302 | struct eeh_pe *phb_pe; | |
303 | unsigned long flags; | |
304 | int ret; | |
305 | ||
05b1721d | 306 | if (!eeh_has_flag(EEH_PROBE_MODE_DEV)) |
b95cd2cd GS |
307 | return -EPERM; |
308 | ||
309 | /* Find the PHB PE */ | |
310 | phb_pe = eeh_phb_pe_get(pe->phb); | |
311 | if (!phb_pe) { | |
312 | pr_warning("%s Can't find PE for PHB#%d\n", | |
313 | __func__, pe->phb->global_number); | |
314 | return -EEXIST; | |
315 | } | |
316 | ||
317 | /* If the PHB has been in problematic state */ | |
318 | eeh_serialize_lock(&flags); | |
9e049375 | 319 | if (phb_pe->state & EEH_PE_ISOLATED) { |
b95cd2cd GS |
320 | ret = 0; |
321 | goto out; | |
322 | } | |
323 | ||
324 | /* Check PHB state */ | |
325 | ret = eeh_ops->get_state(phb_pe, NULL); | |
326 | if ((ret < 0) || | |
327 | (ret == EEH_STATE_NOT_SUPPORT) || | |
328 | (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) == | |
329 | (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) { | |
330 | ret = 0; | |
331 | goto out; | |
332 | } | |
333 | ||
334 | /* Isolate the PHB and send event */ | |
335 | eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED); | |
336 | eeh_serialize_unlock(flags); | |
b95cd2cd | 337 | |
357b2f3d GS |
338 | pr_err("EEH: PHB#%x failure detected, location: %s\n", |
339 | phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe)); | |
56ca4fde | 340 | dump_stack(); |
5293bf97 | 341 | eeh_send_failure_event(phb_pe); |
b95cd2cd GS |
342 | |
343 | return 1; | |
344 | out: | |
345 | eeh_serialize_unlock(flags); | |
346 | return ret; | |
347 | } | |
348 | ||
1da177e4 | 349 | /** |
f8f7d63f GS |
350 | * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze |
351 | * @edev: eeh device | |
1da177e4 LT |
352 | * |
353 | * Check for an EEH failure for the given device node. Call this | |
354 | * routine if the result of a read was all 0xff's and you want to | |
355 | * find out if this is due to an EEH slot freeze. This routine | |
356 | * will query firmware for the EEH status. | |
357 | * | |
358 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 359 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
360 | * |
361 | * It is safe to call this routine in an interrupt context. | |
362 | */ | |
f8f7d63f | 363 | int eeh_dev_check_failure(struct eeh_dev *edev) |
1da177e4 LT |
364 | { |
365 | int ret; | |
1ad7a72c | 366 | int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
1da177e4 | 367 | unsigned long flags; |
f8f7d63f GS |
368 | struct device_node *dn; |
369 | struct pci_dev *dev; | |
357b2f3d | 370 | struct eeh_pe *pe, *parent_pe, *phb_pe; |
fd761fd8 | 371 | int rc = 0; |
f36c5227 | 372 | const char *location; |
1da177e4 | 373 | |
e575f8db | 374 | eeh_stats.total_mmio_ffs++; |
1da177e4 | 375 | |
2ec5a0ad | 376 | if (!eeh_enabled()) |
1da177e4 LT |
377 | return 0; |
378 | ||
f8f7d63f | 379 | if (!edev) { |
e575f8db | 380 | eeh_stats.no_dn++; |
1da177e4 | 381 | return 0; |
177bc936 | 382 | } |
f8f7d63f GS |
383 | dn = eeh_dev_to_of_node(edev); |
384 | dev = eeh_dev_to_pci_dev(edev); | |
66523d9f | 385 | pe = edev->pe; |
1da177e4 LT |
386 | |
387 | /* Access to IO BARs might get this far and still not want checking. */ | |
66523d9f | 388 | if (!pe) { |
e575f8db | 389 | eeh_stats.ignored_check++; |
66523d9f GS |
390 | pr_debug("EEH: Ignored check for %s %s\n", |
391 | eeh_pci_name(dev), dn->full_name); | |
1da177e4 LT |
392 | return 0; |
393 | } | |
394 | ||
66523d9f | 395 | if (!pe->addr && !pe->config_addr) { |
e575f8db | 396 | eeh_stats.no_cfg_addr++; |
1da177e4 LT |
397 | return 0; |
398 | } | |
399 | ||
b95cd2cd GS |
400 | /* |
401 | * On PowerNV platform, we might already have fenced PHB | |
402 | * there and we need take care of that firstly. | |
403 | */ | |
404 | ret = eeh_phb_check_failure(pe); | |
405 | if (ret > 0) | |
406 | return ret; | |
407 | ||
05ec424e GS |
408 | /* |
409 | * If the PE isn't owned by us, we shouldn't check the | |
410 | * state. Instead, let the owner handle it if the PE has | |
411 | * been frozen. | |
412 | */ | |
413 | if (eeh_pe_passed(pe)) | |
414 | return 0; | |
415 | ||
fd761fd8 LV |
416 | /* If we already have a pending isolation event for this |
417 | * slot, we know it's bad already, we don't need to check. | |
418 | * Do this checking under a lock; as multiple PCI devices | |
419 | * in one slot might report errors simultaneously, and we | |
420 | * only want one error recovery routine running. | |
1da177e4 | 421 | */ |
4907581d | 422 | eeh_serialize_lock(&flags); |
fd761fd8 | 423 | rc = 1; |
66523d9f GS |
424 | if (pe->state & EEH_PE_ISOLATED) { |
425 | pe->check_count++; | |
426 | if (pe->check_count % EEH_MAX_FAILS == 0) { | |
f36c5227 | 427 | location = of_get_property(dn, "ibm,loc-code", NULL); |
cb3bc9d0 | 428 | printk(KERN_ERR "EEH: %d reads ignored for recovering device at " |
f36c5227 | 429 | "location=%s driver=%s pci addr=%s\n", |
66523d9f | 430 | pe->check_count, location, |
778a785f | 431 | eeh_driver_name(dev), eeh_pci_name(dev)); |
cb3bc9d0 | 432 | printk(KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
778a785f | 433 | eeh_driver_name(dev)); |
5c1344e9 | 434 | dump_stack(); |
1da177e4 | 435 | } |
fd761fd8 | 436 | goto dn_unlock; |
1da177e4 LT |
437 | } |
438 | ||
439 | /* | |
440 | * Now test for an EEH failure. This is VERY expensive. | |
441 | * Note that the eeh_config_addr may be a parent device | |
442 | * in the case of a device behind a bridge, or it may be | |
443 | * function zero of a multi-function device. | |
444 | * In any case they must share a common PHB. | |
445 | */ | |
66523d9f | 446 | ret = eeh_ops->get_state(pe, NULL); |
76e6faf7 | 447 | |
39d16e29 | 448 | /* Note that config-io to empty slots may fail; |
cb3bc9d0 | 449 | * they are empty when they don't have children. |
eb594a47 GS |
450 | * We will punt with the following conditions: Failure to get |
451 | * PE's state, EEH not support and Permanently unavailable | |
452 | * state, PE is in good state. | |
cb3bc9d0 | 453 | */ |
eb594a47 GS |
454 | if ((ret < 0) || |
455 | (ret == EEH_STATE_NOT_SUPPORT) || | |
1ad7a72c | 456 | ((ret & active_flags) == active_flags)) { |
e575f8db | 457 | eeh_stats.false_positives++; |
66523d9f | 458 | pe->false_positives++; |
fd761fd8 LV |
459 | rc = 0; |
460 | goto dn_unlock; | |
76e6faf7 LV |
461 | } |
462 | ||
1ad7a72c GS |
463 | /* |
464 | * It should be corner case that the parent PE has been | |
465 | * put into frozen state as well. We should take care | |
466 | * that at first. | |
467 | */ | |
468 | parent_pe = pe->parent; | |
469 | while (parent_pe) { | |
470 | /* Hit the ceiling ? */ | |
471 | if (parent_pe->type & EEH_PE_PHB) | |
472 | break; | |
473 | ||
474 | /* Frozen parent PE ? */ | |
475 | ret = eeh_ops->get_state(parent_pe, NULL); | |
476 | if (ret > 0 && | |
477 | (ret & active_flags) != active_flags) | |
478 | pe = parent_pe; | |
479 | ||
480 | /* Next parent level */ | |
481 | parent_pe = parent_pe->parent; | |
482 | } | |
483 | ||
e575f8db | 484 | eeh_stats.slot_resets++; |
a84f273c | 485 | |
fd761fd8 LV |
486 | /* Avoid repeated reports of this failure, including problems |
487 | * with other functions on this device, and functions under | |
cb3bc9d0 GS |
488 | * bridges. |
489 | */ | |
66523d9f | 490 | eeh_pe_state_mark(pe, EEH_PE_ISOLATED); |
4907581d | 491 | eeh_serialize_unlock(flags); |
1da177e4 | 492 | |
1da177e4 LT |
493 | /* Most EEH events are due to device driver bugs. Having |
494 | * a stack trace will help the device-driver authors figure | |
cb3bc9d0 GS |
495 | * out what happened. So print that out. |
496 | */ | |
357b2f3d GS |
497 | phb_pe = eeh_phb_pe_get(pe->phb); |
498 | pr_err("EEH: Frozen PHB#%x-PE#%x detected\n", | |
499 | pe->phb->global_number, pe->addr); | |
500 | pr_err("EEH: PE location: %s, PHB location: %s\n", | |
501 | eeh_pe_loc_get(pe), eeh_pe_loc_get(phb_pe)); | |
56ca4fde GS |
502 | dump_stack(); |
503 | ||
5293bf97 GS |
504 | eeh_send_failure_event(pe); |
505 | ||
fd761fd8 LV |
506 | return 1; |
507 | ||
508 | dn_unlock: | |
4907581d | 509 | eeh_serialize_unlock(flags); |
fd761fd8 | 510 | return rc; |
1da177e4 LT |
511 | } |
512 | ||
f8f7d63f | 513 | EXPORT_SYMBOL_GPL(eeh_dev_check_failure); |
1da177e4 LT |
514 | |
515 | /** | |
cb3bc9d0 GS |
516 | * eeh_check_failure - Check if all 1's data is due to EEH slot freeze |
517 | * @token: I/O token, should be address in the form 0xA.... | |
518 | * @val: value, should be all 1's (XXX why do we need this arg??) | |
1da177e4 | 519 | * |
1da177e4 LT |
520 | * Check for an EEH failure at the given token address. Call this |
521 | * routine if the result of a read was all 0xff's and you want to | |
522 | * find out if this is due to an EEH slot freeze event. This routine | |
523 | * will query firmware for the EEH status. | |
524 | * | |
525 | * Note this routine is safe to call in an interrupt context. | |
526 | */ | |
527 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
528 | { | |
529 | unsigned long addr; | |
f8f7d63f | 530 | struct eeh_dev *edev; |
1da177e4 LT |
531 | |
532 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
533 | addr = eeh_token_to_phys((unsigned long __force) token); | |
3ab96a02 | 534 | edev = eeh_addr_cache_get_dev(addr); |
f8f7d63f | 535 | if (!edev) { |
e575f8db | 536 | eeh_stats.no_device++; |
1da177e4 | 537 | return val; |
177bc936 | 538 | } |
1da177e4 | 539 | |
f8f7d63f | 540 | eeh_dev_check_failure(edev); |
1da177e4 LT |
541 | return val; |
542 | } | |
543 | ||
544 | EXPORT_SYMBOL(eeh_check_failure); | |
545 | ||
6dee3fb9 | 546 | |
47b5c838 | 547 | /** |
cce4b2d2 | 548 | * eeh_pci_enable - Enable MMIO or DMA transfers for this slot |
ff477966 | 549 | * @pe: EEH PE |
cb3bc9d0 GS |
550 | * |
551 | * This routine should be called to reenable frozen MMIO or DMA | |
552 | * so that it would work correctly again. It's useful while doing | |
553 | * recovery or log collection on the indicated device. | |
47b5c838 | 554 | */ |
ff477966 | 555 | int eeh_pci_enable(struct eeh_pe *pe, int function) |
47b5c838 | 556 | { |
78954700 GS |
557 | int rc, flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
558 | ||
559 | /* | |
560 | * pHyp doesn't allow to enable IO or DMA on unfrozen PE. | |
561 | * Also, it's pointless to enable them on unfrozen PE. So | |
562 | * we have the check here. | |
563 | */ | |
564 | if (function == EEH_OPT_THAW_MMIO || | |
565 | function == EEH_OPT_THAW_DMA) { | |
566 | rc = eeh_ops->get_state(pe, NULL); | |
567 | if (rc < 0) | |
568 | return rc; | |
569 | ||
570 | /* Needn't to enable or already enabled */ | |
571 | if ((rc == EEH_STATE_NOT_SUPPORT) || | |
572 | ((rc & flags) == flags)) | |
573 | return 0; | |
574 | } | |
47b5c838 | 575 | |
ff477966 | 576 | rc = eeh_ops->set_option(pe, function); |
47b5c838 | 577 | if (rc) |
78954700 GS |
578 | pr_warn("%s: Unexpected state change %d on " |
579 | "PHB#%d-PE#%x, err=%d\n", | |
580 | __func__, function, pe->phb->global_number, | |
581 | pe->addr, rc); | |
47b5c838 | 582 | |
ff477966 | 583 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 GS |
584 | if (rc <= 0) |
585 | return rc; | |
586 | ||
587 | if ((function == EEH_OPT_THAW_MMIO) && | |
588 | (rc & EEH_STATE_MMIO_ENABLED)) | |
589 | return 0; | |
590 | ||
591 | if ((function == EEH_OPT_THAW_DMA) && | |
592 | (rc & EEH_STATE_DMA_ENABLED)) | |
fa1be476 LV |
593 | return 0; |
594 | ||
47b5c838 LV |
595 | return rc; |
596 | } | |
597 | ||
00c2ae35 BK |
598 | /** |
599 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
cb3bc9d0 GS |
600 | * @dev: pci device struct |
601 | * @state: reset state to enter | |
00c2ae35 BK |
602 | * |
603 | * Return value: | |
604 | * 0 if success | |
cb3bc9d0 | 605 | */ |
00c2ae35 BK |
606 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) |
607 | { | |
c270a24c GS |
608 | struct eeh_dev *edev = pci_dev_to_eeh_dev(dev); |
609 | struct eeh_pe *pe = edev->pe; | |
610 | ||
611 | if (!pe) { | |
612 | pr_err("%s: No PE found on PCI device %s\n", | |
613 | __func__, pci_name(dev)); | |
614 | return -EINVAL; | |
615 | } | |
00c2ae35 BK |
616 | |
617 | switch (state) { | |
618 | case pcie_deassert_reset: | |
c270a24c | 619 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
00c2ae35 BK |
620 | break; |
621 | case pcie_hot_reset: | |
c270a24c | 622 | eeh_ops->reset(pe, EEH_RESET_HOT); |
00c2ae35 BK |
623 | break; |
624 | case pcie_warm_reset: | |
c270a24c | 625 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
00c2ae35 BK |
626 | break; |
627 | default: | |
628 | return -EINVAL; | |
629 | }; | |
630 | ||
631 | return 0; | |
632 | } | |
633 | ||
cb5b5624 | 634 | /** |
c270a24c GS |
635 | * eeh_set_pe_freset - Check the required reset for the indicated device |
636 | * @data: EEH device | |
637 | * @flag: return value | |
cb3bc9d0 GS |
638 | * |
639 | * Each device might have its preferred reset type: fundamental or | |
640 | * hot reset. The routine is used to collected the information for | |
641 | * the indicated device and its children so that the bunch of the | |
642 | * devices could be reset properly. | |
643 | */ | |
c270a24c | 644 | static void *eeh_set_dev_freset(void *data, void *flag) |
cb3bc9d0 GS |
645 | { |
646 | struct pci_dev *dev; | |
c270a24c GS |
647 | unsigned int *freset = (unsigned int *)flag; |
648 | struct eeh_dev *edev = (struct eeh_dev *)data; | |
6dee3fb9 | 649 | |
c270a24c | 650 | dev = eeh_dev_to_pci_dev(edev); |
cb3bc9d0 GS |
651 | if (dev) |
652 | *freset |= dev->needs_freset; | |
653 | ||
c270a24c | 654 | return NULL; |
cb3bc9d0 GS |
655 | } |
656 | ||
657 | /** | |
cce4b2d2 | 658 | * eeh_reset_pe_once - Assert the pci #RST line for 1/4 second |
c270a24c | 659 | * @pe: EEH PE |
cb3bc9d0 GS |
660 | * |
661 | * Assert the PCI #RST line for 1/4 second. | |
662 | */ | |
c270a24c | 663 | static void eeh_reset_pe_once(struct eeh_pe *pe) |
6dee3fb9 | 664 | { |
308fc4f8 | 665 | unsigned int freset = 0; |
6e19314c | 666 | |
308fc4f8 RL |
667 | /* Determine type of EEH reset required for |
668 | * Partitionable Endpoint, a hot-reset (1) | |
669 | * or a fundamental reset (3). | |
670 | * A fundamental reset required by any device under | |
671 | * Partitionable Endpoint trumps hot-reset. | |
a84f273c | 672 | */ |
c270a24c | 673 | eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset); |
308fc4f8 RL |
674 | |
675 | if (freset) | |
c270a24c | 676 | eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); |
6e19314c | 677 | else |
c270a24c | 678 | eeh_ops->reset(pe, EEH_RESET_HOT); |
6dee3fb9 | 679 | |
c270a24c | 680 | eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); |
e1029263 LV |
681 | } |
682 | ||
cb3bc9d0 | 683 | /** |
cce4b2d2 | 684 | * eeh_reset_pe - Reset the indicated PE |
c270a24c | 685 | * @pe: EEH PE |
cb3bc9d0 GS |
686 | * |
687 | * This routine should be called to reset indicated device, including | |
688 | * PE. A PE might include multiple PCI devices and sometimes PCI bridges | |
689 | * might be involved as well. | |
690 | */ | |
c270a24c | 691 | int eeh_reset_pe(struct eeh_pe *pe) |
e1029263 | 692 | { |
326a98ea | 693 | int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); |
e1029263 LV |
694 | int i, rc; |
695 | ||
9c547768 LV |
696 | /* Take three shots at resetting the bus */ |
697 | for (i=0; i<3; i++) { | |
c270a24c | 698 | eeh_reset_pe_once(pe); |
6dee3fb9 | 699 | |
78954700 GS |
700 | /* |
701 | * EEH_PE_ISOLATED is expected to be removed after | |
702 | * BAR restore. | |
703 | */ | |
c270a24c | 704 | rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); |
78954700 | 705 | if ((rc & flags) == flags) |
b6495c0c | 706 | return 0; |
e1029263 | 707 | |
e1029263 | 708 | if (rc < 0) { |
c270a24c GS |
709 | pr_err("%s: Unrecoverable slot failure on PHB#%d-PE#%x", |
710 | __func__, pe->phb->global_number, pe->addr); | |
b6495c0c | 711 | return -1; |
e1029263 | 712 | } |
c270a24c GS |
713 | pr_err("EEH: bus reset %d failed on PHB#%d-PE#%x, rc=%d\n", |
714 | i+1, pe->phb->global_number, pe->addr, rc); | |
6dee3fb9 | 715 | } |
b6495c0c | 716 | |
9c547768 | 717 | return -1; |
6dee3fb9 LV |
718 | } |
719 | ||
8b553f32 | 720 | /** |
cb3bc9d0 | 721 | * eeh_save_bars - Save device bars |
f631acd3 | 722 | * @edev: PCI device associated EEH device |
8b553f32 LV |
723 | * |
724 | * Save the values of the device bars. Unlike the restore | |
725 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 726 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
727 | * an entire slot is reset at a time. |
728 | */ | |
d7bb8862 | 729 | void eeh_save_bars(struct eeh_dev *edev) |
8b553f32 LV |
730 | { |
731 | int i; | |
f631acd3 | 732 | struct device_node *dn; |
8b553f32 | 733 | |
f631acd3 | 734 | if (!edev) |
8b553f32 | 735 | return; |
f631acd3 | 736 | dn = eeh_dev_to_of_node(edev); |
a84f273c | 737 | |
8b553f32 | 738 | for (i = 0; i < 16; i++) |
3780444c | 739 | eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]); |
bf898ec5 GS |
740 | |
741 | /* | |
742 | * For PCI bridges including root port, we need enable bus | |
743 | * master explicitly. Otherwise, it can't fetch IODA table | |
744 | * entries correctly. So we cache the bit in advance so that | |
745 | * we can restore it after reset, either PHB range or PE range. | |
746 | */ | |
747 | if (edev->mode & EEH_DEV_BRIDGE) | |
748 | edev->config_space[1] |= PCI_COMMAND_MASTER; | |
8b553f32 LV |
749 | } |
750 | ||
aa1e6374 GS |
751 | /** |
752 | * eeh_ops_register - Register platform dependent EEH operations | |
753 | * @ops: platform dependent EEH operations | |
754 | * | |
755 | * Register the platform dependent EEH operation callback | |
756 | * functions. The platform should call this function before | |
757 | * any other EEH operations. | |
758 | */ | |
759 | int __init eeh_ops_register(struct eeh_ops *ops) | |
760 | { | |
761 | if (!ops->name) { | |
762 | pr_warning("%s: Invalid EEH ops name for %p\n", | |
763 | __func__, ops); | |
764 | return -EINVAL; | |
765 | } | |
766 | ||
767 | if (eeh_ops && eeh_ops != ops) { | |
768 | pr_warning("%s: EEH ops of platform %s already existing (%s)\n", | |
769 | __func__, eeh_ops->name, ops->name); | |
770 | return -EEXIST; | |
771 | } | |
772 | ||
773 | eeh_ops = ops; | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
778 | /** | |
779 | * eeh_ops_unregister - Unreigster platform dependent EEH operations | |
780 | * @name: name of EEH platform operations | |
781 | * | |
782 | * Unregister the platform dependent EEH operation callback | |
783 | * functions. | |
784 | */ | |
785 | int __exit eeh_ops_unregister(const char *name) | |
786 | { | |
787 | if (!name || !strlen(name)) { | |
788 | pr_warning("%s: Invalid EEH ops name\n", | |
789 | __func__); | |
790 | return -EINVAL; | |
791 | } | |
792 | ||
793 | if (eeh_ops && !strcmp(eeh_ops->name, name)) { | |
794 | eeh_ops = NULL; | |
795 | return 0; | |
796 | } | |
797 | ||
798 | return -EEXIST; | |
799 | } | |
800 | ||
66f9af83 GS |
801 | static int eeh_reboot_notifier(struct notifier_block *nb, |
802 | unsigned long action, void *unused) | |
803 | { | |
05b1721d | 804 | eeh_clear_flag(EEH_ENABLED); |
66f9af83 GS |
805 | return NOTIFY_DONE; |
806 | } | |
807 | ||
808 | static struct notifier_block eeh_reboot_nb = { | |
809 | .notifier_call = eeh_reboot_notifier, | |
810 | }; | |
811 | ||
cb3bc9d0 GS |
812 | /** |
813 | * eeh_init - EEH initialization | |
814 | * | |
1da177e4 LT |
815 | * Initialize EEH by trying to enable it for all of the adapters in the system. |
816 | * As a side effect we can determine here if eeh is supported at all. | |
817 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
818 | * check. If a user turns off EEH for a particular adapter they are really | |
819 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
820 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
821 | * EEH for all slots/all devices. | |
822 | * | |
823 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
824 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
825 | * newer systems can boot. | |
826 | */ | |
eeb6361f | 827 | int eeh_init(void) |
1da177e4 | 828 | { |
1a5c2e63 GS |
829 | struct pci_controller *hose, *tmp; |
830 | struct device_node *phb; | |
51fb5f56 GS |
831 | static int cnt = 0; |
832 | int ret = 0; | |
833 | ||
834 | /* | |
835 | * We have to delay the initialization on PowerNV after | |
836 | * the PCI hierarchy tree has been built because the PEs | |
837 | * are figured out based on PCI devices instead of device | |
838 | * tree nodes | |
839 | */ | |
840 | if (machine_is(powernv) && cnt++ <= 0) | |
841 | return ret; | |
e2af155c | 842 | |
66f9af83 GS |
843 | /* Register reboot notifier */ |
844 | ret = register_reboot_notifier(&eeh_reboot_nb); | |
845 | if (ret) { | |
846 | pr_warn("%s: Failed to register notifier (%d)\n", | |
847 | __func__, ret); | |
848 | return ret; | |
849 | } | |
850 | ||
e2af155c GS |
851 | /* call platform initialization function */ |
852 | if (!eeh_ops) { | |
853 | pr_warning("%s: Platform EEH operation not found\n", | |
854 | __func__); | |
35e5cfe2 | 855 | return -EEXIST; |
e2af155c GS |
856 | } else if ((ret = eeh_ops->init())) { |
857 | pr_warning("%s: Failed to call platform init function (%d)\n", | |
858 | __func__, ret); | |
35e5cfe2 | 859 | return ret; |
e2af155c | 860 | } |
1da177e4 | 861 | |
c8608558 GS |
862 | /* Initialize EEH event */ |
863 | ret = eeh_event_init(); | |
864 | if (ret) | |
865 | return ret; | |
866 | ||
1a5c2e63 | 867 | /* Enable EEH for all adapters */ |
05b1721d | 868 | if (eeh_has_flag(EEH_PROBE_MODE_DEVTREE)) { |
d7bb8862 GS |
869 | list_for_each_entry_safe(hose, tmp, |
870 | &hose_list, list_node) { | |
871 | phb = hose->dn; | |
872 | traverse_pci_devices(phb, eeh_ops->of_probe, NULL); | |
873 | } | |
05b1721d | 874 | } else if (eeh_has_flag(EEH_PROBE_MODE_DEV)) { |
51fb5f56 GS |
875 | list_for_each_entry_safe(hose, tmp, |
876 | &hose_list, list_node) | |
877 | pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL); | |
878 | } else { | |
8a5ad356 GS |
879 | pr_warn("%s: Invalid probe mode %x", |
880 | __func__, eeh_subsystem_flags); | |
51fb5f56 | 881 | return -EINVAL; |
1da177e4 LT |
882 | } |
883 | ||
21fd21f5 GS |
884 | /* |
885 | * Call platform post-initialization. Actually, It's good chance | |
886 | * to inform platform that EEH is ready to supply service if the | |
887 | * I/O cache stuff has been built up. | |
888 | */ | |
889 | if (eeh_ops->post_init) { | |
890 | ret = eeh_ops->post_init(); | |
891 | if (ret) | |
892 | return ret; | |
893 | } | |
894 | ||
2ec5a0ad | 895 | if (eeh_enabled()) |
d7bb8862 | 896 | pr_info("EEH: PCI Enhanced I/O Error Handling Enabled\n"); |
1da177e4 | 897 | else |
d7bb8862 | 898 | pr_warning("EEH: No capable adapters found\n"); |
35e5cfe2 GS |
899 | |
900 | return ret; | |
1da177e4 LT |
901 | } |
902 | ||
35e5cfe2 GS |
903 | core_initcall_sync(eeh_init); |
904 | ||
1da177e4 | 905 | /** |
cb3bc9d0 | 906 | * eeh_add_device_early - Enable EEH for the indicated device_node |
1da177e4 LT |
907 | * @dn: device node for which to set up EEH |
908 | * | |
909 | * This routine must be used to perform EEH initialization for PCI | |
910 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
911 | * This routine must be called before any i/o is performed to the | |
912 | * adapter (inluding any config-space i/o). | |
913 | * Whether this actually enables EEH or not for this device depends | |
914 | * on the CEC architecture, type of the device, on earlier boot | |
915 | * command-line arguments & etc. | |
916 | */ | |
f2856491 | 917 | void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
918 | { |
919 | struct pci_controller *phb; | |
1da177e4 | 920 | |
26a74850 GS |
921 | /* |
922 | * If we're doing EEH probe based on PCI device, we | |
923 | * would delay the probe until late stage because | |
924 | * the PCI device isn't available this moment. | |
925 | */ | |
05b1721d | 926 | if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE)) |
26a74850 GS |
927 | return; |
928 | ||
1e38b714 | 929 | if (!of_node_to_eeh_dev(dn)) |
1da177e4 | 930 | return; |
f631acd3 | 931 | phb = of_node_to_eeh_dev(dn)->phb; |
f751f841 LV |
932 | |
933 | /* USB Bus children of PCI devices will not have BUID's */ | |
934 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 935 | return; |
1da177e4 | 936 | |
d7bb8862 | 937 | eeh_ops->of_probe(dn, NULL); |
1da177e4 | 938 | } |
1da177e4 | 939 | |
cb3bc9d0 GS |
940 | /** |
941 | * eeh_add_device_tree_early - Enable EEH for the indicated device | |
942 | * @dn: device node | |
943 | * | |
944 | * This routine must be used to perform EEH initialization for the | |
945 | * indicated PCI device that was added after system boot (e.g. | |
946 | * hotplug, dlpar). | |
947 | */ | |
e2a296ee LV |
948 | void eeh_add_device_tree_early(struct device_node *dn) |
949 | { | |
950 | struct device_node *sib; | |
acaa6176 SR |
951 | |
952 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
953 | eeh_add_device_tree_early(sib); |
954 | eeh_add_device_early(dn); | |
955 | } | |
956 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
957 | ||
1da177e4 | 958 | /** |
cb3bc9d0 | 959 | * eeh_add_device_late - Perform EEH initialization for the indicated pci device |
1da177e4 LT |
960 | * @dev: pci device for which to set up EEH |
961 | * | |
962 | * This routine must be used to complete EEH initialization for PCI | |
963 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
964 | */ | |
f2856491 | 965 | void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 966 | { |
56b0fca3 | 967 | struct device_node *dn; |
f631acd3 | 968 | struct eeh_dev *edev; |
56b0fca3 | 969 | |
2ec5a0ad | 970 | if (!dev || !eeh_enabled()) |
1da177e4 LT |
971 | return; |
972 | ||
57b066ff | 973 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 974 | |
56b0fca3 | 975 | dn = pci_device_to_OF_node(dev); |
2ef822c5 | 976 | edev = of_node_to_eeh_dev(dn); |
f631acd3 | 977 | if (edev->pdev == dev) { |
57b066ff BH |
978 | pr_debug("EEH: Already referenced !\n"); |
979 | return; | |
980 | } | |
f5c57710 GS |
981 | |
982 | /* | |
983 | * The EEH cache might not be removed correctly because of | |
984 | * unbalanced kref to the device during unplug time, which | |
985 | * relies on pcibios_release_device(). So we have to remove | |
986 | * that here explicitly. | |
987 | */ | |
988 | if (edev->pdev) { | |
989 | eeh_rmv_from_parent_pe(edev); | |
990 | eeh_addr_cache_rmv_dev(edev->pdev); | |
991 | eeh_sysfs_remove_device(edev->pdev); | |
ab55d218 | 992 | edev->mode &= ~EEH_DEV_SYSFS; |
f5c57710 | 993 | |
f26c7a03 GS |
994 | /* |
995 | * We definitely should have the PCI device removed | |
996 | * though it wasn't correctly. So we needn't call | |
997 | * into error handler afterwards. | |
998 | */ | |
999 | edev->mode |= EEH_DEV_NO_HANDLER; | |
1000 | ||
f5c57710 GS |
1001 | edev->pdev = NULL; |
1002 | dev->dev.archdata.edev = NULL; | |
1003 | } | |
57b066ff | 1004 | |
f631acd3 GS |
1005 | edev->pdev = dev; |
1006 | dev->dev.archdata.edev = edev; | |
56b0fca3 | 1007 | |
26a74850 GS |
1008 | /* |
1009 | * We have to do the EEH probe here because the PCI device | |
1010 | * hasn't been created yet in the early stage. | |
1011 | */ | |
05b1721d | 1012 | if (eeh_has_flag(EEH_PROBE_MODE_DEV)) |
26a74850 GS |
1013 | eeh_ops->dev_probe(dev, NULL); |
1014 | ||
3ab96a02 | 1015 | eeh_addr_cache_insert_dev(dev); |
1da177e4 | 1016 | } |
794e085e | 1017 | |
cb3bc9d0 GS |
1018 | /** |
1019 | * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus | |
1020 | * @bus: PCI bus | |
1021 | * | |
1022 | * This routine must be used to perform EEH initialization for PCI | |
1023 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1024 | * is added after system boot through hotplug or dlpar. | |
1025 | */ | |
794e085e NF |
1026 | void eeh_add_device_tree_late(struct pci_bus *bus) |
1027 | { | |
1028 | struct pci_dev *dev; | |
1029 | ||
1030 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
a84f273c GS |
1031 | eeh_add_device_late(dev); |
1032 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1033 | struct pci_bus *subbus = dev->subordinate; | |
1034 | if (subbus) | |
1035 | eeh_add_device_tree_late(subbus); | |
1036 | } | |
794e085e NF |
1037 | } |
1038 | } | |
1039 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 | 1040 | |
6a040ce7 TLSC |
1041 | /** |
1042 | * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus | |
1043 | * @bus: PCI bus | |
1044 | * | |
1045 | * This routine must be used to add EEH sysfs files for PCI | |
1046 | * devices which are attached to the indicated PCI bus. The PCI bus | |
1047 | * is added after system boot through hotplug or dlpar. | |
1048 | */ | |
1049 | void eeh_add_sysfs_files(struct pci_bus *bus) | |
1050 | { | |
1051 | struct pci_dev *dev; | |
1052 | ||
1053 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1054 | eeh_sysfs_add_device(dev); | |
1055 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1056 | struct pci_bus *subbus = dev->subordinate; | |
1057 | if (subbus) | |
1058 | eeh_add_sysfs_files(subbus); | |
1059 | } | |
1060 | } | |
1061 | } | |
1062 | EXPORT_SYMBOL_GPL(eeh_add_sysfs_files); | |
1063 | ||
1da177e4 | 1064 | /** |
cb3bc9d0 | 1065 | * eeh_remove_device - Undo EEH setup for the indicated pci device |
1da177e4 LT |
1066 | * @dev: pci device to be removed |
1067 | * | |
794e085e NF |
1068 | * This routine should be called when a device is removed from |
1069 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1070 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1071 | * this device will no longer be detected after this call; thus, | |
1072 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1073 | */ |
807a827d | 1074 | void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1075 | { |
f631acd3 GS |
1076 | struct eeh_dev *edev; |
1077 | ||
2ec5a0ad | 1078 | if (!dev || !eeh_enabled()) |
1da177e4 | 1079 | return; |
f631acd3 | 1080 | edev = pci_dev_to_eeh_dev(dev); |
1da177e4 LT |
1081 | |
1082 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1083 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 | 1084 | |
f5c57710 | 1085 | if (!edev || !edev->pdev || !edev->pe) { |
57b066ff BH |
1086 | pr_debug("EEH: Not referenced !\n"); |
1087 | return; | |
b055a9e1 | 1088 | } |
f5c57710 GS |
1089 | |
1090 | /* | |
1091 | * During the hotplug for EEH error recovery, we need the EEH | |
1092 | * device attached to the parent PE in order for BAR restore | |
1093 | * a bit later. So we keep it for BAR restore and remove it | |
1094 | * from the parent PE during the BAR resotre. | |
1095 | */ | |
f631acd3 GS |
1096 | edev->pdev = NULL; |
1097 | dev->dev.archdata.edev = NULL; | |
f5c57710 GS |
1098 | if (!(edev->pe->state & EEH_PE_KEEP)) |
1099 | eeh_rmv_from_parent_pe(edev); | |
1100 | else | |
1101 | edev->mode |= EEH_DEV_DISCONNECTED; | |
57b066ff | 1102 | |
f26c7a03 GS |
1103 | /* |
1104 | * We're removing from the PCI subsystem, that means | |
1105 | * the PCI device driver can't support EEH or not | |
1106 | * well. So we rely on hotplug completely to do recovery | |
1107 | * for the specific PCI device. | |
1108 | */ | |
1109 | edev->mode |= EEH_DEV_NO_HANDLER; | |
1110 | ||
3ab96a02 | 1111 | eeh_addr_cache_rmv_dev(dev); |
57b066ff | 1112 | eeh_sysfs_remove_device(dev); |
ab55d218 | 1113 | edev->mode &= ~EEH_DEV_SYSFS; |
1da177e4 | 1114 | } |
1da177e4 | 1115 | |
212d16cd GS |
1116 | /** |
1117 | * eeh_dev_open - Increase count of pass through devices for PE | |
1118 | * @pdev: PCI device | |
1119 | * | |
1120 | * Increase count of passed through devices for the indicated | |
1121 | * PE. In the result, the EEH errors detected on the PE won't be | |
1122 | * reported. The PE owner will be responsible for detection | |
1123 | * and recovery. | |
1124 | */ | |
1125 | int eeh_dev_open(struct pci_dev *pdev) | |
1126 | { | |
1127 | struct eeh_dev *edev; | |
1128 | ||
1129 | mutex_lock(&eeh_dev_mutex); | |
1130 | ||
1131 | /* No PCI device ? */ | |
1132 | if (!pdev) | |
1133 | goto out; | |
1134 | ||
1135 | /* No EEH device or PE ? */ | |
1136 | edev = pci_dev_to_eeh_dev(pdev); | |
1137 | if (!edev || !edev->pe) | |
1138 | goto out; | |
1139 | ||
1140 | /* Increase PE's pass through count */ | |
1141 | atomic_inc(&edev->pe->pass_dev_cnt); | |
1142 | mutex_unlock(&eeh_dev_mutex); | |
1143 | ||
1144 | return 0; | |
1145 | out: | |
1146 | mutex_unlock(&eeh_dev_mutex); | |
1147 | return -ENODEV; | |
1148 | } | |
1149 | EXPORT_SYMBOL_GPL(eeh_dev_open); | |
1150 | ||
1151 | /** | |
1152 | * eeh_dev_release - Decrease count of pass through devices for PE | |
1153 | * @pdev: PCI device | |
1154 | * | |
1155 | * Decrease count of pass through devices for the indicated PE. If | |
1156 | * there is no passed through device in PE, the EEH errors detected | |
1157 | * on the PE will be reported and handled as usual. | |
1158 | */ | |
1159 | void eeh_dev_release(struct pci_dev *pdev) | |
1160 | { | |
1161 | struct eeh_dev *edev; | |
1162 | ||
1163 | mutex_lock(&eeh_dev_mutex); | |
1164 | ||
1165 | /* No PCI device ? */ | |
1166 | if (!pdev) | |
1167 | goto out; | |
1168 | ||
1169 | /* No EEH device ? */ | |
1170 | edev = pci_dev_to_eeh_dev(pdev); | |
1171 | if (!edev || !edev->pe || !eeh_pe_passed(edev->pe)) | |
1172 | goto out; | |
1173 | ||
1174 | /* Decrease PE's pass through count */ | |
1175 | atomic_dec(&edev->pe->pass_dev_cnt); | |
1176 | WARN_ON(atomic_read(&edev->pe->pass_dev_cnt) < 0); | |
1177 | out: | |
1178 | mutex_unlock(&eeh_dev_mutex); | |
1179 | } | |
1180 | EXPORT_SYMBOL(eeh_dev_release); | |
1181 | ||
a3032ca9 GS |
1182 | static int dev_has_iommu_table(struct device *dev, void *data) |
1183 | { | |
1184 | struct pci_dev *pdev = to_pci_dev(dev); | |
1185 | struct pci_dev **ppdev = data; | |
1186 | struct iommu_table *tbl; | |
1187 | ||
1188 | if (!dev) | |
1189 | return 0; | |
1190 | ||
1191 | tbl = get_iommu_table_base(dev); | |
1192 | if (tbl && tbl->it_group) { | |
1193 | *ppdev = pdev; | |
1194 | return 1; | |
1195 | } | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
212d16cd GS |
1200 | /** |
1201 | * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE | |
1202 | * @group: IOMMU group | |
1203 | * | |
1204 | * The routine is called to convert IOMMU group to EEH PE. | |
1205 | */ | |
1206 | struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group) | |
1207 | { | |
212d16cd GS |
1208 | struct pci_dev *pdev = NULL; |
1209 | struct eeh_dev *edev; | |
a3032ca9 | 1210 | int ret; |
212d16cd GS |
1211 | |
1212 | /* No IOMMU group ? */ | |
1213 | if (!group) | |
1214 | return NULL; | |
1215 | ||
a3032ca9 GS |
1216 | ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table); |
1217 | if (!ret || !pdev) | |
212d16cd GS |
1218 | return NULL; |
1219 | ||
1220 | /* No EEH device or PE ? */ | |
1221 | edev = pci_dev_to_eeh_dev(pdev); | |
1222 | if (!edev || !edev->pe) | |
1223 | return NULL; | |
1224 | ||
1225 | return edev->pe; | |
1226 | } | |
1227 | ||
1228 | /** | |
1229 | * eeh_pe_set_option - Set options for the indicated PE | |
1230 | * @pe: EEH PE | |
1231 | * @option: requested option | |
1232 | * | |
1233 | * The routine is called to enable or disable EEH functionality | |
1234 | * on the indicated PE, to enable IO or DMA for the frozen PE. | |
1235 | */ | |
1236 | int eeh_pe_set_option(struct eeh_pe *pe, int option) | |
1237 | { | |
1238 | int ret = 0; | |
1239 | ||
1240 | /* Invalid PE ? */ | |
1241 | if (!pe) | |
1242 | return -ENODEV; | |
1243 | ||
1244 | /* | |
1245 | * EEH functionality could possibly be disabled, just | |
1246 | * return error for the case. And the EEH functinality | |
1247 | * isn't expected to be disabled on one specific PE. | |
1248 | */ | |
1249 | switch (option) { | |
1250 | case EEH_OPT_ENABLE: | |
1251 | if (eeh_enabled()) | |
1252 | break; | |
1253 | ret = -EIO; | |
1254 | break; | |
1255 | case EEH_OPT_DISABLE: | |
1256 | break; | |
1257 | case EEH_OPT_THAW_MMIO: | |
1258 | case EEH_OPT_THAW_DMA: | |
1259 | if (!eeh_ops || !eeh_ops->set_option) { | |
1260 | ret = -ENOENT; | |
1261 | break; | |
1262 | } | |
1263 | ||
1264 | ret = eeh_ops->set_option(pe, option); | |
1265 | break; | |
1266 | default: | |
1267 | pr_debug("%s: Option %d out of range (%d, %d)\n", | |
1268 | __func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA); | |
1269 | ret = -EINVAL; | |
1270 | } | |
1271 | ||
1272 | return ret; | |
1273 | } | |
1274 | EXPORT_SYMBOL_GPL(eeh_pe_set_option); | |
1275 | ||
1276 | /** | |
1277 | * eeh_pe_get_state - Retrieve PE's state | |
1278 | * @pe: EEH PE | |
1279 | * | |
1280 | * Retrieve the PE's state, which includes 3 aspects: enabled | |
1281 | * DMA, enabled IO and asserted reset. | |
1282 | */ | |
1283 | int eeh_pe_get_state(struct eeh_pe *pe) | |
1284 | { | |
1285 | int result, ret = 0; | |
1286 | bool rst_active, dma_en, mmio_en; | |
1287 | ||
1288 | /* Existing PE ? */ | |
1289 | if (!pe) | |
1290 | return -ENODEV; | |
1291 | ||
1292 | if (!eeh_ops || !eeh_ops->get_state) | |
1293 | return -ENOENT; | |
1294 | ||
1295 | result = eeh_ops->get_state(pe, NULL); | |
1296 | rst_active = !!(result & EEH_STATE_RESET_ACTIVE); | |
1297 | dma_en = !!(result & EEH_STATE_DMA_ENABLED); | |
1298 | mmio_en = !!(result & EEH_STATE_MMIO_ENABLED); | |
1299 | ||
1300 | if (rst_active) | |
1301 | ret = EEH_PE_STATE_RESET; | |
1302 | else if (dma_en && mmio_en) | |
1303 | ret = EEH_PE_STATE_NORMAL; | |
1304 | else if (!dma_en && !mmio_en) | |
1305 | ret = EEH_PE_STATE_STOPPED_IO_DMA; | |
1306 | else if (!dma_en && mmio_en) | |
1307 | ret = EEH_PE_STATE_STOPPED_DMA; | |
1308 | else | |
1309 | ret = EEH_PE_STATE_UNAVAIL; | |
1310 | ||
1311 | return ret; | |
1312 | } | |
1313 | EXPORT_SYMBOL_GPL(eeh_pe_get_state); | |
1314 | ||
1315 | /** | |
1316 | * eeh_pe_reset - Issue PE reset according to specified type | |
1317 | * @pe: EEH PE | |
1318 | * @option: reset type | |
1319 | * | |
1320 | * The routine is called to reset the specified PE with the | |
1321 | * indicated type, either fundamental reset or hot reset. | |
1322 | * PE reset is the most important part for error recovery. | |
1323 | */ | |
1324 | int eeh_pe_reset(struct eeh_pe *pe, int option) | |
1325 | { | |
1326 | int ret = 0; | |
1327 | ||
1328 | /* Invalid PE ? */ | |
1329 | if (!pe) | |
1330 | return -ENODEV; | |
1331 | ||
1332 | if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset) | |
1333 | return -ENOENT; | |
1334 | ||
1335 | switch (option) { | |
1336 | case EEH_RESET_DEACTIVATE: | |
1337 | ret = eeh_ops->reset(pe, option); | |
1338 | if (ret) | |
1339 | break; | |
1340 | ||
1341 | /* | |
1342 | * The PE is still in frozen state and we need to clear | |
1343 | * that. It's good to clear frozen state after deassert | |
1344 | * to avoid messy IO access during reset, which might | |
1345 | * cause recursive frozen PE. | |
1346 | */ | |
1347 | ret = eeh_ops->set_option(pe, EEH_OPT_THAW_MMIO); | |
1348 | if (!ret) | |
1349 | ret = eeh_ops->set_option(pe, EEH_OPT_THAW_DMA); | |
1350 | if (!ret) | |
1351 | eeh_pe_state_clear(pe, EEH_PE_ISOLATED); | |
1352 | break; | |
1353 | case EEH_RESET_HOT: | |
1354 | case EEH_RESET_FUNDAMENTAL: | |
1355 | ret = eeh_ops->reset(pe, option); | |
1356 | break; | |
1357 | default: | |
1358 | pr_debug("%s: Unsupported option %d\n", | |
1359 | __func__, option); | |
1360 | ret = -EINVAL; | |
1361 | } | |
1362 | ||
1363 | return ret; | |
1364 | } | |
1365 | EXPORT_SYMBOL_GPL(eeh_pe_reset); | |
1366 | ||
1367 | /** | |
1368 | * eeh_pe_configure - Configure PCI bridges after PE reset | |
1369 | * @pe: EEH PE | |
1370 | * | |
1371 | * The routine is called to restore the PCI config space for | |
1372 | * those PCI devices, especially PCI bridges affected by PE | |
1373 | * reset issued previously. | |
1374 | */ | |
1375 | int eeh_pe_configure(struct eeh_pe *pe) | |
1376 | { | |
1377 | int ret = 0; | |
1378 | ||
1379 | /* Invalid PE ? */ | |
1380 | if (!pe) | |
1381 | return -ENODEV; | |
1382 | ||
1383 | /* Restore config space for the affected devices */ | |
1384 | eeh_pe_restore_bars(pe); | |
1385 | ||
1386 | return ret; | |
1387 | } | |
1388 | EXPORT_SYMBOL_GPL(eeh_pe_configure); | |
1389 | ||
1da177e4 LT |
1390 | static int proc_eeh_show(struct seq_file *m, void *v) |
1391 | { | |
2ec5a0ad | 1392 | if (!eeh_enabled()) { |
1da177e4 | 1393 | seq_printf(m, "EEH Subsystem is globally disabled\n"); |
e575f8db | 1394 | seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs); |
1da177e4 LT |
1395 | } else { |
1396 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 | 1397 | seq_printf(m, |
e575f8db GS |
1398 | "no device=%llu\n" |
1399 | "no device node=%llu\n" | |
1400 | "no config address=%llu\n" | |
1401 | "check not wanted=%llu\n" | |
1402 | "eeh_total_mmio_ffs=%llu\n" | |
1403 | "eeh_false_positives=%llu\n" | |
1404 | "eeh_slot_resets=%llu\n", | |
1405 | eeh_stats.no_device, | |
1406 | eeh_stats.no_dn, | |
1407 | eeh_stats.no_cfg_addr, | |
1408 | eeh_stats.ignored_check, | |
1409 | eeh_stats.total_mmio_ffs, | |
1410 | eeh_stats.false_positives, | |
1411 | eeh_stats.slot_resets); | |
1da177e4 LT |
1412 | } |
1413 | ||
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1418 | { | |
1419 | return single_open(file, proc_eeh_show, NULL); | |
1420 | } | |
1421 | ||
5dfe4c96 | 1422 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1423 | .open = proc_eeh_open, |
1424 | .read = seq_read, | |
1425 | .llseek = seq_lseek, | |
1426 | .release = single_release, | |
1427 | }; | |
1428 | ||
7f52a526 GS |
1429 | #ifdef CONFIG_DEBUG_FS |
1430 | static int eeh_enable_dbgfs_set(void *data, u64 val) | |
1431 | { | |
1432 | if (val) | |
05b1721d | 1433 | eeh_clear_flag(EEH_FORCE_DISABLED); |
7f52a526 | 1434 | else |
05b1721d | 1435 | eeh_add_flag(EEH_FORCE_DISABLED); |
7f52a526 GS |
1436 | |
1437 | /* Notify the backend */ | |
1438 | if (eeh_ops->post_init) | |
1439 | eeh_ops->post_init(); | |
1440 | ||
1441 | return 0; | |
1442 | } | |
1443 | ||
1444 | static int eeh_enable_dbgfs_get(void *data, u64 *val) | |
1445 | { | |
1446 | if (eeh_enabled()) | |
1447 | *val = 0x1ul; | |
1448 | else | |
1449 | *val = 0x0ul; | |
1450 | return 0; | |
1451 | } | |
1452 | ||
1453 | DEFINE_SIMPLE_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get, | |
1454 | eeh_enable_dbgfs_set, "0x%llx\n"); | |
1455 | #endif | |
1456 | ||
1da177e4 LT |
1457 | static int __init eeh_init_proc(void) |
1458 | { | |
7f52a526 | 1459 | if (machine_is(pseries) || machine_is(powernv)) { |
8feaa434 | 1460 | proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations); |
7f52a526 GS |
1461 | #ifdef CONFIG_DEBUG_FS |
1462 | debugfs_create_file("eeh_enable", 0600, | |
1463 | powerpc_debugfs_root, NULL, | |
1464 | &eeh_enable_dbgfs_ops); | |
1465 | #endif | |
1466 | } | |
1467 | ||
1da177e4 LT |
1468 | return 0; |
1469 | } | |
1470 | __initcall(eeh_init_proc); |