[mirror_ubuntu-jammy-kernel.git] / arch / powerpc / kernel / eeh_cache.c

/*
 * PCI address cache; allows the lookup of PCI devices based on I/O address
 *
 * Copyright IBM Corporation 2004
 * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/list.h>
#include <linux/pci.h>
#include <linux/rbtree.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/atomic.h>
#include <asm/pci-bridge.h>
#include <asm/debugfs.h>
#include <asm/ppc-pci.h>


/**
 * The pci address cache subsystem.  This subsystem places
 * PCI device address resources into a red-black tree, sorted
 * according to the address range, so that given only an i/o
 * address, the corresponding PCI device can be **quickly**
 * found. It is safe to perform an address lookup in an interrupt
 * context; this ability is an important feature.
 *
 * Currently, the only customer of this code is the EEH subsystem;
 * thus, this code has been somewhat tailored to suit EEH better.
 * In particular, the cache does *not* hold the addresses of devices
 * for which EEH is not enabled.
 *
 * (Implementation Note: The RB tree seems to be better/faster
 * than any hash algo I could think of for this problem, even
 * with the penalty of slow pointer chases for d-cache misses).
 */
struct pci_io_addr_range {
	struct rb_node rb_node;
	resource_size_t addr_lo;
	resource_size_t addr_hi;
	struct eeh_dev *edev;
	struct pci_dev *pcidev;
	unsigned long flags;
};

static struct pci_io_addr_cache {
	struct rb_root rb_root;
	spinlock_t piar_lock;
} pci_io_addr_cache_root;

static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
{
	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;

	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);

		if (addr < piar->addr_lo)
			n = n->rb_left;
		else if (addr > piar->addr_hi)
			n = n->rb_right;
		else
			return piar->edev;
	}

	return NULL;
}

/**
 * eeh_addr_cache_get_dev - Get device, given only address
 * @addr: mmio (PIO) phys address or i/o port number
 *
 * Given an mmio phys address, or a port number, find a pci device
 * that implements this address.  I/O port numbers are assumed to be offset
 * from zero (that is, they do *not* have pci_io_addr added in).
 * It is safe to call this function within an interrupt.
 */
struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
{
	struct eeh_dev *edev;
	unsigned long flags;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	edev = __eeh_addr_cache_get_device(addr);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	return edev;
}

#ifdef DEBUG
/*
 * Handy-dandy debug print routine, does nothing more
 * than print out the contents of our addr cache.
 */
static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
{
	struct rb_node *n;
	int cnt = 0;

	n = rb_first(&cache->rb_root);
	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);
		pr_info("PCI: %s addr range %d [%pap-%pap]: %s\n",
		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
		       &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
		cnt++;
		n = rb_next(n);
	}
}
#endif

/* Insert address range into the rb tree. */
static struct pci_io_addr_range *
eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
		      resource_size_t ahi, unsigned long flags)
{
	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
	struct rb_node *parent = NULL;
	struct pci_io_addr_range *piar;

	/* Walk tree, find a place to insert into tree */
	while (*p) {
		parent = *p;
		piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
		if (ahi < piar->addr_lo) {
			p = &parent->rb_left;
		} else if (alo > piar->addr_hi) {
			p = &parent->rb_right;
		} else {
			if (dev != piar->pcidev ||
			    alo != piar->addr_lo || ahi != piar->addr_hi) {
				pr_warn("PIAR: overlapping address range\n");
			}
			return piar;
		}
	}
	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
	if (!piar)
		return NULL;

	piar->addr_lo = alo;
	piar->addr_hi = ahi;
	piar->edev = pci_dev_to_eeh_dev(dev);
	piar->pcidev = dev;
	piar->flags = flags;

	pr_debug("PIAR: insert range=[%pap:%pap] dev=%s\n",
		 &alo, &ahi, pci_name(dev));

	rb_link_node(&piar->rb_node, parent, p);
	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);

	return piar;
}

static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
{
	struct pci_dn *pdn;
	struct eeh_dev *edev;
	int i;

	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
	if (!pdn) {
		pr_warn("PCI: no pci dn found for dev=%s\n",
			pci_name(dev));
		return;
	}

	edev = pdn_to_eeh_dev(pdn);
	if (!edev) {
		pr_warn("PCI: no EEH dev found for %s\n",
			pci_name(dev));
		return;
	}

	/* Skip any devices for which EEH is not enabled. */
	if (!edev->pe) {
		dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
		return;
	}

	/*
	 * Walk resources on this device, poke the first 7 (6 normal BAR and 1
	 * ROM BAR) into the tree.
	 */
	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
		resource_size_t start = pci_resource_start(dev,i);
		resource_size_t end = pci_resource_end(dev,i);
		unsigned long flags = pci_resource_flags(dev,i);

		/* We are interested only bus addresses, not dma or other stuff */
		if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
			continue;
		if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
			 continue;
		eeh_addr_cache_insert(dev, start, end, flags);
	}
}

/**
 * eeh_addr_cache_insert_dev - Add a device to the address cache
 * @dev: PCI device whose I/O addresses we are interested in.
 *
 * In order to support the fast lookup of devices based on addresses,
 * we maintain a cache of devices that can be quickly searched.
 * This routine adds a device to that cache.
 */
void eeh_addr_cache_insert_dev(struct pci_dev *dev)
{
	unsigned long flags;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	__eeh_addr_cache_insert_dev(dev);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
}

static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
{
	struct rb_node *n;

restart:
	n = rb_first(&pci_io_addr_cache_root.rb_root);
	while (n) {
		struct pci_io_addr_range *piar;
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);

		if (piar->pcidev == dev) {
			pr_debug("PIAR: remove range=[%pap:%pap] dev=%s\n",
				 &piar->addr_lo, &piar->addr_hi, pci_name(dev));
			rb_erase(n, &pci_io_addr_cache_root.rb_root);
			kfree(piar);
			goto restart;
		}
		n = rb_next(n);
	}
}

/**
 * eeh_addr_cache_rmv_dev - remove pci device from addr cache
 * @dev: device to remove
 *
 * Remove a device from the addr-cache tree.
 * This is potentially expensive, since it will walk
 * the tree multiple times (once per resource).
 * But so what; device removal doesn't need to be that fast.
 */
void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
{
	unsigned long flags;

	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
	__eeh_addr_cache_rmv_dev(dev);
	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
}

/**
 * eeh_addr_cache_build - Build a cache of I/O addresses
 *
 * Build a cache of pci i/o addresses.  This cache will be used to
 * find the pci device that corresponds to a given address.
 * This routine scans all pci busses to build the cache.
 * Must be run late in boot process, after the pci controllers
 * have been scanned for devices (after all device resources are known).
 */
void eeh_addr_cache_build(void)
{
	struct pci_dn *pdn;
	struct eeh_dev *edev;
	struct pci_dev *dev = NULL;

	spin_lock_init(&pci_io_addr_cache_root.piar_lock);

	for_each_pci_dev(dev) {
		pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
		if (!pdn)
			continue;

		edev = pdn_to_eeh_dev(pdn);
		if (!edev)
			continue;

		dev->dev.archdata.edev = edev;
		edev->pdev = dev;

		eeh_addr_cache_insert_dev(dev);
		eeh_sysfs_add_device(dev);
	}
}

static int eeh_addr_cache_show(struct seq_file *s, void *v)
{
	struct pci_io_addr_range *piar;
	struct rb_node *n;

	spin_lock(&pci_io_addr_cache_root.piar_lock);
	for (n = rb_first(&pci_io_addr_cache_root.rb_root); n; n = rb_next(n)) {
		piar = rb_entry(n, struct pci_io_addr_range, rb_node);

		seq_printf(s, "%s addr range [%pap-%pap]: %s\n",
		       (piar->flags & IORESOURCE_IO) ? "i/o" : "mem",
		       &piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
	}
	spin_unlock(&pci_io_addr_cache_root.piar_lock);

	return 0;
}
DEFINE_SHOW_ATTRIBUTE(eeh_addr_cache);

void eeh_cache_debugfs_init(void)
{
	debugfs_create_file_unsafe("eeh_address_cache", 0400,
			powerpc_debugfs_root, NULL,
			&eeh_addr_cache_fops);
}
Commit	Line	Data
5d5a0936	1	/*
5d5a0936 LV	2	* PCI address cache; allows the lookup of PCI devices based on I/O address
5d5a0936 LV	3	*
3c8c90ab LV	4	* Copyright IBM Corporation 2004
3c8c90ab LV	5	* Copyright Linas Vepstas <linas@austin.ibm.com> 2004
5d5a0936 LV	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/list.h>
	23	#include <linux/pci.h>
	24	#include <linux/rbtree.h>
5a0e3ad6	25	#include <linux/slab.h>
5d5a0936	26	#include <linux/spinlock.h>
60063497	27	#include <linux/atomic.h>
5d5a0936	28	#include <asm/pci-bridge.h>
5ca85ae6	29	#include <asm/debugfs.h>
5d5a0936	30	#include <asm/ppc-pci.h>
5d5a0936	31
5d5a0936 LV	32
	33	/**
	34	* The pci address cache subsystem. This subsystem places
	35	* PCI device address resources into a red-black tree, sorted
	36	* according to the address range, so that given only an i/o
	37	* address, the corresponding PCI device can be quickly
	38	* found. It is safe to perform an address lookup in an interrupt
	39	* context; this ability is an important feature.
	40	*
	41	* Currently, the only customer of this code is the EEH subsystem;
	42	* thus, this code has been somewhat tailored to suit EEH better.
	43	* In particular, the cache does not hold the addresses of devices
	44	* for which EEH is not enabled.
	45	*
	46	* (Implementation Note: The RB tree seems to be better/faster
	47	* than any hash algo I could think of for this problem, even
	48	* with the penalty of slow pointer chases for d-cache misses).
	49	*/
29f8bf1b	50	struct pci_io_addr_range {
5d5a0936	51	struct rb_node rb_node;
37213529 WY	52	resource_size_t addr_lo;
37213529 WY	53	resource_size_t addr_hi;
f8f7d63f	54	struct eeh_dev *edev;
5d5a0936	55	struct pci_dev *pcidev;
37213529	56	unsigned long flags;
5d5a0936 LV	57	};
5d5a0936 LV	58
29f8bf1b	59	static struct pci_io_addr_cache {
5d5a0936 LV	60	struct rb_root rb_root;
	61	spinlock_t piar_lock;
	62	} pci_io_addr_cache_root;
	63
3ab96a02	64	static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
5d5a0936 LV	65	{
	66	struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
	67
	68	while (n) {
	69	struct pci_io_addr_range *piar;
	70	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	71
0ba17888	72	if (addr < piar->addr_lo)
5d5a0936	73	n = n->rb_left;
0ba17888 GS	74	else if (addr > piar->addr_hi)
	75	n = n->rb_right;
	76	else
	77	return piar->edev;
5d5a0936 LV	78	}
	79
	80	return NULL;
	81	}
	82
	83	/**
3ab96a02	84	* eeh_addr_cache_get_dev - Get device, given only address
5d5a0936 LV	85	* @addr: mmio (PIO) phys address or i/o port number
	86	*
	87	* Given an mmio phys address, or a port number, find a pci device
63457b14	88	* that implements this address. I/O port numbers are assumed to be offset
5d5a0936 LV	89	* from zero (that is, they do not have pci_io_addr added in).
	90	* It is safe to call this function within an interrupt.
	91	*/
3ab96a02	92	struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
5d5a0936	93	{
f8f7d63f	94	struct eeh_dev *edev;
5d5a0936 LV	95	unsigned long flags;
	96
	97	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
3ab96a02	98	edev = __eeh_addr_cache_get_device(addr);
5d5a0936	99	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
f8f7d63f	100	return edev;
5d5a0936 LV	101	}
	102
	103	#ifdef DEBUG
	104	/*
	105	* Handy-dandy debug print routine, does nothing more
	106	* than print out the contents of our addr cache.
	107	*/
3ab96a02	108	static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
5d5a0936 LV	109	{
	110	struct rb_node *n;
	111	int cnt = 0;
	112
	113	n = rb_first(&cache->rb_root);
	114	while (n) {
	115	struct pci_io_addr_range *piar;
	116	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
c8f02f21	117	pr_info("PCI: %s addr range %d [%pap-%pap]: %s\n",
5d5a0936	118	(piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
91dc0682	119	&piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
5d5a0936 LV	120	cnt++;
	121	n = rb_next(n);
	122	}
	123	}
	124	#endif
	125
	126	/* Insert address range into the rb tree. */
	127	static struct pci_io_addr_range *
37213529 WY	128	eeh_addr_cache_insert(struct pci_dev *dev, resource_size_t alo,
37213529 WY	129	resource_size_t ahi, unsigned long flags)
5d5a0936 LV	130	{
	131	struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
	132	struct rb_node *parent = NULL;
	133	struct pci_io_addr_range *piar;
	134
	135	/* Walk tree, find a place to insert into tree */
	136	while (*p) {
	137	parent = *p;
	138	piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
	139	if (ahi < piar->addr_lo) {
	140	p = &parent->rb_left;
	141	} else if (alo > piar->addr_hi) {
	142	p = &parent->rb_right;
	143	} else {
	144	if (dev != piar->pcidev \|\|
	145	alo != piar->addr_lo \|\| ahi != piar->addr_hi) {
0dae2743	146	pr_warn("PIAR: overlapping address range\n");
5d5a0936 LV	147	}
	148	return piar;
	149	}
	150	}
7e4bbaf0	151	piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
5d5a0936 LV	152	if (!piar)
	153	return NULL;
	154
	155	piar->addr_lo = alo;
	156	piar->addr_hi = ahi;
f8f7d63f	157	piar->edev = pci_dev_to_eeh_dev(dev);
5d5a0936 LV	158	piar->pcidev = dev;
	159	piar->flags = flags;
	160
91dc0682 AD	161	pr_debug("PIAR: insert range=[%pap:%pap] dev=%s\n",
91dc0682 AD	162	&alo, &ahi, pci_name(dev));
5d5a0936 LV	163
	164	rb_link_node(&piar->rb_node, parent, p);
	165	rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
	166
	167	return piar;
	168	}
	169
3ab96a02	170	static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
5d5a0936	171	{
c6406d8f	172	struct pci_dn *pdn;
d50a7d4c	173	struct eeh_dev *edev;
5d5a0936	174	int i;
5d5a0936	175
c6406d8f GS	176	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
c6406d8f GS	177	if (!pdn) {
0dae2743 GS	178	pr_warn("PCI: no pci dn found for dev=%s\n",
0dae2743 GS	179	pci_name(dev));
5d5a0936 LV	180	return;
	181	}
	182
c6406d8f	183	edev = pdn_to_eeh_dev(pdn);
d50a7d4c	184	if (!edev) {
c6406d8f GS	185	pr_warn("PCI: no EEH dev found for %s\n",
c6406d8f GS	186	pci_name(dev));
d50a7d4c GS	187	return;
	188	}
	189
5d5a0936	190	/* Skip any devices for which EEH is not enabled. */
05b1721d	191	if (!edev->pe) {
c6406d8f	192	dev_dbg(&dev->dev, "EEH: Skip building address cache\n");
5d5a0936 LV	193	return;
	194	}
	195
51c0e87e WY	196	/*
	197	* Walk resources on this device, poke the first 7 (6 normal BAR and 1
	198	* ROM BAR) into the tree.
	199	*/
	200	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
37213529 WY	201	resource_size_t start = pci_resource_start(dev,i);
	202	resource_size_t end = pci_resource_end(dev,i);
	203	unsigned long flags = pci_resource_flags(dev,i);
5d5a0936 LV	204
	205	/* We are interested only bus addresses, not dma or other stuff */
	206	if (0 == (flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
	207	continue;
	208	if (start == 0 \|\| ~start == 0 \|\| end == 0 \|\| ~end == 0)
	209	continue;
3ab96a02	210	eeh_addr_cache_insert(dev, start, end, flags);
5d5a0936	211	}
5d5a0936 LV	212	}
	213
	214	/**
3ab96a02	215	* eeh_addr_cache_insert_dev - Add a device to the address cache
5d5a0936 LV	216	* @dev: PCI device whose I/O addresses we are interested in.
	217	*
	218	* In order to support the fast lookup of devices based on addresses,
	219	* we maintain a cache of devices that can be quickly searched.
	220	* This routine adds a device to that cache.
	221	*/
3ab96a02	222	void eeh_addr_cache_insert_dev(struct pci_dev *dev)
5d5a0936 LV	223	{
	224	unsigned long flags;
	225
	226	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
3ab96a02	227	__eeh_addr_cache_insert_dev(dev);
5d5a0936 LV	228	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	229	}
	230
3ab96a02	231	static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
5d5a0936 LV	232	{
5d5a0936 LV	233	struct rb_node *n;
5d5a0936 LV	234
	235	restart:
	236	n = rb_first(&pci_io_addr_cache_root.rb_root);
	237	while (n) {
	238	struct pci_io_addr_range *piar;
	239	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	240
	241	if (piar->pcidev == dev) {
e67fbbec OH	242	pr_debug("PIAR: remove range=[%pap:%pap] dev=%s\n",
e67fbbec OH	243	&piar->addr_lo, &piar->addr_hi, pci_name(dev));
5d5a0936	244	rb_erase(n, &pci_io_addr_cache_root.rb_root);
5d5a0936 LV	245	kfree(piar);
	246	goto restart;
	247	}
	248	n = rb_next(n);
	249	}
5d5a0936 LV	250	}
	251
	252	/**
3ab96a02	253	* eeh_addr_cache_rmv_dev - remove pci device from addr cache
5d5a0936 LV	254	* @dev: device to remove
	255	*
	256	* Remove a device from the addr-cache tree.
	257	* This is potentially expensive, since it will walk
	258	* the tree multiple times (once per resource).
	259	* But so what; device removal doesn't need to be that fast.
	260	*/
3ab96a02	261	void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
5d5a0936 LV	262	{
	263	unsigned long flags;
	264
	265	spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
3ab96a02	266	__eeh_addr_cache_rmv_dev(dev);
5d5a0936 LV	267	spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
	268	}
	269
	270	/**
3ab96a02	271	* eeh_addr_cache_build - Build a cache of I/O addresses
5d5a0936 LV	272	*
	273	* Build a cache of pci i/o addresses. This cache will be used to
	274	* find the pci device that corresponds to a given address.
	275	* This routine scans all pci busses to build the cache.
	276	* Must be run late in boot process, after the pci controllers
d6e05edc	277	* have been scanned for devices (after all device resources are known).
5d5a0936	278	*/
eeb6361f	279	void eeh_addr_cache_build(void)
5d5a0936	280	{
c6406d8f	281	struct pci_dn *pdn;
d50a7d4c	282	struct eeh_dev *edev;
5d5a0936 LV	283	struct pci_dev *dev = NULL;
	284
	285	spin_lock_init(&pci_io_addr_cache_root.piar_lock);
	286
6901c6cc	287	for_each_pci_dev(dev) {
c6406d8f GS	288	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
c6406d8f GS	289	if (!pdn)
ccba051c	290	continue;
d50a7d4c	291
c6406d8f	292	edev = pdn_to_eeh_dev(pdn);
d50a7d4c GS	293	if (!edev)
	294	continue;
	295
d50a7d4c GS	296	dev->dev.archdata.edev = edev;
d50a7d4c GS	297	edev->pdev = dev;
e1d04c97	298
1abd6018	299	eeh_addr_cache_insert_dev(dev);
e1d04c97	300	eeh_sysfs_add_device(dev);
5d5a0936	301	}
5ca85ae6	302	}
5d5a0936	303
5ca85ae6 OH	304	static int eeh_addr_cache_show(struct seq_file s, void v)
	305	{
	306	struct pci_io_addr_range *piar;
	307	struct rb_node *n;
	308
	309	spin_lock(&pci_io_addr_cache_root.piar_lock);
	310	for (n = rb_first(&pci_io_addr_cache_root.rb_root); n; n = rb_next(n)) {
	311	piar = rb_entry(n, struct pci_io_addr_range, rb_node);
	312
	313	seq_printf(s, "%s addr range [%pap-%pap]: %s\n",
	314	(piar->flags & IORESOURCE_IO) ? "i/o" : "mem",
	315	&piar->addr_lo, &piar->addr_hi, pci_name(piar->pcidev));
	316	}
	317	spin_unlock(&pci_io_addr_cache_root.piar_lock);
	318
	319	return 0;
	320	}
	321	DEFINE_SHOW_ATTRIBUTE(eeh_addr_cache);
	322
	323	void eeh_cache_debugfs_init(void)
	324	{
	325	debugfs_create_file_unsafe("eeh_address_cache", 0400,
	326	powerpc_debugfs_root, NULL,
	327	&eeh_addr_cache_fops);
5d5a0936	328	}