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Commit | Line | Data |
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5d5a0936 | 1 | /* |
5d5a0936 LV |
2 | * PCI address cache; allows the lookup of PCI devices based on I/O address |
3 | * | |
3c8c90ab LV |
4 | * Copyright IBM Corporation 2004 |
5 | * Copyright Linas Vepstas <linas@austin.ibm.com> 2004 | |
5d5a0936 LV |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <linux/list.h> | |
23 | #include <linux/pci.h> | |
24 | #include <linux/rbtree.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
5d5a0936 | 26 | #include <linux/spinlock.h> |
60063497 | 27 | #include <linux/atomic.h> |
5d5a0936 LV |
28 | #include <asm/pci-bridge.h> |
29 | #include <asm/ppc-pci.h> | |
5d5a0936 | 30 | |
5d5a0936 LV |
31 | |
32 | /** | |
33 | * The pci address cache subsystem. This subsystem places | |
34 | * PCI device address resources into a red-black tree, sorted | |
35 | * according to the address range, so that given only an i/o | |
36 | * address, the corresponding PCI device can be **quickly** | |
37 | * found. It is safe to perform an address lookup in an interrupt | |
38 | * context; this ability is an important feature. | |
39 | * | |
40 | * Currently, the only customer of this code is the EEH subsystem; | |
41 | * thus, this code has been somewhat tailored to suit EEH better. | |
42 | * In particular, the cache does *not* hold the addresses of devices | |
43 | * for which EEH is not enabled. | |
44 | * | |
45 | * (Implementation Note: The RB tree seems to be better/faster | |
46 | * than any hash algo I could think of for this problem, even | |
47 | * with the penalty of slow pointer chases for d-cache misses). | |
48 | */ | |
29f8bf1b | 49 | struct pci_io_addr_range { |
5d5a0936 LV |
50 | struct rb_node rb_node; |
51 | unsigned long addr_lo; | |
52 | unsigned long addr_hi; | |
f8f7d63f | 53 | struct eeh_dev *edev; |
5d5a0936 LV |
54 | struct pci_dev *pcidev; |
55 | unsigned int flags; | |
56 | }; | |
57 | ||
29f8bf1b | 58 | static struct pci_io_addr_cache { |
5d5a0936 LV |
59 | struct rb_root rb_root; |
60 | spinlock_t piar_lock; | |
61 | } pci_io_addr_cache_root; | |
62 | ||
3ab96a02 | 63 | static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr) |
5d5a0936 LV |
64 | { |
65 | struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node; | |
66 | ||
67 | while (n) { | |
68 | struct pci_io_addr_range *piar; | |
69 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
70 | ||
71 | if (addr < piar->addr_lo) { | |
72 | n = n->rb_left; | |
73 | } else { | |
74 | if (addr > piar->addr_hi) { | |
75 | n = n->rb_right; | |
76 | } else { | |
77 | pci_dev_get(piar->pcidev); | |
f8f7d63f | 78 | return piar->edev; |
5d5a0936 LV |
79 | } |
80 | } | |
81 | } | |
82 | ||
83 | return NULL; | |
84 | } | |
85 | ||
86 | /** | |
3ab96a02 | 87 | * eeh_addr_cache_get_dev - Get device, given only address |
5d5a0936 LV |
88 | * @addr: mmio (PIO) phys address or i/o port number |
89 | * | |
90 | * Given an mmio phys address, or a port number, find a pci device | |
91 | * that implements this address. Be sure to pci_dev_put the device | |
92 | * when finished. I/O port numbers are assumed to be offset | |
93 | * from zero (that is, they do *not* have pci_io_addr added in). | |
94 | * It is safe to call this function within an interrupt. | |
95 | */ | |
3ab96a02 | 96 | struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr) |
5d5a0936 | 97 | { |
f8f7d63f | 98 | struct eeh_dev *edev; |
5d5a0936 LV |
99 | unsigned long flags; |
100 | ||
101 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
3ab96a02 | 102 | edev = __eeh_addr_cache_get_device(addr); |
5d5a0936 | 103 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
f8f7d63f | 104 | return edev; |
5d5a0936 LV |
105 | } |
106 | ||
107 | #ifdef DEBUG | |
108 | /* | |
109 | * Handy-dandy debug print routine, does nothing more | |
110 | * than print out the contents of our addr cache. | |
111 | */ | |
3ab96a02 | 112 | static void eeh_addr_cache_print(struct pci_io_addr_cache *cache) |
5d5a0936 LV |
113 | { |
114 | struct rb_node *n; | |
115 | int cnt = 0; | |
116 | ||
117 | n = rb_first(&cache->rb_root); | |
118 | while (n) { | |
119 | struct pci_io_addr_range *piar; | |
120 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
3ab96a02 | 121 | pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n", |
5d5a0936 LV |
122 | (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt, |
123 | piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev)); | |
124 | cnt++; | |
125 | n = rb_next(n); | |
126 | } | |
127 | } | |
128 | #endif | |
129 | ||
130 | /* Insert address range into the rb tree. */ | |
131 | static struct pci_io_addr_range * | |
3ab96a02 | 132 | eeh_addr_cache_insert(struct pci_dev *dev, unsigned long alo, |
5d5a0936 LV |
133 | unsigned long ahi, unsigned int flags) |
134 | { | |
135 | struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node; | |
136 | struct rb_node *parent = NULL; | |
137 | struct pci_io_addr_range *piar; | |
138 | ||
139 | /* Walk tree, find a place to insert into tree */ | |
140 | while (*p) { | |
141 | parent = *p; | |
142 | piar = rb_entry(parent, struct pci_io_addr_range, rb_node); | |
143 | if (ahi < piar->addr_lo) { | |
144 | p = &parent->rb_left; | |
145 | } else if (alo > piar->addr_hi) { | |
146 | p = &parent->rb_right; | |
147 | } else { | |
148 | if (dev != piar->pcidev || | |
149 | alo != piar->addr_lo || ahi != piar->addr_hi) { | |
3ab96a02 | 150 | pr_warning("PIAR: overlapping address range\n"); |
5d5a0936 LV |
151 | } |
152 | return piar; | |
153 | } | |
154 | } | |
7e4bbaf0 | 155 | piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC); |
5d5a0936 LV |
156 | if (!piar) |
157 | return NULL; | |
158 | ||
af525592 | 159 | pci_dev_get(dev); |
5d5a0936 LV |
160 | piar->addr_lo = alo; |
161 | piar->addr_hi = ahi; | |
f8f7d63f | 162 | piar->edev = pci_dev_to_eeh_dev(dev); |
5d5a0936 LV |
163 | piar->pcidev = dev; |
164 | piar->flags = flags; | |
165 | ||
166 | #ifdef DEBUG | |
3ab96a02 | 167 | pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n", |
29f8bf1b | 168 | alo, ahi, pci_name(dev)); |
5d5a0936 LV |
169 | #endif |
170 | ||
171 | rb_link_node(&piar->rb_node, parent, p); | |
172 | rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root); | |
173 | ||
174 | return piar; | |
175 | } | |
176 | ||
3ab96a02 | 177 | static void __eeh_addr_cache_insert_dev(struct pci_dev *dev) |
5d5a0936 LV |
178 | { |
179 | struct device_node *dn; | |
d50a7d4c | 180 | struct eeh_dev *edev; |
5d5a0936 | 181 | int i; |
5d5a0936 LV |
182 | |
183 | dn = pci_device_to_OF_node(dev); | |
184 | if (!dn) { | |
3ab96a02 | 185 | pr_warning("PCI: no pci dn found for dev=%s\n", pci_name(dev)); |
5d5a0936 LV |
186 | return; |
187 | } | |
188 | ||
d50a7d4c GS |
189 | edev = of_node_to_eeh_dev(dn); |
190 | if (!edev) { | |
191 | pr_warning("PCI: no EEH dev found for dn=%s\n", | |
192 | dn->full_name); | |
193 | return; | |
194 | } | |
195 | ||
5d5a0936 | 196 | /* Skip any devices for which EEH is not enabled. */ |
88b6d14b | 197 | if (!eeh_probe_mode_dev() && !edev->pe) { |
5d5a0936 | 198 | #ifdef DEBUG |
d50a7d4c GS |
199 | pr_info("PCI: skip building address cache for=%s - %s\n", |
200 | pci_name(dev), dn->full_name); | |
5d5a0936 LV |
201 | #endif |
202 | return; | |
203 | } | |
204 | ||
5d5a0936 LV |
205 | /* Walk resources on this device, poke them into the tree */ |
206 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
207 | unsigned long start = pci_resource_start(dev,i); | |
208 | unsigned long end = pci_resource_end(dev,i); | |
209 | unsigned int flags = pci_resource_flags(dev,i); | |
210 | ||
211 | /* We are interested only bus addresses, not dma or other stuff */ | |
212 | if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM))) | |
213 | continue; | |
214 | if (start == 0 || ~start == 0 || end == 0 || ~end == 0) | |
215 | continue; | |
3ab96a02 | 216 | eeh_addr_cache_insert(dev, start, end, flags); |
5d5a0936 | 217 | } |
5d5a0936 LV |
218 | } |
219 | ||
220 | /** | |
3ab96a02 | 221 | * eeh_addr_cache_insert_dev - Add a device to the address cache |
5d5a0936 LV |
222 | * @dev: PCI device whose I/O addresses we are interested in. |
223 | * | |
224 | * In order to support the fast lookup of devices based on addresses, | |
225 | * we maintain a cache of devices that can be quickly searched. | |
226 | * This routine adds a device to that cache. | |
227 | */ | |
3ab96a02 | 228 | void eeh_addr_cache_insert_dev(struct pci_dev *dev) |
5d5a0936 LV |
229 | { |
230 | unsigned long flags; | |
231 | ||
093eda3c LV |
232 | /* Ignore PCI bridges */ |
233 | if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) | |
234 | return; | |
235 | ||
5d5a0936 | 236 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); |
3ab96a02 | 237 | __eeh_addr_cache_insert_dev(dev); |
5d5a0936 LV |
238 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
239 | } | |
240 | ||
3ab96a02 | 241 | static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev) |
5d5a0936 LV |
242 | { |
243 | struct rb_node *n; | |
5d5a0936 LV |
244 | |
245 | restart: | |
246 | n = rb_first(&pci_io_addr_cache_root.rb_root); | |
247 | while (n) { | |
248 | struct pci_io_addr_range *piar; | |
249 | piar = rb_entry(n, struct pci_io_addr_range, rb_node); | |
250 | ||
251 | if (piar->pcidev == dev) { | |
252 | rb_erase(n, &pci_io_addr_cache_root.rb_root); | |
af525592 | 253 | pci_dev_put(piar->pcidev); |
5d5a0936 LV |
254 | kfree(piar); |
255 | goto restart; | |
256 | } | |
257 | n = rb_next(n); | |
258 | } | |
5d5a0936 LV |
259 | } |
260 | ||
261 | /** | |
3ab96a02 | 262 | * eeh_addr_cache_rmv_dev - remove pci device from addr cache |
5d5a0936 LV |
263 | * @dev: device to remove |
264 | * | |
265 | * Remove a device from the addr-cache tree. | |
266 | * This is potentially expensive, since it will walk | |
267 | * the tree multiple times (once per resource). | |
268 | * But so what; device removal doesn't need to be that fast. | |
269 | */ | |
3ab96a02 | 270 | void eeh_addr_cache_rmv_dev(struct pci_dev *dev) |
5d5a0936 LV |
271 | { |
272 | unsigned long flags; | |
273 | ||
274 | spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags); | |
3ab96a02 | 275 | __eeh_addr_cache_rmv_dev(dev); |
5d5a0936 LV |
276 | spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags); |
277 | } | |
278 | ||
279 | /** | |
3ab96a02 | 280 | * eeh_addr_cache_build - Build a cache of I/O addresses |
5d5a0936 LV |
281 | * |
282 | * Build a cache of pci i/o addresses. This cache will be used to | |
283 | * find the pci device that corresponds to a given address. | |
284 | * This routine scans all pci busses to build the cache. | |
285 | * Must be run late in boot process, after the pci controllers | |
d6e05edc | 286 | * have been scanned for devices (after all device resources are known). |
5d5a0936 | 287 | */ |
eeb6361f | 288 | void eeh_addr_cache_build(void) |
5d5a0936 LV |
289 | { |
290 | struct device_node *dn; | |
d50a7d4c | 291 | struct eeh_dev *edev; |
5d5a0936 LV |
292 | struct pci_dev *dev = NULL; |
293 | ||
294 | spin_lock_init(&pci_io_addr_cache_root.piar_lock); | |
295 | ||
6901c6cc | 296 | for_each_pci_dev(dev) { |
5d5a0936 | 297 | dn = pci_device_to_OF_node(dev); |
ccba051c NL |
298 | if (!dn) |
299 | continue; | |
d50a7d4c GS |
300 | |
301 | edev = of_node_to_eeh_dev(dn); | |
302 | if (!edev) | |
303 | continue; | |
304 | ||
093eda3c | 305 | pci_dev_get(dev); /* matching put is in eeh_remove_device() */ |
d50a7d4c GS |
306 | dev->dev.archdata.edev = edev; |
307 | edev->pdev = dev; | |
e1d04c97 | 308 | |
1abd6018 TLSC |
309 | eeh_addr_cache_insert_dev(dev); |
310 | ||
e1d04c97 | 311 | eeh_sysfs_add_device(dev); |
5d5a0936 LV |
312 | } |
313 | ||
314 | #ifdef DEBUG | |
315 | /* Verify tree built up above, echo back the list of addrs. */ | |
3ab96a02 | 316 | eeh_addr_cache_print(&pci_io_addr_cache_root); |
5d5a0936 LV |
317 | #endif |
318 | } |