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Commit | Line | Data |
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9994a338 | 1 | /* |
9994a338 PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
6 | * Adapted for Power Macintosh by Paul Mackerras. | |
7 | * Low-level exception handlers and MMU support | |
8 | * rewritten by Paul Mackerras. | |
9 | * Copyright (C) 1996 Paul Mackerras. | |
10 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
11 | * | |
12 | * This file contains the system call entry code, context switch | |
13 | * code, and exception/interrupt return code for PowerPC. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
9994a338 | 21 | #include <linux/errno.h> |
c3525940 | 22 | #include <linux/err.h> |
9994a338 PM |
23 | #include <asm/unistd.h> |
24 | #include <asm/processor.h> | |
25 | #include <asm/page.h> | |
26 | #include <asm/mmu.h> | |
27 | #include <asm/thread_info.h> | |
28 | #include <asm/ppc_asm.h> | |
29 | #include <asm/asm-offsets.h> | |
30 | #include <asm/cputable.h> | |
3f639ee8 | 31 | #include <asm/firmware.h> |
007d88d0 | 32 | #include <asm/bug.h> |
ec2b36b9 | 33 | #include <asm/ptrace.h> |
945feb17 | 34 | #include <asm/irqflags.h> |
395a59d0 | 35 | #include <asm/ftrace.h> |
7230c564 | 36 | #include <asm/hw_irq.h> |
5d1c5745 | 37 | #include <asm/context_tracking.h> |
b4b56f9e | 38 | #include <asm/tm.h> |
9994a338 PM |
39 | |
40 | /* | |
41 | * System calls. | |
42 | */ | |
43 | .section ".toc","aw" | |
c857c43b AB |
44 | SYS_CALL_TABLE: |
45 | .tc sys_call_table[TC],sys_call_table | |
9994a338 PM |
46 | |
47 | /* This value is used to mark exception frames on the stack. */ | |
48 | exception_marker: | |
ec2b36b9 | 49 | .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER |
9994a338 PM |
50 | |
51 | .section ".text" | |
52 | .align 7 | |
53 | ||
9994a338 PM |
54 | .globl system_call_common |
55 | system_call_common: | |
b4b56f9e S |
56 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
57 | BEGIN_FTR_SECTION | |
58 | extrdi. r10, r12, 1, (63-MSR_TS_T_LG) /* transaction active? */ | |
59 | bne tabort_syscall | |
60 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
61 | #endif | |
9994a338 PM |
62 | andi. r10,r12,MSR_PR |
63 | mr r10,r1 | |
64 | addi r1,r1,-INT_FRAME_SIZE | |
65 | beq- 1f | |
66 | ld r1,PACAKSAVE(r13) | |
67 | 1: std r10,0(r1) | |
68 | std r11,_NIP(r1) | |
69 | std r12,_MSR(r1) | |
70 | std r0,GPR0(r1) | |
71 | std r10,GPR1(r1) | |
5d75b264 | 72 | beq 2f /* if from kernel mode */ |
c6622f63 | 73 | ACCOUNT_CPU_USER_ENTRY(r10, r11) |
5d75b264 | 74 | 2: std r2,GPR2(r1) |
9994a338 | 75 | std r3,GPR3(r1) |
fd6c40f3 | 76 | mfcr r2 |
9994a338 PM |
77 | std r4,GPR4(r1) |
78 | std r5,GPR5(r1) | |
79 | std r6,GPR6(r1) | |
80 | std r7,GPR7(r1) | |
81 | std r8,GPR8(r1) | |
82 | li r11,0 | |
83 | std r11,GPR9(r1) | |
84 | std r11,GPR10(r1) | |
85 | std r11,GPR11(r1) | |
86 | std r11,GPR12(r1) | |
823df435 | 87 | std r11,_XER(r1) |
82087414 | 88 | std r11,_CTR(r1) |
9994a338 | 89 | std r9,GPR13(r1) |
9994a338 | 90 | mflr r10 |
fd6c40f3 AB |
91 | /* |
92 | * This clears CR0.SO (bit 28), which is the error indication on | |
93 | * return from this system call. | |
94 | */ | |
95 | rldimi r2,r11,28,(63-28) | |
9994a338 | 96 | li r11,0xc01 |
9994a338 PM |
97 | std r10,_LINK(r1) |
98 | std r11,_TRAP(r1) | |
9994a338 | 99 | std r3,ORIG_GPR3(r1) |
fd6c40f3 | 100 | std r2,_CCR(r1) |
9994a338 PM |
101 | ld r2,PACATOC(r13) |
102 | addi r9,r1,STACK_FRAME_OVERHEAD | |
103 | ld r11,exception_marker@toc(r2) | |
104 | std r11,-16(r9) /* "regshere" marker */ | |
abf917cd | 105 | #if defined(CONFIG_VIRT_CPU_ACCOUNTING_NATIVE) && defined(CONFIG_PPC_SPLPAR) |
cf9efce0 PM |
106 | BEGIN_FW_FTR_SECTION |
107 | beq 33f | |
108 | /* if from user, see if there are any DTL entries to process */ | |
109 | ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */ | |
110 | ld r11,PACA_DTL_RIDX(r13) /* get log read index */ | |
7ffcf8ec AB |
111 | addi r10,r10,LPPACA_DTLIDX |
112 | LDX_BE r10,0,r10 /* get log write index */ | |
cf9efce0 PM |
113 | cmpd cr1,r11,r10 |
114 | beq+ cr1,33f | |
b1576fec | 115 | bl accumulate_stolen_time |
cf9efce0 PM |
116 | REST_GPR(0,r1) |
117 | REST_4GPRS(3,r1) | |
118 | REST_2GPRS(7,r1) | |
119 | addi r9,r1,STACK_FRAME_OVERHEAD | |
120 | 33: | |
121 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) | |
abf917cd | 122 | #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE && CONFIG_PPC_SPLPAR */ |
cf9efce0 | 123 | |
1421ae0b BH |
124 | /* |
125 | * A syscall should always be called with interrupts enabled | |
126 | * so we just unconditionally hard-enable here. When some kind | |
127 | * of irq tracing is used, we additionally check that condition | |
128 | * is correct | |
129 | */ | |
130 | #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG) | |
131 | lbz r10,PACASOFTIRQEN(r13) | |
132 | xori r10,r10,1 | |
133 | 1: tdnei r10,0 | |
134 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING | |
135 | #endif | |
2d27cfd3 | 136 | |
2d27cfd3 BH |
137 | #ifdef CONFIG_PPC_BOOK3E |
138 | wrteei 1 | |
139 | #else | |
1421ae0b | 140 | ld r11,PACAKMSR(r13) |
9994a338 PM |
141 | ori r11,r11,MSR_EE |
142 | mtmsrd r11,1 | |
2d27cfd3 | 143 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 | 144 | |
1421ae0b BH |
145 | /* We do need to set SOFTE in the stack frame or the return |
146 | * from interrupt will be painful | |
147 | */ | |
148 | li r10,1 | |
149 | std r10,SOFTE(r1) | |
150 | ||
9778b696 | 151 | CURRENT_THREAD_INFO(r11, r1) |
9994a338 | 152 | ld r10,TI_FLAGS(r11) |
10ea8343 | 153 | andi. r11,r10,_TIF_SYSCALL_DOTRACE |
d3837414 | 154 | bne syscall_dotrace /* does not return */ |
9994a338 PM |
155 | cmpldi 0,r0,NR_syscalls |
156 | bge- syscall_enosys | |
157 | ||
158 | system_call: /* label this so stack traces look sane */ | |
159 | /* | |
160 | * Need to vector to 32 Bit or default sys_call_table here, | |
161 | * based on caller's run-mode / personality. | |
162 | */ | |
c857c43b | 163 | ld r11,SYS_CALL_TABLE@toc(2) |
9994a338 PM |
164 | andi. r10,r10,_TIF_32BIT |
165 | beq 15f | |
166 | addi r11,r11,8 /* use 32-bit syscall entries */ | |
167 | clrldi r3,r3,32 | |
168 | clrldi r4,r4,32 | |
169 | clrldi r5,r5,32 | |
170 | clrldi r6,r6,32 | |
171 | clrldi r7,r7,32 | |
172 | clrldi r8,r8,32 | |
173 | 15: | |
174 | slwi r0,r0,4 | |
cc7efbf9 AB |
175 | ldx r12,r11,r0 /* Fetch system call handler [ptr] */ |
176 | mtctr r12 | |
9994a338 PM |
177 | bctrl /* Call handler */ |
178 | ||
4c3b2168 | 179 | .Lsyscall_exit: |
401d1f02 | 180 | std r3,RESULT(r1) |
9778b696 | 181 | CURRENT_THREAD_INFO(r12, r1) |
9994a338 | 182 | |
9994a338 | 183 | ld r8,_MSR(r1) |
2d27cfd3 BH |
184 | #ifdef CONFIG_PPC_BOOK3S |
185 | /* No MSR:RI on BookE */ | |
9994a338 PM |
186 | andi. r10,r8,MSR_RI |
187 | beq- unrecov_restore | |
2d27cfd3 | 188 | #endif |
1421ae0b BH |
189 | /* |
190 | * Disable interrupts so current_thread_info()->flags can't change, | |
2d27cfd3 BH |
191 | * and so that we don't get interrupted after loading SRR0/1. |
192 | */ | |
193 | #ifdef CONFIG_PPC_BOOK3E | |
194 | wrteei 0 | |
195 | #else | |
1421ae0b | 196 | ld r10,PACAKMSR(r13) |
ac1dc365 AB |
197 | /* |
198 | * For performance reasons we clear RI the same time that we | |
199 | * clear EE. We only need to clear RI just before we restore r13 | |
200 | * below, but batching it with EE saves us one expensive mtmsrd call. | |
201 | * We have to be careful to restore RI if we branch anywhere from | |
202 | * here (eg syscall_exit_work). | |
203 | */ | |
204 | li r9,MSR_RI | |
205 | andc r11,r10,r9 | |
206 | mtmsrd r11,1 | |
2d27cfd3 BH |
207 | #endif /* CONFIG_PPC_BOOK3E */ |
208 | ||
9994a338 | 209 | ld r9,TI_FLAGS(r12) |
c3525940 | 210 | li r11,-MAX_ERRNO |
10ea8343 | 211 | andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) |
9994a338 | 212 | bne- syscall_exit_work |
401d1f02 DW |
213 | cmpld r3,r11 |
214 | ld r5,_CCR(r1) | |
215 | bge- syscall_error | |
d14299de | 216 | .Lsyscall_error_cont: |
9994a338 | 217 | ld r7,_NIP(r1) |
f89451fb | 218 | BEGIN_FTR_SECTION |
9994a338 | 219 | stdcx. r0,0,r1 /* to clear the reservation */ |
f89451fb | 220 | END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) |
9994a338 PM |
221 | andi. r6,r8,MSR_PR |
222 | ld r4,_LINK(r1) | |
2d27cfd3 | 223 | |
c6622f63 PM |
224 | beq- 1f |
225 | ACCOUNT_CPU_USER_EXIT(r11, r12) | |
44e9309f | 226 | HMT_MEDIUM_LOW_HAS_PPR |
c6622f63 | 227 | ld r13,GPR13(r1) /* only restore r13 if returning to usermode */ |
9994a338 | 228 | 1: ld r2,GPR2(r1) |
9994a338 PM |
229 | ld r1,GPR1(r1) |
230 | mtlr r4 | |
231 | mtcr r5 | |
232 | mtspr SPRN_SRR0,r7 | |
233 | mtspr SPRN_SRR1,r8 | |
2d27cfd3 | 234 | RFI |
9994a338 PM |
235 | b . /* prevent speculative execution */ |
236 | ||
401d1f02 | 237 | syscall_error: |
9994a338 | 238 | oris r5,r5,0x1000 /* Set SO bit in CR */ |
401d1f02 | 239 | neg r3,r3 |
9994a338 | 240 | std r5,_CCR(r1) |
d14299de | 241 | b .Lsyscall_error_cont |
401d1f02 | 242 | |
9994a338 PM |
243 | /* Traced system call support */ |
244 | syscall_dotrace: | |
b1576fec | 245 | bl save_nvgprs |
9994a338 | 246 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 247 | bl do_syscall_trace_enter |
d3837414 | 248 | |
4f72c427 | 249 | /* |
d3837414 ME |
250 | * We use the return value of do_syscall_trace_enter() as the syscall |
251 | * number. If the syscall was rejected for any reason do_syscall_trace_enter() | |
252 | * returns an invalid syscall number and the test below against | |
253 | * NR_syscalls will fail. | |
4f72c427 RM |
254 | */ |
255 | mr r0,r3 | |
d3837414 ME |
256 | |
257 | /* Restore argument registers just clobbered and/or possibly changed. */ | |
9994a338 PM |
258 | ld r3,GPR3(r1) |
259 | ld r4,GPR4(r1) | |
260 | ld r5,GPR5(r1) | |
261 | ld r6,GPR6(r1) | |
262 | ld r7,GPR7(r1) | |
263 | ld r8,GPR8(r1) | |
d3837414 ME |
264 | |
265 | /* Repopulate r9 and r10 for the system_call path */ | |
9994a338 | 266 | addi r9,r1,STACK_FRAME_OVERHEAD |
9778b696 | 267 | CURRENT_THREAD_INFO(r10, r1) |
9994a338 | 268 | ld r10,TI_FLAGS(r10) |
d3837414 ME |
269 | |
270 | cmpldi r0,NR_syscalls | |
271 | blt+ system_call | |
272 | ||
273 | /* Return code is already in r3 thanks to do_syscall_trace_enter() */ | |
274 | b .Lsyscall_exit | |
275 | ||
9994a338 | 276 | |
401d1f02 DW |
277 | syscall_enosys: |
278 | li r3,-ENOSYS | |
4c3b2168 | 279 | b .Lsyscall_exit |
401d1f02 DW |
280 | |
281 | syscall_exit_work: | |
ac1dc365 AB |
282 | #ifdef CONFIG_PPC_BOOK3S |
283 | mtmsrd r10,1 /* Restore RI */ | |
284 | #endif | |
401d1f02 DW |
285 | /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr. |
286 | If TIF_NOERROR is set, just save r3 as it is. */ | |
287 | ||
288 | andi. r0,r9,_TIF_RESTOREALL | |
1bd79336 PM |
289 | beq+ 0f |
290 | REST_NVGPRS(r1) | |
291 | b 2f | |
c3525940 | 292 | 0: cmpld r3,r11 /* r11 is -MAX_ERRNO */ |
401d1f02 DW |
293 | blt+ 1f |
294 | andi. r0,r9,_TIF_NOERROR | |
295 | bne- 1f | |
296 | ld r5,_CCR(r1) | |
297 | neg r3,r3 | |
298 | oris r5,r5,0x1000 /* Set SO bit in CR */ | |
299 | std r5,_CCR(r1) | |
300 | 1: std r3,GPR3(r1) | |
301 | 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK) | |
302 | beq 4f | |
303 | ||
1bd79336 | 304 | /* Clear per-syscall TIF flags if any are set. */ |
401d1f02 DW |
305 | |
306 | li r11,_TIF_PERSYSCALL_MASK | |
307 | addi r12,r12,TI_FLAGS | |
308 | 3: ldarx r10,0,r12 | |
309 | andc r10,r10,r11 | |
310 | stdcx. r10,0,r12 | |
311 | bne- 3b | |
312 | subi r12,r12,TI_FLAGS | |
1bd79336 PM |
313 | |
314 | 4: /* Anything else left to do? */ | |
05e38e5d | 315 | SET_DEFAULT_THREAD_PPR(r3, r10) /* Set thread.ppr = 3 */ |
10ea8343 | 316 | andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP) |
b1576fec | 317 | beq ret_from_except_lite |
401d1f02 DW |
318 | |
319 | /* Re-enable interrupts */ | |
2d27cfd3 BH |
320 | #ifdef CONFIG_PPC_BOOK3E |
321 | wrteei 1 | |
322 | #else | |
1421ae0b | 323 | ld r10,PACAKMSR(r13) |
401d1f02 DW |
324 | ori r10,r10,MSR_EE |
325 | mtmsrd r10,1 | |
2d27cfd3 | 326 | #endif /* CONFIG_PPC_BOOK3E */ |
401d1f02 | 327 | |
b1576fec | 328 | bl save_nvgprs |
9994a338 | 329 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
330 | bl do_syscall_trace_leave |
331 | b ret_from_except | |
9994a338 | 332 | |
b4b56f9e S |
333 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
334 | tabort_syscall: | |
335 | /* Firstly we need to enable TM in the kernel */ | |
336 | mfmsr r10 | |
337 | li r13, 1 | |
338 | rldimi r10, r13, MSR_TM_LG, 63-MSR_TM_LG | |
339 | mtmsrd r10, 0 | |
340 | ||
341 | /* tabort, this dooms the transaction, nothing else */ | |
342 | li r13, (TM_CAUSE_SYSCALL|TM_CAUSE_PERSISTENT) | |
343 | TABORT(R13) | |
344 | ||
345 | /* | |
346 | * Return directly to userspace. We have corrupted user register state, | |
347 | * but userspace will never see that register state. Execution will | |
348 | * resume after the tbegin of the aborted transaction with the | |
349 | * checkpointed register state. | |
350 | */ | |
351 | li r13, MSR_RI | |
352 | andc r10, r10, r13 | |
353 | mtmsrd r10, 1 | |
354 | mtspr SPRN_SRR0, r11 | |
355 | mtspr SPRN_SRR1, r12 | |
356 | ||
357 | rfid | |
358 | b . /* prevent speculative execution */ | |
359 | #endif | |
360 | ||
9994a338 PM |
361 | /* Save non-volatile GPRs, if not already saved. */ |
362 | _GLOBAL(save_nvgprs) | |
363 | ld r11,_TRAP(r1) | |
364 | andi. r0,r11,1 | |
365 | beqlr- | |
366 | SAVE_NVGPRS(r1) | |
367 | clrrdi r0,r11,1 | |
368 | std r0,_TRAP(r1) | |
369 | blr | |
370 | ||
401d1f02 | 371 | |
9994a338 PM |
372 | /* |
373 | * The sigsuspend and rt_sigsuspend system calls can call do_signal | |
374 | * and thus put the process into the stopped state where we might | |
375 | * want to examine its user state with ptrace. Therefore we need | |
376 | * to save all the nonvolatile registers (r14 - r31) before calling | |
377 | * the C code. Similarly, fork, vfork and clone need the full | |
378 | * register state on the stack so that it can be copied to the child. | |
379 | */ | |
9994a338 PM |
380 | |
381 | _GLOBAL(ppc_fork) | |
b1576fec AB |
382 | bl save_nvgprs |
383 | bl sys_fork | |
4c3b2168 | 384 | b .Lsyscall_exit |
9994a338 PM |
385 | |
386 | _GLOBAL(ppc_vfork) | |
b1576fec AB |
387 | bl save_nvgprs |
388 | bl sys_vfork | |
4c3b2168 | 389 | b .Lsyscall_exit |
9994a338 PM |
390 | |
391 | _GLOBAL(ppc_clone) | |
b1576fec AB |
392 | bl save_nvgprs |
393 | bl sys_clone | |
4c3b2168 | 394 | b .Lsyscall_exit |
9994a338 | 395 | |
1bd79336 | 396 | _GLOBAL(ppc32_swapcontext) |
b1576fec AB |
397 | bl save_nvgprs |
398 | bl compat_sys_swapcontext | |
4c3b2168 | 399 | b .Lsyscall_exit |
1bd79336 PM |
400 | |
401 | _GLOBAL(ppc64_swapcontext) | |
b1576fec AB |
402 | bl save_nvgprs |
403 | bl sys_swapcontext | |
4c3b2168 | 404 | b .Lsyscall_exit |
1bd79336 | 405 | |
529d235a ME |
406 | _GLOBAL(ppc_switch_endian) |
407 | bl save_nvgprs | |
408 | bl sys_switch_endian | |
409 | b .Lsyscall_exit | |
410 | ||
9994a338 | 411 | _GLOBAL(ret_from_fork) |
b1576fec | 412 | bl schedule_tail |
9994a338 PM |
413 | REST_NVGPRS(r1) |
414 | li r3,0 | |
4c3b2168 | 415 | b .Lsyscall_exit |
9994a338 | 416 | |
58254e10 | 417 | _GLOBAL(ret_from_kernel_thread) |
b1576fec | 418 | bl schedule_tail |
58254e10 | 419 | REST_NVGPRS(r1) |
58254e10 AV |
420 | mtlr r14 |
421 | mr r3,r15 | |
7cedd601 AB |
422 | #if defined(_CALL_ELF) && _CALL_ELF == 2 |
423 | mr r12,r14 | |
424 | #endif | |
58254e10 AV |
425 | blrl |
426 | li r3,0 | |
4c3b2168 | 427 | b .Lsyscall_exit |
be6abfa7 | 428 | |
9994a338 PM |
429 | /* |
430 | * This routine switches between two different tasks. The process | |
431 | * state of one is saved on its kernel stack. Then the state | |
432 | * of the other is restored from its kernel stack. The memory | |
433 | * management hardware is updated to the second process's state. | |
434 | * Finally, we can return to the second process, via ret_from_except. | |
435 | * On entry, r3 points to the THREAD for the current task, r4 | |
436 | * points to the THREAD for the new task. | |
437 | * | |
438 | * Note: there are two ways to get to the "going out" portion | |
439 | * of this code; either by coming in via the entry (_switch) | |
440 | * or via "fork" which must set up an environment equivalent | |
441 | * to the "_switch" path. If you change this you'll have to change | |
442 | * the fork code also. | |
443 | * | |
444 | * The code which creates the new task context is in 'copy_thread' | |
2ef9481e | 445 | * in arch/powerpc/kernel/process.c |
9994a338 PM |
446 | */ |
447 | .align 7 | |
448 | _GLOBAL(_switch) | |
449 | mflr r0 | |
450 | std r0,16(r1) | |
451 | stdu r1,-SWITCH_FRAME_SIZE(r1) | |
452 | /* r3-r13 are caller saved -- Cort */ | |
453 | SAVE_8GPRS(14, r1) | |
454 | SAVE_10GPRS(22, r1) | |
455 | mflr r20 /* Return to switch caller */ | |
152d523e | 456 | |
07e45c12 | 457 | std r20,_NIP(r1) |
9994a338 PM |
458 | mfcr r23 |
459 | std r23,_CCR(r1) | |
460 | std r1,KSP(r3) /* Set old stack pointer */ | |
461 | ||
462 | #ifdef CONFIG_SMP | |
463 | /* We need a sync somewhere here to make sure that if the | |
464 | * previous task gets rescheduled on another CPU, it sees all | |
465 | * stores it has performed on this one. | |
466 | */ | |
467 | sync | |
468 | #endif /* CONFIG_SMP */ | |
469 | ||
f89451fb AB |
470 | /* |
471 | * If we optimise away the clear of the reservation in system | |
472 | * calls because we know the CPU tracks the address of the | |
473 | * reservation, then we need to clear it here to cover the | |
474 | * case that the kernel context switch path has no larx | |
475 | * instructions. | |
476 | */ | |
477 | BEGIN_FTR_SECTION | |
478 | ldarx r6,0,r1 | |
479 | END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS) | |
480 | ||
a515348f MN |
481 | #ifdef CONFIG_PPC_BOOK3S |
482 | /* Cancel all explict user streams as they will have no use after context | |
483 | * switch and will stop the HW from creating streams itself | |
484 | */ | |
485 | DCBT_STOP_ALL_STREAM_IDS(r6) | |
486 | #endif | |
487 | ||
9994a338 PM |
488 | addi r6,r4,-THREAD /* Convert THREAD to 'current' */ |
489 | std r6,PACACURRENT(r13) /* Set new 'current' */ | |
490 | ||
491 | ld r8,KSP(r4) /* new stack pointer */ | |
2d27cfd3 | 492 | #ifdef CONFIG_PPC_BOOK3S |
1189be65 | 493 | BEGIN_FTR_SECTION |
9994a338 PM |
494 | clrrdi r6,r8,28 /* get its ESID */ |
495 | clrrdi r9,r1,28 /* get current sp ESID */ | |
13b3d13b | 496 | FTR_SECTION_ELSE |
1189be65 PM |
497 | clrrdi r6,r8,40 /* get its 1T ESID */ |
498 | clrrdi r9,r1,40 /* get current sp 1T ESID */ | |
13b3d13b | 499 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT) |
9994a338 PM |
500 | clrldi. r0,r6,2 /* is new ESID c00000000? */ |
501 | cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ | |
502 | cror eq,4*cr1+eq,eq | |
503 | beq 2f /* if yes, don't slbie it */ | |
504 | ||
505 | /* Bolt in the new stack SLB entry */ | |
506 | ld r7,KSP_VSID(r4) /* Get new stack's VSID */ | |
507 | oris r0,r6,(SLB_ESID_V)@h | |
508 | ori r0,r0,(SLB_NUM_BOLTED-1)@l | |
1189be65 PM |
509 | BEGIN_FTR_SECTION |
510 | li r9,MMU_SEGSIZE_1T /* insert B field */ | |
511 | oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h | |
512 | rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0 | |
44ae3ab3 | 513 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) |
2f6093c8 | 514 | |
00efee7d MN |
515 | /* Update the last bolted SLB. No write barriers are needed |
516 | * here, provided we only update the current CPU's SLB shadow | |
517 | * buffer. | |
518 | */ | |
2f6093c8 | 519 | ld r9,PACA_SLBSHADOWPTR(r13) |
11a27ad7 | 520 | li r12,0 |
7ffcf8ec AB |
521 | std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ |
522 | li r12,SLBSHADOW_STACKVSID | |
523 | STDX_BE r7,r12,r9 /* Save VSID */ | |
524 | li r12,SLBSHADOW_STACKESID | |
525 | STDX_BE r0,r12,r9 /* Save ESID */ | |
2f6093c8 | 526 | |
44ae3ab3 | 527 | /* No need to check for MMU_FTR_NO_SLBIE_B here, since when |
f66bce5e OJ |
528 | * we have 1TB segments, the only CPUs known to have the errata |
529 | * only support less than 1TB of system memory and we'll never | |
530 | * actually hit this code path. | |
531 | */ | |
532 | ||
9994a338 PM |
533 | slbie r6 |
534 | slbie r6 /* Workaround POWER5 < DD2.1 issue */ | |
535 | slbmte r7,r0 | |
536 | isync | |
9994a338 | 537 | 2: |
2d27cfd3 BH |
538 | #endif /* !CONFIG_PPC_BOOK3S */ |
539 | ||
9778b696 | 540 | CURRENT_THREAD_INFO(r7, r8) /* base of new stack */ |
9994a338 PM |
541 | /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE |
542 | because we don't need to leave the 288-byte ABI gap at the | |
543 | top of the kernel stack. */ | |
544 | addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE | |
545 | ||
546 | mr r1,r8 /* start using new stack pointer */ | |
547 | std r7,PACAKSAVE(r13) | |
548 | ||
71433285 AB |
549 | ld r6,_CCR(r1) |
550 | mtcrf 0xFF,r6 | |
551 | ||
9994a338 PM |
552 | /* r3-r13 are destroyed -- Cort */ |
553 | REST_8GPRS(14, r1) | |
554 | REST_10GPRS(22, r1) | |
555 | ||
556 | /* convert old thread to its task_struct for return value */ | |
557 | addi r3,r3,-THREAD | |
558 | ld r7,_NIP(r1) /* Return to _switch caller in new task */ | |
559 | mtlr r7 | |
560 | addi r1,r1,SWITCH_FRAME_SIZE | |
561 | blr | |
562 | ||
563 | .align 7 | |
564 | _GLOBAL(ret_from_except) | |
565 | ld r11,_TRAP(r1) | |
566 | andi. r0,r11,1 | |
b1576fec | 567 | bne ret_from_except_lite |
9994a338 PM |
568 | REST_NVGPRS(r1) |
569 | ||
570 | _GLOBAL(ret_from_except_lite) | |
571 | /* | |
572 | * Disable interrupts so that current_thread_info()->flags | |
573 | * can't change between when we test it and when we return | |
574 | * from the interrupt. | |
575 | */ | |
2d27cfd3 BH |
576 | #ifdef CONFIG_PPC_BOOK3E |
577 | wrteei 0 | |
578 | #else | |
d9ada91a BH |
579 | ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ |
580 | mtmsrd r10,1 /* Update machine state */ | |
2d27cfd3 | 581 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 | 582 | |
9778b696 | 583 | CURRENT_THREAD_INFO(r9, r1) |
9994a338 | 584 | ld r3,_MSR(r1) |
13d543cd BB |
585 | #ifdef CONFIG_PPC_BOOK3E |
586 | ld r10,PACACURRENT(r13) | |
587 | #endif /* CONFIG_PPC_BOOK3E */ | |
9994a338 | 588 | ld r4,TI_FLAGS(r9) |
9994a338 | 589 | andi. r3,r3,MSR_PR |
c58ce2b1 | 590 | beq resume_kernel |
13d543cd BB |
591 | #ifdef CONFIG_PPC_BOOK3E |
592 | lwz r3,(THREAD+THREAD_DBCR0)(r10) | |
593 | #endif /* CONFIG_PPC_BOOK3E */ | |
9994a338 PM |
594 | |
595 | /* Check current_thread_info()->flags */ | |
c58ce2b1 | 596 | andi. r0,r4,_TIF_USER_WORK_MASK |
13d543cd BB |
597 | #ifdef CONFIG_PPC_BOOK3E |
598 | bne 1f | |
599 | /* | |
600 | * Check to see if the dbcr0 register is set up to debug. | |
601 | * Use the internal debug mode bit to do this. | |
602 | */ | |
603 | andis. r0,r3,DBCR0_IDM@h | |
c58ce2b1 | 604 | beq restore |
13d543cd BB |
605 | mfmsr r0 |
606 | rlwinm r0,r0,0,~MSR_DE /* Clear MSR.DE */ | |
607 | mtmsr r0 | |
608 | mtspr SPRN_DBCR0,r3 | |
609 | li r10, -1 | |
610 | mtspr SPRN_DBSR,r10 | |
611 | b restore | |
612 | #else | |
613 | beq restore | |
614 | #endif | |
615 | 1: andi. r0,r4,_TIF_NEED_RESCHED | |
616 | beq 2f | |
b1576fec | 617 | bl restore_interrupts |
5d1c5745 | 618 | SCHEDULE_USER |
b1576fec | 619 | b ret_from_except_lite |
d31626f7 PM |
620 | 2: |
621 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
622 | andi. r0,r4,_TIF_USER_WORK_MASK & ~_TIF_RESTORE_TM | |
623 | bne 3f /* only restore TM if nothing else to do */ | |
624 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 625 | bl restore_tm_state |
d31626f7 PM |
626 | b restore |
627 | 3: | |
628 | #endif | |
b1576fec | 629 | bl save_nvgprs |
808be314 AB |
630 | /* |
631 | * Use a non volatile GPR to save and restore our thread_info flags | |
632 | * across the call to restore_interrupts. | |
633 | */ | |
634 | mr r30,r4 | |
b1576fec | 635 | bl restore_interrupts |
808be314 | 636 | mr r4,r30 |
c58ce2b1 | 637 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
638 | bl do_notify_resume |
639 | b ret_from_except | |
c58ce2b1 TC |
640 | |
641 | resume_kernel: | |
a9c4e541 | 642 | /* check current_thread_info, _TIF_EMULATE_STACK_STORE */ |
0edfdd10 | 643 | andis. r8,r4,_TIF_EMULATE_STACK_STORE@h |
a9c4e541 TC |
644 | beq+ 1f |
645 | ||
646 | addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */ | |
647 | ||
648 | lwz r3,GPR1(r1) | |
649 | subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */ | |
650 | mr r4,r1 /* src: current exception frame */ | |
651 | mr r1,r3 /* Reroute the trampoline frame to r1 */ | |
652 | ||
653 | /* Copy from the original to the trampoline. */ | |
654 | li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */ | |
655 | li r6,0 /* start offset: 0 */ | |
656 | mtctr r5 | |
657 | 2: ldx r0,r6,r4 | |
658 | stdx r0,r6,r3 | |
659 | addi r6,r6,8 | |
660 | bdnz 2b | |
661 | ||
662 | /* Do real store operation to complete stwu */ | |
663 | lwz r5,GPR1(r1) | |
664 | std r8,0(r5) | |
665 | ||
666 | /* Clear _TIF_EMULATE_STACK_STORE flag */ | |
667 | lis r11,_TIF_EMULATE_STACK_STORE@h | |
668 | addi r5,r9,TI_FLAGS | |
d8b92292 | 669 | 0: ldarx r4,0,r5 |
a9c4e541 TC |
670 | andc r4,r4,r11 |
671 | stdcx. r4,0,r5 | |
672 | bne- 0b | |
673 | 1: | |
674 | ||
c58ce2b1 TC |
675 | #ifdef CONFIG_PREEMPT |
676 | /* Check if we need to preempt */ | |
677 | andi. r0,r4,_TIF_NEED_RESCHED | |
678 | beq+ restore | |
679 | /* Check that preempt_count() == 0 and interrupts are enabled */ | |
680 | lwz r8,TI_PREEMPT(r9) | |
681 | cmpwi cr1,r8,0 | |
682 | ld r0,SOFTE(r1) | |
683 | cmpdi r0,0 | |
684 | crandc eq,cr1*4+eq,eq | |
685 | bne restore | |
686 | ||
687 | /* | |
688 | * Here we are preempting the current task. We want to make | |
de021bb7 | 689 | * sure we are soft-disabled first and reconcile irq state. |
c58ce2b1 | 690 | */ |
de021bb7 | 691 | RECONCILE_IRQ_STATE(r3,r4) |
b1576fec | 692 | 1: bl preempt_schedule_irq |
c58ce2b1 TC |
693 | |
694 | /* Re-test flags and eventually loop */ | |
9778b696 | 695 | CURRENT_THREAD_INFO(r9, r1) |
9994a338 | 696 | ld r4,TI_FLAGS(r9) |
c58ce2b1 TC |
697 | andi. r0,r4,_TIF_NEED_RESCHED |
698 | bne 1b | |
572177d7 TC |
699 | |
700 | /* | |
701 | * arch_local_irq_restore() from preempt_schedule_irq above may | |
702 | * enable hard interrupt but we really should disable interrupts | |
703 | * when we return from the interrupt, and so that we don't get | |
704 | * interrupted after loading SRR0/1. | |
705 | */ | |
706 | #ifdef CONFIG_PPC_BOOK3E | |
707 | wrteei 0 | |
708 | #else | |
709 | ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ | |
710 | mtmsrd r10,1 /* Update machine state */ | |
711 | #endif /* CONFIG_PPC_BOOK3E */ | |
c58ce2b1 | 712 | #endif /* CONFIG_PREEMPT */ |
9994a338 | 713 | |
7230c564 BH |
714 | .globl fast_exc_return_irq |
715 | fast_exc_return_irq: | |
9994a338 | 716 | restore: |
7230c564 | 717 | /* |
7c0482e3 BH |
718 | * This is the main kernel exit path. First we check if we |
719 | * are about to re-enable interrupts | |
7230c564 | 720 | */ |
01f3880d | 721 | ld r5,SOFTE(r1) |
7230c564 | 722 | lbz r6,PACASOFTIRQEN(r13) |
7c0482e3 BH |
723 | cmpwi cr0,r5,0 |
724 | beq restore_irq_off | |
7230c564 | 725 | |
7c0482e3 BH |
726 | /* We are enabling, were we already enabled ? Yes, just return */ |
727 | cmpwi cr0,r6,1 | |
728 | beq cr0,do_restore | |
9994a338 | 729 | |
7c0482e3 | 730 | /* |
7230c564 BH |
731 | * We are about to soft-enable interrupts (we are hard disabled |
732 | * at this point). We check if there's anything that needs to | |
733 | * be replayed first. | |
734 | */ | |
735 | lbz r0,PACAIRQHAPPENED(r13) | |
736 | cmpwi cr0,r0,0 | |
737 | bne- restore_check_irq_replay | |
e56a6e20 | 738 | |
7230c564 BH |
739 | /* |
740 | * Get here when nothing happened while soft-disabled, just | |
741 | * soft-enable and move-on. We will hard-enable as a side | |
742 | * effect of rfi | |
743 | */ | |
744 | restore_no_replay: | |
745 | TRACE_ENABLE_INTS | |
746 | li r0,1 | |
747 | stb r0,PACASOFTIRQEN(r13); | |
748 | ||
749 | /* | |
750 | * Final return path. BookE is handled in a different file | |
751 | */ | |
7c0482e3 | 752 | do_restore: |
2d27cfd3 | 753 | #ifdef CONFIG_PPC_BOOK3E |
b1576fec | 754 | b exception_return_book3e |
2d27cfd3 | 755 | #else |
7230c564 BH |
756 | /* |
757 | * Clear the reservation. If we know the CPU tracks the address of | |
758 | * the reservation then we can potentially save some cycles and use | |
759 | * a larx. On POWER6 and POWER7 this is significantly faster. | |
760 | */ | |
761 | BEGIN_FTR_SECTION | |
762 | stdcx. r0,0,r1 /* to clear the reservation */ | |
763 | FTR_SECTION_ELSE | |
764 | ldarx r4,0,r1 | |
765 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) | |
766 | ||
767 | /* | |
768 | * Some code path such as load_up_fpu or altivec return directly | |
769 | * here. They run entirely hard disabled and do not alter the | |
770 | * interrupt state. They also don't use lwarx/stwcx. and thus | |
771 | * are known not to leave dangling reservations. | |
772 | */ | |
773 | .globl fast_exception_return | |
774 | fast_exception_return: | |
775 | ld r3,_MSR(r1) | |
e56a6e20 PM |
776 | ld r4,_CTR(r1) |
777 | ld r0,_LINK(r1) | |
778 | mtctr r4 | |
779 | mtlr r0 | |
780 | ld r4,_XER(r1) | |
781 | mtspr SPRN_XER,r4 | |
782 | ||
783 | REST_8GPRS(5, r1) | |
784 | ||
9994a338 PM |
785 | andi. r0,r3,MSR_RI |
786 | beq- unrecov_restore | |
787 | ||
0c4888ef BH |
788 | /* Load PPR from thread struct before we clear MSR:RI */ |
789 | BEGIN_FTR_SECTION | |
790 | ld r2,PACACURRENT(r13) | |
791 | ld r2,TASKTHREADPPR(r2) | |
792 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
793 | ||
e56a6e20 PM |
794 | /* |
795 | * Clear RI before restoring r13. If we are returning to | |
796 | * userspace and we take an exception after restoring r13, | |
797 | * we end up corrupting the userspace r13 value. | |
798 | */ | |
d9ada91a BH |
799 | ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */ |
800 | andc r4,r4,r0 /* r0 contains MSR_RI here */ | |
e56a6e20 | 801 | mtmsrd r4,1 |
9994a338 | 802 | |
afc07701 MN |
803 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
804 | /* TM debug */ | |
805 | std r3, PACATMSCRATCH(r13) /* Stash returned-to MSR */ | |
806 | #endif | |
9994a338 PM |
807 | /* |
808 | * r13 is our per cpu area, only restore it if we are returning to | |
7230c564 BH |
809 | * userspace the value stored in the stack frame may belong to |
810 | * another CPU. | |
9994a338 | 811 | */ |
e56a6e20 | 812 | andi. r0,r3,MSR_PR |
9994a338 | 813 | beq 1f |
0c4888ef BH |
814 | BEGIN_FTR_SECTION |
815 | mtspr SPRN_PPR,r2 /* Restore PPR */ | |
816 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR) | |
e56a6e20 | 817 | ACCOUNT_CPU_USER_EXIT(r2, r4) |
9994a338 PM |
818 | REST_GPR(13, r1) |
819 | 1: | |
e56a6e20 | 820 | mtspr SPRN_SRR1,r3 |
9994a338 PM |
821 | |
822 | ld r2,_CCR(r1) | |
823 | mtcrf 0xFF,r2 | |
824 | ld r2,_NIP(r1) | |
825 | mtspr SPRN_SRR0,r2 | |
826 | ||
827 | ld r0,GPR0(r1) | |
828 | ld r2,GPR2(r1) | |
829 | ld r3,GPR3(r1) | |
830 | ld r4,GPR4(r1) | |
831 | ld r1,GPR1(r1) | |
832 | ||
833 | rfid | |
834 | b . /* prevent speculative execution */ | |
835 | ||
2d27cfd3 BH |
836 | #endif /* CONFIG_PPC_BOOK3E */ |
837 | ||
7c0482e3 BH |
838 | /* |
839 | * We are returning to a context with interrupts soft disabled. | |
840 | * | |
841 | * However, we may also about to hard enable, so we need to | |
842 | * make sure that in this case, we also clear PACA_IRQ_HARD_DIS | |
843 | * or that bit can get out of sync and bad things will happen | |
844 | */ | |
845 | restore_irq_off: | |
846 | ld r3,_MSR(r1) | |
847 | lbz r7,PACAIRQHAPPENED(r13) | |
848 | andi. r0,r3,MSR_EE | |
849 | beq 1f | |
850 | rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS | |
851 | stb r7,PACAIRQHAPPENED(r13) | |
852 | 1: li r0,0 | |
853 | stb r0,PACASOFTIRQEN(r13); | |
854 | TRACE_DISABLE_INTS | |
855 | b do_restore | |
856 | ||
7230c564 BH |
857 | /* |
858 | * Something did happen, check if a re-emit is needed | |
859 | * (this also clears paca->irq_happened) | |
860 | */ | |
861 | restore_check_irq_replay: | |
862 | /* XXX: We could implement a fast path here where we check | |
863 | * for irq_happened being just 0x01, in which case we can | |
864 | * clear it and return. That means that we would potentially | |
865 | * miss a decrementer having wrapped all the way around. | |
866 | * | |
867 | * Still, this might be useful for things like hash_page | |
868 | */ | |
b1576fec | 869 | bl __check_irq_replay |
7230c564 BH |
870 | cmpwi cr0,r3,0 |
871 | beq restore_no_replay | |
872 | ||
873 | /* | |
874 | * We need to re-emit an interrupt. We do so by re-using our | |
875 | * existing exception frame. We first change the trap value, | |
876 | * but we need to ensure we preserve the low nibble of it | |
877 | */ | |
878 | ld r4,_TRAP(r1) | |
879 | clrldi r4,r4,60 | |
880 | or r4,r4,r3 | |
881 | std r4,_TRAP(r1) | |
882 | ||
883 | /* | |
884 | * Then find the right handler and call it. Interrupts are | |
885 | * still soft-disabled and we keep them that way. | |
886 | */ | |
887 | cmpwi cr0,r3,0x500 | |
888 | bne 1f | |
889 | addi r3,r1,STACK_FRAME_OVERHEAD; | |
b1576fec AB |
890 | bl do_IRQ |
891 | b ret_from_except | |
0869b6fd MS |
892 | 1: cmpwi cr0,r3,0xe60 |
893 | bne 1f | |
894 | addi r3,r1,STACK_FRAME_OVERHEAD; | |
895 | bl handle_hmi_exception | |
896 | b ret_from_except | |
7230c564 BH |
897 | 1: cmpwi cr0,r3,0x900 |
898 | bne 1f | |
899 | addi r3,r1,STACK_FRAME_OVERHEAD; | |
b1576fec AB |
900 | bl timer_interrupt |
901 | b ret_from_except | |
fe9e1d54 IM |
902 | #ifdef CONFIG_PPC_DOORBELL |
903 | 1: | |
7230c564 | 904 | #ifdef CONFIG_PPC_BOOK3E |
fe9e1d54 IM |
905 | cmpwi cr0,r3,0x280 |
906 | #else | |
907 | BEGIN_FTR_SECTION | |
908 | cmpwi cr0,r3,0xe80 | |
909 | FTR_SECTION_ELSE | |
910 | cmpwi cr0,r3,0xa00 | |
911 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
912 | #endif /* CONFIG_PPC_BOOK3E */ | |
7230c564 BH |
913 | bne 1f |
914 | addi r3,r1,STACK_FRAME_OVERHEAD; | |
b1576fec AB |
915 | bl doorbell_exception |
916 | b ret_from_except | |
fe9e1d54 | 917 | #endif /* CONFIG_PPC_DOORBELL */ |
b1576fec | 918 | 1: b ret_from_except /* What else to do here ? */ |
7230c564 | 919 | |
9994a338 PM |
920 | unrecov_restore: |
921 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 922 | bl unrecoverable_exception |
9994a338 PM |
923 | b unrecov_restore |
924 | ||
925 | #ifdef CONFIG_PPC_RTAS | |
926 | /* | |
927 | * On CHRP, the Run-Time Abstraction Services (RTAS) have to be | |
928 | * called with the MMU off. | |
929 | * | |
930 | * In addition, we need to be in 32b mode, at least for now. | |
931 | * | |
932 | * Note: r3 is an input parameter to rtas, so don't trash it... | |
933 | */ | |
934 | _GLOBAL(enter_rtas) | |
935 | mflr r0 | |
936 | std r0,16(r1) | |
937 | stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */ | |
938 | ||
939 | /* Because RTAS is running in 32b mode, it clobbers the high order half | |
940 | * of all registers that it saves. We therefore save those registers | |
941 | * RTAS might touch to the stack. (r0, r3-r13 are caller saved) | |
942 | */ | |
943 | SAVE_GPR(2, r1) /* Save the TOC */ | |
944 | SAVE_GPR(13, r1) /* Save paca */ | |
945 | SAVE_8GPRS(14, r1) /* Save the non-volatiles */ | |
946 | SAVE_10GPRS(22, r1) /* ditto */ | |
947 | ||
948 | mfcr r4 | |
949 | std r4,_CCR(r1) | |
950 | mfctr r5 | |
951 | std r5,_CTR(r1) | |
952 | mfspr r6,SPRN_XER | |
953 | std r6,_XER(r1) | |
954 | mfdar r7 | |
955 | std r7,_DAR(r1) | |
956 | mfdsisr r8 | |
957 | std r8,_DSISR(r1) | |
9994a338 | 958 | |
9fe901d1 MK |
959 | /* Temporary workaround to clear CR until RTAS can be modified to |
960 | * ignore all bits. | |
961 | */ | |
962 | li r0,0 | |
963 | mtcr r0 | |
964 | ||
007d88d0 | 965 | #ifdef CONFIG_BUG |
9994a338 PM |
966 | /* There is no way it is acceptable to get here with interrupts enabled, |
967 | * check it with the asm equivalent of WARN_ON | |
968 | */ | |
d04c56f7 | 969 | lbz r0,PACASOFTIRQEN(r13) |
9994a338 | 970 | 1: tdnei r0,0 |
007d88d0 DW |
971 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING |
972 | #endif | |
973 | ||
d04c56f7 PM |
974 | /* Hard-disable interrupts */ |
975 | mfmsr r6 | |
976 | rldicl r7,r6,48,1 | |
977 | rotldi r7,r7,16 | |
978 | mtmsrd r7,1 | |
979 | ||
9994a338 PM |
980 | /* Unfortunately, the stack pointer and the MSR are also clobbered, |
981 | * so they are saved in the PACA which allows us to restore | |
982 | * our original state after RTAS returns. | |
983 | */ | |
984 | std r1,PACAR1(r13) | |
985 | std r6,PACASAVEDMSR(r13) | |
986 | ||
987 | /* Setup our real return addr */ | |
ad0289e4 | 988 | LOAD_REG_ADDR(r4,rtas_return_loc) |
e58c3495 | 989 | clrldi r4,r4,2 /* convert to realmode address */ |
9994a338 PM |
990 | mtlr r4 |
991 | ||
992 | li r0,0 | |
993 | ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI | |
994 | andc r0,r6,r0 | |
995 | ||
996 | li r9,1 | |
997 | rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) | |
5c0484e2 | 998 | ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI|MSR_LE |
9994a338 | 999 | andc r6,r0,r9 |
9994a338 PM |
1000 | sync /* disable interrupts so SRR0/1 */ |
1001 | mtmsrd r0 /* don't get trashed */ | |
1002 | ||
e58c3495 | 1003 | LOAD_REG_ADDR(r4, rtas) |
9994a338 PM |
1004 | ld r5,RTASENTRY(r4) /* get the rtas->entry value */ |
1005 | ld r4,RTASBASE(r4) /* get the rtas->base value */ | |
1006 | ||
1007 | mtspr SPRN_SRR0,r5 | |
1008 | mtspr SPRN_SRR1,r6 | |
1009 | rfid | |
1010 | b . /* prevent speculative execution */ | |
1011 | ||
ad0289e4 | 1012 | rtas_return_loc: |
5c0484e2 BH |
1013 | FIXUP_ENDIAN |
1014 | ||
9994a338 | 1015 | /* relocation is off at this point */ |
2dd60d79 | 1016 | GET_PACA(r4) |
e58c3495 | 1017 | clrldi r4,r4,2 /* convert to realmode address */ |
9994a338 | 1018 | |
e31aa453 PM |
1019 | bcl 20,31,$+4 |
1020 | 0: mflr r3 | |
ad0289e4 | 1021 | ld r3,(1f-0b)(r3) /* get &rtas_restore_regs */ |
e31aa453 | 1022 | |
9994a338 PM |
1023 | mfmsr r6 |
1024 | li r0,MSR_RI | |
1025 | andc r6,r6,r0 | |
1026 | sync | |
1027 | mtmsrd r6 | |
1028 | ||
1029 | ld r1,PACAR1(r4) /* Restore our SP */ | |
9994a338 PM |
1030 | ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ |
1031 | ||
1032 | mtspr SPRN_SRR0,r3 | |
1033 | mtspr SPRN_SRR1,r4 | |
1034 | rfid | |
1035 | b . /* prevent speculative execution */ | |
1036 | ||
e31aa453 | 1037 | .align 3 |
ad0289e4 | 1038 | 1: .llong rtas_restore_regs |
e31aa453 | 1039 | |
ad0289e4 | 1040 | rtas_restore_regs: |
9994a338 PM |
1041 | /* relocation is on at this point */ |
1042 | REST_GPR(2, r1) /* Restore the TOC */ | |
1043 | REST_GPR(13, r1) /* Restore paca */ | |
1044 | REST_8GPRS(14, r1) /* Restore the non-volatiles */ | |
1045 | REST_10GPRS(22, r1) /* ditto */ | |
1046 | ||
2dd60d79 | 1047 | GET_PACA(r13) |
9994a338 PM |
1048 | |
1049 | ld r4,_CCR(r1) | |
1050 | mtcr r4 | |
1051 | ld r5,_CTR(r1) | |
1052 | mtctr r5 | |
1053 | ld r6,_XER(r1) | |
1054 | mtspr SPRN_XER,r6 | |
1055 | ld r7,_DAR(r1) | |
1056 | mtdar r7 | |
1057 | ld r8,_DSISR(r1) | |
1058 | mtdsisr r8 | |
9994a338 PM |
1059 | |
1060 | addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */ | |
1061 | ld r0,16(r1) /* get return address */ | |
1062 | ||
1063 | mtlr r0 | |
1064 | blr /* return to caller */ | |
1065 | ||
1066 | #endif /* CONFIG_PPC_RTAS */ | |
1067 | ||
9994a338 PM |
1068 | _GLOBAL(enter_prom) |
1069 | mflr r0 | |
1070 | std r0,16(r1) | |
1071 | stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */ | |
1072 | ||
1073 | /* Because PROM is running in 32b mode, it clobbers the high order half | |
1074 | * of all registers that it saves. We therefore save those registers | |
1075 | * PROM might touch to the stack. (r0, r3-r13 are caller saved) | |
1076 | */ | |
6c171994 | 1077 | SAVE_GPR(2, r1) |
9994a338 PM |
1078 | SAVE_GPR(13, r1) |
1079 | SAVE_8GPRS(14, r1) | |
1080 | SAVE_10GPRS(22, r1) | |
6c171994 | 1081 | mfcr r10 |
9994a338 | 1082 | mfmsr r11 |
6c171994 | 1083 | std r10,_CCR(r1) |
9994a338 PM |
1084 | std r11,_MSR(r1) |
1085 | ||
5c0484e2 BH |
1086 | /* Put PROM address in SRR0 */ |
1087 | mtsrr0 r4 | |
1088 | ||
1089 | /* Setup our trampoline return addr in LR */ | |
1090 | bcl 20,31,$+4 | |
1091 | 0: mflr r4 | |
1092 | addi r4,r4,(1f - 0b) | |
1093 | mtlr r4 | |
9994a338 | 1094 | |
5c0484e2 | 1095 | /* Prepare a 32-bit mode big endian MSR |
9994a338 | 1096 | */ |
2d27cfd3 BH |
1097 | #ifdef CONFIG_PPC_BOOK3E |
1098 | rlwinm r11,r11,0,1,31 | |
5c0484e2 BH |
1099 | mtsrr1 r11 |
1100 | rfi | |
2d27cfd3 | 1101 | #else /* CONFIG_PPC_BOOK3E */ |
5c0484e2 BH |
1102 | LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE) |
1103 | andc r11,r11,r12 | |
1104 | mtsrr1 r11 | |
1105 | rfid | |
2d27cfd3 | 1106 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 | 1107 | |
5c0484e2 BH |
1108 | 1: /* Return from OF */ |
1109 | FIXUP_ENDIAN | |
9994a338 PM |
1110 | |
1111 | /* Just make sure that r1 top 32 bits didn't get | |
1112 | * corrupt by OF | |
1113 | */ | |
1114 | rldicl r1,r1,0,32 | |
1115 | ||
1116 | /* Restore the MSR (back to 64 bits) */ | |
1117 | ld r0,_MSR(r1) | |
6c171994 | 1118 | MTMSRD(r0) |
9994a338 PM |
1119 | isync |
1120 | ||
1121 | /* Restore other registers */ | |
1122 | REST_GPR(2, r1) | |
1123 | REST_GPR(13, r1) | |
1124 | REST_8GPRS(14, r1) | |
1125 | REST_10GPRS(22, r1) | |
1126 | ld r4,_CCR(r1) | |
1127 | mtcr r4 | |
9994a338 PM |
1128 | |
1129 | addi r1,r1,PROM_FRAME_SIZE | |
1130 | ld r0,16(r1) | |
1131 | mtlr r0 | |
1132 | blr | |
4e491d14 | 1133 | |
606576ce | 1134 | #ifdef CONFIG_FUNCTION_TRACER |
4e491d14 SR |
1135 | #ifdef CONFIG_DYNAMIC_FTRACE |
1136 | _GLOBAL(mcount) | |
1137 | _GLOBAL(_mcount) | |
4e491d14 SR |
1138 | blr |
1139 | ||
5e66684f | 1140 | _GLOBAL_TOC(ftrace_caller) |
4e491d14 SR |
1141 | /* Taken from output of objdump from lib64/glibc */ |
1142 | mflr r3 | |
1143 | ld r11, 0(r1) | |
1144 | stdu r1, -112(r1) | |
1145 | std r3, 128(r1) | |
1146 | ld r4, 16(r11) | |
395a59d0 | 1147 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
1148 | .globl ftrace_call |
1149 | ftrace_call: | |
1150 | bl ftrace_stub | |
1151 | nop | |
46542888 SR |
1152 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1153 | .globl ftrace_graph_call | |
1154 | ftrace_graph_call: | |
1155 | b ftrace_graph_stub | |
1156 | _GLOBAL(ftrace_graph_stub) | |
1157 | #endif | |
4e491d14 SR |
1158 | ld r0, 128(r1) |
1159 | mtlr r0 | |
1160 | addi r1, r1, 112 | |
1161 | _GLOBAL(ftrace_stub) | |
1162 | blr | |
1163 | #else | |
5e66684f | 1164 | _GLOBAL_TOC(_mcount) |
4e491d14 SR |
1165 | /* Taken from output of objdump from lib64/glibc */ |
1166 | mflr r3 | |
1167 | ld r11, 0(r1) | |
1168 | stdu r1, -112(r1) | |
1169 | std r3, 128(r1) | |
1170 | ld r4, 16(r11) | |
1171 | ||
395a59d0 | 1172 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
1173 | LOAD_REG_ADDR(r5,ftrace_trace_function) |
1174 | ld r5,0(r5) | |
1175 | ld r5,0(r5) | |
1176 | mtctr r5 | |
1177 | bctrl | |
4e491d14 | 1178 | nop |
6794c782 SR |
1179 | |
1180 | ||
1181 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
1182 | b ftrace_graph_caller | |
1183 | #endif | |
4e491d14 SR |
1184 | ld r0, 128(r1) |
1185 | mtlr r0 | |
1186 | addi r1, r1, 112 | |
1187 | _GLOBAL(ftrace_stub) | |
1188 | blr | |
1189 | ||
6794c782 SR |
1190 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
1191 | ||
1192 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
46542888 | 1193 | _GLOBAL(ftrace_graph_caller) |
6794c782 SR |
1194 | /* load r4 with local address */ |
1195 | ld r4, 128(r1) | |
1196 | subi r4, r4, MCOUNT_INSN_SIZE | |
1197 | ||
b3c18725 | 1198 | /* Grab the LR out of the caller stack frame */ |
6794c782 | 1199 | ld r11, 112(r1) |
b3c18725 | 1200 | ld r3, 16(r11) |
6794c782 | 1201 | |
b1576fec | 1202 | bl prepare_ftrace_return |
6794c782 SR |
1203 | nop |
1204 | ||
b3c18725 AB |
1205 | /* |
1206 | * prepare_ftrace_return gives us the address we divert to. | |
1207 | * Change the LR in the callers stack frame to this. | |
1208 | */ | |
1209 | ld r11, 112(r1) | |
1210 | std r3, 16(r11) | |
1211 | ||
6794c782 SR |
1212 | ld r0, 128(r1) |
1213 | mtlr r0 | |
1214 | addi r1, r1, 112 | |
1215 | blr | |
1216 | ||
1217 | _GLOBAL(return_to_handler) | |
1218 | /* need to save return values */ | |
1219 | std r4, -32(r1) | |
1220 | std r3, -24(r1) | |
1221 | /* save TOC */ | |
1222 | std r2, -16(r1) | |
1223 | std r31, -8(r1) | |
1224 | mr r31, r1 | |
1225 | stdu r1, -112(r1) | |
1226 | ||
bb725340 | 1227 | /* |
7d56c65a | 1228 | * We might be called from a module. |
bb725340 SR |
1229 | * Switch to our TOC to run inside the core kernel. |
1230 | */ | |
be10ab10 | 1231 | ld r2, PACATOC(r13) |
6794c782 | 1232 | |
b1576fec | 1233 | bl ftrace_return_to_handler |
6794c782 SR |
1234 | nop |
1235 | ||
1236 | /* return value has real return address */ | |
1237 | mtlr r3 | |
1238 | ||
1239 | ld r1, 0(r1) | |
1240 | ld r4, -32(r1) | |
1241 | ld r3, -24(r1) | |
1242 | ld r2, -16(r1) | |
1243 | ld r31, -8(r1) | |
1244 | ||
1245 | /* Jump back to real return address */ | |
1246 | blr | |
1247 | #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ | |
1248 | #endif /* CONFIG_FUNCTION_TRACER */ |