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9994a338 | 1 | /* |
9994a338 PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
6 | * Adapted for Power Macintosh by Paul Mackerras. | |
7 | * Low-level exception handlers and MMU support | |
8 | * rewritten by Paul Mackerras. | |
9 | * Copyright (C) 1996 Paul Mackerras. | |
10 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
11 | * | |
12 | * This file contains the system call entry code, context switch | |
13 | * code, and exception/interrupt return code for PowerPC. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
9994a338 PM |
21 | #include <linux/errno.h> |
22 | #include <asm/unistd.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/page.h> | |
25 | #include <asm/mmu.h> | |
26 | #include <asm/thread_info.h> | |
27 | #include <asm/ppc_asm.h> | |
28 | #include <asm/asm-offsets.h> | |
29 | #include <asm/cputable.h> | |
3f639ee8 | 30 | #include <asm/firmware.h> |
007d88d0 | 31 | #include <asm/bug.h> |
ec2b36b9 | 32 | #include <asm/ptrace.h> |
945feb17 | 33 | #include <asm/irqflags.h> |
395a59d0 | 34 | #include <asm/ftrace.h> |
7230c564 | 35 | #include <asm/hw_irq.h> |
9994a338 PM |
36 | |
37 | /* | |
38 | * System calls. | |
39 | */ | |
40 | .section ".toc","aw" | |
41 | .SYS_CALL_TABLE: | |
42 | .tc .sys_call_table[TC],.sys_call_table | |
43 | ||
44 | /* This value is used to mark exception frames on the stack. */ | |
45 | exception_marker: | |
ec2b36b9 | 46 | .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER |
9994a338 PM |
47 | |
48 | .section ".text" | |
49 | .align 7 | |
50 | ||
51 | #undef SHOW_SYSCALLS | |
52 | ||
53 | .globl system_call_common | |
54 | system_call_common: | |
55 | andi. r10,r12,MSR_PR | |
56 | mr r10,r1 | |
57 | addi r1,r1,-INT_FRAME_SIZE | |
58 | beq- 1f | |
59 | ld r1,PACAKSAVE(r13) | |
60 | 1: std r10,0(r1) | |
61 | std r11,_NIP(r1) | |
62 | std r12,_MSR(r1) | |
63 | std r0,GPR0(r1) | |
64 | std r10,GPR1(r1) | |
c6622f63 | 65 | ACCOUNT_CPU_USER_ENTRY(r10, r11) |
9994a338 PM |
66 | std r2,GPR2(r1) |
67 | std r3,GPR3(r1) | |
fd6c40f3 | 68 | mfcr r2 |
9994a338 PM |
69 | std r4,GPR4(r1) |
70 | std r5,GPR5(r1) | |
71 | std r6,GPR6(r1) | |
72 | std r7,GPR7(r1) | |
73 | std r8,GPR8(r1) | |
74 | li r11,0 | |
75 | std r11,GPR9(r1) | |
76 | std r11,GPR10(r1) | |
77 | std r11,GPR11(r1) | |
78 | std r11,GPR12(r1) | |
823df435 | 79 | std r11,_XER(r1) |
82087414 | 80 | std r11,_CTR(r1) |
9994a338 | 81 | std r9,GPR13(r1) |
9994a338 | 82 | mflr r10 |
fd6c40f3 AB |
83 | /* |
84 | * This clears CR0.SO (bit 28), which is the error indication on | |
85 | * return from this system call. | |
86 | */ | |
87 | rldimi r2,r11,28,(63-28) | |
9994a338 | 88 | li r11,0xc01 |
9994a338 PM |
89 | std r10,_LINK(r1) |
90 | std r11,_TRAP(r1) | |
9994a338 | 91 | std r3,ORIG_GPR3(r1) |
fd6c40f3 | 92 | std r2,_CCR(r1) |
9994a338 PM |
93 | ld r2,PACATOC(r13) |
94 | addi r9,r1,STACK_FRAME_OVERHEAD | |
95 | ld r11,exception_marker@toc(r2) | |
96 | std r11,-16(r9) /* "regshere" marker */ | |
cf9efce0 PM |
97 | #if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR) |
98 | BEGIN_FW_FTR_SECTION | |
99 | beq 33f | |
100 | /* if from user, see if there are any DTL entries to process */ | |
101 | ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */ | |
102 | ld r11,PACA_DTL_RIDX(r13) /* get log read index */ | |
103 | ld r10,LPPACA_DTLIDX(r10) /* get log write index */ | |
104 | cmpd cr1,r11,r10 | |
105 | beq+ cr1,33f | |
106 | bl .accumulate_stolen_time | |
107 | REST_GPR(0,r1) | |
108 | REST_4GPRS(3,r1) | |
109 | REST_2GPRS(7,r1) | |
110 | addi r9,r1,STACK_FRAME_OVERHEAD | |
111 | 33: | |
112 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) | |
113 | #endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */ | |
114 | ||
1421ae0b BH |
115 | /* |
116 | * A syscall should always be called with interrupts enabled | |
117 | * so we just unconditionally hard-enable here. When some kind | |
118 | * of irq tracing is used, we additionally check that condition | |
119 | * is correct | |
120 | */ | |
121 | #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG) | |
122 | lbz r10,PACASOFTIRQEN(r13) | |
123 | xori r10,r10,1 | |
124 | 1: tdnei r10,0 | |
125 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING | |
126 | #endif | |
2d27cfd3 | 127 | |
2d27cfd3 BH |
128 | #ifdef CONFIG_PPC_BOOK3E |
129 | wrteei 1 | |
130 | #else | |
1421ae0b | 131 | ld r11,PACAKMSR(r13) |
9994a338 PM |
132 | ori r11,r11,MSR_EE |
133 | mtmsrd r11,1 | |
2d27cfd3 | 134 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 | 135 | |
1421ae0b BH |
136 | /* We do need to set SOFTE in the stack frame or the return |
137 | * from interrupt will be painful | |
138 | */ | |
139 | li r10,1 | |
140 | std r10,SOFTE(r1) | |
141 | ||
9994a338 PM |
142 | #ifdef SHOW_SYSCALLS |
143 | bl .do_show_syscall | |
144 | REST_GPR(0,r1) | |
145 | REST_4GPRS(3,r1) | |
146 | REST_2GPRS(7,r1) | |
147 | addi r9,r1,STACK_FRAME_OVERHEAD | |
148 | #endif | |
9778b696 | 149 | CURRENT_THREAD_INFO(r11, r1) |
9994a338 | 150 | ld r10,TI_FLAGS(r11) |
9994a338 PM |
151 | andi. r11,r10,_TIF_SYSCALL_T_OR_A |
152 | bne- syscall_dotrace | |
d14299de | 153 | .Lsyscall_dotrace_cont: |
9994a338 PM |
154 | cmpldi 0,r0,NR_syscalls |
155 | bge- syscall_enosys | |
156 | ||
157 | system_call: /* label this so stack traces look sane */ | |
158 | /* | |
159 | * Need to vector to 32 Bit or default sys_call_table here, | |
160 | * based on caller's run-mode / personality. | |
161 | */ | |
162 | ld r11,.SYS_CALL_TABLE@toc(2) | |
163 | andi. r10,r10,_TIF_32BIT | |
164 | beq 15f | |
165 | addi r11,r11,8 /* use 32-bit syscall entries */ | |
166 | clrldi r3,r3,32 | |
167 | clrldi r4,r4,32 | |
168 | clrldi r5,r5,32 | |
169 | clrldi r6,r6,32 | |
170 | clrldi r7,r7,32 | |
171 | clrldi r8,r8,32 | |
172 | 15: | |
173 | slwi r0,r0,4 | |
174 | ldx r10,r11,r0 /* Fetch system call handler [ptr] */ | |
175 | mtctr r10 | |
176 | bctrl /* Call handler */ | |
177 | ||
178 | syscall_exit: | |
401d1f02 | 179 | std r3,RESULT(r1) |
9994a338 | 180 | #ifdef SHOW_SYSCALLS |
9994a338 | 181 | bl .do_show_syscall_exit |
401d1f02 | 182 | ld r3,RESULT(r1) |
9994a338 | 183 | #endif |
9778b696 | 184 | CURRENT_THREAD_INFO(r12, r1) |
9994a338 | 185 | |
9994a338 | 186 | ld r8,_MSR(r1) |
2d27cfd3 BH |
187 | #ifdef CONFIG_PPC_BOOK3S |
188 | /* No MSR:RI on BookE */ | |
9994a338 PM |
189 | andi. r10,r8,MSR_RI |
190 | beq- unrecov_restore | |
2d27cfd3 | 191 | #endif |
1421ae0b BH |
192 | /* |
193 | * Disable interrupts so current_thread_info()->flags can't change, | |
2d27cfd3 BH |
194 | * and so that we don't get interrupted after loading SRR0/1. |
195 | */ | |
196 | #ifdef CONFIG_PPC_BOOK3E | |
197 | wrteei 0 | |
198 | #else | |
1421ae0b | 199 | ld r10,PACAKMSR(r13) |
ac1dc365 AB |
200 | /* |
201 | * For performance reasons we clear RI the same time that we | |
202 | * clear EE. We only need to clear RI just before we restore r13 | |
203 | * below, but batching it with EE saves us one expensive mtmsrd call. | |
204 | * We have to be careful to restore RI if we branch anywhere from | |
205 | * here (eg syscall_exit_work). | |
206 | */ | |
207 | li r9,MSR_RI | |
208 | andc r11,r10,r9 | |
209 | mtmsrd r11,1 | |
2d27cfd3 BH |
210 | #endif /* CONFIG_PPC_BOOK3E */ |
211 | ||
9994a338 | 212 | ld r9,TI_FLAGS(r12) |
401d1f02 | 213 | li r11,-_LAST_ERRNO |
1bd79336 | 214 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) |
9994a338 | 215 | bne- syscall_exit_work |
401d1f02 DW |
216 | cmpld r3,r11 |
217 | ld r5,_CCR(r1) | |
218 | bge- syscall_error | |
d14299de | 219 | .Lsyscall_error_cont: |
9994a338 | 220 | ld r7,_NIP(r1) |
f89451fb | 221 | BEGIN_FTR_SECTION |
9994a338 | 222 | stdcx. r0,0,r1 /* to clear the reservation */ |
f89451fb | 223 | END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) |
9994a338 PM |
224 | andi. r6,r8,MSR_PR |
225 | ld r4,_LINK(r1) | |
2d27cfd3 | 226 | |
c6622f63 PM |
227 | beq- 1f |
228 | ACCOUNT_CPU_USER_EXIT(r11, r12) | |
229 | ld r13,GPR13(r1) /* only restore r13 if returning to usermode */ | |
9994a338 | 230 | 1: ld r2,GPR2(r1) |
9994a338 PM |
231 | ld r1,GPR1(r1) |
232 | mtlr r4 | |
233 | mtcr r5 | |
234 | mtspr SPRN_SRR0,r7 | |
235 | mtspr SPRN_SRR1,r8 | |
2d27cfd3 | 236 | RFI |
9994a338 PM |
237 | b . /* prevent speculative execution */ |
238 | ||
401d1f02 | 239 | syscall_error: |
9994a338 | 240 | oris r5,r5,0x1000 /* Set SO bit in CR */ |
401d1f02 | 241 | neg r3,r3 |
9994a338 | 242 | std r5,_CCR(r1) |
d14299de | 243 | b .Lsyscall_error_cont |
401d1f02 | 244 | |
9994a338 PM |
245 | /* Traced system call support */ |
246 | syscall_dotrace: | |
247 | bl .save_nvgprs | |
248 | addi r3,r1,STACK_FRAME_OVERHEAD | |
249 | bl .do_syscall_trace_enter | |
4f72c427 RM |
250 | /* |
251 | * Restore argument registers possibly just changed. | |
252 | * We use the return value of do_syscall_trace_enter | |
253 | * for the call number to look up in the table (r0). | |
254 | */ | |
255 | mr r0,r3 | |
9994a338 PM |
256 | ld r3,GPR3(r1) |
257 | ld r4,GPR4(r1) | |
258 | ld r5,GPR5(r1) | |
259 | ld r6,GPR6(r1) | |
260 | ld r7,GPR7(r1) | |
261 | ld r8,GPR8(r1) | |
262 | addi r9,r1,STACK_FRAME_OVERHEAD | |
9778b696 | 263 | CURRENT_THREAD_INFO(r10, r1) |
9994a338 | 264 | ld r10,TI_FLAGS(r10) |
d14299de | 265 | b .Lsyscall_dotrace_cont |
9994a338 | 266 | |
401d1f02 DW |
267 | syscall_enosys: |
268 | li r3,-ENOSYS | |
269 | b syscall_exit | |
270 | ||
271 | syscall_exit_work: | |
ac1dc365 AB |
272 | #ifdef CONFIG_PPC_BOOK3S |
273 | mtmsrd r10,1 /* Restore RI */ | |
274 | #endif | |
401d1f02 DW |
275 | /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr. |
276 | If TIF_NOERROR is set, just save r3 as it is. */ | |
277 | ||
278 | andi. r0,r9,_TIF_RESTOREALL | |
1bd79336 PM |
279 | beq+ 0f |
280 | REST_NVGPRS(r1) | |
281 | b 2f | |
282 | 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */ | |
401d1f02 DW |
283 | blt+ 1f |
284 | andi. r0,r9,_TIF_NOERROR | |
285 | bne- 1f | |
286 | ld r5,_CCR(r1) | |
287 | neg r3,r3 | |
288 | oris r5,r5,0x1000 /* Set SO bit in CR */ | |
289 | std r5,_CCR(r1) | |
290 | 1: std r3,GPR3(r1) | |
291 | 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK) | |
292 | beq 4f | |
293 | ||
1bd79336 | 294 | /* Clear per-syscall TIF flags if any are set. */ |
401d1f02 DW |
295 | |
296 | li r11,_TIF_PERSYSCALL_MASK | |
297 | addi r12,r12,TI_FLAGS | |
298 | 3: ldarx r10,0,r12 | |
299 | andc r10,r10,r11 | |
300 | stdcx. r10,0,r12 | |
301 | bne- 3b | |
302 | subi r12,r12,TI_FLAGS | |
1bd79336 PM |
303 | |
304 | 4: /* Anything else left to do? */ | |
305 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) | |
401d1f02 DW |
306 | beq .ret_from_except_lite |
307 | ||
308 | /* Re-enable interrupts */ | |
2d27cfd3 BH |
309 | #ifdef CONFIG_PPC_BOOK3E |
310 | wrteei 1 | |
311 | #else | |
1421ae0b | 312 | ld r10,PACAKMSR(r13) |
401d1f02 DW |
313 | ori r10,r10,MSR_EE |
314 | mtmsrd r10,1 | |
2d27cfd3 | 315 | #endif /* CONFIG_PPC_BOOK3E */ |
401d1f02 | 316 | |
1bd79336 | 317 | bl .save_nvgprs |
9994a338 PM |
318 | addi r3,r1,STACK_FRAME_OVERHEAD |
319 | bl .do_syscall_trace_leave | |
1bd79336 | 320 | b .ret_from_except |
9994a338 PM |
321 | |
322 | /* Save non-volatile GPRs, if not already saved. */ | |
323 | _GLOBAL(save_nvgprs) | |
324 | ld r11,_TRAP(r1) | |
325 | andi. r0,r11,1 | |
326 | beqlr- | |
327 | SAVE_NVGPRS(r1) | |
328 | clrrdi r0,r11,1 | |
329 | std r0,_TRAP(r1) | |
330 | blr | |
331 | ||
401d1f02 | 332 | |
9994a338 PM |
333 | /* |
334 | * The sigsuspend and rt_sigsuspend system calls can call do_signal | |
335 | * and thus put the process into the stopped state where we might | |
336 | * want to examine its user state with ptrace. Therefore we need | |
337 | * to save all the nonvolatile registers (r14 - r31) before calling | |
338 | * the C code. Similarly, fork, vfork and clone need the full | |
339 | * register state on the stack so that it can be copied to the child. | |
340 | */ | |
9994a338 PM |
341 | |
342 | _GLOBAL(ppc_fork) | |
343 | bl .save_nvgprs | |
344 | bl .sys_fork | |
345 | b syscall_exit | |
346 | ||
347 | _GLOBAL(ppc_vfork) | |
348 | bl .save_nvgprs | |
349 | bl .sys_vfork | |
350 | b syscall_exit | |
351 | ||
352 | _GLOBAL(ppc_clone) | |
353 | bl .save_nvgprs | |
354 | bl .sys_clone | |
355 | b syscall_exit | |
356 | ||
1bd79336 PM |
357 | _GLOBAL(ppc32_swapcontext) |
358 | bl .save_nvgprs | |
359 | bl .compat_sys_swapcontext | |
360 | b syscall_exit | |
361 | ||
362 | _GLOBAL(ppc64_swapcontext) | |
363 | bl .save_nvgprs | |
364 | bl .sys_swapcontext | |
365 | b syscall_exit | |
366 | ||
9994a338 PM |
367 | _GLOBAL(ret_from_fork) |
368 | bl .schedule_tail | |
369 | REST_NVGPRS(r1) | |
370 | li r3,0 | |
371 | b syscall_exit | |
372 | ||
58254e10 AV |
373 | _GLOBAL(ret_from_kernel_thread) |
374 | bl .schedule_tail | |
375 | REST_NVGPRS(r1) | |
12660b17 LZ |
376 | li r3,0 |
377 | std r3,0(r1) | |
53b50f94 | 378 | ld r14, 0(r14) |
58254e10 AV |
379 | mtlr r14 |
380 | mr r3,r15 | |
381 | blrl | |
382 | li r3,0 | |
be6abfa7 AV |
383 | b syscall_exit |
384 | ||
71433285 AB |
385 | .section ".toc","aw" |
386 | DSCR_DEFAULT: | |
387 | .tc dscr_default[TC],dscr_default | |
388 | ||
389 | .section ".text" | |
390 | ||
9994a338 PM |
391 | /* |
392 | * This routine switches between two different tasks. The process | |
393 | * state of one is saved on its kernel stack. Then the state | |
394 | * of the other is restored from its kernel stack. The memory | |
395 | * management hardware is updated to the second process's state. | |
396 | * Finally, we can return to the second process, via ret_from_except. | |
397 | * On entry, r3 points to the THREAD for the current task, r4 | |
398 | * points to the THREAD for the new task. | |
399 | * | |
400 | * Note: there are two ways to get to the "going out" portion | |
401 | * of this code; either by coming in via the entry (_switch) | |
402 | * or via "fork" which must set up an environment equivalent | |
403 | * to the "_switch" path. If you change this you'll have to change | |
404 | * the fork code also. | |
405 | * | |
406 | * The code which creates the new task context is in 'copy_thread' | |
2ef9481e | 407 | * in arch/powerpc/kernel/process.c |
9994a338 PM |
408 | */ |
409 | .align 7 | |
410 | _GLOBAL(_switch) | |
411 | mflr r0 | |
412 | std r0,16(r1) | |
413 | stdu r1,-SWITCH_FRAME_SIZE(r1) | |
414 | /* r3-r13 are caller saved -- Cort */ | |
415 | SAVE_8GPRS(14, r1) | |
416 | SAVE_10GPRS(22, r1) | |
417 | mflr r20 /* Return to switch caller */ | |
418 | mfmsr r22 | |
419 | li r0, MSR_FP | |
ce48b210 MN |
420 | #ifdef CONFIG_VSX |
421 | BEGIN_FTR_SECTION | |
422 | oris r0,r0,MSR_VSX@h /* Disable VSX */ | |
423 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
424 | #endif /* CONFIG_VSX */ | |
9994a338 PM |
425 | #ifdef CONFIG_ALTIVEC |
426 | BEGIN_FTR_SECTION | |
427 | oris r0,r0,MSR_VEC@h /* Disable altivec */ | |
428 | mfspr r24,SPRN_VRSAVE /* save vrsave register value */ | |
429 | std r24,THREAD_VRSAVE(r3) | |
430 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
431 | #endif /* CONFIG_ALTIVEC */ | |
efcac658 AK |
432 | #ifdef CONFIG_PPC64 |
433 | BEGIN_FTR_SECTION | |
434 | mfspr r25,SPRN_DSCR | |
435 | std r25,THREAD_DSCR(r3) | |
436 | END_FTR_SECTION_IFSET(CPU_FTR_DSCR) | |
437 | #endif | |
9994a338 PM |
438 | and. r0,r0,r22 |
439 | beq+ 1f | |
440 | andc r22,r22,r0 | |
2d27cfd3 | 441 | MTMSRD(r22) |
9994a338 PM |
442 | isync |
443 | 1: std r20,_NIP(r1) | |
444 | mfcr r23 | |
445 | std r23,_CCR(r1) | |
446 | std r1,KSP(r3) /* Set old stack pointer */ | |
447 | ||
448 | #ifdef CONFIG_SMP | |
449 | /* We need a sync somewhere here to make sure that if the | |
450 | * previous task gets rescheduled on another CPU, it sees all | |
451 | * stores it has performed on this one. | |
452 | */ | |
453 | sync | |
454 | #endif /* CONFIG_SMP */ | |
455 | ||
f89451fb AB |
456 | /* |
457 | * If we optimise away the clear of the reservation in system | |
458 | * calls because we know the CPU tracks the address of the | |
459 | * reservation, then we need to clear it here to cover the | |
460 | * case that the kernel context switch path has no larx | |
461 | * instructions. | |
462 | */ | |
463 | BEGIN_FTR_SECTION | |
464 | ldarx r6,0,r1 | |
465 | END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS) | |
466 | ||
9994a338 PM |
467 | addi r6,r4,-THREAD /* Convert THREAD to 'current' */ |
468 | std r6,PACACURRENT(r13) /* Set new 'current' */ | |
469 | ||
470 | ld r8,KSP(r4) /* new stack pointer */ | |
2d27cfd3 | 471 | #ifdef CONFIG_PPC_BOOK3S |
1189be65 | 472 | BEGIN_FTR_SECTION |
c230328d | 473 | BEGIN_FTR_SECTION_NESTED(95) |
9994a338 PM |
474 | clrrdi r6,r8,28 /* get its ESID */ |
475 | clrrdi r9,r1,28 /* get current sp ESID */ | |
c230328d | 476 | FTR_SECTION_ELSE_NESTED(95) |
1189be65 PM |
477 | clrrdi r6,r8,40 /* get its 1T ESID */ |
478 | clrrdi r9,r1,40 /* get current sp 1T ESID */ | |
44ae3ab3 | 479 | ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95) |
c230328d ME |
480 | FTR_SECTION_ELSE |
481 | b 2f | |
44ae3ab3 | 482 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB) |
9994a338 PM |
483 | clrldi. r0,r6,2 /* is new ESID c00000000? */ |
484 | cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ | |
485 | cror eq,4*cr1+eq,eq | |
486 | beq 2f /* if yes, don't slbie it */ | |
487 | ||
488 | /* Bolt in the new stack SLB entry */ | |
489 | ld r7,KSP_VSID(r4) /* Get new stack's VSID */ | |
490 | oris r0,r6,(SLB_ESID_V)@h | |
491 | ori r0,r0,(SLB_NUM_BOLTED-1)@l | |
1189be65 PM |
492 | BEGIN_FTR_SECTION |
493 | li r9,MMU_SEGSIZE_1T /* insert B field */ | |
494 | oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h | |
495 | rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0 | |
44ae3ab3 | 496 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) |
2f6093c8 | 497 | |
00efee7d MN |
498 | /* Update the last bolted SLB. No write barriers are needed |
499 | * here, provided we only update the current CPU's SLB shadow | |
500 | * buffer. | |
501 | */ | |
2f6093c8 | 502 | ld r9,PACA_SLBSHADOWPTR(r13) |
11a27ad7 MN |
503 | li r12,0 |
504 | std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ | |
505 | std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */ | |
506 | std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */ | |
2f6093c8 | 507 | |
44ae3ab3 | 508 | /* No need to check for MMU_FTR_NO_SLBIE_B here, since when |
f66bce5e OJ |
509 | * we have 1TB segments, the only CPUs known to have the errata |
510 | * only support less than 1TB of system memory and we'll never | |
511 | * actually hit this code path. | |
512 | */ | |
513 | ||
9994a338 PM |
514 | slbie r6 |
515 | slbie r6 /* Workaround POWER5 < DD2.1 issue */ | |
516 | slbmte r7,r0 | |
517 | isync | |
9994a338 | 518 | 2: |
2d27cfd3 BH |
519 | #endif /* !CONFIG_PPC_BOOK3S */ |
520 | ||
9778b696 | 521 | CURRENT_THREAD_INFO(r7, r8) /* base of new stack */ |
9994a338 PM |
522 | /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE |
523 | because we don't need to leave the 288-byte ABI gap at the | |
524 | top of the kernel stack. */ | |
525 | addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE | |
526 | ||
527 | mr r1,r8 /* start using new stack pointer */ | |
528 | std r7,PACAKSAVE(r13) | |
529 | ||
9994a338 PM |
530 | #ifdef CONFIG_ALTIVEC |
531 | BEGIN_FTR_SECTION | |
532 | ld r0,THREAD_VRSAVE(r4) | |
533 | mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ | |
534 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
535 | #endif /* CONFIG_ALTIVEC */ | |
efcac658 AK |
536 | #ifdef CONFIG_PPC64 |
537 | BEGIN_FTR_SECTION | |
71433285 AB |
538 | lwz r6,THREAD_DSCR_INHERIT(r4) |
539 | ld r7,DSCR_DEFAULT@toc(2) | |
efcac658 | 540 | ld r0,THREAD_DSCR(r4) |
71433285 AB |
541 | cmpwi r6,0 |
542 | bne 1f | |
543 | ld r0,0(r7) | |
544 | 1: cmpd r0,r25 | |
545 | beq 2f | |
efcac658 | 546 | mtspr SPRN_DSCR,r0 |
71433285 | 547 | 2: |
efcac658 AK |
548 | END_FTR_SECTION_IFSET(CPU_FTR_DSCR) |
549 | #endif | |
9994a338 | 550 | |
71433285 AB |
551 | ld r6,_CCR(r1) |
552 | mtcrf 0xFF,r6 | |
553 | ||
9994a338 PM |
554 | /* r3-r13 are destroyed -- Cort */ |
555 | REST_8GPRS(14, r1) | |
556 | REST_10GPRS(22, r1) | |
557 | ||
558 | /* convert old thread to its task_struct for return value */ | |
559 | addi r3,r3,-THREAD | |
560 | ld r7,_NIP(r1) /* Return to _switch caller in new task */ | |
561 | mtlr r7 | |
562 | addi r1,r1,SWITCH_FRAME_SIZE | |
563 | blr | |
564 | ||
565 | .align 7 | |
566 | _GLOBAL(ret_from_except) | |
567 | ld r11,_TRAP(r1) | |
568 | andi. r0,r11,1 | |
569 | bne .ret_from_except_lite | |
570 | REST_NVGPRS(r1) | |
571 | ||
572 | _GLOBAL(ret_from_except_lite) | |
573 | /* | |
574 | * Disable interrupts so that current_thread_info()->flags | |
575 | * can't change between when we test it and when we return | |
576 | * from the interrupt. | |
577 | */ | |
2d27cfd3 BH |
578 | #ifdef CONFIG_PPC_BOOK3E |
579 | wrteei 0 | |
580 | #else | |
d9ada91a BH |
581 | ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ |
582 | mtmsrd r10,1 /* Update machine state */ | |
2d27cfd3 | 583 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 | 584 | |
9778b696 | 585 | CURRENT_THREAD_INFO(r9, r1) |
9994a338 PM |
586 | ld r3,_MSR(r1) |
587 | ld r4,TI_FLAGS(r9) | |
9994a338 | 588 | andi. r3,r3,MSR_PR |
c58ce2b1 | 589 | beq resume_kernel |
9994a338 PM |
590 | |
591 | /* Check current_thread_info()->flags */ | |
c58ce2b1 TC |
592 | andi. r0,r4,_TIF_USER_WORK_MASK |
593 | beq restore | |
594 | ||
595 | andi. r0,r4,_TIF_NEED_RESCHED | |
596 | beq 1f | |
597 | bl .restore_interrupts | |
598 | bl .schedule | |
599 | b .ret_from_except_lite | |
600 | ||
601 | 1: bl .save_nvgprs | |
602 | bl .restore_interrupts | |
603 | addi r3,r1,STACK_FRAME_OVERHEAD | |
604 | bl .do_notify_resume | |
605 | b .ret_from_except | |
606 | ||
607 | resume_kernel: | |
a9c4e541 TC |
608 | /* check current_thread_info, _TIF_EMULATE_STACK_STORE */ |
609 | CURRENT_THREAD_INFO(r9, r1) | |
610 | ld r8,TI_FLAGS(r9) | |
611 | andis. r8,r8,_TIF_EMULATE_STACK_STORE@h | |
612 | beq+ 1f | |
613 | ||
614 | addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */ | |
615 | ||
616 | lwz r3,GPR1(r1) | |
617 | subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */ | |
618 | mr r4,r1 /* src: current exception frame */ | |
619 | mr r1,r3 /* Reroute the trampoline frame to r1 */ | |
620 | ||
621 | /* Copy from the original to the trampoline. */ | |
622 | li r5,INT_FRAME_SIZE/8 /* size: INT_FRAME_SIZE */ | |
623 | li r6,0 /* start offset: 0 */ | |
624 | mtctr r5 | |
625 | 2: ldx r0,r6,r4 | |
626 | stdx r0,r6,r3 | |
627 | addi r6,r6,8 | |
628 | bdnz 2b | |
629 | ||
630 | /* Do real store operation to complete stwu */ | |
631 | lwz r5,GPR1(r1) | |
632 | std r8,0(r5) | |
633 | ||
634 | /* Clear _TIF_EMULATE_STACK_STORE flag */ | |
635 | lis r11,_TIF_EMULATE_STACK_STORE@h | |
636 | addi r5,r9,TI_FLAGS | |
637 | ldarx r4,0,r5 | |
638 | andc r4,r4,r11 | |
639 | stdcx. r4,0,r5 | |
640 | bne- 0b | |
641 | 1: | |
642 | ||
c58ce2b1 TC |
643 | #ifdef CONFIG_PREEMPT |
644 | /* Check if we need to preempt */ | |
645 | andi. r0,r4,_TIF_NEED_RESCHED | |
646 | beq+ restore | |
647 | /* Check that preempt_count() == 0 and interrupts are enabled */ | |
648 | lwz r8,TI_PREEMPT(r9) | |
649 | cmpwi cr1,r8,0 | |
650 | ld r0,SOFTE(r1) | |
651 | cmpdi r0,0 | |
652 | crandc eq,cr1*4+eq,eq | |
653 | bne restore | |
654 | ||
655 | /* | |
656 | * Here we are preempting the current task. We want to make | |
657 | * sure we are soft-disabled first | |
658 | */ | |
659 | SOFT_DISABLE_INTS(r3,r4) | |
660 | 1: bl .preempt_schedule_irq | |
661 | ||
662 | /* Re-test flags and eventually loop */ | |
9778b696 | 663 | CURRENT_THREAD_INFO(r9, r1) |
9994a338 | 664 | ld r4,TI_FLAGS(r9) |
c58ce2b1 TC |
665 | andi. r0,r4,_TIF_NEED_RESCHED |
666 | bne 1b | |
667 | #endif /* CONFIG_PREEMPT */ | |
9994a338 | 668 | |
7230c564 BH |
669 | .globl fast_exc_return_irq |
670 | fast_exc_return_irq: | |
9994a338 | 671 | restore: |
7230c564 | 672 | /* |
7c0482e3 BH |
673 | * This is the main kernel exit path. First we check if we |
674 | * are about to re-enable interrupts | |
7230c564 | 675 | */ |
01f3880d | 676 | ld r5,SOFTE(r1) |
7230c564 | 677 | lbz r6,PACASOFTIRQEN(r13) |
7c0482e3 BH |
678 | cmpwi cr0,r5,0 |
679 | beq restore_irq_off | |
7230c564 | 680 | |
7c0482e3 BH |
681 | /* We are enabling, were we already enabled ? Yes, just return */ |
682 | cmpwi cr0,r6,1 | |
683 | beq cr0,do_restore | |
9994a338 | 684 | |
7c0482e3 | 685 | /* |
7230c564 BH |
686 | * We are about to soft-enable interrupts (we are hard disabled |
687 | * at this point). We check if there's anything that needs to | |
688 | * be replayed first. | |
689 | */ | |
690 | lbz r0,PACAIRQHAPPENED(r13) | |
691 | cmpwi cr0,r0,0 | |
692 | bne- restore_check_irq_replay | |
e56a6e20 | 693 | |
7230c564 BH |
694 | /* |
695 | * Get here when nothing happened while soft-disabled, just | |
696 | * soft-enable and move-on. We will hard-enable as a side | |
697 | * effect of rfi | |
698 | */ | |
699 | restore_no_replay: | |
700 | TRACE_ENABLE_INTS | |
701 | li r0,1 | |
702 | stb r0,PACASOFTIRQEN(r13); | |
703 | ||
704 | /* | |
705 | * Final return path. BookE is handled in a different file | |
706 | */ | |
7c0482e3 | 707 | do_restore: |
2d27cfd3 BH |
708 | #ifdef CONFIG_PPC_BOOK3E |
709 | b .exception_return_book3e | |
710 | #else | |
7230c564 BH |
711 | /* |
712 | * Clear the reservation. If we know the CPU tracks the address of | |
713 | * the reservation then we can potentially save some cycles and use | |
714 | * a larx. On POWER6 and POWER7 this is significantly faster. | |
715 | */ | |
716 | BEGIN_FTR_SECTION | |
717 | stdcx. r0,0,r1 /* to clear the reservation */ | |
718 | FTR_SECTION_ELSE | |
719 | ldarx r4,0,r1 | |
720 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) | |
721 | ||
722 | /* | |
723 | * Some code path such as load_up_fpu or altivec return directly | |
724 | * here. They run entirely hard disabled and do not alter the | |
725 | * interrupt state. They also don't use lwarx/stwcx. and thus | |
726 | * are known not to leave dangling reservations. | |
727 | */ | |
728 | .globl fast_exception_return | |
729 | fast_exception_return: | |
730 | ld r3,_MSR(r1) | |
e56a6e20 PM |
731 | ld r4,_CTR(r1) |
732 | ld r0,_LINK(r1) | |
733 | mtctr r4 | |
734 | mtlr r0 | |
735 | ld r4,_XER(r1) | |
736 | mtspr SPRN_XER,r4 | |
737 | ||
738 | REST_8GPRS(5, r1) | |
739 | ||
9994a338 PM |
740 | andi. r0,r3,MSR_RI |
741 | beq- unrecov_restore | |
742 | ||
e56a6e20 PM |
743 | /* |
744 | * Clear RI before restoring r13. If we are returning to | |
745 | * userspace and we take an exception after restoring r13, | |
746 | * we end up corrupting the userspace r13 value. | |
747 | */ | |
d9ada91a BH |
748 | ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */ |
749 | andc r4,r4,r0 /* r0 contains MSR_RI here */ | |
e56a6e20 | 750 | mtmsrd r4,1 |
9994a338 PM |
751 | |
752 | /* | |
753 | * r13 is our per cpu area, only restore it if we are returning to | |
7230c564 BH |
754 | * userspace the value stored in the stack frame may belong to |
755 | * another CPU. | |
9994a338 | 756 | */ |
e56a6e20 | 757 | andi. r0,r3,MSR_PR |
9994a338 | 758 | beq 1f |
e56a6e20 | 759 | ACCOUNT_CPU_USER_EXIT(r2, r4) |
9994a338 PM |
760 | REST_GPR(13, r1) |
761 | 1: | |
e56a6e20 | 762 | mtspr SPRN_SRR1,r3 |
9994a338 PM |
763 | |
764 | ld r2,_CCR(r1) | |
765 | mtcrf 0xFF,r2 | |
766 | ld r2,_NIP(r1) | |
767 | mtspr SPRN_SRR0,r2 | |
768 | ||
769 | ld r0,GPR0(r1) | |
770 | ld r2,GPR2(r1) | |
771 | ld r3,GPR3(r1) | |
772 | ld r4,GPR4(r1) | |
773 | ld r1,GPR1(r1) | |
774 | ||
775 | rfid | |
776 | b . /* prevent speculative execution */ | |
777 | ||
2d27cfd3 BH |
778 | #endif /* CONFIG_PPC_BOOK3E */ |
779 | ||
7c0482e3 BH |
780 | /* |
781 | * We are returning to a context with interrupts soft disabled. | |
782 | * | |
783 | * However, we may also about to hard enable, so we need to | |
784 | * make sure that in this case, we also clear PACA_IRQ_HARD_DIS | |
785 | * or that bit can get out of sync and bad things will happen | |
786 | */ | |
787 | restore_irq_off: | |
788 | ld r3,_MSR(r1) | |
789 | lbz r7,PACAIRQHAPPENED(r13) | |
790 | andi. r0,r3,MSR_EE | |
791 | beq 1f | |
792 | rlwinm r7,r7,0,~PACA_IRQ_HARD_DIS | |
793 | stb r7,PACAIRQHAPPENED(r13) | |
794 | 1: li r0,0 | |
795 | stb r0,PACASOFTIRQEN(r13); | |
796 | TRACE_DISABLE_INTS | |
797 | b do_restore | |
798 | ||
7230c564 BH |
799 | /* |
800 | * Something did happen, check if a re-emit is needed | |
801 | * (this also clears paca->irq_happened) | |
802 | */ | |
803 | restore_check_irq_replay: | |
804 | /* XXX: We could implement a fast path here where we check | |
805 | * for irq_happened being just 0x01, in which case we can | |
806 | * clear it and return. That means that we would potentially | |
807 | * miss a decrementer having wrapped all the way around. | |
808 | * | |
809 | * Still, this might be useful for things like hash_page | |
810 | */ | |
811 | bl .__check_irq_replay | |
812 | cmpwi cr0,r3,0 | |
813 | beq restore_no_replay | |
814 | ||
815 | /* | |
816 | * We need to re-emit an interrupt. We do so by re-using our | |
817 | * existing exception frame. We first change the trap value, | |
818 | * but we need to ensure we preserve the low nibble of it | |
819 | */ | |
820 | ld r4,_TRAP(r1) | |
821 | clrldi r4,r4,60 | |
822 | or r4,r4,r3 | |
823 | std r4,_TRAP(r1) | |
824 | ||
825 | /* | |
826 | * Then find the right handler and call it. Interrupts are | |
827 | * still soft-disabled and we keep them that way. | |
828 | */ | |
829 | cmpwi cr0,r3,0x500 | |
830 | bne 1f | |
831 | addi r3,r1,STACK_FRAME_OVERHEAD; | |
832 | bl .do_IRQ | |
833 | b .ret_from_except | |
834 | 1: cmpwi cr0,r3,0x900 | |
835 | bne 1f | |
836 | addi r3,r1,STACK_FRAME_OVERHEAD; | |
837 | bl .timer_interrupt | |
838 | b .ret_from_except | |
839 | #ifdef CONFIG_PPC_BOOK3E | |
840 | 1: cmpwi cr0,r3,0x280 | |
841 | bne 1f | |
842 | addi r3,r1,STACK_FRAME_OVERHEAD; | |
843 | bl .doorbell_exception | |
844 | b .ret_from_except | |
845 | #endif /* CONFIG_PPC_BOOK3E */ | |
846 | 1: b .ret_from_except /* What else to do here ? */ | |
847 | ||
9994a338 PM |
848 | unrecov_restore: |
849 | addi r3,r1,STACK_FRAME_OVERHEAD | |
850 | bl .unrecoverable_exception | |
851 | b unrecov_restore | |
852 | ||
853 | #ifdef CONFIG_PPC_RTAS | |
854 | /* | |
855 | * On CHRP, the Run-Time Abstraction Services (RTAS) have to be | |
856 | * called with the MMU off. | |
857 | * | |
858 | * In addition, we need to be in 32b mode, at least for now. | |
859 | * | |
860 | * Note: r3 is an input parameter to rtas, so don't trash it... | |
861 | */ | |
862 | _GLOBAL(enter_rtas) | |
863 | mflr r0 | |
864 | std r0,16(r1) | |
865 | stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */ | |
866 | ||
867 | /* Because RTAS is running in 32b mode, it clobbers the high order half | |
868 | * of all registers that it saves. We therefore save those registers | |
869 | * RTAS might touch to the stack. (r0, r3-r13 are caller saved) | |
870 | */ | |
871 | SAVE_GPR(2, r1) /* Save the TOC */ | |
872 | SAVE_GPR(13, r1) /* Save paca */ | |
873 | SAVE_8GPRS(14, r1) /* Save the non-volatiles */ | |
874 | SAVE_10GPRS(22, r1) /* ditto */ | |
875 | ||
876 | mfcr r4 | |
877 | std r4,_CCR(r1) | |
878 | mfctr r5 | |
879 | std r5,_CTR(r1) | |
880 | mfspr r6,SPRN_XER | |
881 | std r6,_XER(r1) | |
882 | mfdar r7 | |
883 | std r7,_DAR(r1) | |
884 | mfdsisr r8 | |
885 | std r8,_DSISR(r1) | |
9994a338 | 886 | |
9fe901d1 MK |
887 | /* Temporary workaround to clear CR until RTAS can be modified to |
888 | * ignore all bits. | |
889 | */ | |
890 | li r0,0 | |
891 | mtcr r0 | |
892 | ||
007d88d0 | 893 | #ifdef CONFIG_BUG |
9994a338 PM |
894 | /* There is no way it is acceptable to get here with interrupts enabled, |
895 | * check it with the asm equivalent of WARN_ON | |
896 | */ | |
d04c56f7 | 897 | lbz r0,PACASOFTIRQEN(r13) |
9994a338 | 898 | 1: tdnei r0,0 |
007d88d0 DW |
899 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING |
900 | #endif | |
901 | ||
d04c56f7 PM |
902 | /* Hard-disable interrupts */ |
903 | mfmsr r6 | |
904 | rldicl r7,r6,48,1 | |
905 | rotldi r7,r7,16 | |
906 | mtmsrd r7,1 | |
907 | ||
9994a338 PM |
908 | /* Unfortunately, the stack pointer and the MSR are also clobbered, |
909 | * so they are saved in the PACA which allows us to restore | |
910 | * our original state after RTAS returns. | |
911 | */ | |
912 | std r1,PACAR1(r13) | |
913 | std r6,PACASAVEDMSR(r13) | |
914 | ||
915 | /* Setup our real return addr */ | |
e58c3495 DG |
916 | LOAD_REG_ADDR(r4,.rtas_return_loc) |
917 | clrldi r4,r4,2 /* convert to realmode address */ | |
9994a338 PM |
918 | mtlr r4 |
919 | ||
920 | li r0,0 | |
921 | ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI | |
922 | andc r0,r6,r0 | |
923 | ||
924 | li r9,1 | |
925 | rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) | |
44c9f3cc | 926 | ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI |
9994a338 | 927 | andc r6,r0,r9 |
9994a338 PM |
928 | sync /* disable interrupts so SRR0/1 */ |
929 | mtmsrd r0 /* don't get trashed */ | |
930 | ||
e58c3495 | 931 | LOAD_REG_ADDR(r4, rtas) |
9994a338 PM |
932 | ld r5,RTASENTRY(r4) /* get the rtas->entry value */ |
933 | ld r4,RTASBASE(r4) /* get the rtas->base value */ | |
934 | ||
935 | mtspr SPRN_SRR0,r5 | |
936 | mtspr SPRN_SRR1,r6 | |
937 | rfid | |
938 | b . /* prevent speculative execution */ | |
939 | ||
940 | _STATIC(rtas_return_loc) | |
941 | /* relocation is off at this point */ | |
2dd60d79 | 942 | GET_PACA(r4) |
e58c3495 | 943 | clrldi r4,r4,2 /* convert to realmode address */ |
9994a338 | 944 | |
e31aa453 PM |
945 | bcl 20,31,$+4 |
946 | 0: mflr r3 | |
947 | ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */ | |
948 | ||
9994a338 PM |
949 | mfmsr r6 |
950 | li r0,MSR_RI | |
951 | andc r6,r6,r0 | |
952 | sync | |
953 | mtmsrd r6 | |
954 | ||
955 | ld r1,PACAR1(r4) /* Restore our SP */ | |
9994a338 PM |
956 | ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ |
957 | ||
958 | mtspr SPRN_SRR0,r3 | |
959 | mtspr SPRN_SRR1,r4 | |
960 | rfid | |
961 | b . /* prevent speculative execution */ | |
962 | ||
e31aa453 PM |
963 | .align 3 |
964 | 1: .llong .rtas_restore_regs | |
965 | ||
9994a338 PM |
966 | _STATIC(rtas_restore_regs) |
967 | /* relocation is on at this point */ | |
968 | REST_GPR(2, r1) /* Restore the TOC */ | |
969 | REST_GPR(13, r1) /* Restore paca */ | |
970 | REST_8GPRS(14, r1) /* Restore the non-volatiles */ | |
971 | REST_10GPRS(22, r1) /* ditto */ | |
972 | ||
2dd60d79 | 973 | GET_PACA(r13) |
9994a338 PM |
974 | |
975 | ld r4,_CCR(r1) | |
976 | mtcr r4 | |
977 | ld r5,_CTR(r1) | |
978 | mtctr r5 | |
979 | ld r6,_XER(r1) | |
980 | mtspr SPRN_XER,r6 | |
981 | ld r7,_DAR(r1) | |
982 | mtdar r7 | |
983 | ld r8,_DSISR(r1) | |
984 | mtdsisr r8 | |
9994a338 PM |
985 | |
986 | addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */ | |
987 | ld r0,16(r1) /* get return address */ | |
988 | ||
989 | mtlr r0 | |
990 | blr /* return to caller */ | |
991 | ||
992 | #endif /* CONFIG_PPC_RTAS */ | |
993 | ||
9994a338 PM |
994 | _GLOBAL(enter_prom) |
995 | mflr r0 | |
996 | std r0,16(r1) | |
997 | stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */ | |
998 | ||
999 | /* Because PROM is running in 32b mode, it clobbers the high order half | |
1000 | * of all registers that it saves. We therefore save those registers | |
1001 | * PROM might touch to the stack. (r0, r3-r13 are caller saved) | |
1002 | */ | |
6c171994 | 1003 | SAVE_GPR(2, r1) |
9994a338 PM |
1004 | SAVE_GPR(13, r1) |
1005 | SAVE_8GPRS(14, r1) | |
1006 | SAVE_10GPRS(22, r1) | |
6c171994 | 1007 | mfcr r10 |
9994a338 | 1008 | mfmsr r11 |
6c171994 | 1009 | std r10,_CCR(r1) |
9994a338 PM |
1010 | std r11,_MSR(r1) |
1011 | ||
1012 | /* Get the PROM entrypoint */ | |
6c171994 | 1013 | mtlr r4 |
9994a338 PM |
1014 | |
1015 | /* Switch MSR to 32 bits mode | |
1016 | */ | |
2d27cfd3 BH |
1017 | #ifdef CONFIG_PPC_BOOK3E |
1018 | rlwinm r11,r11,0,1,31 | |
1019 | mtmsr r11 | |
1020 | #else /* CONFIG_PPC_BOOK3E */ | |
9994a338 PM |
1021 | mfmsr r11 |
1022 | li r12,1 | |
1023 | rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) | |
1024 | andc r11,r11,r12 | |
1025 | li r12,1 | |
1026 | rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) | |
1027 | andc r11,r11,r12 | |
1028 | mtmsrd r11 | |
2d27cfd3 | 1029 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
1030 | isync |
1031 | ||
6c171994 | 1032 | /* Enter PROM here... */ |
9994a338 PM |
1033 | blrl |
1034 | ||
1035 | /* Just make sure that r1 top 32 bits didn't get | |
1036 | * corrupt by OF | |
1037 | */ | |
1038 | rldicl r1,r1,0,32 | |
1039 | ||
1040 | /* Restore the MSR (back to 64 bits) */ | |
1041 | ld r0,_MSR(r1) | |
6c171994 | 1042 | MTMSRD(r0) |
9994a338 PM |
1043 | isync |
1044 | ||
1045 | /* Restore other registers */ | |
1046 | REST_GPR(2, r1) | |
1047 | REST_GPR(13, r1) | |
1048 | REST_8GPRS(14, r1) | |
1049 | REST_10GPRS(22, r1) | |
1050 | ld r4,_CCR(r1) | |
1051 | mtcr r4 | |
9994a338 PM |
1052 | |
1053 | addi r1,r1,PROM_FRAME_SIZE | |
1054 | ld r0,16(r1) | |
1055 | mtlr r0 | |
1056 | blr | |
4e491d14 | 1057 | |
606576ce | 1058 | #ifdef CONFIG_FUNCTION_TRACER |
4e491d14 SR |
1059 | #ifdef CONFIG_DYNAMIC_FTRACE |
1060 | _GLOBAL(mcount) | |
1061 | _GLOBAL(_mcount) | |
4e491d14 SR |
1062 | blr |
1063 | ||
1064 | _GLOBAL(ftrace_caller) | |
1065 | /* Taken from output of objdump from lib64/glibc */ | |
1066 | mflr r3 | |
1067 | ld r11, 0(r1) | |
1068 | stdu r1, -112(r1) | |
1069 | std r3, 128(r1) | |
1070 | ld r4, 16(r11) | |
395a59d0 | 1071 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
1072 | .globl ftrace_call |
1073 | ftrace_call: | |
1074 | bl ftrace_stub | |
1075 | nop | |
46542888 SR |
1076 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1077 | .globl ftrace_graph_call | |
1078 | ftrace_graph_call: | |
1079 | b ftrace_graph_stub | |
1080 | _GLOBAL(ftrace_graph_stub) | |
1081 | #endif | |
4e491d14 SR |
1082 | ld r0, 128(r1) |
1083 | mtlr r0 | |
1084 | addi r1, r1, 112 | |
1085 | _GLOBAL(ftrace_stub) | |
1086 | blr | |
1087 | #else | |
1088 | _GLOBAL(mcount) | |
1089 | blr | |
1090 | ||
1091 | _GLOBAL(_mcount) | |
1092 | /* Taken from output of objdump from lib64/glibc */ | |
1093 | mflr r3 | |
1094 | ld r11, 0(r1) | |
1095 | stdu r1, -112(r1) | |
1096 | std r3, 128(r1) | |
1097 | ld r4, 16(r11) | |
1098 | ||
395a59d0 | 1099 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
1100 | LOAD_REG_ADDR(r5,ftrace_trace_function) |
1101 | ld r5,0(r5) | |
1102 | ld r5,0(r5) | |
1103 | mtctr r5 | |
1104 | bctrl | |
4e491d14 | 1105 | nop |
6794c782 SR |
1106 | |
1107 | ||
1108 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
1109 | b ftrace_graph_caller | |
1110 | #endif | |
4e491d14 SR |
1111 | ld r0, 128(r1) |
1112 | mtlr r0 | |
1113 | addi r1, r1, 112 | |
1114 | _GLOBAL(ftrace_stub) | |
1115 | blr | |
1116 | ||
6794c782 SR |
1117 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
1118 | ||
1119 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
46542888 | 1120 | _GLOBAL(ftrace_graph_caller) |
6794c782 SR |
1121 | /* load r4 with local address */ |
1122 | ld r4, 128(r1) | |
1123 | subi r4, r4, MCOUNT_INSN_SIZE | |
1124 | ||
1125 | /* get the parent address */ | |
1126 | ld r11, 112(r1) | |
1127 | addi r3, r11, 16 | |
1128 | ||
1129 | bl .prepare_ftrace_return | |
1130 | nop | |
1131 | ||
1132 | ld r0, 128(r1) | |
1133 | mtlr r0 | |
1134 | addi r1, r1, 112 | |
1135 | blr | |
1136 | ||
1137 | _GLOBAL(return_to_handler) | |
bb725340 SR |
1138 | /* need to save return values */ |
1139 | std r4, -24(r1) | |
1140 | std r3, -16(r1) | |
1141 | std r31, -8(r1) | |
1142 | mr r31, r1 | |
1143 | stdu r1, -112(r1) | |
1144 | ||
1145 | bl .ftrace_return_to_handler | |
1146 | nop | |
1147 | ||
1148 | /* return value has real return address */ | |
1149 | mtlr r3 | |
1150 | ||
1151 | ld r1, 0(r1) | |
1152 | ld r4, -24(r1) | |
1153 | ld r3, -16(r1) | |
1154 | ld r31, -8(r1) | |
1155 | ||
1156 | /* Jump back to real return address */ | |
1157 | blr | |
1158 | ||
1159 | _GLOBAL(mod_return_to_handler) | |
6794c782 SR |
1160 | /* need to save return values */ |
1161 | std r4, -32(r1) | |
1162 | std r3, -24(r1) | |
1163 | /* save TOC */ | |
1164 | std r2, -16(r1) | |
1165 | std r31, -8(r1) | |
1166 | mr r31, r1 | |
1167 | stdu r1, -112(r1) | |
1168 | ||
bb725340 SR |
1169 | /* |
1170 | * We are in a module using the module's TOC. | |
1171 | * Switch to our TOC to run inside the core kernel. | |
1172 | */ | |
be10ab10 | 1173 | ld r2, PACATOC(r13) |
6794c782 SR |
1174 | |
1175 | bl .ftrace_return_to_handler | |
1176 | nop | |
1177 | ||
1178 | /* return value has real return address */ | |
1179 | mtlr r3 | |
1180 | ||
1181 | ld r1, 0(r1) | |
1182 | ld r4, -32(r1) | |
1183 | ld r3, -24(r1) | |
1184 | ld r2, -16(r1) | |
1185 | ld r31, -8(r1) | |
1186 | ||
1187 | /* Jump back to real return address */ | |
1188 | blr | |
1189 | #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ | |
1190 | #endif /* CONFIG_FUNCTION_TRACER */ |