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9994a338 | 1 | /* |
9994a338 PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
6 | * Adapted for Power Macintosh by Paul Mackerras. | |
7 | * Low-level exception handlers and MMU support | |
8 | * rewritten by Paul Mackerras. | |
9 | * Copyright (C) 1996 Paul Mackerras. | |
10 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
11 | * | |
12 | * This file contains the system call entry code, context switch | |
13 | * code, and exception/interrupt return code for PowerPC. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
9994a338 PM |
21 | #include <linux/errno.h> |
22 | #include <asm/unistd.h> | |
23 | #include <asm/processor.h> | |
24 | #include <asm/page.h> | |
25 | #include <asm/mmu.h> | |
26 | #include <asm/thread_info.h> | |
27 | #include <asm/ppc_asm.h> | |
28 | #include <asm/asm-offsets.h> | |
29 | #include <asm/cputable.h> | |
3f639ee8 | 30 | #include <asm/firmware.h> |
007d88d0 | 31 | #include <asm/bug.h> |
ec2b36b9 | 32 | #include <asm/ptrace.h> |
945feb17 | 33 | #include <asm/irqflags.h> |
395a59d0 | 34 | #include <asm/ftrace.h> |
9994a338 PM |
35 | |
36 | /* | |
37 | * System calls. | |
38 | */ | |
39 | .section ".toc","aw" | |
40 | .SYS_CALL_TABLE: | |
41 | .tc .sys_call_table[TC],.sys_call_table | |
42 | ||
43 | /* This value is used to mark exception frames on the stack. */ | |
44 | exception_marker: | |
ec2b36b9 | 45 | .tc ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER |
9994a338 PM |
46 | |
47 | .section ".text" | |
48 | .align 7 | |
49 | ||
50 | #undef SHOW_SYSCALLS | |
51 | ||
52 | .globl system_call_common | |
53 | system_call_common: | |
54 | andi. r10,r12,MSR_PR | |
55 | mr r10,r1 | |
56 | addi r1,r1,-INT_FRAME_SIZE | |
57 | beq- 1f | |
58 | ld r1,PACAKSAVE(r13) | |
59 | 1: std r10,0(r1) | |
60 | std r11,_NIP(r1) | |
61 | std r12,_MSR(r1) | |
62 | std r0,GPR0(r1) | |
63 | std r10,GPR1(r1) | |
c6622f63 | 64 | ACCOUNT_CPU_USER_ENTRY(r10, r11) |
ab598b66 PM |
65 | /* |
66 | * This "crclr so" clears CR0.SO, which is the error indication on | |
67 | * return from this system call. There must be no cmp instruction | |
68 | * between it and the "mfcr r9" below, otherwise if XER.SO is set, | |
69 | * CR0.SO will get set, causing all system calls to appear to fail. | |
70 | */ | |
71 | crclr so | |
9994a338 PM |
72 | std r2,GPR2(r1) |
73 | std r3,GPR3(r1) | |
74 | std r4,GPR4(r1) | |
75 | std r5,GPR5(r1) | |
76 | std r6,GPR6(r1) | |
77 | std r7,GPR7(r1) | |
78 | std r8,GPR8(r1) | |
79 | li r11,0 | |
80 | std r11,GPR9(r1) | |
81 | std r11,GPR10(r1) | |
82 | std r11,GPR11(r1) | |
83 | std r11,GPR12(r1) | |
84 | std r9,GPR13(r1) | |
9994a338 PM |
85 | mfcr r9 |
86 | mflr r10 | |
87 | li r11,0xc01 | |
88 | std r9,_CCR(r1) | |
89 | std r10,_LINK(r1) | |
90 | std r11,_TRAP(r1) | |
91 | mfxer r9 | |
92 | mfctr r10 | |
93 | std r9,_XER(r1) | |
94 | std r10,_CTR(r1) | |
95 | std r3,ORIG_GPR3(r1) | |
96 | ld r2,PACATOC(r13) | |
97 | addi r9,r1,STACK_FRAME_OVERHEAD | |
98 | ld r11,exception_marker@toc(r2) | |
99 | std r11,-16(r9) /* "regshere" marker */ | |
cf9efce0 PM |
100 | #if defined(CONFIG_VIRT_CPU_ACCOUNTING) && defined(CONFIG_PPC_SPLPAR) |
101 | BEGIN_FW_FTR_SECTION | |
102 | beq 33f | |
103 | /* if from user, see if there are any DTL entries to process */ | |
104 | ld r10,PACALPPACAPTR(r13) /* get ptr to VPA */ | |
105 | ld r11,PACA_DTL_RIDX(r13) /* get log read index */ | |
106 | ld r10,LPPACA_DTLIDX(r10) /* get log write index */ | |
107 | cmpd cr1,r11,r10 | |
108 | beq+ cr1,33f | |
109 | bl .accumulate_stolen_time | |
110 | REST_GPR(0,r1) | |
111 | REST_4GPRS(3,r1) | |
112 | REST_2GPRS(7,r1) | |
113 | addi r9,r1,STACK_FRAME_OVERHEAD | |
114 | 33: | |
115 | END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR) | |
116 | #endif /* CONFIG_VIRT_CPU_ACCOUNTING && CONFIG_PPC_SPLPAR */ | |
117 | ||
1421ae0b BH |
118 | /* |
119 | * A syscall should always be called with interrupts enabled | |
120 | * so we just unconditionally hard-enable here. When some kind | |
121 | * of irq tracing is used, we additionally check that condition | |
122 | * is correct | |
123 | */ | |
124 | #if defined(CONFIG_TRACE_IRQFLAGS) && defined(CONFIG_BUG) | |
125 | lbz r10,PACASOFTIRQEN(r13) | |
126 | xori r10,r10,1 | |
127 | 1: tdnei r10,0 | |
128 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING | |
129 | #endif | |
2d27cfd3 | 130 | |
2d27cfd3 BH |
131 | #ifdef CONFIG_PPC_BOOK3E |
132 | wrteei 1 | |
133 | #else | |
1421ae0b | 134 | ld r11,PACAKMSR(r13) |
9994a338 PM |
135 | ori r11,r11,MSR_EE |
136 | mtmsrd r11,1 | |
2d27cfd3 | 137 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 | 138 | |
1421ae0b BH |
139 | /* We do need to set SOFTE in the stack frame or the return |
140 | * from interrupt will be painful | |
141 | */ | |
142 | li r10,1 | |
143 | std r10,SOFTE(r1) | |
144 | ||
9994a338 PM |
145 | #ifdef SHOW_SYSCALLS |
146 | bl .do_show_syscall | |
147 | REST_GPR(0,r1) | |
148 | REST_4GPRS(3,r1) | |
149 | REST_2GPRS(7,r1) | |
150 | addi r9,r1,STACK_FRAME_OVERHEAD | |
151 | #endif | |
152 | clrrdi r11,r1,THREAD_SHIFT | |
9994a338 | 153 | ld r10,TI_FLAGS(r11) |
9994a338 PM |
154 | andi. r11,r10,_TIF_SYSCALL_T_OR_A |
155 | bne- syscall_dotrace | |
156 | syscall_dotrace_cont: | |
157 | cmpldi 0,r0,NR_syscalls | |
158 | bge- syscall_enosys | |
159 | ||
160 | system_call: /* label this so stack traces look sane */ | |
161 | /* | |
162 | * Need to vector to 32 Bit or default sys_call_table here, | |
163 | * based on caller's run-mode / personality. | |
164 | */ | |
165 | ld r11,.SYS_CALL_TABLE@toc(2) | |
166 | andi. r10,r10,_TIF_32BIT | |
167 | beq 15f | |
168 | addi r11,r11,8 /* use 32-bit syscall entries */ | |
169 | clrldi r3,r3,32 | |
170 | clrldi r4,r4,32 | |
171 | clrldi r5,r5,32 | |
172 | clrldi r6,r6,32 | |
173 | clrldi r7,r7,32 | |
174 | clrldi r8,r8,32 | |
175 | 15: | |
176 | slwi r0,r0,4 | |
177 | ldx r10,r11,r0 /* Fetch system call handler [ptr] */ | |
178 | mtctr r10 | |
179 | bctrl /* Call handler */ | |
180 | ||
181 | syscall_exit: | |
401d1f02 | 182 | std r3,RESULT(r1) |
9994a338 | 183 | #ifdef SHOW_SYSCALLS |
9994a338 | 184 | bl .do_show_syscall_exit |
401d1f02 | 185 | ld r3,RESULT(r1) |
9994a338 | 186 | #endif |
9994a338 | 187 | clrrdi r12,r1,THREAD_SHIFT |
9994a338 | 188 | |
9994a338 | 189 | ld r8,_MSR(r1) |
2d27cfd3 BH |
190 | #ifdef CONFIG_PPC_BOOK3S |
191 | /* No MSR:RI on BookE */ | |
9994a338 PM |
192 | andi. r10,r8,MSR_RI |
193 | beq- unrecov_restore | |
2d27cfd3 | 194 | #endif |
1421ae0b BH |
195 | /* |
196 | * Disable interrupts so current_thread_info()->flags can't change, | |
2d27cfd3 BH |
197 | * and so that we don't get interrupted after loading SRR0/1. |
198 | */ | |
199 | #ifdef CONFIG_PPC_BOOK3E | |
200 | wrteei 0 | |
201 | #else | |
1421ae0b | 202 | ld r10,PACAKMSR(r13) |
9994a338 | 203 | mtmsrd r10,1 |
2d27cfd3 BH |
204 | #endif /* CONFIG_PPC_BOOK3E */ |
205 | ||
9994a338 | 206 | ld r9,TI_FLAGS(r12) |
401d1f02 | 207 | li r11,-_LAST_ERRNO |
1bd79336 | 208 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) |
9994a338 | 209 | bne- syscall_exit_work |
401d1f02 DW |
210 | cmpld r3,r11 |
211 | ld r5,_CCR(r1) | |
212 | bge- syscall_error | |
213 | syscall_error_cont: | |
9994a338 | 214 | ld r7,_NIP(r1) |
f89451fb | 215 | BEGIN_FTR_SECTION |
9994a338 | 216 | stdcx. r0,0,r1 /* to clear the reservation */ |
f89451fb | 217 | END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) |
9994a338 PM |
218 | andi. r6,r8,MSR_PR |
219 | ld r4,_LINK(r1) | |
e56a6e20 PM |
220 | /* |
221 | * Clear RI before restoring r13. If we are returning to | |
222 | * userspace and we take an exception after restoring r13, | |
223 | * we end up corrupting the userspace r13 value. | |
224 | */ | |
2d27cfd3 BH |
225 | #ifdef CONFIG_PPC_BOOK3S |
226 | /* No MSR:RI on BookE */ | |
e56a6e20 PM |
227 | li r12,MSR_RI |
228 | andc r11,r10,r12 | |
229 | mtmsrd r11,1 /* clear MSR.RI */ | |
2d27cfd3 BH |
230 | #endif /* CONFIG_PPC_BOOK3S */ |
231 | ||
c6622f63 PM |
232 | beq- 1f |
233 | ACCOUNT_CPU_USER_EXIT(r11, r12) | |
234 | ld r13,GPR13(r1) /* only restore r13 if returning to usermode */ | |
9994a338 | 235 | 1: ld r2,GPR2(r1) |
9994a338 PM |
236 | ld r1,GPR1(r1) |
237 | mtlr r4 | |
238 | mtcr r5 | |
239 | mtspr SPRN_SRR0,r7 | |
240 | mtspr SPRN_SRR1,r8 | |
2d27cfd3 | 241 | RFI |
9994a338 PM |
242 | b . /* prevent speculative execution */ |
243 | ||
401d1f02 | 244 | syscall_error: |
9994a338 | 245 | oris r5,r5,0x1000 /* Set SO bit in CR */ |
401d1f02 | 246 | neg r3,r3 |
9994a338 PM |
247 | std r5,_CCR(r1) |
248 | b syscall_error_cont | |
401d1f02 | 249 | |
9994a338 PM |
250 | /* Traced system call support */ |
251 | syscall_dotrace: | |
252 | bl .save_nvgprs | |
253 | addi r3,r1,STACK_FRAME_OVERHEAD | |
254 | bl .do_syscall_trace_enter | |
4f72c427 RM |
255 | /* |
256 | * Restore argument registers possibly just changed. | |
257 | * We use the return value of do_syscall_trace_enter | |
258 | * for the call number to look up in the table (r0). | |
259 | */ | |
260 | mr r0,r3 | |
9994a338 PM |
261 | ld r3,GPR3(r1) |
262 | ld r4,GPR4(r1) | |
263 | ld r5,GPR5(r1) | |
264 | ld r6,GPR6(r1) | |
265 | ld r7,GPR7(r1) | |
266 | ld r8,GPR8(r1) | |
267 | addi r9,r1,STACK_FRAME_OVERHEAD | |
268 | clrrdi r10,r1,THREAD_SHIFT | |
269 | ld r10,TI_FLAGS(r10) | |
270 | b syscall_dotrace_cont | |
271 | ||
401d1f02 DW |
272 | syscall_enosys: |
273 | li r3,-ENOSYS | |
274 | b syscall_exit | |
275 | ||
276 | syscall_exit_work: | |
277 | /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr. | |
278 | If TIF_NOERROR is set, just save r3 as it is. */ | |
279 | ||
280 | andi. r0,r9,_TIF_RESTOREALL | |
1bd79336 PM |
281 | beq+ 0f |
282 | REST_NVGPRS(r1) | |
283 | b 2f | |
284 | 0: cmpld r3,r11 /* r10 is -LAST_ERRNO */ | |
401d1f02 DW |
285 | blt+ 1f |
286 | andi. r0,r9,_TIF_NOERROR | |
287 | bne- 1f | |
288 | ld r5,_CCR(r1) | |
289 | neg r3,r3 | |
290 | oris r5,r5,0x1000 /* Set SO bit in CR */ | |
291 | std r5,_CCR(r1) | |
292 | 1: std r3,GPR3(r1) | |
293 | 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK) | |
294 | beq 4f | |
295 | ||
1bd79336 | 296 | /* Clear per-syscall TIF flags if any are set. */ |
401d1f02 DW |
297 | |
298 | li r11,_TIF_PERSYSCALL_MASK | |
299 | addi r12,r12,TI_FLAGS | |
300 | 3: ldarx r10,0,r12 | |
301 | andc r10,r10,r11 | |
302 | stdcx. r10,0,r12 | |
303 | bne- 3b | |
304 | subi r12,r12,TI_FLAGS | |
1bd79336 PM |
305 | |
306 | 4: /* Anything else left to do? */ | |
307 | andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP) | |
401d1f02 DW |
308 | beq .ret_from_except_lite |
309 | ||
310 | /* Re-enable interrupts */ | |
2d27cfd3 BH |
311 | #ifdef CONFIG_PPC_BOOK3E |
312 | wrteei 1 | |
313 | #else | |
1421ae0b | 314 | ld r10,PACAKMSR(r13) |
401d1f02 DW |
315 | ori r10,r10,MSR_EE |
316 | mtmsrd r10,1 | |
2d27cfd3 | 317 | #endif /* CONFIG_PPC_BOOK3E */ |
401d1f02 | 318 | |
1bd79336 | 319 | bl .save_nvgprs |
9994a338 PM |
320 | addi r3,r1,STACK_FRAME_OVERHEAD |
321 | bl .do_syscall_trace_leave | |
1bd79336 | 322 | b .ret_from_except |
9994a338 PM |
323 | |
324 | /* Save non-volatile GPRs, if not already saved. */ | |
325 | _GLOBAL(save_nvgprs) | |
326 | ld r11,_TRAP(r1) | |
327 | andi. r0,r11,1 | |
328 | beqlr- | |
329 | SAVE_NVGPRS(r1) | |
330 | clrrdi r0,r11,1 | |
331 | std r0,_TRAP(r1) | |
332 | blr | |
333 | ||
401d1f02 | 334 | |
9994a338 PM |
335 | /* |
336 | * The sigsuspend and rt_sigsuspend system calls can call do_signal | |
337 | * and thus put the process into the stopped state where we might | |
338 | * want to examine its user state with ptrace. Therefore we need | |
339 | * to save all the nonvolatile registers (r14 - r31) before calling | |
340 | * the C code. Similarly, fork, vfork and clone need the full | |
341 | * register state on the stack so that it can be copied to the child. | |
342 | */ | |
9994a338 PM |
343 | |
344 | _GLOBAL(ppc_fork) | |
345 | bl .save_nvgprs | |
346 | bl .sys_fork | |
347 | b syscall_exit | |
348 | ||
349 | _GLOBAL(ppc_vfork) | |
350 | bl .save_nvgprs | |
351 | bl .sys_vfork | |
352 | b syscall_exit | |
353 | ||
354 | _GLOBAL(ppc_clone) | |
355 | bl .save_nvgprs | |
356 | bl .sys_clone | |
357 | b syscall_exit | |
358 | ||
1bd79336 PM |
359 | _GLOBAL(ppc32_swapcontext) |
360 | bl .save_nvgprs | |
361 | bl .compat_sys_swapcontext | |
362 | b syscall_exit | |
363 | ||
364 | _GLOBAL(ppc64_swapcontext) | |
365 | bl .save_nvgprs | |
366 | bl .sys_swapcontext | |
367 | b syscall_exit | |
368 | ||
9994a338 PM |
369 | _GLOBAL(ret_from_fork) |
370 | bl .schedule_tail | |
371 | REST_NVGPRS(r1) | |
372 | li r3,0 | |
373 | b syscall_exit | |
374 | ||
375 | /* | |
376 | * This routine switches between two different tasks. The process | |
377 | * state of one is saved on its kernel stack. Then the state | |
378 | * of the other is restored from its kernel stack. The memory | |
379 | * management hardware is updated to the second process's state. | |
380 | * Finally, we can return to the second process, via ret_from_except. | |
381 | * On entry, r3 points to the THREAD for the current task, r4 | |
382 | * points to the THREAD for the new task. | |
383 | * | |
384 | * Note: there are two ways to get to the "going out" portion | |
385 | * of this code; either by coming in via the entry (_switch) | |
386 | * or via "fork" which must set up an environment equivalent | |
387 | * to the "_switch" path. If you change this you'll have to change | |
388 | * the fork code also. | |
389 | * | |
390 | * The code which creates the new task context is in 'copy_thread' | |
2ef9481e | 391 | * in arch/powerpc/kernel/process.c |
9994a338 PM |
392 | */ |
393 | .align 7 | |
394 | _GLOBAL(_switch) | |
395 | mflr r0 | |
396 | std r0,16(r1) | |
397 | stdu r1,-SWITCH_FRAME_SIZE(r1) | |
398 | /* r3-r13 are caller saved -- Cort */ | |
399 | SAVE_8GPRS(14, r1) | |
400 | SAVE_10GPRS(22, r1) | |
401 | mflr r20 /* Return to switch caller */ | |
402 | mfmsr r22 | |
403 | li r0, MSR_FP | |
ce48b210 MN |
404 | #ifdef CONFIG_VSX |
405 | BEGIN_FTR_SECTION | |
406 | oris r0,r0,MSR_VSX@h /* Disable VSX */ | |
407 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
408 | #endif /* CONFIG_VSX */ | |
9994a338 PM |
409 | #ifdef CONFIG_ALTIVEC |
410 | BEGIN_FTR_SECTION | |
411 | oris r0,r0,MSR_VEC@h /* Disable altivec */ | |
412 | mfspr r24,SPRN_VRSAVE /* save vrsave register value */ | |
413 | std r24,THREAD_VRSAVE(r3) | |
414 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
415 | #endif /* CONFIG_ALTIVEC */ | |
efcac658 AK |
416 | #ifdef CONFIG_PPC64 |
417 | BEGIN_FTR_SECTION | |
418 | mfspr r25,SPRN_DSCR | |
419 | std r25,THREAD_DSCR(r3) | |
420 | END_FTR_SECTION_IFSET(CPU_FTR_DSCR) | |
421 | #endif | |
9994a338 PM |
422 | and. r0,r0,r22 |
423 | beq+ 1f | |
424 | andc r22,r22,r0 | |
2d27cfd3 | 425 | MTMSRD(r22) |
9994a338 PM |
426 | isync |
427 | 1: std r20,_NIP(r1) | |
428 | mfcr r23 | |
429 | std r23,_CCR(r1) | |
430 | std r1,KSP(r3) /* Set old stack pointer */ | |
431 | ||
432 | #ifdef CONFIG_SMP | |
433 | /* We need a sync somewhere here to make sure that if the | |
434 | * previous task gets rescheduled on another CPU, it sees all | |
435 | * stores it has performed on this one. | |
436 | */ | |
437 | sync | |
438 | #endif /* CONFIG_SMP */ | |
439 | ||
f89451fb AB |
440 | /* |
441 | * If we optimise away the clear of the reservation in system | |
442 | * calls because we know the CPU tracks the address of the | |
443 | * reservation, then we need to clear it here to cover the | |
444 | * case that the kernel context switch path has no larx | |
445 | * instructions. | |
446 | */ | |
447 | BEGIN_FTR_SECTION | |
448 | ldarx r6,0,r1 | |
449 | END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS) | |
450 | ||
9994a338 PM |
451 | addi r6,r4,-THREAD /* Convert THREAD to 'current' */ |
452 | std r6,PACACURRENT(r13) /* Set new 'current' */ | |
453 | ||
454 | ld r8,KSP(r4) /* new stack pointer */ | |
2d27cfd3 | 455 | #ifdef CONFIG_PPC_BOOK3S |
1189be65 | 456 | BEGIN_FTR_SECTION |
c230328d | 457 | BEGIN_FTR_SECTION_NESTED(95) |
9994a338 PM |
458 | clrrdi r6,r8,28 /* get its ESID */ |
459 | clrrdi r9,r1,28 /* get current sp ESID */ | |
c230328d | 460 | FTR_SECTION_ELSE_NESTED(95) |
1189be65 PM |
461 | clrrdi r6,r8,40 /* get its 1T ESID */ |
462 | clrrdi r9,r1,40 /* get current sp 1T ESID */ | |
44ae3ab3 | 463 | ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95) |
c230328d ME |
464 | FTR_SECTION_ELSE |
465 | b 2f | |
44ae3ab3 | 466 | ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB) |
9994a338 PM |
467 | clrldi. r0,r6,2 /* is new ESID c00000000? */ |
468 | cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ | |
469 | cror eq,4*cr1+eq,eq | |
470 | beq 2f /* if yes, don't slbie it */ | |
471 | ||
472 | /* Bolt in the new stack SLB entry */ | |
473 | ld r7,KSP_VSID(r4) /* Get new stack's VSID */ | |
474 | oris r0,r6,(SLB_ESID_V)@h | |
475 | ori r0,r0,(SLB_NUM_BOLTED-1)@l | |
1189be65 PM |
476 | BEGIN_FTR_SECTION |
477 | li r9,MMU_SEGSIZE_1T /* insert B field */ | |
478 | oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h | |
479 | rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0 | |
44ae3ab3 | 480 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT) |
2f6093c8 | 481 | |
00efee7d MN |
482 | /* Update the last bolted SLB. No write barriers are needed |
483 | * here, provided we only update the current CPU's SLB shadow | |
484 | * buffer. | |
485 | */ | |
2f6093c8 | 486 | ld r9,PACA_SLBSHADOWPTR(r13) |
11a27ad7 MN |
487 | li r12,0 |
488 | std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */ | |
489 | std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */ | |
490 | std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */ | |
2f6093c8 | 491 | |
44ae3ab3 | 492 | /* No need to check for MMU_FTR_NO_SLBIE_B here, since when |
f66bce5e OJ |
493 | * we have 1TB segments, the only CPUs known to have the errata |
494 | * only support less than 1TB of system memory and we'll never | |
495 | * actually hit this code path. | |
496 | */ | |
497 | ||
9994a338 PM |
498 | slbie r6 |
499 | slbie r6 /* Workaround POWER5 < DD2.1 issue */ | |
500 | slbmte r7,r0 | |
501 | isync | |
9994a338 | 502 | 2: |
2d27cfd3 BH |
503 | #endif /* !CONFIG_PPC_BOOK3S */ |
504 | ||
9994a338 PM |
505 | clrrdi r7,r8,THREAD_SHIFT /* base of new stack */ |
506 | /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE | |
507 | because we don't need to leave the 288-byte ABI gap at the | |
508 | top of the kernel stack. */ | |
509 | addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE | |
510 | ||
511 | mr r1,r8 /* start using new stack pointer */ | |
512 | std r7,PACAKSAVE(r13) | |
513 | ||
514 | ld r6,_CCR(r1) | |
515 | mtcrf 0xFF,r6 | |
516 | ||
517 | #ifdef CONFIG_ALTIVEC | |
518 | BEGIN_FTR_SECTION | |
519 | ld r0,THREAD_VRSAVE(r4) | |
520 | mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ | |
521 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
522 | #endif /* CONFIG_ALTIVEC */ | |
efcac658 AK |
523 | #ifdef CONFIG_PPC64 |
524 | BEGIN_FTR_SECTION | |
525 | ld r0,THREAD_DSCR(r4) | |
526 | cmpd r0,r25 | |
527 | beq 1f | |
528 | mtspr SPRN_DSCR,r0 | |
529 | 1: | |
530 | END_FTR_SECTION_IFSET(CPU_FTR_DSCR) | |
531 | #endif | |
9994a338 PM |
532 | |
533 | /* r3-r13 are destroyed -- Cort */ | |
534 | REST_8GPRS(14, r1) | |
535 | REST_10GPRS(22, r1) | |
536 | ||
537 | /* convert old thread to its task_struct for return value */ | |
538 | addi r3,r3,-THREAD | |
539 | ld r7,_NIP(r1) /* Return to _switch caller in new task */ | |
540 | mtlr r7 | |
541 | addi r1,r1,SWITCH_FRAME_SIZE | |
542 | blr | |
543 | ||
544 | .align 7 | |
545 | _GLOBAL(ret_from_except) | |
546 | ld r11,_TRAP(r1) | |
547 | andi. r0,r11,1 | |
548 | bne .ret_from_except_lite | |
549 | REST_NVGPRS(r1) | |
550 | ||
551 | _GLOBAL(ret_from_except_lite) | |
552 | /* | |
553 | * Disable interrupts so that current_thread_info()->flags | |
554 | * can't change between when we test it and when we return | |
555 | * from the interrupt. | |
556 | */ | |
2d27cfd3 BH |
557 | #ifdef CONFIG_PPC_BOOK3E |
558 | wrteei 0 | |
559 | #else | |
d9ada91a BH |
560 | ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ |
561 | mtmsrd r10,1 /* Update machine state */ | |
2d27cfd3 | 562 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
563 | |
564 | #ifdef CONFIG_PREEMPT | |
565 | clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */ | |
566 | li r0,_TIF_NEED_RESCHED /* bits to check */ | |
567 | ld r3,_MSR(r1) | |
568 | ld r4,TI_FLAGS(r9) | |
569 | /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */ | |
570 | rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING | |
571 | and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */ | |
572 | bne do_work | |
573 | ||
574 | #else /* !CONFIG_PREEMPT */ | |
575 | ld r3,_MSR(r1) /* Returning to user mode? */ | |
576 | andi. r3,r3,MSR_PR | |
577 | beq restore /* if not, just restore regs and return */ | |
578 | ||
579 | /* Check current_thread_info()->flags */ | |
580 | clrrdi r9,r1,THREAD_SHIFT | |
581 | ld r4,TI_FLAGS(r9) | |
582 | andi. r0,r4,_TIF_USER_WORK_MASK | |
583 | bne do_work | |
4f8cf36f | 584 | #endif /* !CONFIG_PREEMPT */ |
9994a338 PM |
585 | |
586 | restore: | |
01f3880d | 587 | ld r5,SOFTE(r1) |
945feb17 | 588 | TRACE_AND_RESTORE_IRQ(r5); |
9994a338 | 589 | |
e56a6e20 | 590 | /* extract EE bit and use it to restore paca->hard_enabled */ |
9994a338 | 591 | ld r3,_MSR(r1) |
e56a6e20 PM |
592 | rldicl r4,r3,49,63 /* r0 = (r3 >> 15) & 1 */ |
593 | stb r4,PACAHARDIRQEN(r13) | |
594 | ||
2d27cfd3 BH |
595 | #ifdef CONFIG_PPC_BOOK3E |
596 | b .exception_return_book3e | |
597 | #else | |
e56a6e20 PM |
598 | ld r4,_CTR(r1) |
599 | ld r0,_LINK(r1) | |
600 | mtctr r4 | |
601 | mtlr r0 | |
602 | ld r4,_XER(r1) | |
603 | mtspr SPRN_XER,r4 | |
604 | ||
605 | REST_8GPRS(5, r1) | |
606 | ||
9994a338 PM |
607 | andi. r0,r3,MSR_RI |
608 | beq- unrecov_restore | |
609 | ||
f89451fb AB |
610 | /* |
611 | * Clear the reservation. If we know the CPU tracks the address of | |
612 | * the reservation then we can potentially save some cycles and use | |
613 | * a larx. On POWER6 and POWER7 this is significantly faster. | |
614 | */ | |
615 | BEGIN_FTR_SECTION | |
e56a6e20 | 616 | stdcx. r0,0,r1 /* to clear the reservation */ |
f89451fb AB |
617 | FTR_SECTION_ELSE |
618 | ldarx r4,0,r1 | |
619 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) | |
b0a779de | 620 | |
e56a6e20 PM |
621 | /* |
622 | * Clear RI before restoring r13. If we are returning to | |
623 | * userspace and we take an exception after restoring r13, | |
624 | * we end up corrupting the userspace r13 value. | |
625 | */ | |
d9ada91a BH |
626 | ld r4,PACAKMSR(r13) /* Get kernel MSR without EE */ |
627 | andc r4,r4,r0 /* r0 contains MSR_RI here */ | |
e56a6e20 | 628 | mtmsrd r4,1 |
9994a338 PM |
629 | |
630 | /* | |
631 | * r13 is our per cpu area, only restore it if we are returning to | |
632 | * userspace | |
633 | */ | |
e56a6e20 | 634 | andi. r0,r3,MSR_PR |
9994a338 | 635 | beq 1f |
e56a6e20 | 636 | ACCOUNT_CPU_USER_EXIT(r2, r4) |
9994a338 PM |
637 | REST_GPR(13, r1) |
638 | 1: | |
e56a6e20 | 639 | mtspr SPRN_SRR1,r3 |
9994a338 PM |
640 | |
641 | ld r2,_CCR(r1) | |
642 | mtcrf 0xFF,r2 | |
643 | ld r2,_NIP(r1) | |
644 | mtspr SPRN_SRR0,r2 | |
645 | ||
646 | ld r0,GPR0(r1) | |
647 | ld r2,GPR2(r1) | |
648 | ld r3,GPR3(r1) | |
649 | ld r4,GPR4(r1) | |
650 | ld r1,GPR1(r1) | |
651 | ||
652 | rfid | |
653 | b . /* prevent speculative execution */ | |
654 | ||
2d27cfd3 BH |
655 | #endif /* CONFIG_PPC_BOOK3E */ |
656 | ||
9994a338 PM |
657 | do_work: |
658 | #ifdef CONFIG_PREEMPT | |
659 | andi. r0,r3,MSR_PR /* Returning to user mode? */ | |
660 | bne user_work | |
661 | /* Check that preempt_count() == 0 and interrupts are enabled */ | |
662 | lwz r8,TI_PREEMPT(r9) | |
663 | cmpwi cr1,r8,0 | |
9994a338 PM |
664 | ld r0,SOFTE(r1) |
665 | cmpdi r0,0 | |
9994a338 PM |
666 | crandc eq,cr1*4+eq,eq |
667 | bne restore | |
4f917ba3 BH |
668 | |
669 | /* Here we are preempting the current task. | |
670 | * | |
671 | * Ensure interrupts are soft-disabled. We also properly mark | |
672 | * the PACA to reflect the fact that they are hard-disabled | |
673 | * and trace the change | |
945feb17 | 674 | */ |
4f917ba3 | 675 | li r0,0 |
d04c56f7 PM |
676 | stb r0,PACASOFTIRQEN(r13) |
677 | stb r0,PACAHARDIRQEN(r13) | |
4f917ba3 BH |
678 | TRACE_DISABLE_INTS |
679 | ||
680 | /* Call the scheduler with soft IRQs off */ | |
681 | 1: bl .preempt_schedule_irq | |
682 | ||
683 | /* Hard-disable interrupts again (and update PACA) */ | |
2d27cfd3 | 684 | #ifdef CONFIG_PPC_BOOK3E |
2d27cfd3 BH |
685 | wrteei 0 |
686 | #else | |
d9ada91a | 687 | ld r10,PACAKMSR(r13) /* Get kernel MSR without EE */ |
9994a338 | 688 | mtmsrd r10,1 |
2d27cfd3 | 689 | #endif /* CONFIG_PPC_BOOK3E */ |
4f917ba3 BH |
690 | li r0,0 |
691 | stb r0,PACAHARDIRQEN(r13) | |
692 | ||
693 | /* Re-test flags and eventually loop */ | |
694 | clrrdi r9,r1,THREAD_SHIFT | |
9994a338 PM |
695 | ld r4,TI_FLAGS(r9) |
696 | andi. r0,r4,_TIF_NEED_RESCHED | |
697 | bne 1b | |
698 | b restore | |
699 | ||
700 | user_work: | |
4f917ba3 BH |
701 | #endif /* CONFIG_PREEMPT */ |
702 | ||
9994a338 | 703 | /* Enable interrupts */ |
2d27cfd3 BH |
704 | #ifdef CONFIG_PPC_BOOK3E |
705 | wrteei 1 | |
706 | #else | |
9994a338 PM |
707 | ori r10,r10,MSR_EE |
708 | mtmsrd r10,1 | |
2d27cfd3 | 709 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
710 | |
711 | andi. r0,r4,_TIF_NEED_RESCHED | |
712 | beq 1f | |
18b246fa BH |
713 | li r5,1 |
714 | TRACE_AND_RESTORE_IRQ(r5); | |
9994a338 PM |
715 | bl .schedule |
716 | b .ret_from_except_lite | |
717 | ||
718 | 1: bl .save_nvgprs | |
18b246fa BH |
719 | li r5,1 |
720 | TRACE_AND_RESTORE_IRQ(r5); | |
7d6d637d | 721 | addi r3,r1,STACK_FRAME_OVERHEAD |
18b246fa | 722 | bl .do_notify_resume |
9994a338 PM |
723 | b .ret_from_except |
724 | ||
725 | unrecov_restore: | |
726 | addi r3,r1,STACK_FRAME_OVERHEAD | |
727 | bl .unrecoverable_exception | |
728 | b unrecov_restore | |
729 | ||
730 | #ifdef CONFIG_PPC_RTAS | |
731 | /* | |
732 | * On CHRP, the Run-Time Abstraction Services (RTAS) have to be | |
733 | * called with the MMU off. | |
734 | * | |
735 | * In addition, we need to be in 32b mode, at least for now. | |
736 | * | |
737 | * Note: r3 is an input parameter to rtas, so don't trash it... | |
738 | */ | |
739 | _GLOBAL(enter_rtas) | |
740 | mflr r0 | |
741 | std r0,16(r1) | |
742 | stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */ | |
743 | ||
744 | /* Because RTAS is running in 32b mode, it clobbers the high order half | |
745 | * of all registers that it saves. We therefore save those registers | |
746 | * RTAS might touch to the stack. (r0, r3-r13 are caller saved) | |
747 | */ | |
748 | SAVE_GPR(2, r1) /* Save the TOC */ | |
749 | SAVE_GPR(13, r1) /* Save paca */ | |
750 | SAVE_8GPRS(14, r1) /* Save the non-volatiles */ | |
751 | SAVE_10GPRS(22, r1) /* ditto */ | |
752 | ||
753 | mfcr r4 | |
754 | std r4,_CCR(r1) | |
755 | mfctr r5 | |
756 | std r5,_CTR(r1) | |
757 | mfspr r6,SPRN_XER | |
758 | std r6,_XER(r1) | |
759 | mfdar r7 | |
760 | std r7,_DAR(r1) | |
761 | mfdsisr r8 | |
762 | std r8,_DSISR(r1) | |
9994a338 | 763 | |
9fe901d1 MK |
764 | /* Temporary workaround to clear CR until RTAS can be modified to |
765 | * ignore all bits. | |
766 | */ | |
767 | li r0,0 | |
768 | mtcr r0 | |
769 | ||
007d88d0 | 770 | #ifdef CONFIG_BUG |
9994a338 PM |
771 | /* There is no way it is acceptable to get here with interrupts enabled, |
772 | * check it with the asm equivalent of WARN_ON | |
773 | */ | |
d04c56f7 | 774 | lbz r0,PACASOFTIRQEN(r13) |
9994a338 | 775 | 1: tdnei r0,0 |
007d88d0 DW |
776 | EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,BUGFLAG_WARNING |
777 | #endif | |
778 | ||
d04c56f7 PM |
779 | /* Hard-disable interrupts */ |
780 | mfmsr r6 | |
781 | rldicl r7,r6,48,1 | |
782 | rotldi r7,r7,16 | |
783 | mtmsrd r7,1 | |
784 | ||
9994a338 PM |
785 | /* Unfortunately, the stack pointer and the MSR are also clobbered, |
786 | * so they are saved in the PACA which allows us to restore | |
787 | * our original state after RTAS returns. | |
788 | */ | |
789 | std r1,PACAR1(r13) | |
790 | std r6,PACASAVEDMSR(r13) | |
791 | ||
792 | /* Setup our real return addr */ | |
e58c3495 DG |
793 | LOAD_REG_ADDR(r4,.rtas_return_loc) |
794 | clrldi r4,r4,2 /* convert to realmode address */ | |
9994a338 PM |
795 | mtlr r4 |
796 | ||
797 | li r0,0 | |
798 | ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI | |
799 | andc r0,r6,r0 | |
800 | ||
801 | li r9,1 | |
802 | rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG) | |
44c9f3cc | 803 | ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI |
9994a338 | 804 | andc r6,r0,r9 |
9994a338 PM |
805 | sync /* disable interrupts so SRR0/1 */ |
806 | mtmsrd r0 /* don't get trashed */ | |
807 | ||
e58c3495 | 808 | LOAD_REG_ADDR(r4, rtas) |
9994a338 PM |
809 | ld r5,RTASENTRY(r4) /* get the rtas->entry value */ |
810 | ld r4,RTASBASE(r4) /* get the rtas->base value */ | |
811 | ||
812 | mtspr SPRN_SRR0,r5 | |
813 | mtspr SPRN_SRR1,r6 | |
814 | rfid | |
815 | b . /* prevent speculative execution */ | |
816 | ||
817 | _STATIC(rtas_return_loc) | |
818 | /* relocation is off at this point */ | |
2dd60d79 | 819 | GET_PACA(r4) |
e58c3495 | 820 | clrldi r4,r4,2 /* convert to realmode address */ |
9994a338 | 821 | |
e31aa453 PM |
822 | bcl 20,31,$+4 |
823 | 0: mflr r3 | |
824 | ld r3,(1f-0b)(r3) /* get &.rtas_restore_regs */ | |
825 | ||
9994a338 PM |
826 | mfmsr r6 |
827 | li r0,MSR_RI | |
828 | andc r6,r6,r0 | |
829 | sync | |
830 | mtmsrd r6 | |
831 | ||
832 | ld r1,PACAR1(r4) /* Restore our SP */ | |
9994a338 PM |
833 | ld r4,PACASAVEDMSR(r4) /* Restore our MSR */ |
834 | ||
835 | mtspr SPRN_SRR0,r3 | |
836 | mtspr SPRN_SRR1,r4 | |
837 | rfid | |
838 | b . /* prevent speculative execution */ | |
839 | ||
e31aa453 PM |
840 | .align 3 |
841 | 1: .llong .rtas_restore_regs | |
842 | ||
9994a338 PM |
843 | _STATIC(rtas_restore_regs) |
844 | /* relocation is on at this point */ | |
845 | REST_GPR(2, r1) /* Restore the TOC */ | |
846 | REST_GPR(13, r1) /* Restore paca */ | |
847 | REST_8GPRS(14, r1) /* Restore the non-volatiles */ | |
848 | REST_10GPRS(22, r1) /* ditto */ | |
849 | ||
2dd60d79 | 850 | GET_PACA(r13) |
9994a338 PM |
851 | |
852 | ld r4,_CCR(r1) | |
853 | mtcr r4 | |
854 | ld r5,_CTR(r1) | |
855 | mtctr r5 | |
856 | ld r6,_XER(r1) | |
857 | mtspr SPRN_XER,r6 | |
858 | ld r7,_DAR(r1) | |
859 | mtdar r7 | |
860 | ld r8,_DSISR(r1) | |
861 | mtdsisr r8 | |
9994a338 PM |
862 | |
863 | addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */ | |
864 | ld r0,16(r1) /* get return address */ | |
865 | ||
866 | mtlr r0 | |
867 | blr /* return to caller */ | |
868 | ||
869 | #endif /* CONFIG_PPC_RTAS */ | |
870 | ||
9994a338 PM |
871 | _GLOBAL(enter_prom) |
872 | mflr r0 | |
873 | std r0,16(r1) | |
874 | stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */ | |
875 | ||
876 | /* Because PROM is running in 32b mode, it clobbers the high order half | |
877 | * of all registers that it saves. We therefore save those registers | |
878 | * PROM might touch to the stack. (r0, r3-r13 are caller saved) | |
879 | */ | |
6c171994 | 880 | SAVE_GPR(2, r1) |
9994a338 PM |
881 | SAVE_GPR(13, r1) |
882 | SAVE_8GPRS(14, r1) | |
883 | SAVE_10GPRS(22, r1) | |
6c171994 | 884 | mfcr r10 |
9994a338 | 885 | mfmsr r11 |
6c171994 | 886 | std r10,_CCR(r1) |
9994a338 PM |
887 | std r11,_MSR(r1) |
888 | ||
889 | /* Get the PROM entrypoint */ | |
6c171994 | 890 | mtlr r4 |
9994a338 PM |
891 | |
892 | /* Switch MSR to 32 bits mode | |
893 | */ | |
2d27cfd3 BH |
894 | #ifdef CONFIG_PPC_BOOK3E |
895 | rlwinm r11,r11,0,1,31 | |
896 | mtmsr r11 | |
897 | #else /* CONFIG_PPC_BOOK3E */ | |
9994a338 PM |
898 | mfmsr r11 |
899 | li r12,1 | |
900 | rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) | |
901 | andc r11,r11,r12 | |
902 | li r12,1 | |
903 | rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) | |
904 | andc r11,r11,r12 | |
905 | mtmsrd r11 | |
2d27cfd3 | 906 | #endif /* CONFIG_PPC_BOOK3E */ |
9994a338 PM |
907 | isync |
908 | ||
6c171994 | 909 | /* Enter PROM here... */ |
9994a338 PM |
910 | blrl |
911 | ||
912 | /* Just make sure that r1 top 32 bits didn't get | |
913 | * corrupt by OF | |
914 | */ | |
915 | rldicl r1,r1,0,32 | |
916 | ||
917 | /* Restore the MSR (back to 64 bits) */ | |
918 | ld r0,_MSR(r1) | |
6c171994 | 919 | MTMSRD(r0) |
9994a338 PM |
920 | isync |
921 | ||
922 | /* Restore other registers */ | |
923 | REST_GPR(2, r1) | |
924 | REST_GPR(13, r1) | |
925 | REST_8GPRS(14, r1) | |
926 | REST_10GPRS(22, r1) | |
927 | ld r4,_CCR(r1) | |
928 | mtcr r4 | |
9994a338 PM |
929 | |
930 | addi r1,r1,PROM_FRAME_SIZE | |
931 | ld r0,16(r1) | |
932 | mtlr r0 | |
933 | blr | |
4e491d14 | 934 | |
606576ce | 935 | #ifdef CONFIG_FUNCTION_TRACER |
4e491d14 SR |
936 | #ifdef CONFIG_DYNAMIC_FTRACE |
937 | _GLOBAL(mcount) | |
938 | _GLOBAL(_mcount) | |
4e491d14 SR |
939 | blr |
940 | ||
941 | _GLOBAL(ftrace_caller) | |
942 | /* Taken from output of objdump from lib64/glibc */ | |
943 | mflr r3 | |
944 | ld r11, 0(r1) | |
945 | stdu r1, -112(r1) | |
946 | std r3, 128(r1) | |
947 | ld r4, 16(r11) | |
395a59d0 | 948 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
949 | .globl ftrace_call |
950 | ftrace_call: | |
951 | bl ftrace_stub | |
952 | nop | |
46542888 SR |
953 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
954 | .globl ftrace_graph_call | |
955 | ftrace_graph_call: | |
956 | b ftrace_graph_stub | |
957 | _GLOBAL(ftrace_graph_stub) | |
958 | #endif | |
4e491d14 SR |
959 | ld r0, 128(r1) |
960 | mtlr r0 | |
961 | addi r1, r1, 112 | |
962 | _GLOBAL(ftrace_stub) | |
963 | blr | |
964 | #else | |
965 | _GLOBAL(mcount) | |
966 | blr | |
967 | ||
968 | _GLOBAL(_mcount) | |
969 | /* Taken from output of objdump from lib64/glibc */ | |
970 | mflr r3 | |
971 | ld r11, 0(r1) | |
972 | stdu r1, -112(r1) | |
973 | std r3, 128(r1) | |
974 | ld r4, 16(r11) | |
975 | ||
395a59d0 | 976 | subi r3, r3, MCOUNT_INSN_SIZE |
4e491d14 SR |
977 | LOAD_REG_ADDR(r5,ftrace_trace_function) |
978 | ld r5,0(r5) | |
979 | ld r5,0(r5) | |
980 | mtctr r5 | |
981 | bctrl | |
4e491d14 | 982 | nop |
6794c782 SR |
983 | |
984 | ||
985 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
986 | b ftrace_graph_caller | |
987 | #endif | |
4e491d14 SR |
988 | ld r0, 128(r1) |
989 | mtlr r0 | |
990 | addi r1, r1, 112 | |
991 | _GLOBAL(ftrace_stub) | |
992 | blr | |
993 | ||
6794c782 SR |
994 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
995 | ||
996 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | |
46542888 | 997 | _GLOBAL(ftrace_graph_caller) |
6794c782 SR |
998 | /* load r4 with local address */ |
999 | ld r4, 128(r1) | |
1000 | subi r4, r4, MCOUNT_INSN_SIZE | |
1001 | ||
1002 | /* get the parent address */ | |
1003 | ld r11, 112(r1) | |
1004 | addi r3, r11, 16 | |
1005 | ||
1006 | bl .prepare_ftrace_return | |
1007 | nop | |
1008 | ||
1009 | ld r0, 128(r1) | |
1010 | mtlr r0 | |
1011 | addi r1, r1, 112 | |
1012 | blr | |
1013 | ||
1014 | _GLOBAL(return_to_handler) | |
bb725340 SR |
1015 | /* need to save return values */ |
1016 | std r4, -24(r1) | |
1017 | std r3, -16(r1) | |
1018 | std r31, -8(r1) | |
1019 | mr r31, r1 | |
1020 | stdu r1, -112(r1) | |
1021 | ||
1022 | bl .ftrace_return_to_handler | |
1023 | nop | |
1024 | ||
1025 | /* return value has real return address */ | |
1026 | mtlr r3 | |
1027 | ||
1028 | ld r1, 0(r1) | |
1029 | ld r4, -24(r1) | |
1030 | ld r3, -16(r1) | |
1031 | ld r31, -8(r1) | |
1032 | ||
1033 | /* Jump back to real return address */ | |
1034 | blr | |
1035 | ||
1036 | _GLOBAL(mod_return_to_handler) | |
6794c782 SR |
1037 | /* need to save return values */ |
1038 | std r4, -32(r1) | |
1039 | std r3, -24(r1) | |
1040 | /* save TOC */ | |
1041 | std r2, -16(r1) | |
1042 | std r31, -8(r1) | |
1043 | mr r31, r1 | |
1044 | stdu r1, -112(r1) | |
1045 | ||
bb725340 SR |
1046 | /* |
1047 | * We are in a module using the module's TOC. | |
1048 | * Switch to our TOC to run inside the core kernel. | |
1049 | */ | |
be10ab10 | 1050 | ld r2, PACATOC(r13) |
6794c782 SR |
1051 | |
1052 | bl .ftrace_return_to_handler | |
1053 | nop | |
1054 | ||
1055 | /* return value has real return address */ | |
1056 | mtlr r3 | |
1057 | ||
1058 | ld r1, 0(r1) | |
1059 | ld r4, -32(r1) | |
1060 | ld r3, -24(r1) | |
1061 | ld r2, -16(r1) | |
1062 | ld r31, -8(r1) | |
1063 | ||
1064 | /* Jump back to real return address */ | |
1065 | blr | |
1066 | #endif /* CONFIG_FUNCTION_GRAPH_TRACER */ | |
1067 | #endif /* CONFIG_FUNCTION_TRACER */ |