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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
0ebc4cda BH |
2 | /* |
3 | * This file contains the 64-bit "server" PowerPC variant | |
4 | * of the low level exception handling including exception | |
5 | * vectors, exception return, part of the slb and stab | |
6 | * handling and other fixed offset specific things. | |
7 | * | |
8 | * This file is meant to be #included from head_64.S due to | |
25985edc | 9 | * position dependent assembly. |
0ebc4cda BH |
10 | * |
11 | * Most of this originates from head_64.S and thus has the same | |
12 | * copyright history. | |
13 | * | |
14 | */ | |
15 | ||
7230c564 | 16 | #include <asm/hw_irq.h> |
8aa34ab8 | 17 | #include <asm/exception-64s.h> |
46f52210 | 18 | #include <asm/ptrace.h> |
7cba160a | 19 | #include <asm/cpuidle.h> |
da2bc464 | 20 | #include <asm/head-64.h> |
8aa34ab8 | 21 | |
0ebc4cda | 22 | /* |
57f26649 NP |
23 | * There are a few constraints to be concerned with. |
24 | * - Real mode exceptions code/data must be located at their physical location. | |
25 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
26 | * - Fixed location code must not call directly beyond the __end_interrupts | |
27 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
28 | * must be used. | |
29 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
30 | * virtual 0xc00... | |
31 | * - Conditional branch targets must be within +/-32K of caller. | |
32 | * | |
33 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
34 | * therefore don't have to run in physically located code or rfid to | |
35 | * virtual mode kernel code. However on relocatable kernels they do have | |
36 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
37 | * the exception vectors) may be located elsewhere. | |
38 | * | |
39 | * Virtual exceptions correspond with physical, except their entry points | |
40 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
41 | * offset applied. Virtual exceptions are enabled with the Alternate | |
42 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
43 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
44 | * cause exceptions to be delivered in real mode. | |
45 | * | |
46 | * It's impossible to receive interrupts below 0x300 via AIL. | |
47 | * | |
48 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
49 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
50 | * | |
51 | * | |
0ebc4cda BH |
52 | * We layout physical memory as follows: |
53 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
54 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
55 | * 0x1900 - 0x3fff : Real mode trampolines | |
56 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
57 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 58 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
59 | * 0x8000 - .... : Common interrupt handlers, remaining early |
60 | * setup code, rest of kernel. | |
e0319829 NP |
61 | * |
62 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
63 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
64 | * vectors there. | |
57f26649 NP |
65 | */ |
66 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
67 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
68 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
69 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
70 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
71 | /* | |
72 | * Data area reserved for FWNMI option. | |
73 | * This address (0x7000) is fixed by the RPA. | |
74 | * pseries and powernv need to keep the whole page from | |
75 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 76 | */ |
57f26649 NP |
77 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
78 | OPEN_TEXT_SECTION(0x8000) | |
79 | #else | |
80 | OPEN_TEXT_SECTION(0x7000) | |
81 | #endif | |
82 | ||
83 | USE_FIXED_SECTION(real_vectors) | |
84 | ||
0ebc4cda BH |
85 | /* |
86 | * This is the start of the interrupt handlers for pSeries | |
87 | * This code runs with relocation off. | |
88 | * Code from here to __end_interrupts gets copied down to real | |
89 | * address 0x100 when we are running a relocatable kernel. | |
90 | * Therefore any relative branches in this section must only | |
91 | * branch to labels in this section. | |
92 | */ | |
0ebc4cda BH |
93 | .globl __start_interrupts |
94 | __start_interrupts: | |
95 | ||
e0319829 | 96 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 97 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 98 | |
fb479e44 | 99 | |
948cf67c | 100 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
101 | /* |
102 | * If running native on arch 2.06 or later, check if we are waking up | |
ba6d334a BH |
103 | * from nap/sleep/winkle, and branch to idle handler. This tests SRR1 |
104 | * bits 46:47. A non-0 value indicates that we are coming from a power | |
105 | * saving state. The idle wakeup handler initially runs in real mode, | |
106 | * but we branch to the 0xc000... address so we can turn on relocation | |
107 | * with mtmsr. | |
948cf67c | 108 | */ |
fb479e44 NP |
109 | #define IDLETEST(n) \ |
110 | BEGIN_FTR_SECTION ; \ | |
111 | mfspr r10,SPRN_SRR1 ; \ | |
112 | rlwinm. r10,r10,47-31,30,31 ; \ | |
113 | beq- 1f ; \ | |
114 | cmpwi cr3,r10,2 ; \ | |
b51351e2 | 115 | BRANCH_TO_C000(r10, system_reset_idle_common) ; \ |
fb479e44 | 116 | 1: \ |
6de6638b | 117 | KVMTEST_PR(n) ; \ |
fb479e44 NP |
118 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
119 | #else | |
120 | #define IDLETEST NOTEST | |
121 | #endif | |
371fefd6 | 122 | |
1a6822d1 | 123 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
fb479e44 | 124 | SET_SCRATCH0(r13) |
c4f3b52c NP |
125 | /* |
126 | * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is | |
127 | * being used, so a nested NMI exception would corrupt it. | |
128 | */ | |
129 | EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, EXC_STD, | |
fb479e44 NP |
130 | IDLETEST, 0x100) |
131 | ||
1a6822d1 NP |
132 | EXC_REAL_END(system_reset, 0x100, 0x100) |
133 | EXC_VIRT_NONE(0x4100, 0x100) | |
6de6638b | 134 | TRAMP_KVM(PACA_EXNMI, 0x100) |
fb479e44 NP |
135 | |
136 | #ifdef CONFIG_PPC_P7_NAP | |
137 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
9d292501 | 138 | mfspr r12,SPRN_SRR1 |
bf0153c1 | 139 | b pnv_powersave_wakeup |
371fefd6 PM |
140 | #endif |
141 | ||
a3d96f70 | 142 | EXC_COMMON_BEGIN(system_reset_common) |
c4f3b52c NP |
143 | /* |
144 | * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able | |
145 | * to recover, but nested NMI will notice in_nmi and not recover | |
146 | * because of the use of the NMI stack. in_nmi reentrancy is tested in | |
147 | * system_reset_exception. | |
148 | */ | |
149 | lhz r10,PACA_IN_NMI(r13) | |
150 | addi r10,r10,1 | |
151 | sth r10,PACA_IN_NMI(r13) | |
152 | li r10,MSR_RI | |
153 | mtmsrd r10,1 | |
aca79d2b | 154 | |
b1ee8a3d NP |
155 | mr r10,r1 |
156 | ld r1,PACA_NMI_EMERG_SP(r13) | |
157 | subi r1,r1,INT_FRAME_SIZE | |
158 | EXCEPTION_COMMON_NORET_STACK(PACA_EXNMI, 0x100, | |
159 | system_reset, system_reset_exception, | |
c4f3b52c | 160 | ADD_NVGPRS;ADD_RECONCILE) |
c4f3b52c NP |
161 | |
162 | /* | |
163 | * The stack is no longer in use, decrement in_nmi. | |
164 | */ | |
165 | lhz r10,PACA_IN_NMI(r13) | |
166 | subi r10,r10,1 | |
167 | sth r10,PACA_IN_NMI(r13) | |
168 | ||
169 | b ret_from_except | |
582baf44 NP |
170 | |
171 | #ifdef CONFIG_PPC_PSERIES | |
172 | /* | |
173 | * Vectors for the FWNMI option. Share common code. | |
174 | */ | |
175 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
176 | SET_SCRATCH0(r13) /* save r13 */ | |
c4f3b52c NP |
177 | /* See comment at system_reset exception */ |
178 | EXCEPTION_PROLOG_PSERIES_NORI(PACA_EXNMI, system_reset_common, | |
179 | EXC_STD, NOTEST, 0x100) | |
582baf44 NP |
180 | #endif /* CONFIG_PPC_PSERIES */ |
181 | ||
0ebc4cda | 182 | |
1a6822d1 | 183 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
184 | /* This is moved out of line as it can be patched by FW, but |
185 | * some code path might still want to branch into the original | |
186 | * vector | |
187 | */ | |
1707dd16 PM |
188 | SET_SCRATCH0(r13) /* save r13 */ |
189 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
1e9b4507 | 190 | BEGIN_FTR_SECTION |
2513767d | 191 | b machine_check_powernv_early |
1e9b4507 | 192 | FTR_SECTION_ELSE |
1707dd16 | 193 | b machine_check_pSeries_0 |
1e9b4507 | 194 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
195 | EXC_REAL_END(machine_check, 0x200, 0x100) |
196 | EXC_VIRT_NONE(0x4200, 0x100) | |
afcf0095 NP |
197 | TRAMP_REAL_BEGIN(machine_check_powernv_early) |
198 | BEGIN_FTR_SECTION | |
199 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
200 | /* | |
201 | * Register contents: | |
202 | * R13 = PACA | |
203 | * R9 = CR | |
204 | * Original R9 to R13 is saved on PACA_EXMC | |
205 | * | |
206 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
207 | * the nested MCE upto level 4 to avoid stack overflow). | |
208 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
209 | * | |
210 | * We use paca->in_mce to check whether this is the first entry or | |
211 | * nested machine check. We increment paca->in_mce to track nested | |
212 | * machine checks. | |
213 | * | |
214 | * If this is the first entry then set stack pointer to | |
215 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
216 | * stack frame on mc_emergency stack. | |
217 | * | |
218 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
219 | * checkstop if we get another machine check exception before we do | |
220 | * rfid with MSR_ME=1. | |
1945bc45 NP |
221 | * |
222 | * This interrupt can wake directly from idle. If that is the case, | |
223 | * the machine check is handled then the idle wakeup code is called | |
224 | * to restore state. In that case, the POWER9 DD1 idle PACA workaround | |
225 | * is not applied in the early machine check code, which will cause | |
226 | * bugs. | |
afcf0095 NP |
227 | */ |
228 | mr r11,r1 /* Save r1 */ | |
229 | lhz r10,PACA_IN_MCE(r13) | |
230 | cmpwi r10,0 /* Are we in nested machine check */ | |
231 | bne 0f /* Yes, we are. */ | |
232 | /* First machine check entry */ | |
233 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
234 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
235 | addi r10,r10,1 /* increment paca->in_mce */ | |
236 | sth r10,PACA_IN_MCE(r13) | |
237 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
ba41e1e1 | 238 | cmpwi r10,MAX_MCE_DEPTH |
afcf0095 NP |
239 | bgt 2f /* Check if we hit limit of 4 */ |
240 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
241 | std r11,0(r1) /* make stack chain pointer */ | |
242 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
243 | std r11,_NIP(r1) | |
244 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
245 | std r11,_MSR(r1) | |
246 | mfspr r11,SPRN_DAR /* Save DAR */ | |
247 | std r11,_DAR(r1) | |
248 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
249 | std r11,_DSISR(r1) | |
250 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
251 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
252 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
253 | mfmsr r11 /* get MSR value */ | |
254 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
255 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
256 | LOAD_HANDLER(r12, machine_check_handle_early) | |
257 | 1: mtspr SPRN_SRR0,r12 | |
258 | mtspr SPRN_SRR1,r11 | |
222f20f1 | 259 | RFI_TO_KERNEL |
afcf0095 NP |
260 | b . /* prevent speculative execution */ |
261 | 2: | |
262 | /* Stack overflow. Stay on emergency stack and panic. | |
263 | * Keep the ME bit off while panic-ing, so that if we hit | |
264 | * another machine check we checkstop. | |
265 | */ | |
266 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
267 | ld r11,PACAKMSR(r13) | |
268 | LOAD_HANDLER(r12, unrecover_mce) | |
269 | li r10,MSR_ME | |
270 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
271 | b 1b | |
272 | b . /* prevent speculative execution */ | |
273 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
274 | ||
275 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
276 | .globl machine_check_fwnmi | |
277 | machine_check_fwnmi: | |
278 | SET_SCRATCH0(r13) /* save r13 */ | |
279 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
280 | machine_check_pSeries_0: | |
281 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
282 | /* | |
83a980f7 NP |
283 | * MSR_RI is not enabled, because PACA_EXMC is being used, so a |
284 | * nested machine check corrupts it. machine_check_common enables | |
285 | * MSR_RI. | |
afcf0095 | 286 | */ |
83a980f7 | 287 | EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD) |
afcf0095 NP |
288 | |
289 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
290 | ||
291 | EXC_COMMON_BEGIN(machine_check_common) | |
292 | /* | |
293 | * Machine check is different because we use a different | |
294 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
295 | */ | |
296 | mfspr r10,SPRN_DAR | |
297 | std r10,PACA_EXMC+EX_DAR(r13) | |
298 | mfspr r10,SPRN_DSISR | |
299 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
300 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
301 | FINISH_NAP | |
302 | RECONCILE_IRQ_STATE(r10, r11) | |
303 | ld r3,PACA_EXMC+EX_DAR(r13) | |
304 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
305 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
306 | li r10,MSR_RI | |
307 | mtmsrd r10,1 | |
308 | std r3,_DAR(r1) | |
309 | std r4,_DSISR(r1) | |
310 | bl save_nvgprs | |
311 | addi r3,r1,STACK_FRAME_OVERHEAD | |
312 | bl machine_check_exception | |
313 | b ret_from_except | |
314 | ||
315 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
316 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
317 | li r0,MSR_RI; \ | |
318 | mfmsr r9; /* get MSR value */ \ | |
319 | andc r9,r9,r0; \ | |
320 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
321 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
322 | ld r9,_MSR(r1); \ | |
323 | mtspr SPRN_SRR1,r9; \ | |
324 | ld r3,_NIP(r1); \ | |
325 | mtspr SPRN_SRR0,r3; \ | |
326 | ld r9,_CTR(r1); \ | |
327 | mtctr r9; \ | |
328 | ld r9,_XER(r1); \ | |
329 | mtxer r9; \ | |
330 | ld r9,_LINK(r1); \ | |
331 | mtlr r9; \ | |
332 | REST_GPR(0, r1); \ | |
333 | REST_8GPRS(2, r1); \ | |
334 | REST_GPR(10, r1); \ | |
335 | ld r11,_CCR(r1); \ | |
336 | mtcr r11; \ | |
337 | /* Decrement paca->in_mce. */ \ | |
338 | lhz r12,PACA_IN_MCE(r13); \ | |
339 | subi r12,r12,1; \ | |
340 | sth r12,PACA_IN_MCE(r13); \ | |
341 | REST_GPR(11, r1); \ | |
342 | REST_2GPRS(12, r1); \ | |
343 | /* restore original r1. */ \ | |
344 | ld r1,GPR1(r1) | |
345 | ||
1945bc45 NP |
346 | #ifdef CONFIG_PPC_P7_NAP |
347 | /* | |
348 | * This is an idle wakeup. Low level machine check has already been | |
349 | * done. Queue the event then call the idle code to do the wake up. | |
350 | */ | |
351 | EXC_COMMON_BEGIN(machine_check_idle_common) | |
352 | bl machine_check_queue_event | |
353 | ||
354 | /* | |
355 | * We have not used any non-volatile GPRs here, and as a rule | |
356 | * most exception code including machine check does not. | |
357 | * Therefore PACA_NAPSTATELOST does not need to be set. Idle | |
358 | * wakeup will restore volatile registers. | |
359 | * | |
360 | * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce. | |
361 | * | |
362 | * Then decrement MCE nesting after finishing with the stack. | |
363 | */ | |
364 | ld r3,_MSR(r1) | |
365 | ||
366 | lhz r11,PACA_IN_MCE(r13) | |
367 | subi r11,r11,1 | |
368 | sth r11,PACA_IN_MCE(r13) | |
369 | ||
370 | /* Turn off the RI bit because SRR1 is used by idle wakeup code. */ | |
371 | /* Recoverability could be improved by reducing the use of SRR1. */ | |
372 | li r11,0 | |
373 | mtmsrd r11,1 | |
374 | ||
375 | b pnv_powersave_wakeup_mce | |
376 | #endif | |
afcf0095 NP |
377 | /* |
378 | * Handle machine check early in real mode. We come here with | |
379 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
380 | */ | |
381 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
382 | std r0,GPR0(r1) /* Save r0 */ | |
383 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
384 | bl save_nvgprs | |
385 | addi r3,r1,STACK_FRAME_OVERHEAD | |
386 | bl machine_check_early | |
387 | std r3,RESULT(r1) /* Save result */ | |
388 | ld r12,_MSR(r1) | |
1945bc45 | 389 | |
afcf0095 NP |
390 | #ifdef CONFIG_PPC_P7_NAP |
391 | /* | |
392 | * Check if thread was in power saving mode. We come here when any | |
393 | * of the following is true: | |
394 | * a. thread wasn't in power saving mode | |
395 | * b. thread was in power saving mode with no state loss, | |
396 | * supervisor state loss or hypervisor state loss. | |
397 | * | |
398 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
399 | */ | |
1945bc45 NP |
400 | BEGIN_FTR_SECTION |
401 | rlwinm. r11,r12,47-31,30,31 | |
6102c005 | 402 | bne machine_check_idle_common |
1945bc45 | 403 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
afcf0095 | 404 | #endif |
1945bc45 | 405 | |
afcf0095 NP |
406 | /* |
407 | * Check if we are coming from hypervisor userspace. If yes then we | |
408 | * continue in host kernel in V mode to deliver the MC event. | |
409 | */ | |
410 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
411 | beq 5f | |
412 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
413 | bne 9f /* continue in V mode if we are. */ | |
414 | ||
415 | 5: | |
416 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
417 | /* | |
418 | * We are coming from kernel context. Check if we are coming from | |
419 | * guest. if yes, then we can continue. We will fall through | |
420 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
421 | */ | |
422 | lbz r11,HSTATE_IN_GUEST(r13) | |
423 | cmpwi r11,0 /* Check if coming from guest */ | |
424 | bne 9f /* continue if we are. */ | |
425 | #endif | |
426 | /* | |
427 | * At this point we are not sure about what context we come from. | |
428 | * Queue up the MCE event and return from the interrupt. | |
429 | * But before that, check if this is an un-recoverable exception. | |
430 | * If yes, then stay on emergency stack and panic. | |
431 | */ | |
432 | andi. r11,r12,MSR_RI | |
433 | bne 2f | |
434 | 1: mfspr r11,SPRN_SRR0 | |
435 | LOAD_HANDLER(r10,unrecover_mce) | |
436 | mtspr SPRN_SRR0,r10 | |
437 | ld r10,PACAKMSR(r13) | |
438 | /* | |
439 | * We are going down. But there are chances that we might get hit by | |
440 | * another MCE during panic path and we may run into unstable state | |
441 | * with no way out. Hence, turn ME bit off while going down, so that | |
442 | * when another MCE is hit during panic path, system will checkstop | |
443 | * and hypervisor will get restarted cleanly by SP. | |
444 | */ | |
445 | li r3,MSR_ME | |
446 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
447 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 448 | RFI_TO_KERNEL |
afcf0095 NP |
449 | b . |
450 | 2: | |
451 | /* | |
452 | * Check if we have successfully handled/recovered from error, if not | |
453 | * then stay on emergency stack and panic. | |
454 | */ | |
455 | ld r3,RESULT(r1) /* Load result */ | |
456 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
457 | ||
458 | beq 1b /* if !handled then panic */ | |
459 | /* | |
460 | * Return from MC interrupt. | |
461 | * Queue up the MCE event so that we can log it later, while | |
462 | * returning from kernel or opal call. | |
463 | */ | |
464 | bl machine_check_queue_event | |
465 | MACHINE_CHECK_HANDLER_WINDUP | |
222f20f1 | 466 | RFI_TO_USER_OR_KERNEL |
afcf0095 NP |
467 | 9: |
468 | /* Deliver the machine check to host kernel in V mode. */ | |
469 | MACHINE_CHECK_HANDLER_WINDUP | |
470 | b machine_check_pSeries | |
471 | ||
472 | EXC_COMMON_BEGIN(unrecover_mce) | |
473 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
474 | addi r3,r1,STACK_FRAME_OVERHEAD | |
475 | bl machine_check_exception | |
476 | /* | |
477 | * We will not reach here. Even if we did, there is no way out. Call | |
478 | * unrecoverable_exception and die. | |
479 | */ | |
480 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
481 | bl unrecoverable_exception | |
482 | b 1b | |
483 | ||
0ebc4cda | 484 | |
1a6822d1 NP |
485 | EXC_REAL(data_access, 0x300, 0x80) |
486 | EXC_VIRT(data_access, 0x4300, 0x80, 0x300) | |
80795e6c NP |
487 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
488 | ||
489 | EXC_COMMON_BEGIN(data_access_common) | |
490 | /* | |
491 | * Here r13 points to the paca, r9 contains the saved CR, | |
492 | * SRR0 and SRR1 are saved in r11 and r12, | |
493 | * r9 - r13 are saved in paca->exgen. | |
494 | */ | |
495 | mfspr r10,SPRN_DAR | |
496 | std r10,PACA_EXGEN+EX_DAR(r13) | |
497 | mfspr r10,SPRN_DSISR | |
498 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
499 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
500 | RECONCILE_IRQ_STATE(r10, r11) | |
501 | ld r12,_MSR(r1) | |
502 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
503 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
504 | li r5,0x300 | |
505 | std r3,_DAR(r1) | |
506 | std r4,_DSISR(r1) | |
507 | BEGIN_MMU_FTR_SECTION | |
508 | b do_hash_page /* Try to handle as hpte fault */ | |
509 | MMU_FTR_SECTION_ELSE | |
510 | b handle_page_fault | |
511 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
512 | ||
0ebc4cda | 513 | |
1a6822d1 | 514 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
673b189a | 515 | SET_SCRATCH0(r13) |
1707dd16 | 516 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 517 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
4d7cd3b9 | 518 | mr r12,r3 /* save r3 */ |
0ebc4cda | 519 | mfspr r3,SPRN_DAR |
4d7cd3b9 | 520 | mfspr r11,SPRN_SRR1 |
f0f558b1 | 521 | crset 4*cr6+eq |
442b6e8e | 522 | BRANCH_TO_COMMON(r10, slb_miss_common) |
1a6822d1 | 523 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 524 | |
1a6822d1 | 525 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
2b9af6e4 NP |
526 | SET_SCRATCH0(r13) |
527 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
528 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) | |
4d7cd3b9 | 529 | mr r12,r3 /* save r3 */ |
2b9af6e4 | 530 | mfspr r3,SPRN_DAR |
4d7cd3b9 | 531 | mfspr r11,SPRN_SRR1 |
2b9af6e4 | 532 | crset 4*cr6+eq |
442b6e8e | 533 | BRANCH_TO_COMMON(r10, slb_miss_common) |
1a6822d1 | 534 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
2b9af6e4 NP |
535 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
536 | ||
537 | ||
1a6822d1 NP |
538 | EXC_REAL(instruction_access, 0x400, 0x80) |
539 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
540 | TRAMP_KVM(PACA_EXGEN, 0x400) |
541 | ||
542 | EXC_COMMON_BEGIN(instruction_access_common) | |
543 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
544 | RECONCILE_IRQ_STATE(r10, r11) | |
545 | ld r12,_MSR(r1) | |
546 | ld r3,_NIP(r1) | |
475b581f | 547 | andis. r4,r12,DSISR_SRR1_MATCH_64S@h |
27ce77df NP |
548 | li r5,0x400 |
549 | std r3,_DAR(r1) | |
550 | std r4,_DSISR(r1) | |
551 | BEGIN_MMU_FTR_SECTION | |
552 | b do_hash_page /* Try to handle as hpte fault */ | |
553 | MMU_FTR_SECTION_ELSE | |
554 | b handle_page_fault | |
555 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
556 | ||
0ebc4cda | 557 | |
1a6822d1 | 558 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) |
673b189a | 559 | SET_SCRATCH0(r13) |
1707dd16 | 560 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 561 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
4d7cd3b9 | 562 | mr r12,r3 /* save r3 */ |
0ebc4cda | 563 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ |
4d7cd3b9 | 564 | mfspr r11,SPRN_SRR1 |
f0f558b1 | 565 | crclr 4*cr6+eq |
442b6e8e | 566 | BRANCH_TO_COMMON(r10, slb_miss_common) |
1a6822d1 | 567 | EXC_REAL_END(instruction_access_slb, 0x480, 0x80) |
0ebc4cda | 568 | |
1a6822d1 | 569 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) |
8d04631a NP |
570 | SET_SCRATCH0(r13) |
571 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
572 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) | |
4d7cd3b9 | 573 | mr r12,r3 /* save r3 */ |
8d04631a | 574 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ |
4d7cd3b9 | 575 | mfspr r11,SPRN_SRR1 |
8d04631a | 576 | crclr 4*cr6+eq |
442b6e8e | 577 | BRANCH_TO_COMMON(r10, slb_miss_common) |
1a6822d1 | 578 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) |
8d04631a NP |
579 | TRAMP_KVM(PACA_EXSLB, 0x480) |
580 | ||
581 | ||
442b6e8e ME |
582 | /* |
583 | * This handler is used by the 0x380 and 0x480 SLB miss interrupts, as well as | |
584 | * the virtual mode 0x4380 and 0x4480 interrupts if AIL is enabled. | |
585 | */ | |
586 | EXC_COMMON_BEGIN(slb_miss_common) | |
8d04631a NP |
587 | /* |
588 | * r13 points to the PACA, r9 contains the saved CR, | |
4d7cd3b9 NP |
589 | * r12 contains the saved r3, |
590 | * r11 contain the saved SRR1, SRR0 is still ready for return | |
8d04631a NP |
591 | * r3 has the faulting address |
592 | * r9 - r13 are saved in paca->exslb. | |
8d04631a NP |
593 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss |
594 | * We assume we aren't going to take any exceptions during this | |
595 | * procedure. | |
596 | */ | |
597 | mflr r10 | |
8d04631a NP |
598 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ |
599 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
8d04631a | 600 | |
c7305645 NP |
601 | andi. r9,r11,MSR_PR // Check for exception from userspace |
602 | cmpdi cr4,r9,MSR_PR // And save the result in CR4 for later | |
603 | ||
4d7cd3b9 NP |
604 | /* |
605 | * Test MSR_RI before calling slb_allocate_realmode, because the | |
606 | * MSR in r11 gets clobbered. However we still want to allocate | |
607 | * SLB in case MSR_RI=0, to minimise the risk of getting stuck in | |
608 | * recursive SLB faults. So use cr5 for this, which is preserved. | |
609 | */ | |
610 | andi. r11,r11,MSR_RI /* check for unrecoverable exception */ | |
611 | cmpdi cr5,r11,MSR_RI | |
612 | ||
8d04631a | 613 | crset 4*cr0+eq |
4e003747 | 614 | #ifdef CONFIG_PPC_BOOK3S_64 |
8d04631a | 615 | BEGIN_MMU_FTR_SECTION |
fd88b945 | 616 | bl slb_allocate |
8d04631a NP |
617 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) |
618 | #endif | |
619 | ||
620 | ld r10,PACA_EXSLB+EX_LR(r13) | |
8d04631a NP |
621 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ |
622 | mtlr r10 | |
623 | ||
7c28f048 | 624 | beq- 8f /* if bad address, make full stack frame */ |
8d04631a | 625 | |
4d7cd3b9 | 626 | bne- cr5,2f /* if unrecoverable exception, oops */ |
8d04631a NP |
627 | |
628 | /* All done -- return from exception. */ | |
629 | ||
c7305645 NP |
630 | bne cr4,1f /* returning to kernel */ |
631 | ||
8d04631a NP |
632 | .machine push |
633 | .machine "power4" | |
634 | mtcrf 0x80,r9 | |
c7305645 | 635 | mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */ |
4d7cd3b9 | 636 | mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ |
8d04631a NP |
637 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ |
638 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
639 | .machine pop | |
640 | ||
fe5482c0 | 641 | RESTORE_CTR(r9, PACA_EXSLB) |
8d04631a | 642 | RESTORE_PPR_PACA(PACA_EXSLB, r9) |
4d7cd3b9 | 643 | mr r3,r12 |
8d04631a NP |
644 | ld r9,PACA_EXSLB+EX_R9(r13) |
645 | ld r10,PACA_EXSLB+EX_R10(r13) | |
646 | ld r11,PACA_EXSLB+EX_R11(r13) | |
647 | ld r12,PACA_EXSLB+EX_R12(r13) | |
648 | ld r13,PACA_EXSLB+EX_R13(r13) | |
c7305645 | 649 | RFI_TO_USER |
8d04631a | 650 | b . /* prevent speculative execution */ |
c7305645 NP |
651 | 1: |
652 | .machine push | |
653 | .machine "power4" | |
654 | mtcrf 0x80,r9 | |
655 | mtcrf 0x08,r9 /* MSR[PR] indication is in cr4 */ | |
656 | mtcrf 0x04,r9 /* MSR[RI] indication is in cr5 */ | |
657 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
658 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
659 | .machine pop | |
660 | ||
661 | RESTORE_CTR(r9, PACA_EXSLB) | |
662 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
663 | mr r3,r12 | |
664 | ld r9,PACA_EXSLB+EX_R9(r13) | |
665 | ld r10,PACA_EXSLB+EX_R10(r13) | |
666 | ld r11,PACA_EXSLB+EX_R11(r13) | |
667 | ld r12,PACA_EXSLB+EX_R12(r13) | |
668 | ld r13,PACA_EXSLB+EX_R13(r13) | |
669 | RFI_TO_KERNEL | |
670 | b . /* prevent speculative execution */ | |
671 | ||
8d04631a | 672 | |
7c28f048 | 673 | 2: std r3,PACA_EXSLB+EX_DAR(r13) |
4d7cd3b9 | 674 | mr r3,r12 |
7c28f048 | 675 | mfspr r11,SPRN_SRR0 |
4d7cd3b9 | 676 | mfspr r12,SPRN_SRR1 |
8d04631a NP |
677 | LOAD_HANDLER(r10,unrecov_slb) |
678 | mtspr SPRN_SRR0,r10 | |
679 | ld r10,PACAKMSR(r13) | |
680 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 681 | RFI_TO_KERNEL |
8d04631a NP |
682 | b . |
683 | ||
7c28f048 | 684 | 8: std r3,PACA_EXSLB+EX_DAR(r13) |
4d7cd3b9 | 685 | mr r3,r12 |
7c28f048 | 686 | mfspr r11,SPRN_SRR0 |
4d7cd3b9 | 687 | mfspr r12,SPRN_SRR1 |
8d04631a NP |
688 | LOAD_HANDLER(r10,bad_addr_slb) |
689 | mtspr SPRN_SRR0,r10 | |
690 | ld r10,PACAKMSR(r13) | |
691 | mtspr SPRN_SRR1,r10 | |
222f20f1 | 692 | RFI_TO_KERNEL |
8d04631a NP |
693 | b . |
694 | ||
695 | EXC_COMMON_BEGIN(unrecov_slb) | |
696 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
697 | RECONCILE_IRQ_STATE(r10, r11) | |
698 | bl save_nvgprs | |
699 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
700 | bl unrecoverable_exception | |
701 | b 1b | |
702 | ||
703 | EXC_COMMON_BEGIN(bad_addr_slb) | |
704 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
705 | RECONCILE_IRQ_STATE(r10, r11) | |
706 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
707 | std r3, _DAR(r1) | |
708 | beq cr6, 2f | |
ada7507d | 709 | li r10, 0x481 /* fix trap number for I-SLB miss */ |
8d04631a NP |
710 | std r10, _TRAP(r1) |
711 | 2: bl save_nvgprs | |
712 | addi r3, r1, STACK_FRAME_OVERHEAD | |
713 | bl slb_miss_bad_addr | |
714 | b ret_from_except | |
715 | ||
1a6822d1 | 716 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
b3e6b5df | 717 | .globl hardware_interrupt_hv; |
b3e6b5df | 718 | hardware_interrupt_hv: |
a5d4f3ad | 719 | BEGIN_FTR_SECTION |
da2bc464 | 720 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 721 | EXC_HV, SOFTEN_TEST_HV) |
de56a948 | 722 | FTR_SECTION_ELSE |
da2bc464 | 723 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 724 | EXC_STD, SOFTEN_TEST_PR) |
969391c5 | 725 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
1a6822d1 | 726 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 727 | |
1a6822d1 | 728 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
c138e588 NP |
729 | .globl hardware_interrupt_relon_hv; |
730 | hardware_interrupt_relon_hv: | |
731 | BEGIN_FTR_SECTION | |
732 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) | |
733 | FTR_SECTION_ELSE | |
734 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) | |
735 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1a6822d1 | 736 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 | 737 | |
7ede5317 NP |
738 | TRAMP_KVM(PACA_EXGEN, 0x500) |
739 | TRAMP_KVM_HV(PACA_EXGEN, 0x500) | |
c138e588 NP |
740 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
741 | ||
742 | ||
1a6822d1 NP |
743 | EXC_REAL(alignment, 0x600, 0x100) |
744 | EXC_VIRT(alignment, 0x4600, 0x100, 0x600) | |
da2bc464 | 745 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
746 | EXC_COMMON_BEGIN(alignment_common) |
747 | mfspr r10,SPRN_DAR | |
748 | std r10,PACA_EXGEN+EX_DAR(r13) | |
749 | mfspr r10,SPRN_DSISR | |
750 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
751 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
752 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
753 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
754 | std r3,_DAR(r1) | |
755 | std r4,_DSISR(r1) | |
756 | bl save_nvgprs | |
757 | RECONCILE_IRQ_STATE(r10, r11) | |
758 | addi r3,r1,STACK_FRAME_OVERHEAD | |
759 | bl alignment_exception | |
760 | b ret_from_except | |
761 | ||
da2bc464 | 762 | |
1a6822d1 NP |
763 | EXC_REAL(program_check, 0x700, 0x100) |
764 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 765 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 | 766 | EXC_COMMON_BEGIN(program_check_common) |
265e60a1 CB |
767 | /* |
768 | * It's possible to receive a TM Bad Thing type program check with | |
769 | * userspace register values (in particular r1), but with SRR1 reporting | |
770 | * that we came from the kernel. Normally that would confuse the bad | |
771 | * stack logic, and we would report a bad kernel stack pointer. Instead | |
772 | * we switch to the emergency stack if we're taking a TM Bad Thing from | |
773 | * the kernel. | |
774 | */ | |
775 | li r10,MSR_PR /* Build a mask of MSR_PR .. */ | |
776 | oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */ | |
777 | and r10,r10,r12 /* Mask SRR1 with that. */ | |
778 | srdi r10,r10,8 /* Shift it so we can compare */ | |
779 | cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */ | |
780 | bne 1f /* If != go to normal path. */ | |
781 | ||
782 | /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */ | |
783 | andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */ | |
784 | /* 3 in EXCEPTION_PROLOG_COMMON */ | |
785 | mr r10,r1 /* Save r1 */ | |
786 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
787 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
788 | b 3f /* Jump into the macro !! */ | |
789 | 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
11e87346 NP |
790 | bl save_nvgprs |
791 | RECONCILE_IRQ_STATE(r10, r11) | |
792 | addi r3,r1,STACK_FRAME_OVERHEAD | |
793 | bl program_check_exception | |
794 | b ret_from_except | |
795 | ||
b01c8b54 | 796 | |
1a6822d1 NP |
797 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
798 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 799 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
800 | EXC_COMMON_BEGIN(fp_unavailable_common) |
801 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
802 | bne 1f /* if from user, just load it up */ | |
803 | bl save_nvgprs | |
804 | RECONCILE_IRQ_STATE(r10, r11) | |
805 | addi r3,r1,STACK_FRAME_OVERHEAD | |
806 | bl kernel_fp_unavailable_exception | |
807 | BUG_OPCODE | |
808 | 1: | |
809 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
810 | BEGIN_FTR_SECTION | |
811 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
812 | * transaction), go do TM stuff | |
813 | */ | |
814 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
815 | bne- 2f | |
816 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
817 | #endif | |
818 | bl load_up_fpu | |
819 | b fast_exception_return | |
820 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
821 | 2: /* User process was in a transaction */ | |
822 | bl save_nvgprs | |
823 | RECONCILE_IRQ_STATE(r10, r11) | |
824 | addi r3,r1,STACK_FRAME_OVERHEAD | |
825 | bl fp_unavailable_tm | |
826 | b ret_from_except | |
827 | #endif | |
828 | ||
a5d4f3ad | 829 | |
06f7e3d3 | 830 | EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80) |
1a6822d1 | 831 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900) |
39c0da57 NP |
832 | TRAMP_KVM(PACA_EXGEN, 0x900) |
833 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
834 | ||
a485c709 | 835 | |
1a6822d1 NP |
836 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
837 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
838 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
839 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
840 | ||
a5d4f3ad | 841 | |
1a6822d1 NP |
842 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100) |
843 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00) | |
da2bc464 | 844 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
845 | #ifdef CONFIG_PPC_DOORBELL |
846 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
847 | #else | |
848 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
849 | #endif | |
850 | ||
0ebc4cda | 851 | |
1a6822d1 NP |
852 | EXC_REAL(trap_0b, 0xb00, 0x100) |
853 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 854 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
855 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
856 | ||
acd7d8ce NP |
857 | /* |
858 | * system call / hypercall (0xc00, 0x4c00) | |
859 | * | |
860 | * The system call exception is invoked with "sc 0" and does not alter HV bit. | |
861 | * There is support for kernel code to invoke system calls but there are no | |
862 | * in-tree users. | |
863 | * | |
864 | * The hypercall is invoked with "sc 1" and sets HV=1. | |
865 | * | |
866 | * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to | |
867 | * 0x4c00 virtual mode. | |
868 | * | |
869 | * Call convention: | |
870 | * | |
871 | * syscall register convention is in Documentation/powerpc/syscall64-abi.txt | |
872 | * | |
873 | * For hypercalls, the register convention is as follows: | |
874 | * r0 volatile | |
875 | * r1-2 nonvolatile | |
876 | * r3 volatile parameter and return value for status | |
877 | * r4-r10 volatile input and output value | |
878 | * r11 volatile hypercall number and output value | |
76fc0cfc | 879 | * r12 volatile input and output value |
acd7d8ce NP |
880 | * r13-r31 nonvolatile |
881 | * LR nonvolatile | |
882 | * CTR volatile | |
883 | * XER volatile | |
884 | * CR0-1 CR5-7 volatile | |
885 | * CR2-4 nonvolatile | |
886 | * Other registers nonvolatile | |
887 | * | |
888 | * The intersection of volatile registers that don't contain possible | |
76fc0cfc NP |
889 | * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry |
890 | * without saving, though xer is not a good idea to use, as hardware may | |
891 | * interpret some bits so it may be costly to change them. | |
acd7d8ce | 892 | */ |
bc355125 | 893 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
acd7d8ce NP |
894 | /* |
895 | * There is a little bit of juggling to get syscall and hcall | |
76fc0cfc NP |
896 | * working well. Save r13 in ctr to avoid using SPRG scratch |
897 | * register. | |
acd7d8ce NP |
898 | * |
899 | * Userspace syscalls have already saved the PPR, hcalls must save | |
900 | * it before setting HMT_MEDIUM. | |
901 | */ | |
bc355125 | 902 | #define SYSCALL_KVMTEST \ |
76fc0cfc | 903 | mtctr r13; \ |
bc355125 | 904 | GET_PACA(r13); \ |
76fc0cfc | 905 | std r10,PACA_EXGEN+EX_R10(r13); \ |
06f7e3d3 | 906 | INTERRUPT_TO_KERNEL; \ |
acd7d8ce | 907 | KVMTEST_PR(0xc00); /* uses r10, branch to do_kvm_0xc00_system_call */ \ |
bc355125 | 908 | HMT_MEDIUM; \ |
76fc0cfc | 909 | mfctr r9; |
bc355125 PM |
910 | |
911 | #else | |
912 | #define SYSCALL_KVMTEST \ | |
acd7d8ce NP |
913 | HMT_MEDIUM; \ |
914 | mr r9,r13; \ | |
06f7e3d3 NP |
915 | GET_PACA(r13); \ |
916 | INTERRUPT_TO_KERNEL; | |
bc355125 PM |
917 | #endif |
918 | ||
fb479e44 NP |
919 | #define LOAD_SYSCALL_HANDLER(reg) \ |
920 | __LOAD_HANDLER(reg, system_call_common) | |
d807ad37 | 921 | |
acd7d8ce NP |
922 | /* |
923 | * After SYSCALL_KVMTEST, we reach here with PACA in r13, r13 in r9, | |
924 | * and HMT_MEDIUM. | |
925 | */ | |
926 | #define SYSCALL_REAL \ | |
927 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
928 | mfspr r12,SPRN_SRR1 ; \ |
929 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
930 | mtspr SPRN_SRR0,r10 ; \ | |
931 | ld r10,PACAKMSR(r13) ; \ | |
932 | mtspr SPRN_SRR1,r10 ; \ | |
222f20f1 | 933 | RFI_TO_KERNEL ; \ |
d807ad37 NP |
934 | b . ; /* prevent speculative execution */ |
935 | ||
727f1361 | 936 | #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH |
5c2511bf ME |
937 | #define SYSCALL_FASTENDIAN_TEST \ |
938 | BEGIN_FTR_SECTION \ | |
939 | cmpdi r0,0x1ebe ; \ | |
940 | beq- 1f ; \ | |
941 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
942 | ||
acd7d8ce | 943 | #define SYSCALL_FASTENDIAN \ |
d807ad37 NP |
944 | /* Fast LE/BE switch system call */ \ |
945 | 1: mfspr r12,SPRN_SRR1 ; \ | |
946 | xori r12,r12,MSR_LE ; \ | |
947 | mtspr SPRN_SRR1,r12 ; \ | |
acd7d8ce | 948 | mr r13,r9 ; \ |
222f20f1 | 949 | RFI_TO_USER ; /* return to userspace */ \ |
d807ad37 | 950 | b . ; /* prevent speculative execution */ |
727f1361 ME |
951 | #else |
952 | #define SYSCALL_FASTENDIAN_TEST | |
953 | #define SYSCALL_FASTENDIAN | |
954 | #endif /* CONFIG_PPC_FAST_ENDIAN_SWITCH */ | |
d807ad37 NP |
955 | |
956 | #if defined(CONFIG_RELOCATABLE) | |
957 | /* | |
958 | * We can't branch directly so we do it via the CTR which | |
959 | * is volatile across system calls. | |
960 | */ | |
acd7d8ce NP |
961 | #define SYSCALL_VIRT \ |
962 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
963 | mtctr r10 ; \ | |
964 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
965 | mfspr r12,SPRN_SRR1 ; \ |
966 | li r10,MSR_RI ; \ | |
967 | mtmsrd r10,1 ; \ | |
968 | bctr ; | |
969 | #else | |
970 | /* We can branch directly */ | |
acd7d8ce NP |
971 | #define SYSCALL_VIRT \ |
972 | mfspr r11,SPRN_SRR0 ; \ | |
d807ad37 NP |
973 | mfspr r12,SPRN_SRR1 ; \ |
974 | li r10,MSR_RI ; \ | |
975 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
976 | b system_call_common ; | |
977 | #endif | |
978 | ||
1a6822d1 | 979 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
acd7d8ce NP |
980 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
981 | SYSCALL_FASTENDIAN_TEST | |
982 | SYSCALL_REAL | |
983 | SYSCALL_FASTENDIAN | |
1a6822d1 | 984 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 985 | |
1a6822d1 | 986 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
acd7d8ce NP |
987 | SYSCALL_KVMTEST /* loads PACA into r13, and saves r13 to r9 */ |
988 | SYSCALL_FASTENDIAN_TEST | |
989 | SYSCALL_VIRT | |
990 | SYSCALL_FASTENDIAN | |
1a6822d1 | 991 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 992 | |
acd7d8ce NP |
993 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
994 | /* | |
995 | * This is a hcall, so register convention is as above, with these | |
996 | * differences: | |
997 | * r13 = PACA | |
76fc0cfc NP |
998 | * ctr = orig r13 |
999 | * orig r10 saved in PACA | |
acd7d8ce NP |
1000 | */ |
1001 | TRAMP_KVM_BEGIN(do_kvm_0xc00) | |
1002 | /* | |
1003 | * Save the PPR (on systems that support it) before changing to | |
1004 | * HMT_MEDIUM. That allows the KVM code to save that value into the | |
1005 | * guest state (it is the guest's PPR value). | |
1006 | */ | |
76fc0cfc | 1007 | OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR) |
acd7d8ce | 1008 | HMT_MEDIUM |
76fc0cfc | 1009 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR) |
acd7d8ce | 1010 | mfctr r10 |
76fc0cfc | 1011 | SET_SCRATCH0(r10) |
acd7d8ce NP |
1012 | std r9,PACA_EXGEN+EX_R9(r13) |
1013 | mfcr r9 | |
acd7d8ce NP |
1014 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0xc00) |
1015 | #endif | |
da2bc464 | 1016 | |
d807ad37 | 1017 | |
1a6822d1 NP |
1018 | EXC_REAL(single_step, 0xd00, 0x100) |
1019 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 1020 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 1021 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 1022 | |
1a6822d1 | 1023 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
da0e7e62 | 1024 | EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00) |
f5c32c1d NP |
1025 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
1026 | EXC_COMMON_BEGIN(h_data_storage_common) | |
1027 | mfspr r10,SPRN_HDAR | |
1028 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1029 | mfspr r10,SPRN_HDSISR | |
1030 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1031 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
1032 | bl save_nvgprs | |
1033 | RECONCILE_IRQ_STATE(r10, r11) | |
1034 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1035 | bl unknown_exception | |
1036 | b ret_from_except | |
f5c32c1d | 1037 | |
1707dd16 | 1038 | |
1a6822d1 | 1039 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
da0e7e62 | 1040 | EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20) |
82517cab NP |
1041 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
1042 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
1043 | ||
1707dd16 | 1044 | |
1a6822d1 NP |
1045 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
1046 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
1047 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
1048 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
1049 | ||
1707dd16 | 1050 | |
e0319829 NP |
1051 | /* |
1052 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
1053 | * first, and then eventaully from there to the trampoline to get into virtual | |
1054 | * mode. | |
1055 | */ | |
1a6822d1 | 1056 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
852e5da9 | 1057 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
1a6822d1 | 1058 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
1059 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
1060 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
1061 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
a4087a4d NP |
1062 | mr r10,r1 /* Save r1 */ |
1063 | ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */ | |
62f9b03b | 1064 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ |
62f9b03b | 1065 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ |
a4087a4d NP |
1066 | mfspr r12,SPRN_HSRR1 /* Save HSRR1 */ |
1067 | EXCEPTION_PROLOG_COMMON_1() | |
62f9b03b NP |
1068 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) |
1069 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1070 | addi r3,r1,STACK_FRAME_OVERHEAD | |
be5c5e84 | 1071 | BRANCH_LINK_TO_FAR(hmi_exception_realmode) /* Function call ABI */ |
5080332c MN |
1072 | cmpdi cr0,r3,0 |
1073 | ||
62f9b03b NP |
1074 | /* Windup the stack. */ |
1075 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
1076 | ld r9,_MSR(r1) | |
1077 | mtspr SPRN_HSRR1,r9 | |
1078 | ld r3,_NIP(r1) | |
1079 | mtspr SPRN_HSRR0,r3 | |
1080 | ld r9,_CTR(r1) | |
1081 | mtctr r9 | |
1082 | ld r9,_XER(r1) | |
1083 | mtxer r9 | |
1084 | ld r9,_LINK(r1) | |
1085 | mtlr r9 | |
1086 | REST_GPR(0, r1) | |
1087 | REST_8GPRS(2, r1) | |
1088 | REST_GPR(10, r1) | |
1089 | ld r11,_CCR(r1) | |
5080332c MN |
1090 | REST_2GPRS(12, r1) |
1091 | bne 1f | |
62f9b03b NP |
1092 | mtcr r11 |
1093 | REST_GPR(11, r1) | |
5080332c | 1094 | ld r1,GPR1(r1) |
222f20f1 | 1095 | HRFI_TO_USER_OR_KERNEL |
5080332c MN |
1096 | |
1097 | 1: mtcr r11 | |
1098 | REST_GPR(11, r1) | |
62f9b03b NP |
1099 | ld r1,GPR1(r1) |
1100 | ||
1101 | /* | |
1102 | * Go to virtual mode and pull the HMI event information from | |
1103 | * firmware. | |
1104 | */ | |
1105 | .globl hmi_exception_after_realmode | |
1106 | hmi_exception_after_realmode: | |
1107 | SET_SCRATCH0(r13) | |
1108 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
1109 | b tramp_real_hmi_exception | |
1110 | ||
5080332c MN |
1111 | EXC_COMMON_BEGIN(hmi_exception_common) |
1112 | EXCEPTION_COMMON(PACA_EXGEN, 0xe60, hmi_exception_common, handle_hmi_exception, | |
1113 | ret_from_except, FINISH_NAP;ADD_NVGPRS;ADD_RECONCILE;RUNLATCH_ON) | |
1707dd16 | 1114 | |
1a6822d1 NP |
1115 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20) |
1116 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80) | |
9bcb81bf NP |
1117 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1118 | #ifdef CONFIG_PPC_DOORBELL | |
1119 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1120 | #else | |
1121 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1122 | #endif | |
1123 | ||
0ebc4cda | 1124 | |
1a6822d1 NP |
1125 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20) |
1126 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0) | |
74408776 NP |
1127 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1128 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1129 | ||
9baaef0a | 1130 | |
1a6822d1 NP |
1131 | EXC_REAL_NONE(0xec0, 0x20) |
1132 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1133 | EXC_REAL_NONE(0xee0, 0x20) | |
1134 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1135 | |
0ebc4cda | 1136 | |
1a6822d1 NP |
1137 | EXC_REAL_OOL(performance_monitor, 0xf00, 0x20) |
1138 | EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00) | |
b1c7f150 NP |
1139 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1140 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1141 | ||
0ebc4cda | 1142 | |
1a6822d1 NP |
1143 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1144 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1145 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1146 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1147 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1148 | #ifdef CONFIG_ALTIVEC | |
1149 | BEGIN_FTR_SECTION | |
1150 | beq 1f | |
1151 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1152 | BEGIN_FTR_SECTION_NESTED(69) | |
1153 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1154 | * transaction), go do TM stuff | |
1155 | */ | |
1156 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1157 | bne- 2f | |
1158 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1159 | #endif | |
1160 | bl load_up_altivec | |
1161 | b fast_exception_return | |
1162 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1163 | 2: /* User process was in a transaction */ | |
1164 | bl save_nvgprs | |
1165 | RECONCILE_IRQ_STATE(r10, r11) | |
1166 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1167 | bl altivec_unavailable_tm | |
1168 | b ret_from_except | |
1169 | #endif | |
1170 | 1: | |
1171 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1172 | #endif | |
1173 | bl save_nvgprs | |
1174 | RECONCILE_IRQ_STATE(r10, r11) | |
1175 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1176 | bl altivec_unavailable_exception | |
1177 | b ret_from_except | |
1178 | ||
0ebc4cda | 1179 | |
1a6822d1 NP |
1180 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1181 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1182 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1183 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1184 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1185 | #ifdef CONFIG_VSX | |
1186 | BEGIN_FTR_SECTION | |
1187 | beq 1f | |
1188 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1189 | BEGIN_FTR_SECTION_NESTED(69) | |
1190 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1191 | * transaction), go do TM stuff | |
1192 | */ | |
1193 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1194 | bne- 2f | |
1195 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1196 | #endif | |
1197 | b load_up_vsx | |
1198 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1199 | 2: /* User process was in a transaction */ | |
1200 | bl save_nvgprs | |
1201 | RECONCILE_IRQ_STATE(r10, r11) | |
1202 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1203 | bl vsx_unavailable_tm | |
1204 | b ret_from_except | |
1205 | #endif | |
1206 | 1: | |
1207 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1208 | #endif | |
1209 | bl save_nvgprs | |
1210 | RECONCILE_IRQ_STATE(r10, r11) | |
1211 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1212 | bl vsx_unavailable_exception | |
1213 | b ret_from_except | |
1214 | ||
da2bc464 | 1215 | |
1a6822d1 NP |
1216 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1217 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1218 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1219 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1220 | ||
da2bc464 | 1221 | |
1a6822d1 NP |
1222 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1223 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1224 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1225 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1226 | ||
da2bc464 | 1227 | |
1a6822d1 NP |
1228 | EXC_REAL_NONE(0xfa0, 0x20) |
1229 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1230 | EXC_REAL_NONE(0xfc0, 0x20) | |
1231 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1232 | EXC_REAL_NONE(0xfe0, 0x20) | |
1233 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1234 | ||
1235 | EXC_REAL_NONE(0x1000, 0x100) | |
1236 | EXC_VIRT_NONE(0x5000, 0x100) | |
1237 | EXC_REAL_NONE(0x1100, 0x100) | |
1238 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1239 | |
0ebc4cda | 1240 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1241 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1242 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1243 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1244 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1245 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1246 | EXC_REAL_NONE(0x1200, 0x100) |
1247 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1248 | #endif |
b01c8b54 | 1249 | |
ff1b3206 | 1250 | |
1a6822d1 NP |
1251 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1252 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1253 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1254 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1255 | ||
1a6822d1 NP |
1256 | EXC_REAL_NONE(0x1400, 0x100) |
1257 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1258 | |
1a6822d1 | 1259 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
b92a66a6 | 1260 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 1261 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 1262 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
1263 | |
1264 | #ifdef CONFIG_PPC_DENORMALISATION | |
1265 | mfspr r10,SPRN_HSRR1 | |
1266 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
afcf0095 NP |
1267 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
1268 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
1269 | bne+ denorm_assist | |
1270 | #endif | |
1e9b4507 | 1271 | |
f175c5ce | 1272 | KVMTEST_HV(0x1500) |
afcf0095 | 1273 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) |
1a6822d1 | 1274 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1275 | |
d7e89849 | 1276 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1277 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1278 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1279 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1280 | #else |
1a6822d1 | 1281 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1282 | #endif |
1283 | ||
f175c5ce | 1284 | TRAMP_KVM_HV(PACA_EXGEN, 0x1500) |
b01c8b54 | 1285 | |
b92a66a6 | 1286 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1287 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1288 | BEGIN_FTR_SECTION |
1289 | /* | |
1290 | * To denormalise we need to move a copy of the register to itself. | |
1291 | * For POWER6 do that here for all FP regs. | |
1292 | */ | |
1293 | mfmsr r10 | |
1294 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1295 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1296 | mtmsrd r10 | |
1297 | sync | |
d7c67fb1 MN |
1298 | |
1299 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1300 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1301 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1302 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1303 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1304 | FMR32(0) | |
1305 | ||
b92a66a6 MN |
1306 | FTR_SECTION_ELSE |
1307 | /* | |
1308 | * To denormalise we need to move a copy of the register to itself. | |
1309 | * For POWER7 do that here for the first 32 VSX registers only. | |
1310 | */ | |
1311 | mfmsr r10 | |
1312 | oris r10,r10,MSR_VSX@h | |
1313 | mtmsrd r10 | |
1314 | sync | |
d7c67fb1 MN |
1315 | |
1316 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1317 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1318 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1319 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1320 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1321 | XVCPSGNDP32(0) | |
1322 | ||
b92a66a6 | 1323 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1324 | |
1325 | BEGIN_FTR_SECTION | |
1326 | b denorm_done | |
1327 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1328 | /* | |
1329 | * To denormalise we need to move a copy of the register to itself. | |
1330 | * For POWER8 we need to do that for all 64 VSX registers | |
1331 | */ | |
1332 | XVCPSGNDP32(32) | |
1333 | denorm_done: | |
b92a66a6 MN |
1334 | mtspr SPRN_HSRR0,r11 |
1335 | mtcrf 0x80,r9 | |
1336 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1337 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1338 | BEGIN_FTR_SECTION |
1339 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1340 | mtspr SPRN_CFAR,r10 | |
1341 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1342 | ld r10,PACA_EXGEN+EX_R10(r13) |
1343 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1344 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1345 | ld r13,PACA_EXGEN+EX_R13(r13) | |
222f20f1 | 1346 | HRFI_TO_UNKNOWN |
b92a66a6 MN |
1347 | b . |
1348 | #endif | |
1349 | ||
d7e89849 NP |
1350 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
1351 | ||
1352 | ||
1353 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1354 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
1355 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 1356 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1357 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 1358 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1359 | EXC_REAL_NONE(0x1600, 0x100) |
1360 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
1361 | #endif |
1362 | ||
69a79344 | 1363 | |
1a6822d1 NP |
1364 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
1365 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 1366 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1367 | #ifdef CONFIG_ALTIVEC |
1368 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1369 | #else | |
1370 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1371 | #endif | |
1372 | ||
d7e89849 NP |
1373 | |
1374 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1375 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
1376 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 1377 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1378 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 1379 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1380 | EXC_REAL_NONE(0x1800, 0x100) |
1381 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
1382 | #endif |
1383 | ||
75eb767e | 1384 | #ifdef CONFIG_PPC_WATCHDOG |
2104180a NP |
1385 | |
1386 | #define MASKED_DEC_HANDLER_LABEL 3f | |
1387 | ||
1388 | #define MASKED_DEC_HANDLER(_H) \ | |
1389 | 3: /* soft-nmi */ \ | |
1390 | std r12,PACA_EXGEN+EX_R12(r13); \ | |
1391 | GET_SCRATCH0(r10); \ | |
1392 | std r10,PACA_EXGEN+EX_R13(r13); \ | |
1393 | EXCEPTION_PROLOG_PSERIES_1(soft_nmi_common, _H) | |
1394 | ||
cc491f1d NP |
1395 | /* |
1396 | * Branch to soft_nmi_interrupt using the emergency stack. The emergency | |
1397 | * stack is one that is usable by maskable interrupts so long as MSR_EE | |
1398 | * remains off. It is used for recovery when something has corrupted the | |
1399 | * normal kernel stack, for example. The "soft NMI" must not use the process | |
1400 | * stack because we want irq disabled sections to avoid touching the stack | |
1401 | * at all (other than PMU interrupts), so use the emergency stack for this, | |
1402 | * and run it entirely with interrupts hard disabled. | |
1403 | */ | |
2104180a NP |
1404 | EXC_COMMON_BEGIN(soft_nmi_common) |
1405 | mr r10,r1 | |
1406 | ld r1,PACAEMERGSP(r13) | |
2104180a NP |
1407 | subi r1,r1,INT_FRAME_SIZE |
1408 | EXCEPTION_COMMON_NORET_STACK(PACA_EXGEN, 0x900, | |
1409 | system_reset, soft_nmi_interrupt, | |
1410 | ADD_NVGPRS;ADD_RECONCILE) | |
1411 | b ret_from_except | |
1412 | ||
75eb767e | 1413 | #else /* CONFIG_PPC_WATCHDOG */ |
2104180a NP |
1414 | #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */ |
1415 | #define MASKED_DEC_HANDLER(_H) | |
75eb767e | 1416 | #endif /* CONFIG_PPC_WATCHDOG */ |
d7e89849 | 1417 | |
0ebc4cda | 1418 | /* |
fe9e1d54 IM |
1419 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1420 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1421 | * - If it was a doorbell we return immediately since doorbells are edge | |
1422 | * triggered and won't automatically refire. | |
0869b6fd MS |
1423 | * - If it was a HMI we return immediately since we handled it in realmode |
1424 | * and it won't refire. | |
fe9e1d54 IM |
1425 | * - else we hard disable and return. |
1426 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 1427 | */ |
7230c564 BH |
1428 | #define MASKED_INTERRUPT(_H) \ |
1429 | masked_##_H##interrupt: \ | |
1430 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1431 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1432 | or r11,r11,r10; \ | |
1433 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1434 | cmpwi r10,PACA_IRQ_DEC; \ |
1435 | bne 1f; \ | |
7230c564 BH |
1436 | lis r10,0x7fff; \ |
1437 | ori r10,r10,0xffff; \ | |
1438 | mtspr SPRN_DEC,r10; \ | |
2104180a | 1439 | b MASKED_DEC_HANDLER_LABEL; \ |
e0c827c0 NP |
1440 | 1: andi. r10,r10,(PACA_IRQ_DBELL|PACA_IRQ_HMI); \ |
1441 | bne 2f; \ | |
fe9e1d54 | 1442 | mfspr r10,SPRN_##_H##SRR1; \ |
6e9a2f6e | 1443 | xori r10,r10,MSR_EE; /* clear MSR_EE */ \ |
7230c564 BH |
1444 | mtspr SPRN_##_H##SRR1,r10; \ |
1445 | 2: mtcrf 0x80,r9; \ | |
1446 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
1447 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1448 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
c05f0be8 | 1449 | /* returns to kernel where r13 must be set up, so don't restore it */ \ |
222f20f1 | 1450 | ##_H##RFI_TO_KERNEL; \ |
2104180a NP |
1451 | b .; \ |
1452 | MASKED_DEC_HANDLER(_H) | |
57f26649 | 1453 | |
06f7e3d3 NP |
1454 | TRAMP_REAL_BEGIN(stf_barrier_fallback) |
1455 | std r9,PACA_EXRFI+EX_R9(r13) | |
1456 | std r10,PACA_EXRFI+EX_R10(r13) | |
1457 | sync | |
1458 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1459 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1460 | ori 31,31,0 | |
1461 | .rept 14 | |
1462 | b 1f | |
1463 | 1: | |
1464 | .endr | |
1465 | blr | |
1466 | ||
aa8a5e00 ME |
1467 | TRAMP_REAL_BEGIN(rfi_flush_fallback) |
1468 | SET_SCRATCH0(r13); | |
1469 | GET_PACA(r13); | |
1470 | std r9,PACA_EXRFI+EX_R9(r13) | |
1471 | std r10,PACA_EXRFI+EX_R10(r13) | |
1472 | std r11,PACA_EXRFI+EX_R11(r13) | |
1473 | std r12,PACA_EXRFI+EX_R12(r13) | |
1474 | std r8,PACA_EXRFI+EX_R13(r13) | |
1475 | mfctr r9 | |
1476 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
1477 | ld r11,PACA_L1D_FLUSH_SETS(r13) | |
1478 | ld r12,PACA_L1D_FLUSH_CONGRUENCE(r13) | |
1479 | /* | |
1480 | * The load adresses are at staggered offsets within cachelines, | |
1481 | * which suits some pipelines better (on others it should not | |
1482 | * hurt). | |
1483 | */ | |
1484 | addi r12,r12,8 | |
1485 | mtctr r11 | |
1486 | DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ | |
1487 | ||
1488 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1489 | sync | |
1490 | 1: li r8,0 | |
1491 | .rept 8 /* 8-way set associative */ | |
1492 | ldx r11,r10,r8 | |
1493 | add r8,r8,r12 | |
1494 | xor r11,r11,r11 // Ensure r11 is 0 even if fallback area is not | |
1495 | add r8,r8,r11 // Add 0, this creates a dependency on the ldx | |
1496 | .endr | |
1497 | addi r10,r10,128 /* 128 byte cache line */ | |
1498 | bdnz 1b | |
1499 | ||
1500 | mtctr r9 | |
1501 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1502 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1503 | ld r11,PACA_EXRFI+EX_R11(r13) | |
1504 | ld r12,PACA_EXRFI+EX_R12(r13) | |
1505 | ld r8,PACA_EXRFI+EX_R13(r13) | |
1506 | GET_SCRATCH0(r13); | |
1507 | rfid | |
1508 | ||
1509 | TRAMP_REAL_BEGIN(hrfi_flush_fallback) | |
1510 | SET_SCRATCH0(r13); | |
1511 | GET_PACA(r13); | |
1512 | std r9,PACA_EXRFI+EX_R9(r13) | |
1513 | std r10,PACA_EXRFI+EX_R10(r13) | |
1514 | std r11,PACA_EXRFI+EX_R11(r13) | |
1515 | std r12,PACA_EXRFI+EX_R12(r13) | |
1516 | std r8,PACA_EXRFI+EX_R13(r13) | |
1517 | mfctr r9 | |
1518 | ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13) | |
1519 | ld r11,PACA_L1D_FLUSH_SETS(r13) | |
1520 | ld r12,PACA_L1D_FLUSH_CONGRUENCE(r13) | |
1521 | /* | |
1522 | * The load adresses are at staggered offsets within cachelines, | |
1523 | * which suits some pipelines better (on others it should not | |
1524 | * hurt). | |
1525 | */ | |
1526 | addi r12,r12,8 | |
1527 | mtctr r11 | |
1528 | DCBT_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */ | |
1529 | ||
1530 | /* order ld/st prior to dcbt stop all streams with flushing */ | |
1531 | sync | |
1532 | 1: li r8,0 | |
1533 | .rept 8 /* 8-way set associative */ | |
1534 | ldx r11,r10,r8 | |
1535 | add r8,r8,r12 | |
1536 | xor r11,r11,r11 // Ensure r11 is 0 even if fallback area is not | |
1537 | add r8,r8,r11 // Add 0, this creates a dependency on the ldx | |
1538 | .endr | |
1539 | addi r10,r10,128 /* 128 byte cache line */ | |
1540 | bdnz 1b | |
1541 | ||
1542 | mtctr r9 | |
1543 | ld r9,PACA_EXRFI+EX_R9(r13) | |
1544 | ld r10,PACA_EXRFI+EX_R10(r13) | |
1545 | ld r11,PACA_EXRFI+EX_R11(r13) | |
1546 | ld r12,PACA_EXRFI+EX_R12(r13) | |
1547 | ld r8,PACA_EXRFI+EX_R13(r13) | |
1548 | GET_SCRATCH0(r13); | |
1549 | hrfid | |
1550 | ||
57f26649 NP |
1551 | /* |
1552 | * Real mode exceptions actually use this too, but alternate | |
1553 | * instruction code patches (which end up in the common .text area) | |
1554 | * cannot reach these if they are put there. | |
1555 | */ | |
1556 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1557 | MASKED_INTERRUPT() |
1558 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1559 | |
4f6c11db | 1560 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1561 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1562 | /* |
1563 | * Here all GPRs are unchanged from when the interrupt happened | |
1564 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1565 | */ | |
1566 | mfspr r13, SPRN_SRR0 | |
1567 | addi r13, r13, 4 | |
1568 | mtspr SPRN_SRR0, r13 | |
1569 | GET_SCRATCH0(r13) | |
222f20f1 | 1570 | RFI_TO_KERNEL |
4f6c11db PM |
1571 | b . |
1572 | ||
da2bc464 | 1573 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1574 | /* |
1575 | * Here all GPRs are unchanged from when the interrupt happened | |
1576 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1577 | */ | |
1578 | mfspr r13, SPRN_HSRR0 | |
1579 | addi r13, r13, 4 | |
1580 | mtspr SPRN_HSRR0, r13 | |
1581 | GET_SCRATCH0(r13) | |
222f20f1 | 1582 | HRFI_TO_KERNEL |
4f6c11db PM |
1583 | b . |
1584 | #endif | |
1585 | ||
0ebc4cda | 1586 | /* |
057b6d7e HB |
1587 | * Ensure that any handlers that get invoked from the exception prologs |
1588 | * above are below the first 64KB (0x10000) of the kernel image because | |
1589 | * the prologs assemble the addresses of these handlers using the | |
1590 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1591 | */ |
1592 | ||
1593 | /*** Common interrupt handlers ***/ | |
1594 | ||
0ebc4cda | 1595 | |
c1fb6816 MN |
1596 | /* |
1597 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1598 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1599 | * it. Addresses are the same as the original interrupt addresses, but | |
1600 | * offset by 0xc000000000004000. | |
1601 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1602 | * KVM: None of these traps are from the guest ; anything that escalated | |
1603 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1604 | */ | |
1605 | ||
1606 | /* | |
1607 | * This uses the standard macro, since the original 0x300 vector | |
1608 | * only has extra guff for STAB-based processors -- which never | |
1609 | * come here. | |
1610 | */ | |
da2bc464 | 1611 | |
57f26649 | 1612 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1613 | b __ppc64_runlatch_on |
fe1952fc | 1614 | |
57f26649 | 1615 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1616 | /* |
1617 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1618 | * handlers, so that they are copied to real address 0x100 when running | |
1619 | * a relocatable kernel. This ensures they can be reached from the short | |
1620 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1621 | * directly, without using LOAD_HANDLER(). | |
1622 | */ | |
1623 | .align 7 | |
1624 | .globl __end_interrupts | |
1625 | __end_interrupts: | |
57f26649 | 1626 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1627 | |
087aa036 | 1628 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 1629 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
1630 | andc r9,r9,r10 |
1631 | std r9,TI_LOCAL_FLAGS(r11) | |
1632 | ld r10,_LINK(r1) /* make idle task do the */ | |
1633 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1634 | blr | |
1635 | #endif | |
1636 | ||
57f26649 NP |
1637 | CLOSE_FIXED_SECTION(real_vectors); |
1638 | CLOSE_FIXED_SECTION(real_trampolines); | |
1639 | CLOSE_FIXED_SECTION(virt_vectors); | |
1640 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1641 | ||
1642 | USE_TEXT_SECTION() | |
1643 | ||
0ebc4cda BH |
1644 | /* |
1645 | * Hash table stuff | |
1646 | */ | |
f4329f2e | 1647 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 1648 | do_hash_page: |
4e003747 | 1649 | #ifdef CONFIG_PPC_BOOK3S_64 |
f23ab3ef | 1650 | lis r0,(DSISR_BAD_FAULT_64S|DSISR_DABRMATCH)@h |
398a719d BH |
1651 | ori r0,r0,DSISR_BAD_FAULT_64S@l |
1652 | and. r0,r4,r0 /* weird error? */ | |
0ebc4cda | 1653 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9778b696 | 1654 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1655 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1656 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1657 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1658 | |
1659 | /* | |
1660 | * r3 contains the faulting address | |
106713a1 | 1661 | * r4 msr |
0ebc4cda | 1662 | * r5 contains the trap number |
aefa5688 | 1663 | * r6 contains dsisr |
0ebc4cda | 1664 | * |
7230c564 | 1665 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1666 | */ |
106713a1 | 1667 | mr r4,r12 |
aefa5688 | 1668 | ld r6,_DSISR(r1) |
106713a1 AK |
1669 | bl __hash_page /* build HPTE if possible */ |
1670 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1671 | |
7230c564 | 1672 | /* Success */ |
0ebc4cda | 1673 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1674 | |
7230c564 BH |
1675 | /* Error */ |
1676 | blt- 13f | |
d89ba535 NR |
1677 | |
1678 | /* Reload DSISR into r4 for the DABR check below */ | |
1679 | ld r4,_DSISR(r1) | |
4e003747 | 1680 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
9c7cc234 | 1681 | |
0ebc4cda BH |
1682 | /* Here we have a page fault that hash_page can't handle. */ |
1683 | handle_page_fault: | |
d89ba535 NR |
1684 | 11: andis. r0,r4,DSISR_DABRMATCH@h |
1685 | bne- handle_dabr_fault | |
1686 | ld r4,_DAR(r1) | |
0ebc4cda BH |
1687 | ld r5,_DSISR(r1) |
1688 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1689 | bl do_page_fault |
0ebc4cda | 1690 | cmpdi r3,0 |
a546498f | 1691 | beq+ 12f |
b1576fec | 1692 | bl save_nvgprs |
0ebc4cda BH |
1693 | mr r5,r3 |
1694 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1695 | lwz r4,_DAR(r1) | |
b1576fec AB |
1696 | bl bad_page_fault |
1697 | b ret_from_except | |
0ebc4cda | 1698 | |
a546498f BH |
1699 | /* We have a data breakpoint exception - handle it */ |
1700 | handle_dabr_fault: | |
b1576fec | 1701 | bl save_nvgprs |
a546498f BH |
1702 | ld r4,_DAR(r1) |
1703 | ld r5,_DSISR(r1) | |
1704 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1705 | bl do_break |
1706 | 12: b ret_from_except_lite | |
a546498f | 1707 | |
0ebc4cda | 1708 | |
4e003747 | 1709 | #ifdef CONFIG_PPC_BOOK3S_64 |
0ebc4cda BH |
1710 | /* We have a page fault that hash_page could handle but HV refused |
1711 | * the PTE insertion | |
1712 | */ | |
b1576fec | 1713 | 13: bl save_nvgprs |
0ebc4cda BH |
1714 | mr r5,r3 |
1715 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1716 | ld r4,_DAR(r1) | |
b1576fec AB |
1717 | bl low_hash_fault |
1718 | b ret_from_except | |
caca285e | 1719 | #endif |
0ebc4cda | 1720 | |
9c1e1052 PM |
1721 | /* |
1722 | * We come here as a result of a DSI at a point where we don't want | |
1723 | * to call hash_page, such as when we are accessing memory (possibly | |
1724 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1725 | * were soft-disabled. We want to invoke the exception handler for | |
1726 | * the access, or panic if there isn't a handler. | |
1727 | */ | |
b1576fec | 1728 | 77: bl save_nvgprs |
9c1e1052 PM |
1729 | mr r4,r3 |
1730 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1731 | li r5,SIGSEGV | |
b1576fec AB |
1732 | bl bad_page_fault |
1733 | b ret_from_except | |
4e2bf01b ME |
1734 | |
1735 | /* | |
1736 | * Here we have detected that the kernel stack pointer is bad. | |
1737 | * R9 contains the saved CR, r13 points to the paca, | |
1738 | * r10 contains the (bad) kernel stack pointer, | |
1739 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1740 | * We switch to using an emergency stack, save the registers there, | |
1741 | * and call kernel_bad_stack(), which panics. | |
1742 | */ | |
1743 | bad_stack: | |
1744 | ld r1,PACAEMERGSP(r13) | |
1745 | subi r1,r1,64+INT_FRAME_SIZE | |
1746 | std r9,_CCR(r1) | |
1747 | std r10,GPR1(r1) | |
1748 | std r11,_NIP(r1) | |
1749 | std r12,_MSR(r1) | |
1750 | mfspr r11,SPRN_DAR | |
1751 | mfspr r12,SPRN_DSISR | |
1752 | std r11,_DAR(r1) | |
1753 | std r12,_DSISR(r1) | |
1754 | mflr r10 | |
1755 | mfctr r11 | |
1756 | mfxer r12 | |
1757 | std r10,_LINK(r1) | |
1758 | std r11,_CTR(r1) | |
1759 | std r12,_XER(r1) | |
1760 | SAVE_GPR(0,r1) | |
1761 | SAVE_GPR(2,r1) | |
1762 | ld r10,EX_R3(r3) | |
1763 | std r10,GPR3(r1) | |
1764 | SAVE_GPR(4,r1) | |
1765 | SAVE_4GPRS(5,r1) | |
1766 | ld r9,EX_R9(r3) | |
1767 | ld r10,EX_R10(r3) | |
1768 | SAVE_2GPRS(9,r1) | |
1769 | ld r9,EX_R11(r3) | |
1770 | ld r10,EX_R12(r3) | |
1771 | ld r11,EX_R13(r3) | |
1772 | std r9,GPR11(r1) | |
1773 | std r10,GPR12(r1) | |
1774 | std r11,GPR13(r1) | |
1775 | BEGIN_FTR_SECTION | |
1776 | ld r10,EX_CFAR(r3) | |
1777 | std r10,ORIG_GPR3(r1) | |
1778 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1779 | SAVE_8GPRS(14,r1) | |
1780 | SAVE_10GPRS(22,r1) | |
1781 | lhz r12,PACA_TRAP_SAVE(r13) | |
1782 | std r12,_TRAP(r1) | |
1783 | addi r11,r1,INT_FRAME_SIZE | |
1784 | std r11,0(r1) | |
1785 | li r12,0 | |
1786 | std r12,0(r11) | |
1787 | ld r2,PACATOC(r13) | |
1788 | ld r11,exception_marker@toc(r2) | |
1789 | std r12,RESULT(r1) | |
1790 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1791 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1792 | bl kernel_bad_stack | |
1793 | b 1b | |
15770a13 | 1794 | _ASM_NOKPROBE_SYMBOL(bad_stack); |
0f0c6ca1 | 1795 | |
a9af97aa NP |
1796 | /* |
1797 | * When doorbell is triggered from system reset wakeup, the message is | |
1798 | * not cleared, so it would fire again when EE is enabled. | |
1799 | * | |
1800 | * When coming from local_irq_enable, there may be the same problem if | |
1801 | * we were hard disabled. | |
1802 | * | |
1803 | * Execute msgclr to clear pending exceptions before handling it. | |
1804 | */ | |
1805 | h_doorbell_common_msgclr: | |
1806 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1807 | PPC_MSGCLR(3) | |
1808 | b h_doorbell_common | |
1809 | ||
1810 | doorbell_super_common_msgclr: | |
1811 | LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36)) | |
1812 | PPC_MSGCLRP(3) | |
1813 | b doorbell_super_common | |
1814 | ||
0f0c6ca1 NP |
1815 | /* |
1816 | * Called from arch_local_irq_enable when an interrupt needs | |
1817 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1818 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1819 | * stackframe like if a real interrupt had happened. | |
1820 | * | |
1821 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1822 | * in the generated frame has EE set to 1 or the exception | |
1823 | * handler will not properly re-enable them. | |
b48bbb82 NP |
1824 | * |
1825 | * Note that we don't specify LR as the NIP (return address) for | |
1826 | * the interrupt because that would unbalance the return branch | |
1827 | * predictor. | |
0f0c6ca1 NP |
1828 | */ |
1829 | _GLOBAL(__replay_interrupt) | |
1830 | /* We are going to jump to the exception common code which | |
1831 | * will retrieve various register values from the PACA which | |
1832 | * we don't give a damn about, so we don't bother storing them. | |
1833 | */ | |
1834 | mfmsr r12 | |
3e23a12b | 1835 | LOAD_REG_ADDR(r11, replay_interrupt_return) |
0f0c6ca1 NP |
1836 | mfcr r9 |
1837 | ori r12,r12,MSR_EE | |
1838 | cmpwi r3,0x900 | |
1839 | beq decrementer_common | |
1840 | cmpwi r3,0x500 | |
e6c1203d NP |
1841 | BEGIN_FTR_SECTION |
1842 | beq h_virt_irq_common | |
1843 | FTR_SECTION_ELSE | |
0f0c6ca1 | 1844 | beq hardware_interrupt_common |
e6c1203d | 1845 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300) |
0f0c6ca1 | 1846 | BEGIN_FTR_SECTION |
d6f73fc6 | 1847 | cmpwi r3,0xa00 |
a9af97aa | 1848 | beq h_doorbell_common_msgclr |
0f0c6ca1 NP |
1849 | cmpwi r3,0xe60 |
1850 | beq hmi_exception_common | |
1851 | FTR_SECTION_ELSE | |
1852 | cmpwi r3,0xa00 | |
a9af97aa | 1853 | beq doorbell_super_common_msgclr |
0f0c6ca1 | 1854 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
3e23a12b | 1855 | replay_interrupt_return: |
0f0c6ca1 | 1856 | blr |
b48bbb82 | 1857 | |
15770a13 | 1858 | _ASM_NOKPROBE_SYMBOL(__replay_interrupt) |