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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
7cba160a | 18 | #include <asm/cpuidle.h> |
da2bc464 | 19 | #include <asm/head-64.h> |
8aa34ab8 | 20 | |
0ebc4cda | 21 | /* |
57f26649 NP |
22 | * There are a few constraints to be concerned with. |
23 | * - Real mode exceptions code/data must be located at their physical location. | |
24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
25 | * - Fixed location code must not call directly beyond the __end_interrupts | |
26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
27 | * must be used. | |
28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
29 | * virtual 0xc00... | |
30 | * - Conditional branch targets must be within +/-32K of caller. | |
31 | * | |
32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
33 | * therefore don't have to run in physically located code or rfid to | |
34 | * virtual mode kernel code. However on relocatable kernels they do have | |
35 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
36 | * the exception vectors) may be located elsewhere. | |
37 | * | |
38 | * Virtual exceptions correspond with physical, except their entry points | |
39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
40 | * offset applied. Virtual exceptions are enabled with the Alternate | |
41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
43 | * cause exceptions to be delivered in real mode. | |
44 | * | |
45 | * It's impossible to receive interrupts below 0x300 via AIL. | |
46 | * | |
47 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
49 | * | |
50 | * | |
0ebc4cda BH |
51 | * We layout physical memory as follows: |
52 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
54 | * 0x1900 - 0x3fff : Real mode trampolines | |
55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
56 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 57 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
59 | * setup code, rest of kernel. | |
e0319829 NP |
60 | * |
61 | * We could reclaim 0x4000-0x42ff for real mode trampolines if the space | |
62 | * is necessary. Until then it's more consistent to explicitly put VIRT_NONE | |
63 | * vectors there. | |
57f26649 NP |
64 | */ |
65 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
66 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
67 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
68 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
69 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
70 | /* | |
71 | * Data area reserved for FWNMI option. | |
72 | * This address (0x7000) is fixed by the RPA. | |
73 | * pseries and powernv need to keep the whole page from | |
74 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 75 | */ |
57f26649 NP |
76 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
77 | OPEN_TEXT_SECTION(0x8000) | |
78 | #else | |
79 | OPEN_TEXT_SECTION(0x7000) | |
80 | #endif | |
81 | ||
82 | USE_FIXED_SECTION(real_vectors) | |
83 | ||
0ebc4cda BH |
84 | /* |
85 | * This is the start of the interrupt handlers for pSeries | |
86 | * This code runs with relocation off. | |
87 | * Code from here to __end_interrupts gets copied down to real | |
88 | * address 0x100 when we are running a relocatable kernel. | |
89 | * Therefore any relative branches in this section must only | |
90 | * branch to labels in this section. | |
91 | */ | |
0ebc4cda BH |
92 | .globl __start_interrupts |
93 | __start_interrupts: | |
94 | ||
e0319829 | 95 | /* No virt vectors corresponding with 0x0..0x100 */ |
1a6822d1 | 96 | EXC_VIRT_NONE(0x4000, 0x100) |
e0319829 | 97 | |
fb479e44 | 98 | |
948cf67c | 99 | #ifdef CONFIG_PPC_P7_NAP |
fb479e44 NP |
100 | /* |
101 | * If running native on arch 2.06 or later, check if we are waking up | |
102 | * from nap/sleep/winkle, and branch to idle handler. | |
948cf67c | 103 | */ |
fb479e44 NP |
104 | #define IDLETEST(n) \ |
105 | BEGIN_FTR_SECTION ; \ | |
106 | mfspr r10,SPRN_SRR1 ; \ | |
107 | rlwinm. r10,r10,47-31,30,31 ; \ | |
108 | beq- 1f ; \ | |
109 | cmpwi cr3,r10,2 ; \ | |
110 | BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \ | |
111 | 1: \ | |
112 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) | |
113 | #else | |
114 | #define IDLETEST NOTEST | |
115 | #endif | |
371fefd6 | 116 | |
1a6822d1 | 117 | EXC_REAL_BEGIN(system_reset, 0x100, 0x100) |
fb479e44 | 118 | SET_SCRATCH0(r13) |
f23ed166 NP |
119 | GET_PACA(r13) |
120 | clrrdi r13,r13,1 /* Last bit of HSPRG0 is set if waking from winkle */ | |
121 | EXCEPTION_PROLOG_PSERIES_PACA(PACA_EXGEN, system_reset_common, EXC_STD, | |
fb479e44 NP |
122 | IDLETEST, 0x100) |
123 | ||
1a6822d1 NP |
124 | EXC_REAL_END(system_reset, 0x100, 0x100) |
125 | EXC_VIRT_NONE(0x4100, 0x100) | |
fb479e44 NP |
126 | |
127 | #ifdef CONFIG_PPC_P7_NAP | |
128 | EXC_COMMON_BEGIN(system_reset_idle_common) | |
f23ed166 NP |
129 | BEGIN_FTR_SECTION |
130 | GET_PACA(r13) /* Restore HSPRG0 to get the winkle bit in r13 */ | |
131 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300) | |
5fa6b6bd | 132 | bl pnv_restore_hyp_resource |
77b54e9f | 133 | |
7cba160a SP |
134 | li r0,PNV_THREAD_RUNNING |
135 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
371fefd6 | 136 | |
3a167bea | 137 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
f0888f70 PM |
138 | li r0,KVM_HWTHREAD_IN_KERNEL |
139 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
140 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
141 | sync | |
142 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
143 | cmpwi r0,0 | |
144 | beq 1f | |
371fefd6 PM |
145 | b kvm_start_guest |
146 | 1: | |
147 | #endif | |
148 | ||
56548fc0 PM |
149 | /* Return SRR1 from power7_nap() */ |
150 | mfspr r3,SPRN_SRR1 | |
17065671 | 151 | blt cr3,2f |
5fa6b6bd SP |
152 | b pnv_wakeup_loss |
153 | 2: b pnv_wakeup_noloss | |
fb479e44 | 154 | #endif |
aca79d2b | 155 | |
582baf44 NP |
156 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) |
157 | ||
158 | #ifdef CONFIG_PPC_PSERIES | |
159 | /* | |
160 | * Vectors for the FWNMI option. Share common code. | |
161 | */ | |
162 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
163 | SET_SCRATCH0(r13) /* save r13 */ | |
164 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, | |
165 | NOTEST, 0x100) | |
166 | #endif /* CONFIG_PPC_PSERIES */ | |
167 | ||
0ebc4cda | 168 | |
1a6822d1 | 169 | EXC_REAL_BEGIN(machine_check, 0x200, 0x100) |
b01c8b54 PM |
170 | /* This is moved out of line as it can be patched by FW, but |
171 | * some code path might still want to branch into the original | |
172 | * vector | |
173 | */ | |
1707dd16 | 174 | SET_SCRATCH0(r13) /* save r13 */ |
bc14c491 MS |
175 | /* |
176 | * Running native on arch 2.06 or later, we may wakeup from winkle | |
f23ed166 | 177 | * inside machine check. If yes, then last bit of HSPRG0 would be set |
bc14c491 | 178 | * to 1. Hence clear it unconditionally. |
1c51089f | 179 | */ |
bc14c491 MS |
180 | GET_PACA(r13) |
181 | clrrdi r13,r13,1 | |
182 | SET_PACA(r13) | |
1707dd16 | 183 | EXCEPTION_PROLOG_0(PACA_EXMC) |
1e9b4507 | 184 | BEGIN_FTR_SECTION |
2513767d | 185 | b machine_check_powernv_early |
1e9b4507 | 186 | FTR_SECTION_ELSE |
1707dd16 | 187 | b machine_check_pSeries_0 |
1e9b4507 | 188 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
1a6822d1 NP |
189 | EXC_REAL_END(machine_check, 0x200, 0x100) |
190 | EXC_VIRT_NONE(0x4200, 0x100) | |
afcf0095 NP |
191 | TRAMP_REAL_BEGIN(machine_check_powernv_early) |
192 | BEGIN_FTR_SECTION | |
193 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
194 | /* | |
195 | * Register contents: | |
196 | * R13 = PACA | |
197 | * R9 = CR | |
198 | * Original R9 to R13 is saved on PACA_EXMC | |
199 | * | |
200 | * Switch to mc_emergency stack and handle re-entrancy (we limit | |
201 | * the nested MCE upto level 4 to avoid stack overflow). | |
202 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
203 | * | |
204 | * We use paca->in_mce to check whether this is the first entry or | |
205 | * nested machine check. We increment paca->in_mce to track nested | |
206 | * machine checks. | |
207 | * | |
208 | * If this is the first entry then set stack pointer to | |
209 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
210 | * stack frame on mc_emergency stack. | |
211 | * | |
212 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
213 | * checkstop if we get another machine check exception before we do | |
214 | * rfid with MSR_ME=1. | |
215 | */ | |
216 | mr r11,r1 /* Save r1 */ | |
217 | lhz r10,PACA_IN_MCE(r13) | |
218 | cmpwi r10,0 /* Are we in nested machine check */ | |
219 | bne 0f /* Yes, we are. */ | |
220 | /* First machine check entry */ | |
221 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
222 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
223 | addi r10,r10,1 /* increment paca->in_mce */ | |
224 | sth r10,PACA_IN_MCE(r13) | |
225 | /* Limit nested MCE to level 4 to avoid stack overflow */ | |
226 | cmpwi r10,4 | |
227 | bgt 2f /* Check if we hit limit of 4 */ | |
228 | std r11,GPR1(r1) /* Save r1 on the stack. */ | |
229 | std r11,0(r1) /* make stack chain pointer */ | |
230 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
231 | std r11,_NIP(r1) | |
232 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
233 | std r11,_MSR(r1) | |
234 | mfspr r11,SPRN_DAR /* Save DAR */ | |
235 | std r11,_DAR(r1) | |
236 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
237 | std r11,_DSISR(r1) | |
238 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
239 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
240 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
241 | mfmsr r11 /* get MSR value */ | |
242 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
243 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
244 | LOAD_HANDLER(r12, machine_check_handle_early) | |
245 | 1: mtspr SPRN_SRR0,r12 | |
246 | mtspr SPRN_SRR1,r11 | |
247 | rfid | |
248 | b . /* prevent speculative execution */ | |
249 | 2: | |
250 | /* Stack overflow. Stay on emergency stack and panic. | |
251 | * Keep the ME bit off while panic-ing, so that if we hit | |
252 | * another machine check we checkstop. | |
253 | */ | |
254 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
255 | ld r11,PACAKMSR(r13) | |
256 | LOAD_HANDLER(r12, unrecover_mce) | |
257 | li r10,MSR_ME | |
258 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
259 | b 1b | |
260 | b . /* prevent speculative execution */ | |
261 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
262 | ||
263 | TRAMP_REAL_BEGIN(machine_check_pSeries) | |
264 | .globl machine_check_fwnmi | |
265 | machine_check_fwnmi: | |
266 | SET_SCRATCH0(r13) /* save r13 */ | |
267 | EXCEPTION_PROLOG_0(PACA_EXMC) | |
268 | machine_check_pSeries_0: | |
269 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) | |
270 | /* | |
271 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the | |
272 | * difference that MSR_RI is not enabled, because PACA_EXMC is being | |
273 | * used, so nested machine check corrupts it. machine_check_common | |
274 | * enables MSR_RI. | |
275 | */ | |
276 | ld r10,PACAKMSR(r13) | |
277 | xori r10,r10,MSR_RI | |
278 | mfspr r11,SPRN_SRR0 | |
279 | LOAD_HANDLER(r12, machine_check_common) | |
280 | mtspr SPRN_SRR0,r12 | |
281 | mfspr r12,SPRN_SRR1 | |
282 | mtspr SPRN_SRR1,r10 | |
283 | rfid | |
284 | b . /* prevent speculative execution */ | |
285 | ||
286 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
287 | ||
288 | EXC_COMMON_BEGIN(machine_check_common) | |
289 | /* | |
290 | * Machine check is different because we use a different | |
291 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
292 | */ | |
293 | mfspr r10,SPRN_DAR | |
294 | std r10,PACA_EXMC+EX_DAR(r13) | |
295 | mfspr r10,SPRN_DSISR | |
296 | stw r10,PACA_EXMC+EX_DSISR(r13) | |
297 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
298 | FINISH_NAP | |
299 | RECONCILE_IRQ_STATE(r10, r11) | |
300 | ld r3,PACA_EXMC+EX_DAR(r13) | |
301 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
302 | /* Enable MSR_RI when finished with PACA_EXMC */ | |
303 | li r10,MSR_RI | |
304 | mtmsrd r10,1 | |
305 | std r3,_DAR(r1) | |
306 | std r4,_DSISR(r1) | |
307 | bl save_nvgprs | |
308 | addi r3,r1,STACK_FRAME_OVERHEAD | |
309 | bl machine_check_exception | |
310 | b ret_from_except | |
311 | ||
312 | #define MACHINE_CHECK_HANDLER_WINDUP \ | |
313 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
314 | li r0,MSR_RI; \ | |
315 | mfmsr r9; /* get MSR value */ \ | |
316 | andc r9,r9,r0; \ | |
317 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
318 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
319 | ld r9,_MSR(r1); \ | |
320 | mtspr SPRN_SRR1,r9; \ | |
321 | ld r3,_NIP(r1); \ | |
322 | mtspr SPRN_SRR0,r3; \ | |
323 | ld r9,_CTR(r1); \ | |
324 | mtctr r9; \ | |
325 | ld r9,_XER(r1); \ | |
326 | mtxer r9; \ | |
327 | ld r9,_LINK(r1); \ | |
328 | mtlr r9; \ | |
329 | REST_GPR(0, r1); \ | |
330 | REST_8GPRS(2, r1); \ | |
331 | REST_GPR(10, r1); \ | |
332 | ld r11,_CCR(r1); \ | |
333 | mtcr r11; \ | |
334 | /* Decrement paca->in_mce. */ \ | |
335 | lhz r12,PACA_IN_MCE(r13); \ | |
336 | subi r12,r12,1; \ | |
337 | sth r12,PACA_IN_MCE(r13); \ | |
338 | REST_GPR(11, r1); \ | |
339 | REST_2GPRS(12, r1); \ | |
340 | /* restore original r1. */ \ | |
341 | ld r1,GPR1(r1) | |
342 | ||
343 | /* | |
344 | * Handle machine check early in real mode. We come here with | |
345 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
346 | */ | |
347 | EXC_COMMON_BEGIN(machine_check_handle_early) | |
348 | std r0,GPR0(r1) /* Save r0 */ | |
349 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
350 | bl save_nvgprs | |
351 | addi r3,r1,STACK_FRAME_OVERHEAD | |
352 | bl machine_check_early | |
353 | std r3,RESULT(r1) /* Save result */ | |
354 | ld r12,_MSR(r1) | |
355 | #ifdef CONFIG_PPC_P7_NAP | |
356 | /* | |
357 | * Check if thread was in power saving mode. We come here when any | |
358 | * of the following is true: | |
359 | * a. thread wasn't in power saving mode | |
360 | * b. thread was in power saving mode with no state loss, | |
361 | * supervisor state loss or hypervisor state loss. | |
362 | * | |
363 | * Go back to nap/sleep/winkle mode again if (b) is true. | |
364 | */ | |
365 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ | |
366 | beq 4f /* No, it wasn;t */ | |
367 | /* Thread was in power saving mode. Go back to nap again. */ | |
368 | cmpwi r11,2 | |
369 | blt 3f | |
370 | /* Supervisor/Hypervisor state loss */ | |
371 | li r0,1 | |
372 | stb r0,PACA_NAPSTATELOST(r13) | |
373 | 3: bl machine_check_queue_event | |
374 | MACHINE_CHECK_HANDLER_WINDUP | |
375 | GET_PACA(r13) | |
376 | ld r1,PACAR1(r13) | |
377 | /* | |
378 | * Check what idle state this CPU was in and go back to same mode | |
379 | * again. | |
380 | */ | |
381 | lbz r3,PACA_THREAD_IDLE_STATE(r13) | |
382 | cmpwi r3,PNV_THREAD_NAP | |
383 | bgt 10f | |
823b7bd5 | 384 | IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP) |
afcf0095 NP |
385 | /* No return */ |
386 | 10: | |
387 | cmpwi r3,PNV_THREAD_SLEEP | |
388 | bgt 2f | |
823b7bd5 | 389 | IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP) |
afcf0095 NP |
390 | /* No return */ |
391 | ||
392 | 2: | |
393 | /* | |
394 | * Go back to winkle. Please note that this thread was woken up in | |
395 | * machine check from winkle and have not restored the per-subcore | |
f23ed166 | 396 | * state. Hence before going back to winkle, set last bit of HSPRG0 |
afcf0095 NP |
397 | * to 1. This will make sure that if this thread gets woken up |
398 | * again at reset vector 0x100 then it will get chance to restore | |
399 | * the subcore state. | |
400 | */ | |
401 | ori r13,r13,1 | |
402 | SET_PACA(r13) | |
823b7bd5 | 403 | IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE) |
afcf0095 NP |
404 | /* No return */ |
405 | 4: | |
406 | #endif | |
407 | /* | |
408 | * Check if we are coming from hypervisor userspace. If yes then we | |
409 | * continue in host kernel in V mode to deliver the MC event. | |
410 | */ | |
411 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
412 | beq 5f | |
413 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
414 | bne 9f /* continue in V mode if we are. */ | |
415 | ||
416 | 5: | |
417 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER | |
418 | /* | |
419 | * We are coming from kernel context. Check if we are coming from | |
420 | * guest. if yes, then we can continue. We will fall through | |
421 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
422 | */ | |
423 | lbz r11,HSTATE_IN_GUEST(r13) | |
424 | cmpwi r11,0 /* Check if coming from guest */ | |
425 | bne 9f /* continue if we are. */ | |
426 | #endif | |
427 | /* | |
428 | * At this point we are not sure about what context we come from. | |
429 | * Queue up the MCE event and return from the interrupt. | |
430 | * But before that, check if this is an un-recoverable exception. | |
431 | * If yes, then stay on emergency stack and panic. | |
432 | */ | |
433 | andi. r11,r12,MSR_RI | |
434 | bne 2f | |
435 | 1: mfspr r11,SPRN_SRR0 | |
436 | LOAD_HANDLER(r10,unrecover_mce) | |
437 | mtspr SPRN_SRR0,r10 | |
438 | ld r10,PACAKMSR(r13) | |
439 | /* | |
440 | * We are going down. But there are chances that we might get hit by | |
441 | * another MCE during panic path and we may run into unstable state | |
442 | * with no way out. Hence, turn ME bit off while going down, so that | |
443 | * when another MCE is hit during panic path, system will checkstop | |
444 | * and hypervisor will get restarted cleanly by SP. | |
445 | */ | |
446 | li r3,MSR_ME | |
447 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
448 | mtspr SPRN_SRR1,r10 | |
449 | rfid | |
450 | b . | |
451 | 2: | |
452 | /* | |
453 | * Check if we have successfully handled/recovered from error, if not | |
454 | * then stay on emergency stack and panic. | |
455 | */ | |
456 | ld r3,RESULT(r1) /* Load result */ | |
457 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
458 | ||
459 | beq 1b /* if !handled then panic */ | |
460 | /* | |
461 | * Return from MC interrupt. | |
462 | * Queue up the MCE event so that we can log it later, while | |
463 | * returning from kernel or opal call. | |
464 | */ | |
465 | bl machine_check_queue_event | |
466 | MACHINE_CHECK_HANDLER_WINDUP | |
467 | rfid | |
468 | 9: | |
469 | /* Deliver the machine check to host kernel in V mode. */ | |
470 | MACHINE_CHECK_HANDLER_WINDUP | |
471 | b machine_check_pSeries | |
472 | ||
473 | EXC_COMMON_BEGIN(unrecover_mce) | |
474 | /* Invoke machine_check_exception to print MCE event and panic. */ | |
475 | addi r3,r1,STACK_FRAME_OVERHEAD | |
476 | bl machine_check_exception | |
477 | /* | |
478 | * We will not reach here. Even if we did, there is no way out. Call | |
479 | * unrecoverable_exception and die. | |
480 | */ | |
481 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
482 | bl unrecoverable_exception | |
483 | b 1b | |
484 | ||
0ebc4cda | 485 | |
1a6822d1 NP |
486 | EXC_REAL(data_access, 0x300, 0x80) |
487 | EXC_VIRT(data_access, 0x4300, 0x80, 0x300) | |
80795e6c NP |
488 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) |
489 | ||
490 | EXC_COMMON_BEGIN(data_access_common) | |
491 | /* | |
492 | * Here r13 points to the paca, r9 contains the saved CR, | |
493 | * SRR0 and SRR1 are saved in r11 and r12, | |
494 | * r9 - r13 are saved in paca->exgen. | |
495 | */ | |
496 | mfspr r10,SPRN_DAR | |
497 | std r10,PACA_EXGEN+EX_DAR(r13) | |
498 | mfspr r10,SPRN_DSISR | |
499 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
500 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
501 | RECONCILE_IRQ_STATE(r10, r11) | |
502 | ld r12,_MSR(r1) | |
503 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
504 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
505 | li r5,0x300 | |
506 | std r3,_DAR(r1) | |
507 | std r4,_DSISR(r1) | |
508 | BEGIN_MMU_FTR_SECTION | |
509 | b do_hash_page /* Try to handle as hpte fault */ | |
510 | MMU_FTR_SECTION_ELSE | |
511 | b handle_page_fault | |
512 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
513 | ||
0ebc4cda | 514 | |
1a6822d1 | 515 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80) |
673b189a | 516 | SET_SCRATCH0(r13) |
1707dd16 | 517 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 518 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
519 | std r3,PACA_EXSLB+EX_R3(r13) |
520 | mfspr r3,SPRN_DAR | |
b01c8b54 | 521 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 522 | crset 4*cr6+eq |
0ebc4cda | 523 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 524 | b slb_miss_realmode |
0ebc4cda BH |
525 | #else |
526 | /* | |
ad0289e4 | 527 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
528 | * because the distance from here to there depends on where |
529 | * the kernel ends up being put. | |
530 | */ | |
531 | mfctr r11 | |
ad0289e4 | 532 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
533 | mtctr r10 |
534 | bctr | |
535 | #endif | |
1a6822d1 | 536 | EXC_REAL_END(data_access_slb, 0x380, 0x80) |
0ebc4cda | 537 | |
1a6822d1 | 538 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80) |
2b9af6e4 NP |
539 | SET_SCRATCH0(r13) |
540 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
541 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) | |
542 | std r3,PACA_EXSLB+EX_R3(r13) | |
543 | mfspr r3,SPRN_DAR | |
544 | mfspr r12,SPRN_SRR1 | |
545 | crset 4*cr6+eq | |
546 | #ifndef CONFIG_RELOCATABLE | |
547 | b slb_miss_realmode | |
548 | #else | |
549 | /* | |
550 | * We can't just use a direct branch to slb_miss_realmode | |
551 | * because the distance from here to there depends on where | |
552 | * the kernel ends up being put. | |
553 | */ | |
554 | mfctr r11 | |
555 | LOAD_HANDLER(r10, slb_miss_realmode) | |
556 | mtctr r10 | |
557 | bctr | |
558 | #endif | |
1a6822d1 | 559 | EXC_VIRT_END(data_access_slb, 0x4380, 0x80) |
2b9af6e4 NP |
560 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) |
561 | ||
562 | ||
1a6822d1 NP |
563 | EXC_REAL(instruction_access, 0x400, 0x80) |
564 | EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400) | |
27ce77df NP |
565 | TRAMP_KVM(PACA_EXGEN, 0x400) |
566 | ||
567 | EXC_COMMON_BEGIN(instruction_access_common) | |
568 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
569 | RECONCILE_IRQ_STATE(r10, r11) | |
570 | ld r12,_MSR(r1) | |
571 | ld r3,_NIP(r1) | |
572 | andis. r4,r12,0x5820 | |
573 | li r5,0x400 | |
574 | std r3,_DAR(r1) | |
575 | std r4,_DSISR(r1) | |
576 | BEGIN_MMU_FTR_SECTION | |
577 | b do_hash_page /* Try to handle as hpte fault */ | |
578 | MMU_FTR_SECTION_ELSE | |
579 | b handle_page_fault | |
580 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) | |
581 | ||
0ebc4cda | 582 | |
1a6822d1 | 583 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80) |
673b189a | 584 | SET_SCRATCH0(r13) |
1707dd16 | 585 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 586 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
587 | std r3,PACA_EXSLB+EX_R3(r13) |
588 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
b01c8b54 | 589 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 590 | crclr 4*cr6+eq |
0ebc4cda | 591 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 592 | b slb_miss_realmode |
0ebc4cda BH |
593 | #else |
594 | mfctr r11 | |
ad0289e4 | 595 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
596 | mtctr r10 |
597 | bctr | |
598 | #endif | |
1a6822d1 | 599 | EXC_REAL_END(instruction_access_slb, 0x480, 0x80) |
0ebc4cda | 600 | |
1a6822d1 | 601 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80) |
8d04631a NP |
602 | SET_SCRATCH0(r13) |
603 | EXCEPTION_PROLOG_0(PACA_EXSLB) | |
604 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) | |
605 | std r3,PACA_EXSLB+EX_R3(r13) | |
606 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
607 | mfspr r12,SPRN_SRR1 | |
608 | crclr 4*cr6+eq | |
609 | #ifndef CONFIG_RELOCATABLE | |
610 | b slb_miss_realmode | |
611 | #else | |
612 | mfctr r11 | |
613 | LOAD_HANDLER(r10, slb_miss_realmode) | |
614 | mtctr r10 | |
615 | bctr | |
616 | #endif | |
1a6822d1 | 617 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80) |
8d04631a NP |
618 | TRAMP_KVM(PACA_EXSLB, 0x480) |
619 | ||
620 | ||
621 | /* This handler is used by both 0x380 and 0x480 slb miss interrupts */ | |
622 | EXC_COMMON_BEGIN(slb_miss_realmode) | |
623 | /* | |
624 | * r13 points to the PACA, r9 contains the saved CR, | |
625 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
626 | * r3 has the faulting address | |
627 | * r9 - r13 are saved in paca->exslb. | |
628 | * r3 is saved in paca->slb_r3 | |
629 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss | |
630 | * We assume we aren't going to take any exceptions during this | |
631 | * procedure. | |
632 | */ | |
633 | mflr r10 | |
634 | #ifdef CONFIG_RELOCATABLE | |
635 | mtctr r11 | |
636 | #endif | |
637 | ||
638 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
639 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
640 | std r3,PACA_EXSLB+EX_DAR(r13) | |
641 | ||
642 | crset 4*cr0+eq | |
643 | #ifdef CONFIG_PPC_STD_MMU_64 | |
644 | BEGIN_MMU_FTR_SECTION | |
645 | bl slb_allocate_realmode | |
646 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) | |
647 | #endif | |
648 | ||
649 | ld r10,PACA_EXSLB+EX_LR(r13) | |
650 | ld r3,PACA_EXSLB+EX_R3(r13) | |
651 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
652 | mtlr r10 | |
653 | ||
654 | beq 8f /* if bad address, make full stack frame */ | |
655 | ||
656 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
657 | beq- 2f | |
658 | ||
659 | /* All done -- return from exception. */ | |
660 | ||
661 | .machine push | |
662 | .machine "power4" | |
663 | mtcrf 0x80,r9 | |
664 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ | |
665 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
666 | .machine pop | |
667 | ||
668 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
669 | ld r9,PACA_EXSLB+EX_R9(r13) | |
670 | ld r10,PACA_EXSLB+EX_R10(r13) | |
671 | ld r11,PACA_EXSLB+EX_R11(r13) | |
672 | ld r12,PACA_EXSLB+EX_R12(r13) | |
673 | ld r13,PACA_EXSLB+EX_R13(r13) | |
674 | rfid | |
675 | b . /* prevent speculative execution */ | |
676 | ||
677 | 2: mfspr r11,SPRN_SRR0 | |
678 | LOAD_HANDLER(r10,unrecov_slb) | |
679 | mtspr SPRN_SRR0,r10 | |
680 | ld r10,PACAKMSR(r13) | |
681 | mtspr SPRN_SRR1,r10 | |
682 | rfid | |
683 | b . | |
684 | ||
685 | 8: mfspr r11,SPRN_SRR0 | |
686 | LOAD_HANDLER(r10,bad_addr_slb) | |
687 | mtspr SPRN_SRR0,r10 | |
688 | ld r10,PACAKMSR(r13) | |
689 | mtspr SPRN_SRR1,r10 | |
690 | rfid | |
691 | b . | |
692 | ||
693 | EXC_COMMON_BEGIN(unrecov_slb) | |
694 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
695 | RECONCILE_IRQ_STATE(r10, r11) | |
696 | bl save_nvgprs | |
697 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
698 | bl unrecoverable_exception | |
699 | b 1b | |
700 | ||
701 | EXC_COMMON_BEGIN(bad_addr_slb) | |
702 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) | |
703 | RECONCILE_IRQ_STATE(r10, r11) | |
704 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
705 | std r3, _DAR(r1) | |
706 | beq cr6, 2f | |
707 | li r10, 0x480 /* fix trap number for I-SLB miss */ | |
708 | std r10, _TRAP(r1) | |
709 | 2: bl save_nvgprs | |
710 | addi r3, r1, STACK_FRAME_OVERHEAD | |
711 | bl slb_miss_bad_addr | |
712 | b ret_from_except | |
713 | ||
1a6822d1 | 714 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100) |
b3e6b5df | 715 | .globl hardware_interrupt_hv; |
b3e6b5df | 716 | hardware_interrupt_hv: |
a5d4f3ad | 717 | BEGIN_FTR_SECTION |
da2bc464 | 718 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 719 | EXC_HV, SOFTEN_TEST_HV) |
da2bc464 | 720 | do_kvm_H0x500: |
b01c8b54 | 721 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) |
de56a948 | 722 | FTR_SECTION_ELSE |
da2bc464 | 723 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 724 | EXC_STD, SOFTEN_TEST_PR) |
da2bc464 | 725 | do_kvm_0x500: |
de56a948 | 726 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 727 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
1a6822d1 | 728 | EXC_REAL_END(hardware_interrupt, 0x500, 0x100) |
da2bc464 | 729 | |
1a6822d1 | 730 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100) |
c138e588 NP |
731 | .globl hardware_interrupt_relon_hv; |
732 | hardware_interrupt_relon_hv: | |
733 | BEGIN_FTR_SECTION | |
734 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) | |
735 | FTR_SECTION_ELSE | |
736 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) | |
737 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1a6822d1 | 738 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100) |
c138e588 NP |
739 | |
740 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) | |
741 | ||
742 | ||
1a6822d1 NP |
743 | EXC_REAL(alignment, 0x600, 0x100) |
744 | EXC_VIRT(alignment, 0x4600, 0x100, 0x600) | |
da2bc464 | 745 | TRAMP_KVM(PACA_EXGEN, 0x600) |
f9aa6714 NP |
746 | EXC_COMMON_BEGIN(alignment_common) |
747 | mfspr r10,SPRN_DAR | |
748 | std r10,PACA_EXGEN+EX_DAR(r13) | |
749 | mfspr r10,SPRN_DSISR | |
750 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
751 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
752 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
753 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
754 | std r3,_DAR(r1) | |
755 | std r4,_DSISR(r1) | |
756 | bl save_nvgprs | |
757 | RECONCILE_IRQ_STATE(r10, r11) | |
758 | addi r3,r1,STACK_FRAME_OVERHEAD | |
759 | bl alignment_exception | |
760 | b ret_from_except | |
761 | ||
da2bc464 | 762 | |
1a6822d1 NP |
763 | EXC_REAL(program_check, 0x700, 0x100) |
764 | EXC_VIRT(program_check, 0x4700, 0x100, 0x700) | |
da2bc464 | 765 | TRAMP_KVM(PACA_EXGEN, 0x700) |
11e87346 NP |
766 | EXC_COMMON_BEGIN(program_check_common) |
767 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
768 | bl save_nvgprs | |
769 | RECONCILE_IRQ_STATE(r10, r11) | |
770 | addi r3,r1,STACK_FRAME_OVERHEAD | |
771 | bl program_check_exception | |
772 | b ret_from_except | |
773 | ||
b01c8b54 | 774 | |
1a6822d1 NP |
775 | EXC_REAL(fp_unavailable, 0x800, 0x100) |
776 | EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800) | |
da2bc464 | 777 | TRAMP_KVM(PACA_EXGEN, 0x800) |
c78d9b97 NP |
778 | EXC_COMMON_BEGIN(fp_unavailable_common) |
779 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
780 | bne 1f /* if from user, just load it up */ | |
781 | bl save_nvgprs | |
782 | RECONCILE_IRQ_STATE(r10, r11) | |
783 | addi r3,r1,STACK_FRAME_OVERHEAD | |
784 | bl kernel_fp_unavailable_exception | |
785 | BUG_OPCODE | |
786 | 1: | |
787 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
788 | BEGIN_FTR_SECTION | |
789 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
790 | * transaction), go do TM stuff | |
791 | */ | |
792 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
793 | bne- 2f | |
794 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
795 | #endif | |
796 | bl load_up_fpu | |
797 | b fast_exception_return | |
798 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
799 | 2: /* User process was in a transaction */ | |
800 | bl save_nvgprs | |
801 | RECONCILE_IRQ_STATE(r10, r11) | |
802 | addi r3,r1,STACK_FRAME_OVERHEAD | |
803 | bl fp_unavailable_tm | |
804 | b ret_from_except | |
805 | #endif | |
806 | ||
a5d4f3ad | 807 | |
1a6822d1 NP |
808 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x80) |
809 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900) | |
39c0da57 NP |
810 | TRAMP_KVM(PACA_EXGEN, 0x900) |
811 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) | |
812 | ||
a485c709 | 813 | |
1a6822d1 NP |
814 | EXC_REAL_HV(hdecrementer, 0x980, 0x80) |
815 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980) | |
facc6d74 NP |
816 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) |
817 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) | |
818 | ||
a5d4f3ad | 819 | |
1a6822d1 NP |
820 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100) |
821 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00) | |
da2bc464 | 822 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
ca243163 NP |
823 | #ifdef CONFIG_PPC_DOORBELL |
824 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) | |
825 | #else | |
826 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) | |
827 | #endif | |
828 | ||
0ebc4cda | 829 | |
1a6822d1 NP |
830 | EXC_REAL(trap_0b, 0xb00, 0x100) |
831 | EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00) | |
da2bc464 | 832 | TRAMP_KVM(PACA_EXGEN, 0xb00) |
341215dc NP |
833 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
834 | ||
fb479e44 NP |
835 | #define LOAD_SYSCALL_HANDLER(reg) \ |
836 | __LOAD_HANDLER(reg, system_call_common) | |
d807ad37 NP |
837 | |
838 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ | |
839 | #define SYSCALL_PSERIES_1 \ | |
840 | BEGIN_FTR_SECTION \ | |
841 | cmpdi r0,0x1ebe ; \ | |
842 | beq- 1f ; \ | |
843 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
844 | mr r9,r13 ; \ | |
845 | GET_PACA(r13) ; \ | |
846 | mfspr r11,SPRN_SRR0 ; \ | |
847 | 0: | |
848 | ||
849 | #define SYSCALL_PSERIES_2_RFID \ | |
850 | mfspr r12,SPRN_SRR1 ; \ | |
851 | LOAD_SYSCALL_HANDLER(r10) ; \ | |
852 | mtspr SPRN_SRR0,r10 ; \ | |
853 | ld r10,PACAKMSR(r13) ; \ | |
854 | mtspr SPRN_SRR1,r10 ; \ | |
855 | rfid ; \ | |
856 | b . ; /* prevent speculative execution */ | |
857 | ||
858 | #define SYSCALL_PSERIES_3 \ | |
859 | /* Fast LE/BE switch system call */ \ | |
860 | 1: mfspr r12,SPRN_SRR1 ; \ | |
861 | xori r12,r12,MSR_LE ; \ | |
862 | mtspr SPRN_SRR1,r12 ; \ | |
863 | rfid ; /* return to userspace */ \ | |
864 | b . ; /* prevent speculative execution */ | |
865 | ||
866 | #if defined(CONFIG_RELOCATABLE) | |
867 | /* | |
868 | * We can't branch directly so we do it via the CTR which | |
869 | * is volatile across system calls. | |
870 | */ | |
871 | #define SYSCALL_PSERIES_2_DIRECT \ | |
872 | LOAD_SYSCALL_HANDLER(r12) ; \ | |
873 | mtctr r12 ; \ | |
874 | mfspr r12,SPRN_SRR1 ; \ | |
875 | li r10,MSR_RI ; \ | |
876 | mtmsrd r10,1 ; \ | |
877 | bctr ; | |
878 | #else | |
879 | /* We can branch directly */ | |
880 | #define SYSCALL_PSERIES_2_DIRECT \ | |
881 | mfspr r12,SPRN_SRR1 ; \ | |
882 | li r10,MSR_RI ; \ | |
883 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
884 | b system_call_common ; | |
885 | #endif | |
886 | ||
1a6822d1 | 887 | EXC_REAL_BEGIN(system_call, 0xc00, 0x100) |
8b91a255 SW |
888 | /* |
889 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems | |
890 | * that support it) before changing to HMT_MEDIUM. That allows the KVM | |
891 | * code to save that value into the guest state (it is the guest's PPR | |
892 | * value). Otherwise just change to HMT_MEDIUM as userspace has | |
893 | * already saved the PPR. | |
894 | */ | |
b01c8b54 PM |
895 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
896 | SET_SCRATCH0(r13) | |
897 | GET_PACA(r13) | |
898 | std r9,PACA_EXGEN+EX_R9(r13) | |
8b91a255 SW |
899 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); |
900 | HMT_MEDIUM; | |
b01c8b54 | 901 | std r10,PACA_EXGEN+EX_R10(r13) |
8b91a255 | 902 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); |
b01c8b54 | 903 | mfcr r9 |
da2bc464 | 904 | KVMTEST_PR(0xc00) |
b01c8b54 | 905 | GET_SCRATCH0(r13) |
8b91a255 SW |
906 | #else |
907 | HMT_MEDIUM; | |
b01c8b54 | 908 | #endif |
742415d6 MN |
909 | SYSCALL_PSERIES_1 |
910 | SYSCALL_PSERIES_2_RFID | |
911 | SYSCALL_PSERIES_3 | |
1a6822d1 | 912 | EXC_REAL_END(system_call, 0xc00, 0x100) |
da2bc464 | 913 | |
1a6822d1 | 914 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100) |
d807ad37 NP |
915 | HMT_MEDIUM |
916 | SYSCALL_PSERIES_1 | |
917 | SYSCALL_PSERIES_2_DIRECT | |
918 | SYSCALL_PSERIES_3 | |
1a6822d1 | 919 | EXC_VIRT_END(system_call, 0x4c00, 0x100) |
d807ad37 | 920 | |
da2bc464 ME |
921 | TRAMP_KVM(PACA_EXGEN, 0xc00) |
922 | ||
d807ad37 | 923 | |
1a6822d1 NP |
924 | EXC_REAL(single_step, 0xd00, 0x100) |
925 | EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00) | |
da2bc464 | 926 | TRAMP_KVM(PACA_EXGEN, 0xd00) |
bc6675c6 | 927 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
b01c8b54 | 928 | |
1a6822d1 NP |
929 | EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20) |
930 | EXC_VIRT_NONE(0x4e00, 0x20) | |
f5c32c1d NP |
931 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) |
932 | EXC_COMMON_BEGIN(h_data_storage_common) | |
933 | mfspr r10,SPRN_HDAR | |
934 | std r10,PACA_EXGEN+EX_DAR(r13) | |
935 | mfspr r10,SPRN_HDSISR | |
936 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
937 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
938 | bl save_nvgprs | |
939 | RECONCILE_IRQ_STATE(r10, r11) | |
940 | addi r3,r1,STACK_FRAME_OVERHEAD | |
941 | bl unknown_exception | |
942 | b ret_from_except | |
f5c32c1d | 943 | |
1707dd16 | 944 | |
1a6822d1 NP |
945 | EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20) |
946 | EXC_VIRT_NONE(0x4e20, 0x20) | |
82517cab NP |
947 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) |
948 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) | |
949 | ||
1707dd16 | 950 | |
1a6822d1 NP |
951 | EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20) |
952 | EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40) | |
031b4026 NP |
953 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) |
954 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) | |
955 | ||
1707dd16 | 956 | |
e0319829 NP |
957 | /* |
958 | * hmi_exception trampoline is a special case. It jumps to hmi_exception_early | |
959 | * first, and then eventaully from there to the trampoline to get into virtual | |
960 | * mode. | |
961 | */ | |
1a6822d1 | 962 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early) |
852e5da9 | 963 | __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
1a6822d1 | 964 | EXC_VIRT_NONE(0x4e60, 0x20) |
62f9b03b NP |
965 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) |
966 | TRAMP_REAL_BEGIN(hmi_exception_early) | |
967 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) | |
968 | mr r10,r1 /* Save r1 */ | |
969 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
970 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
971 | std r9,_CCR(r1) /* save CR in stackframe */ | |
972 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ | |
973 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ | |
974 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ | |
975 | std r12,_MSR(r1) /* save SRR1 in stackframe */ | |
976 | std r10,0(r1) /* make stack chain pointer */ | |
977 | std r0,GPR0(r1) /* save r0 in stackframe */ | |
978 | std r10,GPR1(r1) /* save r1 in stackframe */ | |
979 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) | |
980 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
981 | addi r3,r1,STACK_FRAME_OVERHEAD | |
982 | bl hmi_exception_realmode | |
983 | /* Windup the stack. */ | |
984 | /* Move original HSRR0 and HSRR1 into the respective regs */ | |
985 | ld r9,_MSR(r1) | |
986 | mtspr SPRN_HSRR1,r9 | |
987 | ld r3,_NIP(r1) | |
988 | mtspr SPRN_HSRR0,r3 | |
989 | ld r9,_CTR(r1) | |
990 | mtctr r9 | |
991 | ld r9,_XER(r1) | |
992 | mtxer r9 | |
993 | ld r9,_LINK(r1) | |
994 | mtlr r9 | |
995 | REST_GPR(0, r1) | |
996 | REST_8GPRS(2, r1) | |
997 | REST_GPR(10, r1) | |
998 | ld r11,_CCR(r1) | |
999 | mtcr r11 | |
1000 | REST_GPR(11, r1) | |
1001 | REST_2GPRS(12, r1) | |
1002 | /* restore original r1. */ | |
1003 | ld r1,GPR1(r1) | |
1004 | ||
1005 | /* | |
1006 | * Go to virtual mode and pull the HMI event information from | |
1007 | * firmware. | |
1008 | */ | |
1009 | .globl hmi_exception_after_realmode | |
1010 | hmi_exception_after_realmode: | |
1011 | SET_SCRATCH0(r13) | |
1012 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
1013 | b tramp_real_hmi_exception | |
1014 | ||
1015 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) | |
1016 | ||
1707dd16 | 1017 | |
1a6822d1 NP |
1018 | EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20) |
1019 | EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80) | |
9bcb81bf NP |
1020 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) |
1021 | #ifdef CONFIG_PPC_DOORBELL | |
1022 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) | |
1023 | #else | |
1024 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) | |
1025 | #endif | |
1026 | ||
0ebc4cda | 1027 | |
1a6822d1 NP |
1028 | EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20) |
1029 | EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0) | |
74408776 NP |
1030 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) |
1031 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) | |
1032 | ||
9baaef0a | 1033 | |
1a6822d1 NP |
1034 | EXC_REAL_NONE(0xec0, 0x20) |
1035 | EXC_VIRT_NONE(0x4ec0, 0x20) | |
1036 | EXC_REAL_NONE(0xee0, 0x20) | |
1037 | EXC_VIRT_NONE(0x4ee0, 0x20) | |
bda7fea2 | 1038 | |
0ebc4cda | 1039 | |
1a6822d1 NP |
1040 | EXC_REAL_OOL(performance_monitor, 0xf00, 0x20) |
1041 | EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00) | |
b1c7f150 NP |
1042 | TRAMP_KVM(PACA_EXGEN, 0xf00) |
1043 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) | |
1044 | ||
0ebc4cda | 1045 | |
1a6822d1 NP |
1046 | EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20) |
1047 | EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20) | |
d1a0ca9c NP |
1048 | TRAMP_KVM(PACA_EXGEN, 0xf20) |
1049 | EXC_COMMON_BEGIN(altivec_unavailable_common) | |
1050 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1051 | #ifdef CONFIG_ALTIVEC | |
1052 | BEGIN_FTR_SECTION | |
1053 | beq 1f | |
1054 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1055 | BEGIN_FTR_SECTION_NESTED(69) | |
1056 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1057 | * transaction), go do TM stuff | |
1058 | */ | |
1059 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1060 | bne- 2f | |
1061 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1062 | #endif | |
1063 | bl load_up_altivec | |
1064 | b fast_exception_return | |
1065 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1066 | 2: /* User process was in a transaction */ | |
1067 | bl save_nvgprs | |
1068 | RECONCILE_IRQ_STATE(r10, r11) | |
1069 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1070 | bl altivec_unavailable_tm | |
1071 | b ret_from_except | |
1072 | #endif | |
1073 | 1: | |
1074 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1075 | #endif | |
1076 | bl save_nvgprs | |
1077 | RECONCILE_IRQ_STATE(r10, r11) | |
1078 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1079 | bl altivec_unavailable_exception | |
1080 | b ret_from_except | |
1081 | ||
0ebc4cda | 1082 | |
1a6822d1 NP |
1083 | EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20) |
1084 | EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40) | |
792cbddd NP |
1085 | TRAMP_KVM(PACA_EXGEN, 0xf40) |
1086 | EXC_COMMON_BEGIN(vsx_unavailable_common) | |
1087 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) | |
1088 | #ifdef CONFIG_VSX | |
1089 | BEGIN_FTR_SECTION | |
1090 | beq 1f | |
1091 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1092 | BEGIN_FTR_SECTION_NESTED(69) | |
1093 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1094 | * transaction), go do TM stuff | |
1095 | */ | |
1096 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1097 | bne- 2f | |
1098 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1099 | #endif | |
1100 | b load_up_vsx | |
1101 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1102 | 2: /* User process was in a transaction */ | |
1103 | bl save_nvgprs | |
1104 | RECONCILE_IRQ_STATE(r10, r11) | |
1105 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1106 | bl vsx_unavailable_tm | |
1107 | b ret_from_except | |
1108 | #endif | |
1109 | 1: | |
1110 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1111 | #endif | |
1112 | bl save_nvgprs | |
1113 | RECONCILE_IRQ_STATE(r10, r11) | |
1114 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1115 | bl vsx_unavailable_exception | |
1116 | b ret_from_except | |
1117 | ||
da2bc464 | 1118 | |
1a6822d1 NP |
1119 | EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20) |
1120 | EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60) | |
1134713c NP |
1121 | TRAMP_KVM(PACA_EXGEN, 0xf60) |
1122 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) | |
1123 | ||
da2bc464 | 1124 | |
1a6822d1 NP |
1125 | EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20) |
1126 | EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80) | |
14b0072c NP |
1127 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) |
1128 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) | |
1129 | ||
da2bc464 | 1130 | |
1a6822d1 NP |
1131 | EXC_REAL_NONE(0xfa0, 0x20) |
1132 | EXC_VIRT_NONE(0x4fa0, 0x20) | |
1133 | EXC_REAL_NONE(0xfc0, 0x20) | |
1134 | EXC_VIRT_NONE(0x4fc0, 0x20) | |
1135 | EXC_REAL_NONE(0xfe0, 0x20) | |
1136 | EXC_VIRT_NONE(0x4fe0, 0x20) | |
1137 | ||
1138 | EXC_REAL_NONE(0x1000, 0x100) | |
1139 | EXC_VIRT_NONE(0x5000, 0x100) | |
1140 | EXC_REAL_NONE(0x1100, 0x100) | |
1141 | EXC_VIRT_NONE(0x5100, 0x100) | |
d0c0c9a1 | 1142 | |
0ebc4cda | 1143 | #ifdef CONFIG_CBE_RAS |
1a6822d1 NP |
1144 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x100) |
1145 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1146 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) |
ff1b3206 | 1147 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1148 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1149 | EXC_REAL_NONE(0x1200, 0x100) |
1150 | EXC_VIRT_NONE(0x5200, 0x100) | |
da2bc464 | 1151 | #endif |
b01c8b54 | 1152 | |
ff1b3206 | 1153 | |
1a6822d1 NP |
1154 | EXC_REAL(instruction_breakpoint, 0x1300, 0x100) |
1155 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300) | |
da2bc464 | 1156 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
4e96dbbf NP |
1157 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
1158 | ||
1a6822d1 NP |
1159 | EXC_REAL_NONE(0x1400, 0x100) |
1160 | EXC_VIRT_NONE(0x5400, 0x100) | |
da2bc464 | 1161 | |
1a6822d1 | 1162 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100) |
b92a66a6 | 1163 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 1164 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 1165 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
1166 | |
1167 | #ifdef CONFIG_PPC_DENORMALISATION | |
1168 | mfspr r10,SPRN_HSRR1 | |
1169 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
afcf0095 NP |
1170 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ |
1171 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
1172 | bne+ denorm_assist | |
1173 | #endif | |
1e9b4507 | 1174 | |
afcf0095 NP |
1175 | KVMTEST_PR(0x1500) |
1176 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) | |
1a6822d1 | 1177 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100) |
a74599a5 | 1178 | |
d7e89849 | 1179 | #ifdef CONFIG_PPC_DENORMALISATION |
1a6822d1 | 1180 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1181 | b exc_real_0x1500_denorm_exception_hv |
1a6822d1 | 1182 | EXC_VIRT_END(denorm_exception, 0x5500, 0x100) |
d7e89849 | 1183 | #else |
1a6822d1 | 1184 | EXC_VIRT_NONE(0x5500, 0x100) |
afcf0095 NP |
1185 | #endif |
1186 | ||
d7e89849 | 1187 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) |
b01c8b54 | 1188 | |
b92a66a6 | 1189 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 1190 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
1191 | BEGIN_FTR_SECTION |
1192 | /* | |
1193 | * To denormalise we need to move a copy of the register to itself. | |
1194 | * For POWER6 do that here for all FP regs. | |
1195 | */ | |
1196 | mfmsr r10 | |
1197 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
1198 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
1199 | mtmsrd r10 | |
1200 | sync | |
d7c67fb1 MN |
1201 | |
1202 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
1203 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
1204 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
1205 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
1206 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
1207 | FMR32(0) | |
1208 | ||
b92a66a6 MN |
1209 | FTR_SECTION_ELSE |
1210 | /* | |
1211 | * To denormalise we need to move a copy of the register to itself. | |
1212 | * For POWER7 do that here for the first 32 VSX registers only. | |
1213 | */ | |
1214 | mfmsr r10 | |
1215 | oris r10,r10,MSR_VSX@h | |
1216 | mtmsrd r10 | |
1217 | sync | |
d7c67fb1 MN |
1218 | |
1219 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
1220 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
1221 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
1222 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
1223 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
1224 | XVCPSGNDP32(0) | |
1225 | ||
b92a66a6 | 1226 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
1227 | |
1228 | BEGIN_FTR_SECTION | |
1229 | b denorm_done | |
1230 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
1231 | /* | |
1232 | * To denormalise we need to move a copy of the register to itself. | |
1233 | * For POWER8 we need to do that for all 64 VSX registers | |
1234 | */ | |
1235 | XVCPSGNDP32(32) | |
1236 | denorm_done: | |
b92a66a6 MN |
1237 | mtspr SPRN_HSRR0,r11 |
1238 | mtcrf 0x80,r9 | |
1239 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 1240 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
1241 | BEGIN_FTR_SECTION |
1242 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
1243 | mtspr SPRN_CFAR,r10 | |
1244 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
1245 | ld r10,PACA_EXGEN+EX_R10(r13) |
1246 | ld r11,PACA_EXGEN+EX_R11(r13) | |
1247 | ld r12,PACA_EXGEN+EX_R12(r13) | |
1248 | ld r13,PACA_EXGEN+EX_R13(r13) | |
1249 | HRFID | |
1250 | b . | |
1251 | #endif | |
1252 | ||
d7e89849 NP |
1253 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
1254 | ||
1255 | ||
1256 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1257 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100) |
1258 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 | 1259 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
69a79344 | 1260 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
d7e89849 | 1261 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1262 | EXC_REAL_NONE(0x1600, 0x100) |
1263 | EXC_VIRT_NONE(0x5600, 0x100) | |
d7e89849 NP |
1264 | #endif |
1265 | ||
69a79344 | 1266 | |
1a6822d1 NP |
1267 | EXC_REAL(altivec_assist, 0x1700, 0x100) |
1268 | EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700) | |
d7e89849 | 1269 | TRAMP_KVM(PACA_EXGEN, 0x1700) |
b51c079e NP |
1270 | #ifdef CONFIG_ALTIVEC |
1271 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) | |
1272 | #else | |
1273 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) | |
1274 | #endif | |
1275 | ||
d7e89849 NP |
1276 | |
1277 | #ifdef CONFIG_CBE_RAS | |
1a6822d1 NP |
1278 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x100) |
1279 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 | 1280 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) |
3965f8ab | 1281 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
d7e89849 | 1282 | #else /* CONFIG_CBE_RAS */ |
1a6822d1 NP |
1283 | EXC_REAL_NONE(0x1800, 0x100) |
1284 | EXC_VIRT_NONE(0x5800, 0x100) | |
d7e89849 NP |
1285 | #endif |
1286 | ||
1287 | ||
0ebc4cda | 1288 | /* |
fe9e1d54 IM |
1289 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
1290 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
1291 | * - If it was a doorbell we return immediately since doorbells are edge | |
1292 | * triggered and won't automatically refire. | |
0869b6fd MS |
1293 | * - If it was a HMI we return immediately since we handled it in realmode |
1294 | * and it won't refire. | |
fe9e1d54 IM |
1295 | * - else we hard disable and return. |
1296 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 1297 | */ |
7230c564 BH |
1298 | #define MASKED_INTERRUPT(_H) \ |
1299 | masked_##_H##interrupt: \ | |
1300 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
1301 | lbz r11,PACAIRQHAPPENED(r13); \ | |
1302 | or r11,r11,r10; \ | |
1303 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
1304 | cmpwi r10,PACA_IRQ_DEC; \ |
1305 | bne 1f; \ | |
7230c564 BH |
1306 | lis r10,0x7fff; \ |
1307 | ori r10,r10,0xffff; \ | |
1308 | mtspr SPRN_DEC,r10; \ | |
1309 | b 2f; \ | |
fe9e1d54 | 1310 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
0869b6fd MS |
1311 | beq 2f; \ |
1312 | cmpwi r10,PACA_IRQ_HMI; \ | |
fe9e1d54 IM |
1313 | beq 2f; \ |
1314 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
1315 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
1316 | rotldi r10,r10,16; \ | |
1317 | mtspr SPRN_##_H##SRR1,r10; \ | |
1318 | 2: mtcrf 0x80,r9; \ | |
1319 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
1320 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
1321 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
1322 | GET_SCRATCH0(r13); \ | |
1323 | ##_H##rfid; \ | |
0ebc4cda | 1324 | b . |
57f26649 NP |
1325 | |
1326 | /* | |
1327 | * Real mode exceptions actually use this too, but alternate | |
1328 | * instruction code patches (which end up in the common .text area) | |
1329 | * cannot reach these if they are put there. | |
1330 | */ | |
1331 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
1332 | MASKED_INTERRUPT() |
1333 | MASKED_INTERRUPT(H) | |
0ebc4cda | 1334 | |
4f6c11db | 1335 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 1336 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
1337 | /* |
1338 | * Here all GPRs are unchanged from when the interrupt happened | |
1339 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1340 | */ | |
1341 | mfspr r13, SPRN_SRR0 | |
1342 | addi r13, r13, 4 | |
1343 | mtspr SPRN_SRR0, r13 | |
1344 | GET_SCRATCH0(r13) | |
1345 | rfid | |
1346 | b . | |
1347 | ||
da2bc464 | 1348 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
1349 | /* |
1350 | * Here all GPRs are unchanged from when the interrupt happened | |
1351 | * except for r13, which is saved in SPRG_SCRATCH0. | |
1352 | */ | |
1353 | mfspr r13, SPRN_HSRR0 | |
1354 | addi r13, r13, 4 | |
1355 | mtspr SPRN_HSRR0, r13 | |
1356 | GET_SCRATCH0(r13) | |
1357 | hrfid | |
1358 | b . | |
1359 | #endif | |
1360 | ||
0ebc4cda | 1361 | /* |
057b6d7e HB |
1362 | * Ensure that any handlers that get invoked from the exception prologs |
1363 | * above are below the first 64KB (0x10000) of the kernel image because | |
1364 | * the prologs assemble the addresses of these handlers using the | |
1365 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
1366 | */ |
1367 | ||
1368 | /*** Common interrupt handlers ***/ | |
1369 | ||
0ebc4cda | 1370 | |
c1fb6816 MN |
1371 | /* |
1372 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
1373 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
1374 | * it. Addresses are the same as the original interrupt addresses, but | |
1375 | * offset by 0xc000000000004000. | |
1376 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
1377 | * KVM: None of these traps are from the guest ; anything that escalated | |
1378 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
1379 | */ | |
1380 | ||
1381 | /* | |
1382 | * This uses the standard macro, since the original 0x300 vector | |
1383 | * only has extra guff for STAB-based processors -- which never | |
1384 | * come here. | |
1385 | */ | |
da2bc464 | 1386 | |
57f26649 | 1387 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 1388 | b __ppc64_runlatch_on |
fe1952fc | 1389 | |
57f26649 | 1390 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1391 | /* |
1392 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1393 | * handlers, so that they are copied to real address 0x100 when running | |
1394 | * a relocatable kernel. This ensures they can be reached from the short | |
1395 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1396 | * directly, without using LOAD_HANDLER(). | |
1397 | */ | |
1398 | .align 7 | |
1399 | .globl __end_interrupts | |
1400 | __end_interrupts: | |
57f26649 | 1401 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1402 | |
087aa036 | 1403 | #ifdef CONFIG_PPC_970_NAP |
7c8cb4b5 | 1404 | EXC_COMMON_BEGIN(power4_fixup_nap) |
087aa036 CG |
1405 | andc r9,r9,r10 |
1406 | std r9,TI_LOCAL_FLAGS(r11) | |
1407 | ld r10,_LINK(r1) /* make idle task do the */ | |
1408 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1409 | blr | |
1410 | #endif | |
1411 | ||
57f26649 NP |
1412 | CLOSE_FIXED_SECTION(real_vectors); |
1413 | CLOSE_FIXED_SECTION(real_trampolines); | |
1414 | CLOSE_FIXED_SECTION(virt_vectors); | |
1415 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1416 | ||
1417 | USE_TEXT_SECTION() | |
1418 | ||
0ebc4cda BH |
1419 | /* |
1420 | * Hash table stuff | |
1421 | */ | |
f4329f2e | 1422 | .balign IFETCH_ALIGN_BYTES |
6a3bab90 | 1423 | do_hash_page: |
caca285e | 1424 | #ifdef CONFIG_PPC_STD_MMU_64 |
9c7cc234 | 1425 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1426 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1427 | andis. r0,r4,DSISR_DABRMATCH@h |
1428 | bne- handle_dabr_fault | |
9778b696 | 1429 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1430 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1431 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1432 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1433 | |
1434 | /* | |
1435 | * r3 contains the faulting address | |
106713a1 | 1436 | * r4 msr |
0ebc4cda | 1437 | * r5 contains the trap number |
aefa5688 | 1438 | * r6 contains dsisr |
0ebc4cda | 1439 | * |
7230c564 | 1440 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1441 | */ |
106713a1 | 1442 | mr r4,r12 |
aefa5688 | 1443 | ld r6,_DSISR(r1) |
106713a1 AK |
1444 | bl __hash_page /* build HPTE if possible */ |
1445 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1446 | |
7230c564 | 1447 | /* Success */ |
0ebc4cda | 1448 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1449 | |
7230c564 BH |
1450 | /* Error */ |
1451 | blt- 13f | |
caca285e | 1452 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
9c7cc234 | 1453 | |
0ebc4cda BH |
1454 | /* Here we have a page fault that hash_page can't handle. */ |
1455 | handle_page_fault: | |
0ebc4cda BH |
1456 | 11: ld r4,_DAR(r1) |
1457 | ld r5,_DSISR(r1) | |
1458 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1459 | bl do_page_fault |
0ebc4cda | 1460 | cmpdi r3,0 |
a546498f | 1461 | beq+ 12f |
b1576fec | 1462 | bl save_nvgprs |
0ebc4cda BH |
1463 | mr r5,r3 |
1464 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1465 | lwz r4,_DAR(r1) | |
b1576fec AB |
1466 | bl bad_page_fault |
1467 | b ret_from_except | |
0ebc4cda | 1468 | |
a546498f BH |
1469 | /* We have a data breakpoint exception - handle it */ |
1470 | handle_dabr_fault: | |
b1576fec | 1471 | bl save_nvgprs |
a546498f BH |
1472 | ld r4,_DAR(r1) |
1473 | ld r5,_DSISR(r1) | |
1474 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1475 | bl do_break |
1476 | 12: b ret_from_except_lite | |
a546498f | 1477 | |
0ebc4cda | 1478 | |
caca285e | 1479 | #ifdef CONFIG_PPC_STD_MMU_64 |
0ebc4cda BH |
1480 | /* We have a page fault that hash_page could handle but HV refused |
1481 | * the PTE insertion | |
1482 | */ | |
b1576fec | 1483 | 13: bl save_nvgprs |
0ebc4cda BH |
1484 | mr r5,r3 |
1485 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1486 | ld r4,_DAR(r1) | |
b1576fec AB |
1487 | bl low_hash_fault |
1488 | b ret_from_except | |
caca285e | 1489 | #endif |
0ebc4cda | 1490 | |
9c1e1052 PM |
1491 | /* |
1492 | * We come here as a result of a DSI at a point where we don't want | |
1493 | * to call hash_page, such as when we are accessing memory (possibly | |
1494 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1495 | * were soft-disabled. We want to invoke the exception handler for | |
1496 | * the access, or panic if there isn't a handler. | |
1497 | */ | |
b1576fec | 1498 | 77: bl save_nvgprs |
9c1e1052 PM |
1499 | mr r4,r3 |
1500 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1501 | li r5,SIGSEGV | |
b1576fec AB |
1502 | bl bad_page_fault |
1503 | b ret_from_except | |
4e2bf01b ME |
1504 | |
1505 | /* | |
1506 | * Here we have detected that the kernel stack pointer is bad. | |
1507 | * R9 contains the saved CR, r13 points to the paca, | |
1508 | * r10 contains the (bad) kernel stack pointer, | |
1509 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1510 | * We switch to using an emergency stack, save the registers there, | |
1511 | * and call kernel_bad_stack(), which panics. | |
1512 | */ | |
1513 | bad_stack: | |
1514 | ld r1,PACAEMERGSP(r13) | |
1515 | subi r1,r1,64+INT_FRAME_SIZE | |
1516 | std r9,_CCR(r1) | |
1517 | std r10,GPR1(r1) | |
1518 | std r11,_NIP(r1) | |
1519 | std r12,_MSR(r1) | |
1520 | mfspr r11,SPRN_DAR | |
1521 | mfspr r12,SPRN_DSISR | |
1522 | std r11,_DAR(r1) | |
1523 | std r12,_DSISR(r1) | |
1524 | mflr r10 | |
1525 | mfctr r11 | |
1526 | mfxer r12 | |
1527 | std r10,_LINK(r1) | |
1528 | std r11,_CTR(r1) | |
1529 | std r12,_XER(r1) | |
1530 | SAVE_GPR(0,r1) | |
1531 | SAVE_GPR(2,r1) | |
1532 | ld r10,EX_R3(r3) | |
1533 | std r10,GPR3(r1) | |
1534 | SAVE_GPR(4,r1) | |
1535 | SAVE_4GPRS(5,r1) | |
1536 | ld r9,EX_R9(r3) | |
1537 | ld r10,EX_R10(r3) | |
1538 | SAVE_2GPRS(9,r1) | |
1539 | ld r9,EX_R11(r3) | |
1540 | ld r10,EX_R12(r3) | |
1541 | ld r11,EX_R13(r3) | |
1542 | std r9,GPR11(r1) | |
1543 | std r10,GPR12(r1) | |
1544 | std r11,GPR13(r1) | |
1545 | BEGIN_FTR_SECTION | |
1546 | ld r10,EX_CFAR(r3) | |
1547 | std r10,ORIG_GPR3(r1) | |
1548 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1549 | SAVE_8GPRS(14,r1) | |
1550 | SAVE_10GPRS(22,r1) | |
1551 | lhz r12,PACA_TRAP_SAVE(r13) | |
1552 | std r12,_TRAP(r1) | |
1553 | addi r11,r1,INT_FRAME_SIZE | |
1554 | std r11,0(r1) | |
1555 | li r12,0 | |
1556 | std r12,0(r11) | |
1557 | ld r2,PACATOC(r13) | |
1558 | ld r11,exception_marker@toc(r2) | |
1559 | std r12,RESULT(r1) | |
1560 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1561 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1562 | bl kernel_bad_stack | |
1563 | b 1b | |
0f0c6ca1 NP |
1564 | |
1565 | /* | |
1566 | * Called from arch_local_irq_enable when an interrupt needs | |
1567 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate | |
1568 | * which kind of interrupt. MSR:EE is already off. We generate a | |
1569 | * stackframe like if a real interrupt had happened. | |
1570 | * | |
1571 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
1572 | * in the generated frame has EE set to 1 or the exception | |
1573 | * handler will not properly re-enable them. | |
1574 | */ | |
1575 | _GLOBAL(__replay_interrupt) | |
1576 | /* We are going to jump to the exception common code which | |
1577 | * will retrieve various register values from the PACA which | |
1578 | * we don't give a damn about, so we don't bother storing them. | |
1579 | */ | |
1580 | mfmsr r12 | |
1581 | mflr r11 | |
1582 | mfcr r9 | |
1583 | ori r12,r12,MSR_EE | |
1584 | cmpwi r3,0x900 | |
1585 | beq decrementer_common | |
1586 | cmpwi r3,0x500 | |
1587 | beq hardware_interrupt_common | |
1588 | BEGIN_FTR_SECTION | |
1589 | cmpwi r3,0xe80 | |
1590 | beq h_doorbell_common | |
1591 | cmpwi r3,0xea0 | |
1592 | beq h_virt_irq_common | |
1593 | cmpwi r3,0xe60 | |
1594 | beq hmi_exception_common | |
1595 | FTR_SECTION_ELSE | |
1596 | cmpwi r3,0xa00 | |
1597 | beq doorbell_super_common | |
1598 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
1599 | blr |