]>
Commit | Line | Data |
---|---|---|
2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
14cf11af PM |
2 | /* |
3 | * FPU support code, moved here from head.S so that it can be used | |
4 | * by chips which use other head-whatever.S files. | |
5 | * | |
fea23bfe PM |
6 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
7 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
8 | * Copyright (C) 1996 Paul Mackerras. | |
9 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
14cf11af PM |
10 | */ |
11 | ||
b3b8dc6c | 12 | #include <asm/reg.h> |
14cf11af PM |
13 | #include <asm/page.h> |
14 | #include <asm/mmu.h> | |
15 | #include <asm/pgtable.h> | |
16 | #include <asm/cputable.h> | |
17 | #include <asm/cache.h> | |
18 | #include <asm/thread_info.h> | |
19 | #include <asm/ppc_asm.h> | |
20 | #include <asm/asm-offsets.h> | |
46f52210 | 21 | #include <asm/ptrace.h> |
9445aa1a | 22 | #include <asm/export.h> |
ec0c464c | 23 | #include <asm/asm-compat.h> |
2c86cd18 | 24 | #include <asm/feature-fixups.h> |
14cf11af | 25 | |
72ffff5b | 26 | #ifdef CONFIG_VSX |
0b7673c3 | 27 | #define __REST_32FPVSRS(n,c,base) \ |
72ffff5b MN |
28 | BEGIN_FTR_SECTION \ |
29 | b 2f; \ | |
30 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
31 | REST_32FPRS(n,base); \ | |
32 | b 3f; \ | |
33 | 2: REST_32VSRS(n,c,base); \ | |
34 | 3: | |
35 | ||
0b7673c3 | 36 | #define __SAVE_32FPVSRS(n,c,base) \ |
72ffff5b MN |
37 | BEGIN_FTR_SECTION \ |
38 | b 2f; \ | |
39 | END_FTR_SECTION_IFSET(CPU_FTR_VSX); \ | |
40 | SAVE_32FPRS(n,base); \ | |
41 | b 3f; \ | |
42 | 2: SAVE_32VSRS(n,c,base); \ | |
43 | 3: | |
44 | #else | |
0b7673c3 MN |
45 | #define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base) |
46 | #define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base) | |
72ffff5b | 47 | #endif |
0b7673c3 MN |
48 | #define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base) |
49 | #define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base) | |
72ffff5b | 50 | |
18461960 PM |
51 | /* |
52 | * Load state from memory into FP registers including FPSCR. | |
53 | * Assumes the caller has enabled FP in the MSR. | |
54 | */ | |
55 | _GLOBAL(load_fp_state) | |
56 | lfd fr0,FPSTATE_FPSCR(r3) | |
57 | MTFSF_L(fr0) | |
58 | REST_32FPVSRS(0, R4, R3) | |
59 | blr | |
9445aa1a | 60 | EXPORT_SYMBOL(load_fp_state) |
e2b36d59 | 61 | _ASM_NOKPROBE_SYMBOL(load_fp_state); /* used by restore_math */ |
18461960 PM |
62 | |
63 | /* | |
64 | * Store FP state into memory, including FPSCR | |
65 | * Assumes the caller has enabled FP in the MSR. | |
66 | */ | |
67 | _GLOBAL(store_fp_state) | |
68 | SAVE_32FPVSRS(0, R4, R3) | |
69 | mffs fr0 | |
70 | stfd fr0,FPSTATE_FPSCR(r3) | |
71 | blr | |
9445aa1a | 72 | EXPORT_SYMBOL(store_fp_state) |
18461960 | 73 | |
14cf11af PM |
74 | /* |
75 | * This task wants to use the FPU now. | |
76 | * On UP, disable FP for the task which had the FPU previously, | |
77 | * and save its floating-point registers in its thread_struct. | |
78 | * Load up this task's FP registers from its thread_struct, | |
79 | * enable the FPU for the current task and return to the task. | |
955c1cab PM |
80 | * Note that on 32-bit this can only use registers that will be |
81 | * restored by fast_exception_return, i.e. r3 - r6, r10 and r11. | |
14cf11af | 82 | */ |
b85a046a | 83 | _GLOBAL(load_up_fpu) |
14cf11af PM |
84 | mfmsr r5 |
85 | ori r5,r5,MSR_FP | |
ce48b210 MN |
86 | #ifdef CONFIG_VSX |
87 | BEGIN_FTR_SECTION | |
88 | oris r5,r5,MSR_VSX@h | |
89 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
90 | #endif | |
14cf11af PM |
91 | SYNC |
92 | MTMSRD(r5) /* enable use of fpu now */ | |
93 | isync | |
14cf11af | 94 | /* enable use of FP after return */ |
b85a046a | 95 | #ifdef CONFIG_PPC32 |
de79f7b9 | 96 | mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */ |
14cf11af PM |
97 | lwz r4,THREAD_FPEXC_MODE(r5) |
98 | ori r9,r9,MSR_FP /* enable FP for current */ | |
99 | or r9,r9,r4 | |
b85a046a PM |
100 | #else |
101 | ld r4,PACACURRENT(r13) | |
102 | addi r5,r4,THREAD /* Get THREAD */ | |
e2f5a3c1 | 103 | lwz r4,THREAD_FPEXC_MODE(r5) |
b85a046a PM |
104 | ori r12,r12,MSR_FP |
105 | or r12,r12,r4 | |
106 | std r12,_MSR(r1) | |
107 | #endif | |
70fe3d98 CB |
108 | /* Don't care if r4 overflows, this is desired behaviour */ |
109 | lbz r4,THREAD_LOAD_FP(r5) | |
110 | addi r4,r4,1 | |
111 | stb r4,THREAD_LOAD_FP(r5) | |
955c1cab PM |
112 | addi r10,r5,THREAD_FPSTATE |
113 | lfd fr0,FPSTATE_FPSCR(r10) | |
3a2c48cf | 114 | MTFSF_L(fr0) |
955c1cab | 115 | REST_32FPVSRS(0, R4, R10) |
14cf11af PM |
116 | /* restore registers and return */ |
117 | /* we haven't used ctr or xer or lr */ | |
6f3d8e69 | 118 | blr |
14cf11af | 119 | |
14cf11af | 120 | /* |
8792468d CB |
121 | * save_fpu(tsk) |
122 | * Save the floating-point registers in its thread_struct. | |
14cf11af PM |
123 | * Enables the FPU for use in the kernel on return. |
124 | */ | |
8792468d | 125 | _GLOBAL(save_fpu) |
14cf11af | 126 | addi r3,r3,THREAD /* want THREAD of task */ |
18461960 | 127 | PPC_LL r6,THREAD_FPSAVEAREA(r3) |
3ddfbcf1 | 128 | PPC_LL r5,PT_REGS(r3) |
18461960 PM |
129 | PPC_LCMPI 0,r6,0 |
130 | bne 2f | |
de79f7b9 | 131 | addi r6,r3,THREAD_FPSTATE |
8792468d | 132 | 2: SAVE_32FPVSRS(0, R4, R6) |
14cf11af | 133 | mffs fr0 |
de79f7b9 | 134 | stfd fr0,FPSTATE_FPSCR(r6) |
14cf11af | 135 | blr |
25c8a78b DG |
136 | |
137 | /* | |
138 | * These are used in the alignment trap handler when emulating | |
139 | * single-precision loads and stores. | |
25c8a78b DG |
140 | */ |
141 | ||
142 | _GLOBAL(cvt_fd) | |
25c8a78b DG |
143 | lfs 0,0(r3) |
144 | stfd 0,0(r4) | |
25c8a78b DG |
145 | blr |
146 | ||
147 | _GLOBAL(cvt_df) | |
25c8a78b DG |
148 | lfd 0,0(r3) |
149 | stfs 0,0(r4) | |
25c8a78b | 150 | blr |