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14cf11af PM |
1 | /* |
2 | * PowerPC version | |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
12 | * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk). | |
13 | * | |
14 | * This file contains the low-level support and setup for the | |
15 | * PowerPC platform, including trap and interrupt dispatch. | |
16 | * (The PPC 8xx embedded CPUs use head_8xx.S instead.) | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or | |
19 | * modify it under the terms of the GNU General Public License | |
20 | * as published by the Free Software Foundation; either version | |
21 | * 2 of the License, or (at your option) any later version. | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/config.h> | |
b3b8dc6c | 26 | #include <asm/reg.h> |
14cf11af PM |
27 | #include <asm/page.h> |
28 | #include <asm/mmu.h> | |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/cputable.h> | |
31 | #include <asm/cache.h> | |
32 | #include <asm/thread_info.h> | |
33 | #include <asm/ppc_asm.h> | |
34 | #include <asm/asm-offsets.h> | |
35 | ||
36 | #ifdef CONFIG_APUS | |
37 | #include <asm/amigappc.h> | |
38 | #endif | |
39 | ||
14cf11af PM |
40 | /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */ |
41 | #define LOAD_BAT(n, reg, RA, RB) \ | |
42 | /* see the comment for clear_bats() -- Cort */ \ | |
43 | li RA,0; \ | |
44 | mtspr SPRN_IBAT##n##U,RA; \ | |
45 | mtspr SPRN_DBAT##n##U,RA; \ | |
46 | lwz RA,(n*16)+0(reg); \ | |
47 | lwz RB,(n*16)+4(reg); \ | |
48 | mtspr SPRN_IBAT##n##U,RA; \ | |
49 | mtspr SPRN_IBAT##n##L,RB; \ | |
50 | beq 1f; \ | |
51 | lwz RA,(n*16)+8(reg); \ | |
52 | lwz RB,(n*16)+12(reg); \ | |
53 | mtspr SPRN_DBAT##n##U,RA; \ | |
54 | mtspr SPRN_DBAT##n##L,RB; \ | |
55 | 1: | |
14cf11af PM |
56 | |
57 | .text | |
b3b8dc6c PM |
58 | .stabs "arch/powerpc/kernel/",N_SO,0,0,0f |
59 | .stabs "head_32.S",N_SO,0,0,0f | |
14cf11af PM |
60 | 0: |
61 | .globl _stext | |
62 | _stext: | |
63 | ||
64 | /* | |
65 | * _start is defined this way because the XCOFF loader in the OpenFirmware | |
66 | * on the powermac expects the entry point to be a procedure descriptor. | |
67 | */ | |
68 | .text | |
69 | .globl _start | |
70 | _start: | |
71 | /* | |
72 | * These are here for legacy reasons, the kernel used to | |
73 | * need to look like a coff function entry for the pmac | |
74 | * but we're always started by some kind of bootloader now. | |
75 | * -- Cort | |
76 | */ | |
77 | nop /* used by __secondary_hold on prep (mtx) and chrp smp */ | |
78 | nop /* used by __secondary_hold on prep (mtx) and chrp smp */ | |
79 | nop | |
80 | ||
81 | /* PMAC | |
82 | * Enter here with the kernel text, data and bss loaded starting at | |
83 | * 0, running with virtual == physical mapping. | |
84 | * r5 points to the prom entry point (the client interface handler | |
85 | * address). Address translation is turned on, with the prom | |
86 | * managing the hash table. Interrupts are disabled. The stack | |
87 | * pointer (r1) points to just below the end of the half-meg region | |
88 | * from 0x380000 - 0x400000, which is mapped in already. | |
89 | * | |
90 | * If we are booted from MacOS via BootX, we enter with the kernel | |
91 | * image loaded somewhere, and the following values in registers: | |
92 | * r3: 'BooX' (0x426f6f58) | |
93 | * r4: virtual address of boot_infos_t | |
94 | * r5: 0 | |
95 | * | |
96 | * APUS | |
97 | * r3: 'APUS' | |
98 | * r4: physical address of memory base | |
99 | * Linux/m68k style BootInfo structure at &_end. | |
100 | * | |
101 | * PREP | |
102 | * This is jumped to on prep systems right after the kernel is relocated | |
103 | * to its proper place in memory by the boot loader. The expected layout | |
104 | * of the regs is: | |
105 | * r3: ptr to residual data | |
106 | * r4: initrd_start or if no initrd then 0 | |
107 | * r5: initrd_end - unused if r4 is 0 | |
108 | * r6: Start of command line string | |
109 | * r7: End of command line string | |
110 | * | |
111 | * This just gets a minimal mmu environment setup so we can call | |
112 | * start_here() to do the real work. | |
113 | * -- Cort | |
114 | */ | |
115 | ||
116 | .globl __start | |
117 | __start: | |
118 | /* | |
119 | * We have to do any OF calls before we map ourselves to KERNELBASE, | |
120 | * because OF may have I/O devices mapped into that area | |
121 | * (particularly on CHRP). | |
122 | */ | |
9b6b563c PM |
123 | cmpwi 0,r5,0 |
124 | beq 1f | |
125 | bl prom_init | |
126 | trap | |
127 | ||
128 | 1: mr r31,r3 /* save parameters */ | |
14cf11af | 129 | mr r30,r4 |
14cf11af PM |
130 | li r24,0 /* cpu # */ |
131 | ||
132 | /* | |
133 | * early_init() does the early machine identification and does | |
134 | * the necessary low-level setup and clears the BSS | |
135 | * -- Cort <cort@fsmlabs.com> | |
136 | */ | |
137 | bl early_init | |
138 | ||
14cf11af PM |
139 | #ifdef CONFIG_APUS |
140 | /* On APUS the __va/__pa constants need to be set to the correct | |
141 | * values before continuing. | |
142 | */ | |
143 | mr r4,r30 | |
144 | bl fix_mem_constants | |
145 | #endif /* CONFIG_APUS */ | |
146 | ||
147 | /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains | |
148 | * the physical address we are running at, returned by early_init() | |
149 | */ | |
150 | bl mmu_off | |
151 | __after_mmu_off: | |
14cf11af PM |
152 | bl clear_bats |
153 | bl flush_tlbs | |
154 | ||
155 | bl initial_bats | |
51d3082f BH |
156 | #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) |
157 | bl setup_disp_bat | |
158 | #endif | |
14cf11af PM |
159 | |
160 | /* | |
161 | * Call setup_cpu for CPU 0 and initialize 6xx Idle | |
162 | */ | |
163 | bl reloc_offset | |
164 | li r24,0 /* cpu# */ | |
165 | bl call_setup_cpu /* Call setup_cpu for this CPU */ | |
166 | #ifdef CONFIG_6xx | |
167 | bl reloc_offset | |
168 | bl init_idle_6xx | |
169 | #endif /* CONFIG_6xx */ | |
14cf11af PM |
170 | |
171 | ||
172 | #ifndef CONFIG_APUS | |
173 | /* | |
174 | * We need to run with _start at physical address 0. | |
175 | * On CHRP, we are loaded at 0x10000 since OF on CHRP uses | |
176 | * the exception vectors at 0 (and therefore this copy | |
177 | * overwrites OF's exception vectors with our own). | |
9b6b563c | 178 | * The MMU is off at this point. |
14cf11af PM |
179 | */ |
180 | bl reloc_offset | |
181 | mr r26,r3 | |
182 | addis r4,r3,KERNELBASE@h /* current address of _start */ | |
183 | cmpwi 0,r4,0 /* are we already running at 0? */ | |
184 | bne relocate_kernel | |
185 | #endif /* CONFIG_APUS */ | |
186 | /* | |
187 | * we now have the 1st 16M of ram mapped with the bats. | |
188 | * prep needs the mmu to be turned on here, but pmac already has it on. | |
189 | * this shouldn't bother the pmac since it just gets turned on again | |
190 | * as we jump to our code at KERNELBASE. -- Cort | |
191 | * Actually no, pmac doesn't have it on any more. BootX enters with MMU | |
192 | * off, and in other cases, we now turn it off before changing BATs above. | |
193 | */ | |
194 | turn_on_mmu: | |
195 | mfmsr r0 | |
196 | ori r0,r0,MSR_DR|MSR_IR | |
197 | mtspr SPRN_SRR1,r0 | |
198 | lis r0,start_here@h | |
199 | ori r0,r0,start_here@l | |
200 | mtspr SPRN_SRR0,r0 | |
201 | SYNC | |
202 | RFI /* enables MMU */ | |
203 | ||
204 | /* | |
205 | * We need __secondary_hold as a place to hold the other cpus on | |
206 | * an SMP machine, even when we are running a UP kernel. | |
207 | */ | |
208 | . = 0xc0 /* for prep bootloader */ | |
209 | li r3,1 /* MTX only has 1 cpu */ | |
210 | .globl __secondary_hold | |
211 | __secondary_hold: | |
212 | /* tell the master we're here */ | |
bbd0abda | 213 | stw r3,__secondary_hold_acknowledge@l(0) |
14cf11af PM |
214 | #ifdef CONFIG_SMP |
215 | 100: lwz r4,0(0) | |
216 | /* wait until we're told to start */ | |
217 | cmpw 0,r4,r3 | |
218 | bne 100b | |
219 | /* our cpu # was at addr 0 - go */ | |
220 | mr r24,r3 /* cpu # */ | |
221 | b __secondary_start | |
222 | #else | |
223 | b . | |
224 | #endif /* CONFIG_SMP */ | |
225 | ||
bbd0abda PM |
226 | .globl __secondary_hold_spinloop |
227 | __secondary_hold_spinloop: | |
228 | .long 0 | |
229 | .globl __secondary_hold_acknowledge | |
230 | __secondary_hold_acknowledge: | |
231 | .long -1 | |
232 | ||
14cf11af PM |
233 | /* |
234 | * Exception entry code. This code runs with address translation | |
235 | * turned off, i.e. using physical addresses. | |
236 | * We assume sprg3 has the physical address of the current | |
237 | * task's thread_struct. | |
238 | */ | |
239 | #define EXCEPTION_PROLOG \ | |
240 | mtspr SPRN_SPRG0,r10; \ | |
241 | mtspr SPRN_SPRG1,r11; \ | |
242 | mfcr r10; \ | |
243 | EXCEPTION_PROLOG_1; \ | |
244 | EXCEPTION_PROLOG_2 | |
245 | ||
246 | #define EXCEPTION_PROLOG_1 \ | |
247 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ | |
248 | andi. r11,r11,MSR_PR; \ | |
249 | tophys(r11,r1); /* use tophys(r1) if kernel */ \ | |
250 | beq 1f; \ | |
251 | mfspr r11,SPRN_SPRG3; \ | |
252 | lwz r11,THREAD_INFO-THREAD(r11); \ | |
253 | addi r11,r11,THREAD_SIZE; \ | |
254 | tophys(r11,r11); \ | |
255 | 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ | |
256 | ||
257 | ||
258 | #define EXCEPTION_PROLOG_2 \ | |
259 | CLR_TOP32(r11); \ | |
260 | stw r10,_CCR(r11); /* save registers */ \ | |
261 | stw r12,GPR12(r11); \ | |
262 | stw r9,GPR9(r11); \ | |
263 | mfspr r10,SPRN_SPRG0; \ | |
264 | stw r10,GPR10(r11); \ | |
265 | mfspr r12,SPRN_SPRG1; \ | |
266 | stw r12,GPR11(r11); \ | |
267 | mflr r10; \ | |
268 | stw r10,_LINK(r11); \ | |
269 | mfspr r12,SPRN_SRR0; \ | |
270 | mfspr r9,SPRN_SRR1; \ | |
271 | stw r1,GPR1(r11); \ | |
272 | stw r1,0(r11); \ | |
273 | tovirt(r1,r11); /* set new kernel sp */ \ | |
274 | li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ | |
275 | MTMSRD(r10); /* (except for mach check in rtas) */ \ | |
276 | stw r0,GPR0(r11); \ | |
f78541dc PM |
277 | lis r10,0x7265; /* put exception frame marker */ \ |
278 | addi r10,r10,0x6773; \ | |
279 | stw r10,8(r11); \ | |
14cf11af PM |
280 | SAVE_4GPRS(3, r11); \ |
281 | SAVE_2GPRS(7, r11) | |
282 | ||
283 | /* | |
284 | * Note: code which follows this uses cr0.eq (set if from kernel), | |
285 | * r11, r12 (SRR0), and r9 (SRR1). | |
286 | * | |
287 | * Note2: once we have set r1 we are in a position to take exceptions | |
288 | * again, and we could thus set MSR:RI at that point. | |
289 | */ | |
290 | ||
291 | /* | |
292 | * Exception vectors. | |
293 | */ | |
294 | #define EXCEPTION(n, label, hdlr, xfer) \ | |
295 | . = n; \ | |
296 | label: \ | |
297 | EXCEPTION_PROLOG; \ | |
298 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
299 | xfer(n, hdlr) | |
300 | ||
301 | #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ | |
302 | li r10,trap; \ | |
d73e0c99 | 303 | stw r10,_TRAP(r11); \ |
14cf11af PM |
304 | li r10,MSR_KERNEL; \ |
305 | copyee(r10, r9); \ | |
306 | bl tfer; \ | |
307 | i##n: \ | |
308 | .long hdlr; \ | |
309 | .long ret | |
310 | ||
311 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 | |
312 | #define NOCOPY(d, s) | |
313 | ||
314 | #define EXC_XFER_STD(n, hdlr) \ | |
315 | EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ | |
316 | ret_from_except_full) | |
317 | ||
318 | #define EXC_XFER_LITE(n, hdlr) \ | |
319 | EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ | |
320 | ret_from_except) | |
321 | ||
322 | #define EXC_XFER_EE(n, hdlr) \ | |
323 | EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ | |
324 | ret_from_except_full) | |
325 | ||
326 | #define EXC_XFER_EE_LITE(n, hdlr) \ | |
327 | EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ | |
328 | ret_from_except) | |
329 | ||
330 | /* System reset */ | |
331 | /* core99 pmac starts the seconary here by changing the vector, and | |
dc1c1ca3 | 332 | putting it back to what it was (unknown_exception) when done. */ |
14cf11af PM |
333 | #if defined(CONFIG_GEMINI) && defined(CONFIG_SMP) |
334 | . = 0x100 | |
335 | b __secondary_start_gemini | |
336 | #else | |
dc1c1ca3 | 337 | EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) |
14cf11af PM |
338 | #endif |
339 | ||
340 | /* Machine check */ | |
341 | /* | |
342 | * On CHRP, this is complicated by the fact that we could get a | |
343 | * machine check inside RTAS, and we have no guarantee that certain | |
344 | * critical registers will have the values we expect. The set of | |
345 | * registers that might have bad values includes all the GPRs | |
346 | * and all the BATs. We indicate that we are in RTAS by putting | |
347 | * a non-zero value, the address of the exception frame to use, | |
348 | * in SPRG2. The machine check handler checks SPRG2 and uses its | |
349 | * value if it is non-zero. If we ever needed to free up SPRG2, | |
350 | * we could use a field in the thread_info or thread_struct instead. | |
351 | * (Other exception handlers assume that r1 is a valid kernel stack | |
352 | * pointer when we take an exception from supervisor mode.) | |
353 | * -- paulus. | |
354 | */ | |
355 | . = 0x200 | |
356 | mtspr SPRN_SPRG0,r10 | |
357 | mtspr SPRN_SPRG1,r11 | |
358 | mfcr r10 | |
359 | #ifdef CONFIG_PPC_CHRP | |
360 | mfspr r11,SPRN_SPRG2 | |
361 | cmpwi 0,r11,0 | |
362 | bne 7f | |
363 | #endif /* CONFIG_PPC_CHRP */ | |
364 | EXCEPTION_PROLOG_1 | |
365 | 7: EXCEPTION_PROLOG_2 | |
366 | addi r3,r1,STACK_FRAME_OVERHEAD | |
367 | #ifdef CONFIG_PPC_CHRP | |
368 | mfspr r4,SPRN_SPRG2 | |
369 | cmpwi cr1,r4,0 | |
370 | bne cr1,1f | |
371 | #endif | |
dc1c1ca3 | 372 | EXC_XFER_STD(0x200, machine_check_exception) |
14cf11af PM |
373 | #ifdef CONFIG_PPC_CHRP |
374 | 1: b machine_check_in_rtas | |
375 | #endif | |
376 | ||
377 | /* Data access exception. */ | |
378 | . = 0x300 | |
14cf11af PM |
379 | DataAccess: |
380 | EXCEPTION_PROLOG | |
14cf11af PM |
381 | mfspr r10,SPRN_DSISR |
382 | andis. r0,r10,0xa470 /* weird error? */ | |
383 | bne 1f /* if not, try to put a PTE */ | |
384 | mfspr r4,SPRN_DAR /* into the hash table */ | |
385 | rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */ | |
386 | bl hash_page | |
387 | 1: stw r10,_DSISR(r11) | |
388 | mr r5,r10 | |
389 | mfspr r4,SPRN_DAR | |
390 | EXC_XFER_EE_LITE(0x300, handle_page_fault) | |
391 | ||
14cf11af PM |
392 | |
393 | /* Instruction access exception. */ | |
394 | . = 0x400 | |
14cf11af PM |
395 | InstructionAccess: |
396 | EXCEPTION_PROLOG | |
14cf11af PM |
397 | andis. r0,r9,0x4000 /* no pte found? */ |
398 | beq 1f /* if so, try to put a PTE */ | |
399 | li r3,0 /* into the hash table */ | |
400 | mr r4,r12 /* SRR0 is fault address */ | |
401 | bl hash_page | |
402 | 1: mr r4,r12 | |
403 | mr r5,r9 | |
404 | EXC_XFER_EE_LITE(0x400, handle_page_fault) | |
405 | ||
14cf11af PM |
406 | /* External interrupt */ |
407 | EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) | |
408 | ||
409 | /* Alignment exception */ | |
410 | . = 0x600 | |
411 | Alignment: | |
412 | EXCEPTION_PROLOG | |
413 | mfspr r4,SPRN_DAR | |
414 | stw r4,_DAR(r11) | |
415 | mfspr r5,SPRN_DSISR | |
416 | stw r5,_DSISR(r11) | |
417 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 418 | EXC_XFER_EE(0x600, alignment_exception) |
14cf11af PM |
419 | |
420 | /* Program check exception */ | |
dc1c1ca3 | 421 | EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) |
14cf11af PM |
422 | |
423 | /* Floating-point unavailable */ | |
424 | . = 0x800 | |
425 | FPUnavailable: | |
426 | EXCEPTION_PROLOG | |
427 | bne load_up_fpu /* if from user, just load it up */ | |
428 | addi r3,r1,STACK_FRAME_OVERHEAD | |
8dad3f92 | 429 | EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception) |
14cf11af PM |
430 | |
431 | /* Decrementer */ | |
432 | EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) | |
433 | ||
dc1c1ca3 SR |
434 | EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) |
435 | EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
436 | |
437 | /* System call */ | |
438 | . = 0xc00 | |
439 | SystemCall: | |
440 | EXCEPTION_PROLOG | |
441 | EXC_XFER_EE_LITE(0xc00, DoSyscall) | |
442 | ||
443 | /* Single step - not used on 601 */ | |
dc1c1ca3 SR |
444 | EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) |
445 | EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
446 | |
447 | /* | |
448 | * The Altivec unavailable trap is at 0x0f20. Foo. | |
449 | * We effectively remap it to 0x3000. | |
450 | * We include an altivec unavailable exception vector even if | |
451 | * not configured for Altivec, so that you can't panic a | |
452 | * non-altivec kernel running on a machine with altivec just | |
453 | * by executing an altivec instruction. | |
454 | */ | |
455 | . = 0xf00 | |
456 | b Trap_0f | |
457 | ||
458 | . = 0xf20 | |
459 | b AltiVecUnavailable | |
460 | ||
461 | Trap_0f: | |
462 | EXCEPTION_PROLOG | |
463 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 464 | EXC_XFER_EE(0xf00, unknown_exception) |
14cf11af PM |
465 | |
466 | /* | |
467 | * Handle TLB miss for instruction on 603/603e. | |
468 | * Note: we get an alternate set of r0 - r3 to use automatically. | |
469 | */ | |
470 | . = 0x1000 | |
471 | InstructionTLBMiss: | |
472 | /* | |
473 | * r0: stored ctr | |
474 | * r1: linux style pte ( later becomes ppc hardware pte ) | |
475 | * r2: ptr to linux-style pte | |
476 | * r3: scratch | |
477 | */ | |
478 | mfctr r0 | |
479 | /* Get PTE (linux-style) and check access */ | |
480 | mfspr r3,SPRN_IMISS | |
481 | lis r1,KERNELBASE@h /* check if kernel address */ | |
482 | cmplw 0,r3,r1 | |
483 | mfspr r2,SPRN_SPRG3 | |
484 | li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ | |
485 | lwz r2,PGDIR(r2) | |
486 | blt+ 112f | |
487 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ | |
488 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ | |
489 | mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ | |
490 | rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ | |
491 | 112: tophys(r2,r2) | |
492 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ | |
493 | lwz r2,0(r2) /* get pmd entry */ | |
494 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ | |
495 | beq- InstructionAddressInvalid /* return if no mapping */ | |
496 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ | |
497 | lwz r3,0(r2) /* get linux-style pte */ | |
498 | andc. r1,r1,r3 /* check access & ~permission */ | |
499 | bne- InstructionAddressInvalid /* return if access not permitted */ | |
500 | ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ | |
501 | /* | |
502 | * NOTE! We are assuming this is not an SMP system, otherwise | |
503 | * we would need to update the pte atomically with lwarx/stwcx. | |
504 | */ | |
505 | stw r3,0(r2) /* update PTE (accessed bit) */ | |
506 | /* Convert linux-style PTE to low word of PPC-style PTE */ | |
507 | rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ | |
508 | rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ | |
509 | and r1,r1,r2 /* writable if _RW and _DIRTY */ | |
510 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | |
511 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ | |
512 | ori r1,r1,0xe14 /* clear out reserved bits and M */ | |
513 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ | |
514 | mtspr SPRN_RPA,r1 | |
515 | mfspr r3,SPRN_IMISS | |
516 | tlbli r3 | |
517 | mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ | |
518 | mtcrf 0x80,r3 | |
519 | rfi | |
520 | InstructionAddressInvalid: | |
521 | mfspr r3,SPRN_SRR1 | |
522 | rlwinm r1,r3,9,6,6 /* Get load/store bit */ | |
523 | ||
524 | addis r1,r1,0x2000 | |
525 | mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */ | |
526 | mtctr r0 /* Restore CTR */ | |
527 | andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ | |
528 | or r2,r2,r1 | |
529 | mtspr SPRN_SRR1,r2 | |
530 | mfspr r1,SPRN_IMISS /* Get failing address */ | |
531 | rlwinm. r2,r2,0,31,31 /* Check for little endian access */ | |
532 | rlwimi r2,r2,1,30,30 /* change 1 -> 3 */ | |
533 | xor r1,r1,r2 | |
534 | mtspr SPRN_DAR,r1 /* Set fault address */ | |
535 | mfmsr r0 /* Restore "normal" registers */ | |
536 | xoris r0,r0,MSR_TGPR>>16 | |
537 | mtcrf 0x80,r3 /* Restore CR0 */ | |
538 | mtmsr r0 | |
539 | b InstructionAccess | |
540 | ||
541 | /* | |
542 | * Handle TLB miss for DATA Load operation on 603/603e | |
543 | */ | |
544 | . = 0x1100 | |
545 | DataLoadTLBMiss: | |
546 | /* | |
547 | * r0: stored ctr | |
548 | * r1: linux style pte ( later becomes ppc hardware pte ) | |
549 | * r2: ptr to linux-style pte | |
550 | * r3: scratch | |
551 | */ | |
552 | mfctr r0 | |
553 | /* Get PTE (linux-style) and check access */ | |
554 | mfspr r3,SPRN_DMISS | |
555 | lis r1,KERNELBASE@h /* check if kernel address */ | |
556 | cmplw 0,r3,r1 | |
557 | mfspr r2,SPRN_SPRG3 | |
558 | li r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */ | |
559 | lwz r2,PGDIR(r2) | |
560 | blt+ 112f | |
561 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ | |
562 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ | |
563 | mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ | |
564 | rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ | |
565 | 112: tophys(r2,r2) | |
566 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ | |
567 | lwz r2,0(r2) /* get pmd entry */ | |
568 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ | |
569 | beq- DataAddressInvalid /* return if no mapping */ | |
570 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ | |
571 | lwz r3,0(r2) /* get linux-style pte */ | |
572 | andc. r1,r1,r3 /* check access & ~permission */ | |
573 | bne- DataAddressInvalid /* return if access not permitted */ | |
574 | ori r3,r3,_PAGE_ACCESSED /* set _PAGE_ACCESSED in pte */ | |
575 | /* | |
576 | * NOTE! We are assuming this is not an SMP system, otherwise | |
577 | * we would need to update the pte atomically with lwarx/stwcx. | |
578 | */ | |
579 | stw r3,0(r2) /* update PTE (accessed bit) */ | |
580 | /* Convert linux-style PTE to low word of PPC-style PTE */ | |
581 | rlwinm r1,r3,32-10,31,31 /* _PAGE_RW -> PP lsb */ | |
582 | rlwinm r2,r3,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */ | |
583 | and r1,r1,r2 /* writable if _RW and _DIRTY */ | |
584 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | |
585 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ | |
586 | ori r1,r1,0xe14 /* clear out reserved bits and M */ | |
587 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ | |
588 | mtspr SPRN_RPA,r1 | |
589 | mfspr r3,SPRN_DMISS | |
590 | tlbld r3 | |
591 | mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ | |
592 | mtcrf 0x80,r3 | |
593 | rfi | |
594 | DataAddressInvalid: | |
595 | mfspr r3,SPRN_SRR1 | |
596 | rlwinm r1,r3,9,6,6 /* Get load/store bit */ | |
597 | addis r1,r1,0x2000 | |
598 | mtspr SPRN_DSISR,r1 | |
599 | mtctr r0 /* Restore CTR */ | |
600 | andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */ | |
601 | mtspr SPRN_SRR1,r2 | |
602 | mfspr r1,SPRN_DMISS /* Get failing address */ | |
603 | rlwinm. r2,r2,0,31,31 /* Check for little endian access */ | |
604 | beq 20f /* Jump if big endian */ | |
605 | xori r1,r1,3 | |
606 | 20: mtspr SPRN_DAR,r1 /* Set fault address */ | |
607 | mfmsr r0 /* Restore "normal" registers */ | |
608 | xoris r0,r0,MSR_TGPR>>16 | |
609 | mtcrf 0x80,r3 /* Restore CR0 */ | |
610 | mtmsr r0 | |
611 | b DataAccess | |
612 | ||
613 | /* | |
614 | * Handle TLB miss for DATA Store on 603/603e | |
615 | */ | |
616 | . = 0x1200 | |
617 | DataStoreTLBMiss: | |
618 | /* | |
619 | * r0: stored ctr | |
620 | * r1: linux style pte ( later becomes ppc hardware pte ) | |
621 | * r2: ptr to linux-style pte | |
622 | * r3: scratch | |
623 | */ | |
624 | mfctr r0 | |
625 | /* Get PTE (linux-style) and check access */ | |
626 | mfspr r3,SPRN_DMISS | |
627 | lis r1,KERNELBASE@h /* check if kernel address */ | |
628 | cmplw 0,r3,r1 | |
629 | mfspr r2,SPRN_SPRG3 | |
630 | li r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */ | |
631 | lwz r2,PGDIR(r2) | |
632 | blt+ 112f | |
633 | lis r2,swapper_pg_dir@ha /* if kernel address, use */ | |
634 | addi r2,r2,swapper_pg_dir@l /* kernel page table */ | |
635 | mfspr r1,SPRN_SRR1 /* and MSR_PR bit from SRR1 */ | |
636 | rlwinm r1,r1,32-12,29,29 /* shift MSR_PR to _PAGE_USER posn */ | |
637 | 112: tophys(r2,r2) | |
638 | rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */ | |
639 | lwz r2,0(r2) /* get pmd entry */ | |
640 | rlwinm. r2,r2,0,0,19 /* extract address of pte page */ | |
641 | beq- DataAddressInvalid /* return if no mapping */ | |
642 | rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */ | |
643 | lwz r3,0(r2) /* get linux-style pte */ | |
644 | andc. r1,r1,r3 /* check access & ~permission */ | |
645 | bne- DataAddressInvalid /* return if access not permitted */ | |
646 | ori r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY | |
647 | /* | |
648 | * NOTE! We are assuming this is not an SMP system, otherwise | |
649 | * we would need to update the pte atomically with lwarx/stwcx. | |
650 | */ | |
651 | stw r3,0(r2) /* update PTE (accessed/dirty bits) */ | |
652 | /* Convert linux-style PTE to low word of PPC-style PTE */ | |
653 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | |
654 | li r1,0xe15 /* clear out reserved bits and M */ | |
655 | andc r1,r3,r1 /* PP = user? 2: 0 */ | |
656 | mtspr SPRN_RPA,r1 | |
657 | mfspr r3,SPRN_DMISS | |
658 | tlbld r3 | |
659 | mfspr r3,SPRN_SRR1 /* Need to restore CR0 */ | |
660 | mtcrf 0x80,r3 | |
661 | rfi | |
662 | ||
663 | #ifndef CONFIG_ALTIVEC | |
dc1c1ca3 | 664 | #define altivec_assist_exception unknown_exception |
14cf11af PM |
665 | #endif |
666 | ||
dc1c1ca3 | 667 | EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE) |
14cf11af | 668 | EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE) |
dc1c1ca3 | 669 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
dc1c1ca3 | 670 | EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE) |
14cf11af | 671 | EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD) |
dc1c1ca3 | 672 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) |
dc1c1ca3 SR |
673 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) |
674 | EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) | |
675 | EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) | |
676 | EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) | |
677 | EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) | |
678 | EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) | |
679 | EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) | |
14cf11af | 680 | EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE) |
dc1c1ca3 SR |
681 | EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE) |
682 | EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE) | |
683 | EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE) | |
684 | EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE) | |
685 | EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE) | |
686 | EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE) | |
687 | EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE) | |
688 | EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE) | |
689 | EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE) | |
690 | EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE) | |
691 | EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE) | |
692 | EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE) | |
693 | EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE) | |
694 | EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE) | |
695 | EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE) | |
14cf11af PM |
696 | |
697 | .globl mol_trampoline | |
698 | .set mol_trampoline, i0x2f00 | |
699 | ||
700 | . = 0x3000 | |
701 | ||
702 | AltiVecUnavailable: | |
703 | EXCEPTION_PROLOG | |
704 | #ifdef CONFIG_ALTIVEC | |
705 | bne load_up_altivec /* if from user, just load it up */ | |
706 | #endif /* CONFIG_ALTIVEC */ | |
dc1c1ca3 | 707 | EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) |
14cf11af | 708 | |
14cf11af PM |
709 | #ifdef CONFIG_ALTIVEC |
710 | /* Note that the AltiVec support is closely modeled after the FP | |
711 | * support. Changes to one are likely to be applicable to the | |
712 | * other! */ | |
713 | load_up_altivec: | |
714 | /* | |
715 | * Disable AltiVec for the task which had AltiVec previously, | |
716 | * and save its AltiVec registers in its thread_struct. | |
717 | * Enables AltiVec for use in the kernel on return. | |
718 | * On SMP we know the AltiVec units are free, since we give it up every | |
719 | * switch. -- Kumar | |
720 | */ | |
721 | mfmsr r5 | |
722 | oris r5,r5,MSR_VEC@h | |
723 | MTMSRD(r5) /* enable use of AltiVec now */ | |
724 | isync | |
725 | /* | |
726 | * For SMP, we don't do lazy AltiVec switching because it just gets too | |
727 | * horrendously complex, especially when a task switches from one CPU | |
728 | * to another. Instead we call giveup_altivec in switch_to. | |
729 | */ | |
730 | #ifndef CONFIG_SMP | |
731 | tophys(r6,0) | |
732 | addis r3,r6,last_task_used_altivec@ha | |
733 | lwz r4,last_task_used_altivec@l(r3) | |
734 | cmpwi 0,r4,0 | |
735 | beq 1f | |
736 | add r4,r4,r6 | |
737 | addi r4,r4,THREAD /* want THREAD of last_task_used_altivec */ | |
738 | SAVE_32VRS(0,r10,r4) | |
739 | mfvscr vr0 | |
740 | li r10,THREAD_VSCR | |
741 | stvx vr0,r10,r4 | |
742 | lwz r5,PT_REGS(r4) | |
743 | add r5,r5,r6 | |
744 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
745 | lis r10,MSR_VEC@h | |
746 | andc r4,r4,r10 /* disable altivec for previous task */ | |
747 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
748 | 1: | |
749 | #endif /* CONFIG_SMP */ | |
750 | /* enable use of AltiVec after return */ | |
751 | oris r9,r9,MSR_VEC@h | |
752 | mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ | |
753 | li r4,1 | |
754 | li r10,THREAD_VSCR | |
755 | stw r4,THREAD_USED_VR(r5) | |
756 | lvx vr0,r10,r5 | |
757 | mtvscr vr0 | |
758 | REST_32VRS(0,r10,r5) | |
759 | #ifndef CONFIG_SMP | |
760 | subi r4,r5,THREAD | |
761 | sub r4,r4,r6 | |
762 | stw r4,last_task_used_altivec@l(r3) | |
763 | #endif /* CONFIG_SMP */ | |
764 | /* restore registers and return */ | |
765 | /* we haven't used ctr or xer or lr */ | |
766 | b fast_exception_return | |
767 | ||
768 | /* | |
769 | * AltiVec unavailable trap from kernel - print a message, but let | |
770 | * the task use AltiVec in the kernel until it returns to user mode. | |
771 | */ | |
772 | KernelAltiVec: | |
773 | lwz r3,_MSR(r1) | |
774 | oris r3,r3,MSR_VEC@h | |
775 | stw r3,_MSR(r1) /* enable use of AltiVec after return */ | |
776 | lis r3,87f@h | |
777 | ori r3,r3,87f@l | |
778 | mr r4,r2 /* current */ | |
779 | lwz r5,_NIP(r1) | |
780 | bl printk | |
781 | b ret_from_except | |
782 | 87: .string "AltiVec used in kernel (task=%p, pc=%x) \n" | |
783 | .align 4,0 | |
784 | ||
785 | /* | |
786 | * giveup_altivec(tsk) | |
787 | * Disable AltiVec for the task given as the argument, | |
788 | * and save the AltiVec registers in its thread_struct. | |
789 | * Enables AltiVec for use in the kernel on return. | |
790 | */ | |
791 | ||
792 | .globl giveup_altivec | |
793 | giveup_altivec: | |
794 | mfmsr r5 | |
795 | oris r5,r5,MSR_VEC@h | |
796 | SYNC | |
797 | MTMSRD(r5) /* enable use of AltiVec now */ | |
798 | isync | |
799 | cmpwi 0,r3,0 | |
800 | beqlr- /* if no previous owner, done */ | |
801 | addi r3,r3,THREAD /* want THREAD of task */ | |
802 | lwz r5,PT_REGS(r3) | |
803 | cmpwi 0,r5,0 | |
804 | SAVE_32VRS(0, r4, r3) | |
805 | mfvscr vr0 | |
806 | li r4,THREAD_VSCR | |
807 | stvx vr0,r4,r3 | |
808 | beq 1f | |
809 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
810 | lis r3,MSR_VEC@h | |
811 | andc r4,r4,r3 /* disable AltiVec for previous task */ | |
812 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
813 | 1: | |
814 | #ifndef CONFIG_SMP | |
815 | li r5,0 | |
816 | lis r4,last_task_used_altivec@ha | |
817 | stw r5,last_task_used_altivec@l(r4) | |
818 | #endif /* CONFIG_SMP */ | |
819 | blr | |
820 | #endif /* CONFIG_ALTIVEC */ | |
821 | ||
822 | /* | |
823 | * This code is jumped to from the startup code to copy | |
824 | * the kernel image to physical address 0. | |
825 | */ | |
826 | relocate_kernel: | |
827 | addis r9,r26,klimit@ha /* fetch klimit */ | |
828 | lwz r25,klimit@l(r9) | |
829 | addis r25,r25,-KERNELBASE@h | |
830 | li r3,0 /* Destination base address */ | |
831 | li r6,0 /* Destination offset */ | |
832 | li r5,0x4000 /* # bytes of memory to copy */ | |
833 | bl copy_and_flush /* copy the first 0x4000 bytes */ | |
834 | addi r0,r3,4f@l /* jump to the address of 4f */ | |
835 | mtctr r0 /* in copy and do the rest. */ | |
836 | bctr /* jump to the copy */ | |
837 | 4: mr r5,r25 | |
838 | bl copy_and_flush /* copy the rest */ | |
839 | b turn_on_mmu | |
840 | ||
841 | /* | |
842 | * Copy routine used to copy the kernel to start at physical address 0 | |
843 | * and flush and invalidate the caches as needed. | |
844 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
845 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
846 | */ | |
77f543cb | 847 | _GLOBAL(copy_and_flush) |
14cf11af PM |
848 | addi r5,r5,-4 |
849 | addi r6,r6,-4 | |
7dffb720 | 850 | 4: li r0,L1_CACHE_BYTES/4 |
14cf11af PM |
851 | mtctr r0 |
852 | 3: addi r6,r6,4 /* copy a cache line */ | |
853 | lwzx r0,r6,r4 | |
854 | stwx r0,r6,r3 | |
855 | bdnz 3b | |
856 | dcbst r6,r3 /* write it to memory */ | |
857 | sync | |
858 | icbi r6,r3 /* flush the icache line */ | |
859 | cmplw 0,r6,r5 | |
860 | blt 4b | |
861 | sync /* additional sync needed on g4 */ | |
862 | isync | |
863 | addi r5,r5,4 | |
864 | addi r6,r6,4 | |
865 | blr | |
866 | ||
867 | #ifdef CONFIG_APUS | |
868 | /* | |
869 | * On APUS the physical base address of the kernel is not known at compile | |
870 | * time, which means the __pa/__va constants used are incorrect. In the | |
871 | * __init section is recorded the virtual addresses of instructions using | |
872 | * these constants, so all that has to be done is fix these before | |
873 | * continuing the kernel boot. | |
874 | * | |
875 | * r4 = The physical address of the kernel base. | |
876 | */ | |
877 | fix_mem_constants: | |
878 | mr r10,r4 | |
879 | addis r10,r10,-KERNELBASE@h /* virt_to_phys constant */ | |
880 | neg r11,r10 /* phys_to_virt constant */ | |
881 | ||
882 | lis r12,__vtop_table_begin@h | |
883 | ori r12,r12,__vtop_table_begin@l | |
884 | add r12,r12,r10 /* table begin phys address */ | |
885 | lis r13,__vtop_table_end@h | |
886 | ori r13,r13,__vtop_table_end@l | |
887 | add r13,r13,r10 /* table end phys address */ | |
888 | subi r12,r12,4 | |
889 | subi r13,r13,4 | |
890 | 1: lwzu r14,4(r12) /* virt address of instruction */ | |
891 | add r14,r14,r10 /* phys address of instruction */ | |
892 | lwz r15,0(r14) /* instruction, now insert top */ | |
893 | rlwimi r15,r10,16,16,31 /* half of vp const in low half */ | |
894 | stw r15,0(r14) /* of instruction and restore. */ | |
895 | dcbst r0,r14 /* write it to memory */ | |
896 | sync | |
897 | icbi r0,r14 /* flush the icache line */ | |
898 | cmpw r12,r13 | |
899 | bne 1b | |
900 | sync /* additional sync needed on g4 */ | |
901 | isync | |
902 | ||
903 | /* | |
904 | * Map the memory where the exception handlers will | |
905 | * be copied to when hash constants have been patched. | |
906 | */ | |
907 | #ifdef CONFIG_APUS_FAST_EXCEPT | |
908 | lis r8,0xfff0 | |
909 | #else | |
910 | lis r8,0 | |
911 | #endif | |
912 | ori r8,r8,0x2 /* 128KB, supervisor */ | |
913 | mtspr SPRN_DBAT3U,r8 | |
914 | mtspr SPRN_DBAT3L,r8 | |
915 | ||
916 | lis r12,__ptov_table_begin@h | |
917 | ori r12,r12,__ptov_table_begin@l | |
918 | add r12,r12,r10 /* table begin phys address */ | |
919 | lis r13,__ptov_table_end@h | |
920 | ori r13,r13,__ptov_table_end@l | |
921 | add r13,r13,r10 /* table end phys address */ | |
922 | subi r12,r12,4 | |
923 | subi r13,r13,4 | |
924 | 1: lwzu r14,4(r12) /* virt address of instruction */ | |
925 | add r14,r14,r10 /* phys address of instruction */ | |
926 | lwz r15,0(r14) /* instruction, now insert top */ | |
927 | rlwimi r15,r11,16,16,31 /* half of pv const in low half*/ | |
928 | stw r15,0(r14) /* of instruction and restore. */ | |
929 | dcbst r0,r14 /* write it to memory */ | |
930 | sync | |
931 | icbi r0,r14 /* flush the icache line */ | |
932 | cmpw r12,r13 | |
933 | bne 1b | |
934 | ||
935 | sync /* additional sync needed on g4 */ | |
936 | isync /* No speculative loading until now */ | |
937 | blr | |
938 | ||
939 | /*********************************************************************** | |
940 | * Please note that on APUS the exception handlers are located at the | |
941 | * physical address 0xfff0000. For this reason, the exception handlers | |
942 | * cannot use relative branches to access the code below. | |
943 | ***********************************************************************/ | |
944 | #endif /* CONFIG_APUS */ | |
945 | ||
946 | #ifdef CONFIG_SMP | |
947 | #ifdef CONFIG_GEMINI | |
948 | .globl __secondary_start_gemini | |
949 | __secondary_start_gemini: | |
950 | mfspr r4,SPRN_HID0 | |
951 | ori r4,r4,HID0_ICFI | |
952 | li r3,0 | |
953 | ori r3,r3,HID0_ICE | |
954 | andc r4,r4,r3 | |
955 | mtspr SPRN_HID0,r4 | |
956 | sync | |
957 | b __secondary_start | |
958 | #endif /* CONFIG_GEMINI */ | |
959 | ||
960 | .globl __secondary_start_pmac_0 | |
961 | __secondary_start_pmac_0: | |
962 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
963 | li r24,0 | |
964 | b 1f | |
965 | li r24,1 | |
966 | b 1f | |
967 | li r24,2 | |
968 | b 1f | |
969 | li r24,3 | |
970 | 1: | |
971 | /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0 | |
972 | set to map the 0xf0000000 - 0xffffffff region */ | |
973 | mfmsr r0 | |
974 | rlwinm r0,r0,0,28,26 /* clear DR (0x10) */ | |
975 | SYNC | |
976 | mtmsr r0 | |
977 | isync | |
978 | ||
979 | .globl __secondary_start | |
980 | __secondary_start: | |
14cf11af PM |
981 | /* Copy some CPU settings from CPU 0 */ |
982 | bl __restore_cpu_setup | |
983 | ||
984 | lis r3,-KERNELBASE@h | |
985 | mr r4,r24 | |
14cf11af PM |
986 | bl call_setup_cpu /* Call setup_cpu for this CPU */ |
987 | #ifdef CONFIG_6xx | |
988 | lis r3,-KERNELBASE@h | |
989 | bl init_idle_6xx | |
990 | #endif /* CONFIG_6xx */ | |
14cf11af PM |
991 | |
992 | /* get current_thread_info and current */ | |
993 | lis r1,secondary_ti@ha | |
994 | tophys(r1,r1) | |
995 | lwz r1,secondary_ti@l(r1) | |
996 | tophys(r2,r1) | |
997 | lwz r2,TI_TASK(r2) | |
998 | ||
999 | /* stack */ | |
1000 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1001 | li r0,0 | |
1002 | tophys(r3,r1) | |
1003 | stw r0,0(r3) | |
1004 | ||
1005 | /* load up the MMU */ | |
1006 | bl load_up_mmu | |
1007 | ||
1008 | /* ptr to phys current thread */ | |
1009 | tophys(r4,r2) | |
1010 | addi r4,r4,THREAD /* phys address of our thread_struct */ | |
1011 | CLR_TOP32(r4) | |
1012 | mtspr SPRN_SPRG3,r4 | |
1013 | li r3,0 | |
1014 | mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ | |
1015 | ||
1016 | /* enable MMU and jump to start_secondary */ | |
1017 | li r4,MSR_KERNEL | |
1018 | FIX_SRR1(r4,r5) | |
1019 | lis r3,start_secondary@h | |
1020 | ori r3,r3,start_secondary@l | |
1021 | mtspr SPRN_SRR0,r3 | |
1022 | mtspr SPRN_SRR1,r4 | |
1023 | SYNC | |
1024 | RFI | |
1025 | #endif /* CONFIG_SMP */ | |
1026 | ||
1027 | /* | |
1028 | * Those generic dummy functions are kept for CPUs not | |
1029 | * included in CONFIG_6xx | |
1030 | */ | |
187a0067 | 1031 | #if !defined(CONFIG_6xx) |
14cf11af PM |
1032 | _GLOBAL(__save_cpu_setup) |
1033 | blr | |
1034 | _GLOBAL(__restore_cpu_setup) | |
1035 | blr | |
187a0067 | 1036 | #endif /* !defined(CONFIG_6xx) */ |
14cf11af PM |
1037 | |
1038 | ||
1039 | /* | |
1040 | * Load stuff into the MMU. Intended to be called with | |
1041 | * IR=0 and DR=0. | |
1042 | */ | |
1043 | load_up_mmu: | |
1044 | sync /* Force all PTE updates to finish */ | |
1045 | isync | |
1046 | tlbia /* Clear all TLB entries */ | |
1047 | sync /* wait for tlbia/tlbie to finish */ | |
1048 | TLBSYNC /* ... on all CPUs */ | |
1049 | /* Load the SDR1 register (hash table base & size) */ | |
1050 | lis r6,_SDR1@ha | |
1051 | tophys(r6,r6) | |
1052 | lwz r6,_SDR1@l(r6) | |
1053 | mtspr SPRN_SDR1,r6 | |
14cf11af PM |
1054 | li r0,16 /* load up segment register values */ |
1055 | mtctr r0 /* for context 0 */ | |
1056 | lis r3,0x2000 /* Ku = 1, VSID = 0 */ | |
1057 | li r4,0 | |
1058 | 3: mtsrin r3,r4 | |
1059 | addi r3,r3,0x111 /* increment VSID */ | |
1060 | addis r4,r4,0x1000 /* address of next segment */ | |
1061 | bdnz 3b | |
187a0067 | 1062 | |
14cf11af PM |
1063 | /* Load the BAT registers with the values set up by MMU_init. |
1064 | MMU_init takes care of whether we're on a 601 or not. */ | |
1065 | mfpvr r3 | |
1066 | srwi r3,r3,16 | |
1067 | cmpwi r3,1 | |
1068 | lis r3,BATS@ha | |
1069 | addi r3,r3,BATS@l | |
1070 | tophys(r3,r3) | |
1071 | LOAD_BAT(0,r3,r4,r5) | |
1072 | LOAD_BAT(1,r3,r4,r5) | |
1073 | LOAD_BAT(2,r3,r4,r5) | |
1074 | LOAD_BAT(3,r3,r4,r5) | |
187a0067 | 1075 | |
14cf11af PM |
1076 | blr |
1077 | ||
1078 | /* | |
1079 | * This is where the main kernel code starts. | |
1080 | */ | |
1081 | start_here: | |
1082 | /* ptr to current */ | |
1083 | lis r2,init_task@h | |
1084 | ori r2,r2,init_task@l | |
1085 | /* Set up for using our exception vectors */ | |
1086 | /* ptr to phys current thread */ | |
1087 | tophys(r4,r2) | |
1088 | addi r4,r4,THREAD /* init task's THREAD */ | |
1089 | CLR_TOP32(r4) | |
1090 | mtspr SPRN_SPRG3,r4 | |
1091 | li r3,0 | |
1092 | mtspr SPRN_SPRG2,r3 /* 0 => not in RTAS */ | |
1093 | ||
1094 | /* stack */ | |
1095 | lis r1,init_thread_union@ha | |
1096 | addi r1,r1,init_thread_union@l | |
1097 | li r0,0 | |
1098 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
1099 | /* | |
187a0067 | 1100 | * Do early platform-specific initialization, |
14cf11af PM |
1101 | * and set up the MMU. |
1102 | */ | |
1103 | mr r3,r31 | |
1104 | mr r4,r30 | |
14cf11af | 1105 | bl machine_init |
22c841c9 | 1106 | bl __save_cpu_setup |
14cf11af PM |
1107 | bl MMU_init |
1108 | ||
1109 | #ifdef CONFIG_APUS | |
1110 | /* Copy exception code to exception vector base on APUS. */ | |
1111 | lis r4,KERNELBASE@h | |
1112 | #ifdef CONFIG_APUS_FAST_EXCEPT | |
1113 | lis r3,0xfff0 /* Copy to 0xfff00000 */ | |
1114 | #else | |
1115 | lis r3,0 /* Copy to 0x00000000 */ | |
1116 | #endif | |
1117 | li r5,0x4000 /* # bytes of memory to copy */ | |
1118 | li r6,0 | |
1119 | bl copy_and_flush /* copy the first 0x4000 bytes */ | |
1120 | #endif /* CONFIG_APUS */ | |
1121 | ||
1122 | /* | |
1123 | * Go back to running unmapped so we can load up new values | |
1124 | * for SDR1 (hash table pointer) and the segment registers | |
1125 | * and change to using our exception vectors. | |
1126 | */ | |
1127 | lis r4,2f@h | |
1128 | ori r4,r4,2f@l | |
1129 | tophys(r4,r4) | |
1130 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) | |
1131 | FIX_SRR1(r3,r5) | |
1132 | mtspr SPRN_SRR0,r4 | |
1133 | mtspr SPRN_SRR1,r3 | |
1134 | SYNC | |
1135 | RFI | |
1136 | /* Load up the kernel context */ | |
1137 | 2: bl load_up_mmu | |
1138 | ||
1139 | #ifdef CONFIG_BDI_SWITCH | |
1140 | /* Add helper information for the Abatron bdiGDB debugger. | |
1141 | * We do this here because we know the mmu is disabled, and | |
1142 | * will be enabled for real in just a few instructions. | |
1143 | */ | |
1144 | lis r5, abatron_pteptrs@h | |
1145 | ori r5, r5, abatron_pteptrs@l | |
1146 | stw r5, 0xf0(r0) /* This much match your Abatron config */ | |
1147 | lis r6, swapper_pg_dir@h | |
1148 | ori r6, r6, swapper_pg_dir@l | |
1149 | tophys(r5, r5) | |
1150 | stw r6, 0(r5) | |
1151 | #endif /* CONFIG_BDI_SWITCH */ | |
1152 | ||
1153 | /* Now turn on the MMU for real! */ | |
1154 | li r4,MSR_KERNEL | |
1155 | FIX_SRR1(r4,r5) | |
1156 | lis r3,start_kernel@h | |
1157 | ori r3,r3,start_kernel@l | |
1158 | mtspr SPRN_SRR0,r3 | |
1159 | mtspr SPRN_SRR1,r4 | |
1160 | SYNC | |
1161 | RFI | |
1162 | ||
1163 | /* | |
1164 | * Set up the segment registers for a new context. | |
1165 | */ | |
1166 | _GLOBAL(set_context) | |
1167 | mulli r3,r3,897 /* multiply context by skew factor */ | |
1168 | rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */ | |
1169 | addis r3,r3,0x6000 /* Set Ks, Ku bits */ | |
1170 | li r0,NUM_USER_SEGMENTS | |
1171 | mtctr r0 | |
1172 | ||
1173 | #ifdef CONFIG_BDI_SWITCH | |
1174 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
1175 | * The PGDIR is passed as second argument. | |
1176 | */ | |
1177 | lis r5, KERNELBASE@h | |
1178 | lwz r5, 0xf0(r5) | |
1179 | stw r4, 0x4(r5) | |
1180 | #endif | |
1181 | li r4,0 | |
1182 | isync | |
1183 | 3: | |
14cf11af PM |
1184 | mtsrin r3,r4 |
1185 | addi r3,r3,0x111 /* next VSID */ | |
1186 | rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */ | |
1187 | addis r4,r4,0x1000 /* address of next segment */ | |
1188 | bdnz 3b | |
1189 | sync | |
1190 | isync | |
1191 | blr | |
1192 | ||
1193 | /* | |
1194 | * An undocumented "feature" of 604e requires that the v bit | |
1195 | * be cleared before changing BAT values. | |
1196 | * | |
1197 | * Also, newer IBM firmware does not clear bat3 and 4 so | |
1198 | * this makes sure it's done. | |
1199 | * -- Cort | |
1200 | */ | |
1201 | clear_bats: | |
1202 | li r10,0 | |
1203 | mfspr r9,SPRN_PVR | |
1204 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | |
1205 | cmpwi r9, 1 | |
1206 | beq 1f | |
1207 | ||
1208 | mtspr SPRN_DBAT0U,r10 | |
1209 | mtspr SPRN_DBAT0L,r10 | |
1210 | mtspr SPRN_DBAT1U,r10 | |
1211 | mtspr SPRN_DBAT1L,r10 | |
1212 | mtspr SPRN_DBAT2U,r10 | |
1213 | mtspr SPRN_DBAT2L,r10 | |
1214 | mtspr SPRN_DBAT3U,r10 | |
1215 | mtspr SPRN_DBAT3L,r10 | |
1216 | 1: | |
1217 | mtspr SPRN_IBAT0U,r10 | |
1218 | mtspr SPRN_IBAT0L,r10 | |
1219 | mtspr SPRN_IBAT1U,r10 | |
1220 | mtspr SPRN_IBAT1L,r10 | |
1221 | mtspr SPRN_IBAT2U,r10 | |
1222 | mtspr SPRN_IBAT2L,r10 | |
1223 | mtspr SPRN_IBAT3U,r10 | |
1224 | mtspr SPRN_IBAT3L,r10 | |
1225 | BEGIN_FTR_SECTION | |
1226 | /* Here's a tweak: at this point, CPU setup have | |
1227 | * not been called yet, so HIGH_BAT_EN may not be | |
1228 | * set in HID0 for the 745x processors. However, it | |
1229 | * seems that doesn't affect our ability to actually | |
1230 | * write to these SPRs. | |
1231 | */ | |
1232 | mtspr SPRN_DBAT4U,r10 | |
1233 | mtspr SPRN_DBAT4L,r10 | |
1234 | mtspr SPRN_DBAT5U,r10 | |
1235 | mtspr SPRN_DBAT5L,r10 | |
1236 | mtspr SPRN_DBAT6U,r10 | |
1237 | mtspr SPRN_DBAT6L,r10 | |
1238 | mtspr SPRN_DBAT7U,r10 | |
1239 | mtspr SPRN_DBAT7L,r10 | |
1240 | mtspr SPRN_IBAT4U,r10 | |
1241 | mtspr SPRN_IBAT4L,r10 | |
1242 | mtspr SPRN_IBAT5U,r10 | |
1243 | mtspr SPRN_IBAT5L,r10 | |
1244 | mtspr SPRN_IBAT6U,r10 | |
1245 | mtspr SPRN_IBAT6L,r10 | |
1246 | mtspr SPRN_IBAT7U,r10 | |
1247 | mtspr SPRN_IBAT7L,r10 | |
1248 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | |
1249 | blr | |
1250 | ||
1251 | flush_tlbs: | |
1252 | lis r10, 0x40 | |
1253 | 1: addic. r10, r10, -0x1000 | |
1254 | tlbie r10 | |
1255 | blt 1b | |
1256 | sync | |
1257 | blr | |
1258 | ||
1259 | mmu_off: | |
1260 | addi r4, r3, __after_mmu_off - _start | |
1261 | mfmsr r3 | |
1262 | andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */ | |
1263 | beqlr | |
1264 | andc r3,r3,r0 | |
1265 | mtspr SPRN_SRR0,r4 | |
1266 | mtspr SPRN_SRR1,r3 | |
1267 | sync | |
1268 | RFI | |
1269 | ||
14cf11af PM |
1270 | /* |
1271 | * Use the first pair of BAT registers to map the 1st 16MB | |
1272 | * of RAM to KERNELBASE. From this point on we can't safely | |
1273 | * call OF any more. | |
1274 | */ | |
1275 | initial_bats: | |
1276 | lis r11,KERNELBASE@h | |
14cf11af PM |
1277 | mfspr r9,SPRN_PVR |
1278 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | |
1279 | cmpwi 0,r9,1 | |
1280 | bne 4f | |
1281 | ori r11,r11,4 /* set up BAT registers for 601 */ | |
1282 | li r8,0x7f /* valid, block length = 8MB */ | |
1283 | oris r9,r11,0x800000@h /* set up BAT reg for 2nd 8M */ | |
1284 | oris r10,r8,0x800000@h /* set up BAT reg for 2nd 8M */ | |
1285 | mtspr SPRN_IBAT0U,r11 /* N.B. 601 has valid bit in */ | |
1286 | mtspr SPRN_IBAT0L,r8 /* lower BAT register */ | |
1287 | mtspr SPRN_IBAT1U,r9 | |
1288 | mtspr SPRN_IBAT1L,r10 | |
1289 | isync | |
1290 | blr | |
14cf11af PM |
1291 | |
1292 | 4: tophys(r8,r11) | |
1293 | #ifdef CONFIG_SMP | |
1294 | ori r8,r8,0x12 /* R/W access, M=1 */ | |
1295 | #else | |
1296 | ori r8,r8,2 /* R/W access */ | |
1297 | #endif /* CONFIG_SMP */ | |
1298 | #ifdef CONFIG_APUS | |
1299 | ori r11,r11,BL_8M<<2|0x2 /* set up 8MB BAT registers for 604 */ | |
1300 | #else | |
1301 | ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */ | |
1302 | #endif /* CONFIG_APUS */ | |
1303 | ||
14cf11af PM |
1304 | mtspr SPRN_DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ |
1305 | mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */ | |
1306 | mtspr SPRN_IBAT0L,r8 | |
1307 | mtspr SPRN_IBAT0U,r11 | |
1308 | isync | |
1309 | blr | |
1310 | ||
14cf11af | 1311 | |
51d3082f BH |
1312 | #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) |
1313 | setup_disp_bat: | |
1314 | /* | |
1315 | * setup the display bat prepared for us in prom.c | |
1316 | */ | |
1317 | mflr r8 | |
1318 | bl reloc_offset | |
1319 | mtlr r8 | |
1320 | addis r8,r3,disp_BAT@ha | |
1321 | addi r8,r8,disp_BAT@l | |
1322 | cmpwi cr0,r8,0 | |
1323 | beqlr | |
1324 | lwz r11,0(r8) | |
1325 | lwz r8,4(r8) | |
1326 | mfspr r9,SPRN_PVR | |
1327 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | |
1328 | cmpwi 0,r9,1 | |
1329 | beq 1f | |
1330 | mtspr SPRN_DBAT3L,r8 | |
1331 | mtspr SPRN_DBAT3U,r11 | |
1332 | blr | |
1333 | 1: mtspr SPRN_IBAT3L,r8 | |
1334 | mtspr SPRN_IBAT3U,r11 | |
1335 | blr | |
1336 | #endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */ | |
1337 | ||
14cf11af PM |
1338 | #ifdef CONFIG_8260 |
1339 | /* Jump into the system reset for the rom. | |
1340 | * We first disable the MMU, and then jump to the ROM reset address. | |
1341 | * | |
1342 | * r3 is the board info structure, r4 is the location for starting. | |
1343 | * I use this for building a small kernel that can load other kernels, | |
1344 | * rather than trying to write or rely on a rom monitor that can tftp load. | |
1345 | */ | |
1346 | .globl m8260_gorom | |
1347 | m8260_gorom: | |
1348 | mfmsr r0 | |
1349 | rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */ | |
1350 | sync | |
1351 | mtmsr r0 | |
1352 | sync | |
1353 | mfspr r11, SPRN_HID0 | |
1354 | lis r10, 0 | |
1355 | ori r10,r10,HID0_ICE|HID0_DCE | |
1356 | andc r11, r11, r10 | |
1357 | mtspr SPRN_HID0, r11 | |
1358 | isync | |
1359 | li r5, MSR_ME|MSR_RI | |
1360 | lis r6,2f@h | |
1361 | addis r6,r6,-KERNELBASE@h | |
1362 | ori r6,r6,2f@l | |
1363 | mtspr SPRN_SRR0,r6 | |
1364 | mtspr SPRN_SRR1,r5 | |
1365 | isync | |
1366 | sync | |
1367 | rfi | |
1368 | 2: | |
1369 | mtlr r4 | |
1370 | blr | |
1371 | #endif | |
1372 | ||
1373 | ||
1374 | /* | |
1375 | * We put a few things here that have to be page-aligned. | |
1376 | * This stuff goes at the beginning of the data segment, | |
1377 | * which is page-aligned. | |
1378 | */ | |
1379 | .data | |
1380 | .globl sdata | |
1381 | sdata: | |
1382 | .globl empty_zero_page | |
1383 | empty_zero_page: | |
1384 | .space 4096 | |
1385 | ||
1386 | .globl swapper_pg_dir | |
1387 | swapper_pg_dir: | |
1388 | .space 4096 | |
1389 | ||
1390 | /* | |
1391 | * This space gets a copy of optional info passed to us by the bootstrap | |
1392 | * Used to pass parameters into the kernel like root=/dev/sda1, etc. | |
1393 | */ | |
1394 | .globl cmd_line | |
1395 | cmd_line: | |
1396 | .space 512 | |
1397 | ||
1398 | .globl intercept_table | |
1399 | intercept_table: | |
1400 | .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700 | |
1401 | .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0 | |
1402 | .long 0, 0, 0, i0x1300, 0, 0, 0, 0 | |
1403 | .long 0, 0, 0, 0, 0, 0, 0, 0 | |
1404 | .long 0, 0, 0, 0, 0, 0, 0, 0 | |
1405 | .long 0, 0, 0, 0, 0, 0, 0, 0 | |
1406 | ||
1407 | /* Room for two PTE pointers, usually the kernel and current user pointers | |
1408 | * to their respective root page table. | |
1409 | */ | |
1410 | abatron_pteptrs: | |
1411 | .space 8 |