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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
14cf11af | 2 | /* |
14cf11af PM |
3 | * PowerPC version |
4 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
5 | * | |
6 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
7 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
8 | * Adapted for Power Macintosh by Paul Mackerras. | |
9 | * Low-level exception handlers and MMU support | |
10 | * rewritten by Paul Mackerras. | |
11 | * Copyright (C) 1996 Paul Mackerras. | |
12 | * | |
13 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
14 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
15 | * | |
0ebc4cda BH |
16 | * This file contains the entry point for the 64-bit kernel along |
17 | * with some early initialization code common to all 64-bit powerpc | |
18 | * variants. | |
14cf11af PM |
19 | */ |
20 | ||
14cf11af | 21 | #include <linux/threads.h> |
c141611f | 22 | #include <linux/init.h> |
b5bbeb23 | 23 | #include <asm/reg.h> |
14cf11af PM |
24 | #include <asm/page.h> |
25 | #include <asm/mmu.h> | |
14cf11af | 26 | #include <asm/ppc_asm.h> |
57f26649 | 27 | #include <asm/head-64.h> |
14cf11af PM |
28 | #include <asm/asm-offsets.h> |
29 | #include <asm/bug.h> | |
30 | #include <asm/cputable.h> | |
31 | #include <asm/setup.h> | |
32 | #include <asm/hvcall.h> | |
6cb7bfeb | 33 | #include <asm/thread_info.h> |
3f639ee8 | 34 | #include <asm/firmware.h> |
16a15a30 | 35 | #include <asm/page_64.h> |
945feb17 | 36 | #include <asm/irqflags.h> |
2191d657 | 37 | #include <asm/kvm_book3s_asm.h> |
46f52210 | 38 | #include <asm/ptrace.h> |
7230c564 | 39 | #include <asm/hw_irq.h> |
6becef7e | 40 | #include <asm/cputhreads.h> |
7a25d912 | 41 | #include <asm/ppc-opcode.h> |
9445aa1a | 42 | #include <asm/export.h> |
2c86cd18 | 43 | #include <asm/feature-fixups.h> |
14cf11af | 44 | |
25985edc | 45 | /* The physical memory is laid out such that the secondary processor |
0ebc4cda BH |
46 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow |
47 | * using the layout described in exceptions-64s.S | |
14cf11af PM |
48 | */ |
49 | ||
50 | /* | |
51 | * Entering into this code we make the following assumptions: | |
0ebc4cda BH |
52 | * |
53 | * For pSeries or server processors: | |
14cf11af | 54 | * 1. The MMU is off & open firmware is running in real mode. |
339a3293 NP |
55 | * 2. The primary CPU enters at __start. |
56 | * 3. If the RTAS supports "query-cpu-stopped-state", then secondary | |
57 | * CPUs will enter as directed by "start-cpu" RTAS call, which is | |
58 | * generic_secondary_smp_init, with PIR in r3. | |
59 | * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as | |
60 | * directed by the "start-cpu" RTS call, with PIR in r3. | |
27f44888 | 61 | * -or- For OPAL entry: |
339a3293 NP |
62 | * 1. The MMU is off, processor in HV mode. |
63 | * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base | |
64 | * in r8, and entry in r9 for debugging purposes. | |
65 | * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which | |
66 | * is at generic_secondary_smp_init, with PIR in r3. | |
14cf11af | 67 | * |
0ebc4cda BH |
68 | * For Book3E processors: |
69 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | |
70 | * 2. The kernel is entered at __start | |
14cf11af PM |
71 | */ |
72 | ||
57f26649 NP |
73 | OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) |
74 | USE_FIXED_SECTION(first_256B) | |
75 | /* | |
76 | * Offsets are relative from the start of fixed section, and | |
77 | * first_256B starts at 0. Offsets are a bit easier to use here | |
78 | * than the fixed section entry macros. | |
79 | */ | |
80 | . = 0x0 | |
14cf11af PM |
81 | _GLOBAL(__start) |
82 | /* NOP this out unconditionally */ | |
83 | BEGIN_FTR_SECTION | |
5c0484e2 | 84 | FIXUP_ENDIAN |
b1576fec | 85 | b __start_initialization_multiplatform |
14cf11af | 86 | END_FTR_SECTION(0, 1) |
14cf11af PM |
87 | |
88 | /* Catch branch to 0 in real mode */ | |
89 | trap | |
90 | ||
2751b628 AB |
91 | /* Secondary processors spin on this value until it becomes non-zero. |
92 | * When non-zero, it contains the real address of the function the cpu | |
93 | * should jump to. | |
1f6a93e4 | 94 | */ |
7d4151b5 | 95 | .balign 8 |
14cf11af PM |
96 | .globl __secondary_hold_spinloop |
97 | __secondary_hold_spinloop: | |
eb039161 | 98 | .8byte 0x0 |
14cf11af PM |
99 | |
100 | /* Secondary processors write this value with their cpu # */ | |
101 | /* after they enter the spin loop immediately below. */ | |
102 | .globl __secondary_hold_acknowledge | |
103 | __secondary_hold_acknowledge: | |
eb039161 | 104 | .8byte 0x0 |
14cf11af | 105 | |
928a3197 | 106 | #ifdef CONFIG_RELOCATABLE |
8b8b0cc1 MM |
107 | /* This flag is set to 1 by a loader if the kernel should run |
108 | * at the loaded address instead of the linked address. This | |
109 | * is used by kexec-tools to keep the the kdump kernel in the | |
110 | * crash_kernel region. The loader is responsible for | |
111 | * observing the alignment requirement. | |
112 | */ | |
70839d20 NP |
113 | |
114 | #ifdef CONFIG_RELOCATABLE_TEST | |
115 | #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ | |
116 | #else | |
117 | #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ | |
118 | #endif | |
119 | ||
8b8b0cc1 MM |
120 | /* Do not move this variable as kexec-tools knows about it. */ |
121 | . = 0x5c | |
122 | .globl __run_at_load | |
123 | __run_at_load: | |
57f26649 | 124 | DEFINE_FIXED_SYMBOL(__run_at_load) |
70839d20 | 125 | .long RUN_AT_LOAD_DEFAULT |
8b8b0cc1 MM |
126 | #endif |
127 | ||
14cf11af PM |
128 | . = 0x60 |
129 | /* | |
75423b7b GL |
130 | * The following code is used to hold secondary processors |
131 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
132 | * before the bulk of the kernel has been relocated. This code |
133 | * is relocated to physical address 0x60 before prom_init is run. | |
134 | * All of it must fit below the first exception vector at 0x100. | |
1f6a93e4 PM |
135 | * Use .globl here not _GLOBAL because we want __secondary_hold |
136 | * to be the actual text address, not a descriptor. | |
14cf11af | 137 | */ |
1f6a93e4 PM |
138 | .globl __secondary_hold |
139 | __secondary_hold: | |
5c0484e2 | 140 | FIXUP_ENDIAN |
2d27cfd3 | 141 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
142 | mfmsr r24 |
143 | ori r24,r24,MSR_RI | |
144 | mtmsrd r24 /* RI on */ | |
2d27cfd3 | 145 | #endif |
f1870f77 | 146 | /* Grab our physical cpu number */ |
14cf11af | 147 | mr r24,r3 |
96f013fe JX |
148 | /* stash r4 for book3e */ |
149 | mr r25,r4 | |
14cf11af PM |
150 | |
151 | /* Tell the master cpu we're here */ | |
152 | /* Relocation is off & we are located at an address less */ | |
153 | /* than 0x100, so only need to grab low order offset. */ | |
57f26649 | 154 | std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0) |
14cf11af PM |
155 | sync |
156 | ||
96f013fe JX |
157 | li r26,0 |
158 | #ifdef CONFIG_PPC_BOOK3E | |
159 | tovirt(r26,r26) | |
160 | #endif | |
14cf11af | 161 | /* All secondary cpus wait here until told to start. */ |
57f26649 | 162 | 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26) |
cc7efbf9 | 163 | cmpdi 0,r12,0 |
1f6a93e4 | 164 | beq 100b |
14cf11af | 165 | |
da665885 | 166 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) |
96f013fe | 167 | #ifdef CONFIG_PPC_BOOK3E |
cc7efbf9 | 168 | tovirt(r12,r12) |
cc7efbf9 AB |
169 | #endif |
170 | mtctr r12 | |
14cf11af | 171 | mr r3,r24 |
96f013fe JX |
172 | /* |
173 | * it may be the case that other platforms have r4 right to | |
174 | * begin with, this gives us some safety in case it is not | |
175 | */ | |
176 | #ifdef CONFIG_PPC_BOOK3E | |
177 | mr r4,r25 | |
178 | #else | |
2d27cfd3 | 179 | li r4,0 |
96f013fe | 180 | #endif |
dd797738 BH |
181 | /* Make sure that patched code is visible */ |
182 | isync | |
758438a7 | 183 | bctr |
14cf11af PM |
184 | #else |
185 | BUG_OPCODE | |
186 | #endif | |
57f26649 | 187 | CLOSE_FIXED_SECTION(first_256B) |
14cf11af PM |
188 | |
189 | /* This value is used to mark exception frames on the stack. */ | |
190 | .section ".toc","aw" | |
191 | exception_marker: | |
192 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
57f26649 | 193 | .previous |
14cf11af | 194 | |
14cf11af | 195 | /* |
0ebc4cda BH |
196 | * On server, we include the exception vectors code here as it |
197 | * relies on absolute addressing which is only possible within | |
198 | * this compilation unit | |
3c726f8d | 199 | */ |
0ebc4cda BH |
200 | #ifdef CONFIG_PPC_BOOK3S |
201 | #include "exceptions-64s.S" | |
57f26649 NP |
202 | #else |
203 | OPEN_TEXT_SECTION(0x100) | |
1f6a93e4 | 204 | #endif |
3c726f8d | 205 | |
57f26649 NP |
206 | USE_TEXT_SECTION() |
207 | ||
e16c8765 | 208 | #ifdef CONFIG_PPC_BOOK3E |
6becef7e | 209 | /* |
210 | * The booting_thread_hwid holds the thread id we want to boot in cpu | |
211 | * hotplug case. It is set by cpu hotplug code, and is invalid by default. | |
212 | * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] | |
213 | * bit field. | |
214 | */ | |
215 | .globl booting_thread_hwid | |
216 | booting_thread_hwid: | |
217 | .long INVALID_THREAD_HWID | |
218 | .align 3 | |
219 | /* | |
220 | * start a thread in the same core | |
221 | * input parameters: | |
222 | * r3 = the thread physical id | |
223 | * r4 = the entry point where thread starts | |
224 | */ | |
225 | _GLOBAL(book3e_start_thread) | |
226 | LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) | |
f87f253b | 227 | cmpwi r3, 0 |
6becef7e | 228 | beq 10f |
f87f253b | 229 | cmpwi r3, 1 |
6becef7e | 230 | beq 11f |
231 | /* If the thread id is invalid, just exit. */ | |
232 | b 13f | |
233 | 10: | |
7a25d912 SW |
234 | MTTMR(TMRN_IMSR0, 5) |
235 | MTTMR(TMRN_INIA0, 4) | |
6becef7e | 236 | b 12f |
237 | 11: | |
7a25d912 SW |
238 | MTTMR(TMRN_IMSR1, 5) |
239 | MTTMR(TMRN_INIA1, 4) | |
6becef7e | 240 | 12: |
241 | isync | |
242 | li r6, 1 | |
243 | sld r6, r6, r3 | |
244 | mtspr SPRN_TENS, r6 | |
245 | 13: | |
246 | blr | |
247 | ||
d17799f9 | 248 | /* |
249 | * stop a thread in the same core | |
250 | * input parameter: | |
251 | * r3 = the thread physical id | |
252 | */ | |
253 | _GLOBAL(book3e_stop_thread) | |
f87f253b | 254 | cmpwi r3, 0 |
d17799f9 | 255 | beq 10f |
f87f253b | 256 | cmpwi r3, 1 |
d17799f9 | 257 | beq 10f |
258 | /* If the thread id is invalid, just exit. */ | |
259 | b 13f | |
260 | 10: | |
261 | li r4, 1 | |
262 | sld r4, r4, r3 | |
263 | mtspr SPRN_TENC, r4 | |
264 | 13: | |
265 | blr | |
266 | ||
e16c8765 | 267 | _GLOBAL(fsl_secondary_thread_init) |
f34b3e19 SW |
268 | mfspr r4,SPRN_BUCSR |
269 | ||
e16c8765 AF |
270 | /* Enable branch prediction */ |
271 | lis r3,BUCSR_INIT@h | |
272 | ori r3,r3,BUCSR_INIT@l | |
273 | mtspr SPRN_BUCSR,r3 | |
274 | isync | |
275 | ||
276 | /* | |
277 | * Fix PIR to match the linear numbering in the device tree. | |
278 | * | |
279 | * On e6500, the reset value of PIR uses the low three bits for | |
280 | * the thread within a core, and the upper bits for the core | |
281 | * number. There are two threads per core, so shift everything | |
282 | * but the low bit right by two bits so that the cpu numbering is | |
283 | * continuous. | |
f34b3e19 SW |
284 | * |
285 | * If the old value of BUCSR is non-zero, this thread has run | |
286 | * before. Thus, we assume we are coming from kexec or a similar | |
287 | * scenario, and PIR is already set to the correct value. This | |
288 | * is a bit of a hack, but there are limited opportunities for | |
289 | * getting information into the thread and the alternatives | |
290 | * seemed like they'd be overkill. We can't tell just by looking | |
291 | * at the old PIR value which state it's in, since the same value | |
292 | * could be valid for one thread out of reset and for a different | |
293 | * thread in Linux. | |
e16c8765 | 294 | */ |
f34b3e19 | 295 | |
e16c8765 | 296 | mfspr r3, SPRN_PIR |
f34b3e19 SW |
297 | cmpwi r4,0 |
298 | bne 1f | |
e16c8765 AF |
299 | rlwimi r3, r3, 30, 2, 30 |
300 | mtspr SPRN_PIR, r3 | |
f34b3e19 | 301 | 1: |
e16c8765 AF |
302 | #endif |
303 | ||
2d27cfd3 BH |
304 | _GLOBAL(generic_secondary_thread_init) |
305 | mr r24,r3 | |
306 | ||
307 | /* turn on 64-bit mode */ | |
b1576fec | 308 | bl enable_64b_mode |
2d27cfd3 BH |
309 | |
310 | /* get a valid TOC pointer, wherever we're mapped at */ | |
b1576fec | 311 | bl relative_toc |
1fbe9cf2 | 312 | tovirt(r2,r2) |
2d27cfd3 BH |
313 | |
314 | #ifdef CONFIG_PPC_BOOK3E | |
315 | /* Book3E initialization */ | |
316 | mr r3,r24 | |
b1576fec | 317 | bl book3e_secondary_thread_init |
2d27cfd3 BH |
318 | #endif |
319 | b generic_secondary_common_init | |
14cf11af PM |
320 | |
321 | /* | |
f39b7a55 OJ |
322 | * On pSeries and most other platforms, secondary processors spin |
323 | * in the following code. | |
14cf11af | 324 | * At entry, r3 = this processor's number (physical cpu id) |
2d27cfd3 BH |
325 | * |
326 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for | |
327 | * this core already exists (setup via some other mechanism such | |
328 | * as SCOM before entry). | |
14cf11af | 329 | */ |
f39b7a55 | 330 | _GLOBAL(generic_secondary_smp_init) |
5c0484e2 | 331 | FIXUP_ENDIAN |
14cf11af | 332 | mr r24,r3 |
2d27cfd3 BH |
333 | mr r25,r4 |
334 | ||
14cf11af | 335 | /* turn on 64-bit mode */ |
b1576fec | 336 | bl enable_64b_mode |
14cf11af | 337 | |
2d27cfd3 | 338 | /* get a valid TOC pointer, wherever we're mapped at */ |
b1576fec | 339 | bl relative_toc |
1fbe9cf2 | 340 | tovirt(r2,r2) |
e31aa453 | 341 | |
2d27cfd3 BH |
342 | #ifdef CONFIG_PPC_BOOK3E |
343 | /* Book3E initialization */ | |
344 | mr r3,r24 | |
345 | mr r4,r25 | |
b1576fec | 346 | bl book3e_secondary_core_init |
6becef7e | 347 | |
348 | /* | |
349 | * After common core init has finished, check if the current thread is the | |
350 | * one we wanted to boot. If not, start the specified thread and stop the | |
351 | * current thread. | |
352 | */ | |
353 | LOAD_REG_ADDR(r4, booting_thread_hwid) | |
354 | lwz r3, 0(r4) | |
355 | li r5, INVALID_THREAD_HWID | |
356 | cmpw r3, r5 | |
357 | beq 20f | |
358 | ||
359 | /* | |
360 | * The value of booting_thread_hwid has been stored in r3, | |
361 | * so make it invalid. | |
362 | */ | |
363 | stw r5, 0(r4) | |
364 | ||
365 | /* | |
366 | * Get the current thread id and check if it is the one we wanted. | |
367 | * If not, start the one specified in booting_thread_hwid and stop | |
368 | * the current thread. | |
369 | */ | |
370 | mfspr r8, SPRN_TIR | |
371 | cmpw r3, r8 | |
372 | beq 20f | |
373 | ||
374 | /* start the specified thread */ | |
375 | LOAD_REG_ADDR(r5, fsl_secondary_thread_init) | |
376 | ld r4, 0(r5) | |
377 | bl book3e_start_thread | |
378 | ||
379 | /* stop the current thread */ | |
380 | mr r3, r8 | |
381 | bl book3e_stop_thread | |
382 | 10: | |
383 | b 10b | |
384 | 20: | |
2d27cfd3 BH |
385 | #endif |
386 | ||
387 | generic_secondary_common_init: | |
14cf11af PM |
388 | /* Set up a paca value for this processor. Since we have the |
389 | * physical cpu id in r24, we need to search the pacas to find | |
390 | * which logical id maps to our physical one. | |
391 | */ | |
768d18ad | 392 | #ifndef CONFIG_SMP |
b1576fec | 393 | b kexec_wait /* wait for next kernel if !SMP */ |
768d18ad | 394 | #else |
d2e60075 NP |
395 | LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ |
396 | ld r8,0(r8) /* Get base vaddr of array */ | |
768d18ad MM |
397 | LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ |
398 | lwz r7,0(r7) /* also the max paca allocated */ | |
14cf11af | 399 | li r5,0 /* logical cpu id */ |
d2e60075 NP |
400 | 1: |
401 | sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ | |
402 | ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ | |
403 | lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
14cf11af PM |
404 | cmpw r6,r24 /* Compare to our id */ |
405 | beq 2f | |
14cf11af | 406 | addi r5,r5,1 |
768d18ad | 407 | cmpw r5,r7 /* Check if more pacas exist */ |
14cf11af PM |
408 | blt 1b |
409 | ||
410 | mr r3,r24 /* not found, copy phys to r3 */ | |
b1576fec | 411 | b kexec_wait /* next kernel might do better */ |
14cf11af | 412 | |
2dd60d79 | 413 | 2: SET_PACA(r13) |
2d27cfd3 BH |
414 | #ifdef CONFIG_PPC_BOOK3E |
415 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ | |
416 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 | |
417 | #endif | |
418 | ||
14cf11af PM |
419 | /* From now on, r24 is expected to be logical cpuid */ |
420 | mr r24,r5 | |
b6f6b98a | 421 | |
f39b7a55 | 422 | /* See if we need to call a cpu state restore handler */ |
e31aa453 | 423 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
f39b7a55 | 424 | ld r23,0(r23) |
2751b628 AB |
425 | ld r12,CPU_SPEC_RESTORE(r23) |
426 | cmpdi 0,r12,0 | |
9d07bc84 | 427 | beq 3f |
f55d9665 | 428 | #ifdef PPC64_ELF_ABI_v1 |
2751b628 AB |
429 | ld r12,0(r12) |
430 | #endif | |
cc7efbf9 | 431 | mtctr r12 |
f39b7a55 OJ |
432 | bctrl |
433 | ||
7ac87abb | 434 | 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ |
9d07bc84 BH |
435 | lwarx r4,0,r3 |
436 | subi r4,r4,1 | |
437 | stwcx. r4,0,r3 | |
438 | bne 3b | |
439 | isync | |
440 | ||
441 | 4: HMT_LOW | |
ad0693ee BH |
442 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ |
443 | /* start. */ | |
ad0693ee | 444 | cmpwi 0,r23,0 |
9d07bc84 | 445 | beq 4b /* Loop until told to go */ |
ad0693ee BH |
446 | |
447 | sync /* order paca.run and cur_cpu_spec */ | |
9d07bc84 | 448 | isync /* In case code patching happened */ |
ad0693ee | 449 | |
9d07bc84 | 450 | /* Create a temp kernel stack for use before relocation is on. */ |
14cf11af PM |
451 | ld r1,PACAEMERGSP(r13) |
452 | subi r1,r1,STACK_FRAME_OVERHEAD | |
453 | ||
c705677e | 454 | b __secondary_start |
768d18ad | 455 | #endif /* SMP */ |
14cf11af | 456 | |
e31aa453 PM |
457 | /* |
458 | * Turn the MMU off. | |
459 | * Assumes we're mapped EA == RA if the MMU is on. | |
460 | */ | |
2d27cfd3 | 461 | #ifdef CONFIG_PPC_BOOK3S |
6a3bab90 | 462 | __mmu_off: |
14cf11af PM |
463 | mfmsr r3 |
464 | andi. r0,r3,MSR_IR|MSR_DR | |
465 | beqlr | |
e31aa453 | 466 | mflr r4 |
14cf11af PM |
467 | andc r3,r3,r0 |
468 | mtspr SPRN_SRR0,r4 | |
469 | mtspr SPRN_SRR1,r3 | |
470 | sync | |
471 | rfid | |
472 | b . /* prevent speculative execution */ | |
2d27cfd3 | 473 | #endif |
14cf11af PM |
474 | |
475 | ||
476 | /* | |
477 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
478 | * depending on the value of r5. | |
479 | * | |
480 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
481 | * in r3...r7 | |
482 | * | |
483 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
484 | * DT block, r4 is a physical pointer to the kernel itself | |
485 | * | |
486 | */ | |
6a3bab90 | 487 | __start_initialization_multiplatform: |
e31aa453 | 488 | /* Make sure we are running in 64 bits mode */ |
b1576fec | 489 | bl enable_64b_mode |
e31aa453 PM |
490 | |
491 | /* Get TOC pointer (current runtime address) */ | |
b1576fec | 492 | bl relative_toc |
e31aa453 PM |
493 | |
494 | /* find out where we are now */ | |
495 | bcl 20,31,$+4 | |
496 | 0: mflr r26 /* r26 = runtime addr here */ | |
497 | addis r26,r26,(_stext - 0b)@ha | |
498 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ | |
499 | ||
14cf11af PM |
500 | /* |
501 | * Are we booted from a PROM Of-type client-interface ? | |
502 | */ | |
503 | cmpldi cr0,r5,0 | |
939e60f6 | 504 | beq 1f |
b1576fec | 505 | b __boot_from_prom /* yes -> prom */ |
939e60f6 | 506 | 1: |
14cf11af PM |
507 | /* Save parameters */ |
508 | mr r31,r3 | |
509 | mr r30,r4 | |
daea1175 BH |
510 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
511 | /* Save OPAL entry */ | |
512 | mr r28,r8 | |
513 | mr r29,r9 | |
514 | #endif | |
14cf11af | 515 | |
2d27cfd3 | 516 | #ifdef CONFIG_PPC_BOOK3E |
b1576fec AB |
517 | bl start_initialization_book3e |
518 | b __after_prom_start | |
2d27cfd3 | 519 | #else |
14cf11af | 520 | /* Setup some critical 970 SPRs before switching MMU off */ |
f39b7a55 OJ |
521 | mfspr r0,SPRN_PVR |
522 | srwi r0,r0,16 | |
523 | cmpwi r0,0x39 /* 970 */ | |
524 | beq 1f | |
525 | cmpwi r0,0x3c /* 970FX */ | |
526 | beq 1f | |
527 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
528 | beq 1f |
529 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 | 530 | bne 2f |
b1576fec | 531 | 1: bl __cpu_preinit_ppc970 |
f39b7a55 | 532 | 2: |
14cf11af | 533 | |
e31aa453 | 534 | /* Switch off MMU if not already off */ |
b1576fec AB |
535 | bl __mmu_off |
536 | b __after_prom_start | |
2d27cfd3 | 537 | #endif /* CONFIG_PPC_BOOK3E */ |
14cf11af | 538 | |
6a3bab90 | 539 | __boot_from_prom: |
28794d34 | 540 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
14cf11af PM |
541 | /* Save parameters */ |
542 | mr r31,r3 | |
543 | mr r30,r4 | |
544 | mr r29,r5 | |
545 | mr r28,r6 | |
546 | mr r27,r7 | |
547 | ||
6088857b OH |
548 | /* |
549 | * Align the stack to 16-byte boundary | |
550 | * Depending on the size and layout of the ELF sections in the initial | |
e31aa453 | 551 | * boot binary, the stack pointer may be unaligned on PowerMac |
6088857b | 552 | */ |
c05b4770 LT |
553 | rldicr r1,r1,0,59 |
554 | ||
549e8152 PM |
555 | #ifdef CONFIG_RELOCATABLE |
556 | /* Relocate code for where we are now */ | |
557 | mr r3,r26 | |
b1576fec | 558 | bl relocate |
549e8152 PM |
559 | #endif |
560 | ||
14cf11af PM |
561 | /* Restore parameters */ |
562 | mr r3,r31 | |
563 | mr r4,r30 | |
564 | mr r5,r29 | |
565 | mr r6,r28 | |
566 | mr r7,r27 | |
567 | ||
568 | /* Do all of the interaction with OF client interface */ | |
549e8152 | 569 | mr r8,r26 |
b1576fec | 570 | bl prom_init |
28794d34 BH |
571 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
572 | ||
573 | /* We never return. We also hit that trap if trying to boot | |
574 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
14cf11af PM |
575 | trap |
576 | ||
6a3bab90 | 577 | __after_prom_start: |
549e8152 PM |
578 | #ifdef CONFIG_RELOCATABLE |
579 | /* process relocations for the final address of the kernel */ | |
580 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ | |
581 | sldi r25,r25,32 | |
1cb6e064 TC |
582 | #if defined(CONFIG_PPC_BOOK3E) |
583 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ | |
584 | #endif | |
57f26649 | 585 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) |
1cb6e064 TC |
586 | #if defined(CONFIG_PPC_BOOK3E) |
587 | tophys(r26,r26) | |
588 | #endif | |
928a3197 | 589 | cmplwi cr0,r7,1 /* flagged to stay where we are ? */ |
54622f10 MK |
590 | bne 1f |
591 | add r25,r25,r26 | |
54622f10 | 592 | 1: mr r3,r25 |
b1576fec | 593 | bl relocate |
1cb6e064 TC |
594 | #if defined(CONFIG_PPC_BOOK3E) |
595 | /* IVPR needs to be set after relocation. */ | |
596 | bl init_core_book3e | |
597 | #endif | |
549e8152 | 598 | #endif |
14cf11af PM |
599 | |
600 | /* | |
e31aa453 | 601 | * We need to run with _stext at physical address PHYSICAL_START. |
14cf11af PM |
602 | * This will leave some code in the first 256B of |
603 | * real memory, which are reserved for software use. | |
14cf11af PM |
604 | * |
605 | * Note: This process overwrites the OF exception vectors. | |
14cf11af | 606 | */ |
549e8152 | 607 | li r3,0 /* target addr */ |
2d27cfd3 | 608 | #ifdef CONFIG_PPC_BOOK3E |
835c031c | 609 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ |
2d27cfd3 | 610 | #endif |
549e8152 | 611 | mr. r4,r26 /* In some cases the loader may */ |
835c031c TC |
612 | #if defined(CONFIG_PPC_BOOK3E) |
613 | tovirt(r4,r4) | |
614 | #endif | |
e31aa453 | 615 | beq 9f /* have already put us at zero */ |
14cf11af PM |
616 | li r6,0x100 /* Start offset, the first 0x100 */ |
617 | /* bytes were copied earlier. */ | |
618 | ||
11ee7e99 | 619 | #ifdef CONFIG_RELOCATABLE |
54622f10 MK |
620 | /* |
621 | * Check if the kernel has to be running as relocatable kernel based on the | |
8b8b0cc1 | 622 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
54622f10 MK |
623 | * kernel, otherwise it will be moved to PHYSICAL_START |
624 | */ | |
1cb6e064 TC |
625 | #if defined(CONFIG_PPC_BOOK3E) |
626 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ | |
627 | #endif | |
57f26649 | 628 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) |
8b8b0cc1 | 629 | cmplwi cr0,r7,1 |
54622f10 MK |
630 | bne 3f |
631 | ||
1cb6e064 TC |
632 | #ifdef CONFIG_PPC_BOOK3E |
633 | LOAD_REG_ADDR(r5, __end_interrupts) | |
634 | LOAD_REG_ADDR(r11, _stext) | |
635 | sub r5,r5,r11 | |
636 | #else | |
c1fb6816 | 637 | /* just copy interrupts */ |
57f26649 | 638 | LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) |
1cb6e064 | 639 | #endif |
54622f10 MK |
640 | b 5f |
641 | 3: | |
642 | #endif | |
57f26649 NP |
643 | /* # bytes of memory to copy */ |
644 | lis r5,(ABS_ADDR(copy_to_here))@ha | |
645 | addi r5,r5,(ABS_ADDR(copy_to_here))@l | |
54622f10 | 646 | |
b1576fec | 647 | bl copy_and_flush /* copy the first n bytes */ |
14cf11af PM |
648 | /* this includes the code being */ |
649 | /* executed here. */ | |
57f26649 NP |
650 | /* Jump to the copy of this code that we just made */ |
651 | addis r8,r3,(ABS_ADDR(4f))@ha | |
652 | addi r12,r8,(ABS_ADDR(4f))@l | |
cc7efbf9 | 653 | mtctr r12 |
14cf11af PM |
654 | bctr |
655 | ||
286e4f90 | 656 | .balign 8 |
eb039161 | 657 | p_end: .8byte _end - copy_to_here |
54622f10 | 658 | |
573819e3 NP |
659 | 4: |
660 | /* | |
661 | * Now copy the rest of the kernel up to _end, add | |
662 | * _end - copy_to_here to the copy limit and run again. | |
663 | */ | |
57f26649 NP |
664 | addis r8,r26,(ABS_ADDR(p_end))@ha |
665 | ld r8,(ABS_ADDR(p_end))@l(r8) | |
573819e3 | 666 | add r5,r5,r8 |
b1576fec | 667 | 5: bl copy_and_flush /* copy the rest */ |
e31aa453 | 668 | |
b1576fec | 669 | 9: b start_here_multiplatform |
e31aa453 | 670 | |
14cf11af PM |
671 | /* |
672 | * Copy routine used to copy the kernel to start at physical address 0 | |
673 | * and flush and invalidate the caches as needed. | |
674 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
675 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
676 | * | |
677 | * Note: this routine *only* clobbers r0, r6 and lr | |
678 | */ | |
679 | _GLOBAL(copy_and_flush) | |
680 | addi r5,r5,-8 | |
681 | addi r6,r6,-8 | |
5a2fe38d | 682 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
683 | /* denominator cache line */ |
684 | /* size. This results in */ | |
685 | /* extra cache line flushes */ | |
686 | /* but operation is correct. */ | |
687 | /* Can't get cache line size */ | |
688 | /* from NACA as it is being */ | |
689 | /* moved too. */ | |
690 | ||
691 | mtctr r0 /* put # words/line in ctr */ | |
692 | 3: addi r6,r6,8 /* copy a cache line */ | |
693 | ldx r0,r6,r4 | |
694 | stdx r0,r6,r3 | |
695 | bdnz 3b | |
696 | dcbst r6,r3 /* write it to memory */ | |
697 | sync | |
698 | icbi r6,r3 /* flush the icache line */ | |
699 | cmpld 0,r6,r5 | |
700 | blt 4b | |
701 | sync | |
702 | addi r5,r5,8 | |
703 | addi r6,r6,8 | |
29ce3c50 | 704 | isync |
14cf11af PM |
705 | blr |
706 | ||
707 | .align 8 | |
708 | copy_to_here: | |
709 | ||
710 | #ifdef CONFIG_SMP | |
711 | #ifdef CONFIG_PPC_PMAC | |
712 | /* | |
713 | * On PowerMac, secondary processors starts from the reset vector, which | |
714 | * is temporarily turned into a call to one of the functions below. | |
715 | */ | |
716 | .section ".text"; | |
717 | .align 2 ; | |
718 | ||
35499c01 PM |
719 | .globl __secondary_start_pmac_0 |
720 | __secondary_start_pmac_0: | |
721 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
722 | li r24,0 | |
723 | b 1f | |
724 | li r24,1 | |
725 | b 1f | |
726 | li r24,2 | |
727 | b 1f | |
728 | li r24,3 | |
729 | 1: | |
14cf11af PM |
730 | |
731 | _GLOBAL(pmac_secondary_start) | |
732 | /* turn on 64-bit mode */ | |
b1576fec | 733 | bl enable_64b_mode |
14cf11af | 734 | |
c478b581 BH |
735 | li r0,0 |
736 | mfspr r3,SPRN_HID4 | |
737 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ | |
738 | sync | |
739 | mtspr SPRN_HID4,r3 | |
740 | isync | |
741 | sync | |
742 | slbia | |
743 | ||
e31aa453 | 744 | /* get TOC pointer (real address) */ |
b1576fec | 745 | bl relative_toc |
1fbe9cf2 | 746 | tovirt(r2,r2) |
e31aa453 | 747 | |
14cf11af | 748 | /* Copy some CPU settings from CPU 0 */ |
b1576fec | 749 | bl __restore_cpu_ppc970 |
14cf11af PM |
750 | |
751 | /* pSeries do that early though I don't think we really need it */ | |
752 | mfmsr r3 | |
753 | ori r3,r3,MSR_RI | |
754 | mtmsrd r3 /* RI on */ | |
755 | ||
756 | /* Set up a paca value for this processor. */ | |
d2e60075 NP |
757 | LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ |
758 | ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ | |
759 | sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ | |
760 | ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ | |
2dd60d79 | 761 | SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ |
14cf11af | 762 | |
62cc67b9 BH |
763 | /* Mark interrupts soft and hard disabled (they might be enabled |
764 | * in the PACA when doing hotplug) | |
765 | */ | |
c2e480ba | 766 | li r0,IRQS_DISABLED |
4e26bc4a | 767 | stb r0,PACAIRQSOFTMASK(r13) |
7230c564 BH |
768 | li r0,PACA_IRQ_HARD_DIS |
769 | stb r0,PACAIRQHAPPENED(r13) | |
62cc67b9 | 770 | |
14cf11af PM |
771 | /* Create a temp kernel stack for use before relocation is on. */ |
772 | ld r1,PACAEMERGSP(r13) | |
773 | subi r1,r1,STACK_FRAME_OVERHEAD | |
774 | ||
c705677e | 775 | b __secondary_start |
14cf11af PM |
776 | |
777 | #endif /* CONFIG_PPC_PMAC */ | |
778 | ||
779 | /* | |
780 | * This function is called after the master CPU has released the | |
781 | * secondary processors. The execution environment is relocation off. | |
782 | * The paca for this processor has the following fields initialized at | |
783 | * this point: | |
784 | * 1. Processor number | |
785 | * 2. Segment table pointer (virtual address) | |
786 | * On entry the following are set: | |
4f8cf36f | 787 | * r1 = stack pointer (real addr of temp stack) |
ee43eb78 BH |
788 | * r24 = cpu# (in Linux terms) |
789 | * r13 = paca virtual address | |
790 | * SPRG_PACA = paca virtual address | |
14cf11af | 791 | */ |
2d27cfd3 BH |
792 | .section ".text"; |
793 | .align 2 ; | |
794 | ||
fc68e869 | 795 | .globl __secondary_start |
c705677e | 796 | __secondary_start: |
799d6046 PM |
797 | /* Set thread priority to MEDIUM */ |
798 | HMT_MEDIUM | |
14cf11af | 799 | |
eafd825e ME |
800 | /* |
801 | * Do early setup for this CPU, in particular initialising the MMU so we | |
802 | * can turn it on below. This is a call to C, which is OK, we're still | |
803 | * running on the emergency stack. | |
804 | */ | |
b1576fec | 805 | bl early_setup_secondary |
f761622e | 806 | |
54a83404 | 807 | /* |
eafd825e ME |
808 | * The primary has initialized our kernel stack for us in the paca, grab |
809 | * it and put it in r1. We must *not* use it until we turn on the MMU | |
810 | * below, because it may not be inside the RMO. | |
54a83404 | 811 | */ |
eafd825e | 812 | ld r1, PACAKSAVE(r13) |
54a83404 | 813 | |
799d6046 | 814 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
815 | li r7,0 |
816 | mtlr r7 | |
817 | ||
7230c564 BH |
818 | /* Mark interrupts soft and hard disabled (they might be enabled |
819 | * in the PACA when doing hotplug) | |
820 | */ | |
c2e480ba | 821 | li r7,IRQS_DISABLED |
4e26bc4a | 822 | stb r7,PACAIRQSOFTMASK(r13) |
7230c564 BH |
823 | li r0,PACA_IRQ_HARD_DIS |
824 | stb r0,PACAIRQHAPPENED(r13) | |
4f8cf36f | 825 | |
14cf11af | 826 | /* enable MMU and jump to start_secondary */ |
ad0289e4 | 827 | LOAD_REG_ADDR(r3, start_secondary_prolog) |
e58c3495 | 828 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) |
d04c56f7 | 829 | |
b5bbeb23 PM |
830 | mtspr SPRN_SRR0,r3 |
831 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 832 | RFI |
14cf11af PM |
833 | b . /* prevent speculative execution */ |
834 | ||
835 | /* | |
836 | * Running with relocation on at this point. All we want to do is | |
e31aa453 PM |
837 | * zero the stack back-chain pointer and get the TOC virtual address |
838 | * before going into C code. | |
14cf11af | 839 | */ |
ad0289e4 | 840 | start_secondary_prolog: |
e31aa453 | 841 | ld r2,PACATOC(r13) |
14cf11af PM |
842 | li r3,0 |
843 | std r3,0(r1) /* Zero the stack frame pointer */ | |
b1576fec | 844 | bl start_secondary |
799d6046 | 845 | b . |
8dbce53c VS |
846 | /* |
847 | * Reset stack pointer and call start_secondary | |
848 | * to continue with online operation when woken up | |
849 | * from cede in cpu offline. | |
850 | */ | |
851 | _GLOBAL(start_secondary_resume) | |
852 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ | |
853 | li r3,0 | |
854 | std r3,0(r1) /* Zero the stack frame pointer */ | |
b1576fec | 855 | bl start_secondary |
8dbce53c | 856 | b . |
14cf11af PM |
857 | #endif |
858 | ||
859 | /* | |
860 | * This subroutine clobbers r11 and r12 | |
861 | */ | |
6a3bab90 | 862 | enable_64b_mode: |
14cf11af | 863 | mfmsr r11 /* grab the current MSR */ |
2d27cfd3 BH |
864 | #ifdef CONFIG_PPC_BOOK3E |
865 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ | |
866 | mtmsr r11 | |
867 | #else /* CONFIG_PPC_BOOK3E */ | |
9f0b0793 | 868 | li r12,(MSR_64BIT | MSR_ISF)@highest |
e31aa453 | 869 | sldi r12,r12,48 |
14cf11af PM |
870 | or r11,r11,r12 |
871 | mtmsrd r11 | |
872 | isync | |
2d27cfd3 | 873 | #endif |
14cf11af PM |
874 | blr |
875 | ||
e31aa453 PM |
876 | /* |
877 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected | |
878 | * by the toolchain). It computes the correct value for wherever we | |
879 | * are running at the moment, using position-independent code. | |
1fbe9cf2 AB |
880 | * |
881 | * Note: The compiler constructs pointers using offsets from the | |
882 | * TOC in -mcmodel=medium mode. After we relocate to 0 but before | |
883 | * the MMU is on we need our TOC to be a virtual address otherwise | |
884 | * these pointers will be real addresses which may get stored and | |
885 | * accessed later with the MMU on. We use tovirt() at the call | |
886 | * sites to handle this. | |
e31aa453 PM |
887 | */ |
888 | _GLOBAL(relative_toc) | |
889 | mflr r0 | |
890 | bcl 20,31,$+4 | |
e550592e BH |
891 | 0: mflr r11 |
892 | ld r2,(p_toc - 0b)(r11) | |
893 | add r2,r2,r11 | |
e31aa453 PM |
894 | mtlr r0 |
895 | blr | |
896 | ||
5b63fee1 | 897 | .balign 8 |
eb039161 | 898 | p_toc: .8byte __toc_start + 0x8000 - 0b |
e31aa453 | 899 | |
14cf11af PM |
900 | /* |
901 | * This is where the main kernel code starts. | |
902 | */ | |
6a3bab90 | 903 | start_here_multiplatform: |
1fbe9cf2 | 904 | /* set up the TOC */ |
b1576fec | 905 | bl relative_toc |
1fbe9cf2 | 906 | tovirt(r2,r2) |
14cf11af PM |
907 | |
908 | /* Clear out the BSS. It may have been done in prom_init, | |
909 | * already but that's irrelevant since prom_init will soon | |
910 | * be detached from the kernel completely. Besides, we need | |
911 | * to clear it now for kexec-style entry. | |
912 | */ | |
e31aa453 PM |
913 | LOAD_REG_ADDR(r11,__bss_stop) |
914 | LOAD_REG_ADDR(r8,__bss_start) | |
14cf11af PM |
915 | sub r11,r11,r8 /* bss size */ |
916 | addi r11,r11,7 /* round up to an even double word */ | |
e31aa453 | 917 | srdi. r11,r11,3 /* shift right by 3 */ |
14cf11af PM |
918 | beq 4f |
919 | addi r8,r8,-8 | |
920 | li r0,0 | |
921 | mtctr r11 /* zero this many doublewords */ | |
922 | 3: stdu r0,8(r8) | |
923 | bdnz 3b | |
924 | 4: | |
925 | ||
daea1175 BH |
926 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
927 | /* Setup OPAL entry */ | |
ab7f961a | 928 | LOAD_REG_ADDR(r11, opal) |
daea1175 BH |
929 | std r28,0(r11); |
930 | std r29,8(r11); | |
931 | #endif | |
932 | ||
2d27cfd3 | 933 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
934 | mfmsr r6 |
935 | ori r6,r6,MSR_RI | |
936 | mtmsrd r6 /* RI on */ | |
2d27cfd3 | 937 | #endif |
14cf11af | 938 | |
549e8152 PM |
939 | #ifdef CONFIG_RELOCATABLE |
940 | /* Save the physical address we're running at in kernstart_addr */ | |
941 | LOAD_REG_ADDR(r4, kernstart_addr) | |
942 | clrldi r0,r25,2 | |
943 | std r0,0(r4) | |
944 | #endif | |
945 | ||
e31aa453 | 946 | /* The following gets the stack set up with the regs */ |
14cf11af PM |
947 | /* pointing to the real addr of the kernel stack. This is */ |
948 | /* all done to support the C function call below which sets */ | |
949 | /* up the htab. This is done because we have relocated the */ | |
950 | /* kernel but are still running in real mode. */ | |
951 | ||
e31aa453 | 952 | LOAD_REG_ADDR(r3,init_thread_union) |
14cf11af | 953 | |
e31aa453 | 954 | /* set up a stack pointer */ |
cabed148 HM |
955 | LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) |
956 | add r1,r3,r1 | |
14cf11af PM |
957 | li r0,0 |
958 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
959 | ||
376af594 ME |
960 | /* |
961 | * Do very early kernel initializations, including initial hash table | |
962 | * and SLB setup before we turn on relocation. | |
963 | */ | |
14cf11af PM |
964 | |
965 | /* Restore parameters passed from prom_init/kexec */ | |
966 | mr r3,r31 | |
56c46bba RC |
967 | LOAD_REG_ADDR(r12, DOTSYM(early_setup)) |
968 | mtctr r12 | |
969 | bctrl /* also sets r13 and SPRG_PACA */ | |
14cf11af | 970 | |
ad0289e4 | 971 | LOAD_REG_ADDR(r3, start_here_common) |
e31aa453 | 972 | ld r4,PACAKMSR(r13) |
b5bbeb23 PM |
973 | mtspr SPRN_SRR0,r3 |
974 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 975 | RFI |
14cf11af | 976 | b . /* prevent speculative execution */ |
fa745a12 | 977 | |
14cf11af | 978 | /* This is where all platforms converge execution */ |
ad0289e4 AB |
979 | |
980 | start_here_common: | |
14cf11af | 981 | /* relocation is on at this point */ |
e31aa453 | 982 | std r1,PACAKSAVE(r13) |
14cf11af | 983 | |
e31aa453 | 984 | /* Load the TOC (virtual address) */ |
14cf11af | 985 | ld r2,PACATOC(r13) |
14cf11af | 986 | |
7230c564 BH |
987 | /* Mark interrupts soft and hard disabled (they might be enabled |
988 | * in the PACA when doing hotplug) | |
989 | */ | |
c2e480ba | 990 | li r0,IRQS_DISABLED |
4e26bc4a | 991 | stb r0,PACAIRQSOFTMASK(r13) |
7230c564 BH |
992 | li r0,PACA_IRQ_HARD_DIS |
993 | stb r0,PACAIRQHAPPENED(r13) | |
14cf11af | 994 | |
7230c564 | 995 | /* Generic kernel entry */ |
b1576fec | 996 | bl start_kernel |
14cf11af | 997 | |
f1870f77 AB |
998 | /* Not reached */ |
999 | BUG_OPCODE | |
14cf11af | 1000 | |
14cf11af PM |
1001 | /* |
1002 | * We put a few things here that have to be page-aligned. | |
1003 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
1004 | */ | |
1005 | .section ".bss" | |
43a5c684 AK |
1006 | /* |
1007 | * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. | |
1008 | * We will need to find a better way to fix this | |
1009 | */ | |
1010 | .align 16 | |
14cf11af | 1011 | |
43a5c684 AK |
1012 | .globl swapper_pg_dir |
1013 | swapper_pg_dir: | |
1014 | .space PGD_TABLE_SIZE | |
14cf11af PM |
1015 | |
1016 | .globl empty_zero_page | |
1017 | empty_zero_page: | |
1018 | .space PAGE_SIZE | |
9445aa1a | 1019 | EXPORT_SYMBOL(empty_zero_page) |