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14cf11af PM |
1 | /* |
2 | * arch/ppc64/kernel/head.S | |
3 | * | |
4 | * PowerPC version | |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
6 | * | |
7 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
8 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
9 | * Adapted for Power Macintosh by Paul Mackerras. | |
10 | * Low-level exception handlers and MMU support | |
11 | * rewritten by Paul Mackerras. | |
12 | * Copyright (C) 1996 Paul Mackerras. | |
13 | * | |
14 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
15 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
16 | * | |
17 | * This file contains the low-level support and setup for the | |
18 | * PowerPC-64 platform, including trap and interrupt dispatch. | |
19 | * | |
20 | * This program is free software; you can redistribute it and/or | |
21 | * modify it under the terms of the GNU General Public License | |
22 | * as published by the Free Software Foundation; either version | |
23 | * 2 of the License, or (at your option) any later version. | |
24 | */ | |
25 | ||
26 | #include <linux/config.h> | |
27 | #include <linux/threads.h> | |
b5bbeb23 | 28 | #include <asm/reg.h> |
14cf11af PM |
29 | #include <asm/page.h> |
30 | #include <asm/mmu.h> | |
14cf11af PM |
31 | #include <asm/ppc_asm.h> |
32 | #include <asm/asm-offsets.h> | |
33 | #include <asm/bug.h> | |
34 | #include <asm/cputable.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/hvcall.h> | |
c43a55ff | 37 | #include <asm/iseries/lpar_map.h> |
6cb7bfeb | 38 | #include <asm/thread_info.h> |
14cf11af PM |
39 | |
40 | #ifdef CONFIG_PPC_ISERIES | |
41 | #define DO_SOFT_DISABLE | |
42 | #endif | |
43 | ||
44 | /* | |
45 | * We layout physical memory as follows: | |
46 | * 0x0000 - 0x00ff : Secondary processor spin code | |
47 | * 0x0100 - 0x2fff : pSeries Interrupt prologs | |
48 | * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs | |
49 | * 0x6000 - 0x6fff : Initial (CPU0) segment table | |
50 | * 0x7000 - 0x7fff : FWNMI data area | |
51 | * 0x8000 - : Early init and support code | |
52 | */ | |
53 | ||
54 | /* | |
55 | * SPRG Usage | |
56 | * | |
57 | * Register Definition | |
58 | * | |
59 | * SPRG0 reserved for hypervisor | |
60 | * SPRG1 temp - used to save gpr | |
61 | * SPRG2 temp - used to save gpr | |
62 | * SPRG3 virt addr of paca | |
63 | */ | |
64 | ||
65 | /* | |
66 | * Entering into this code we make the following assumptions: | |
67 | * For pSeries: | |
68 | * 1. The MMU is off & open firmware is running in real mode. | |
69 | * 2. The kernel is entered at __start | |
70 | * | |
71 | * For iSeries: | |
72 | * 1. The MMU is on (as it always is for iSeries) | |
73 | * 2. The kernel is entered at system_reset_iSeries | |
74 | */ | |
75 | ||
76 | .text | |
77 | .globl _stext | |
78 | _stext: | |
79 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
80 | _GLOBAL(__start) | |
81 | /* NOP this out unconditionally */ | |
82 | BEGIN_FTR_SECTION | |
b85a046a | 83 | b .__start_initialization_multiplatform |
14cf11af PM |
84 | END_FTR_SECTION(0, 1) |
85 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
86 | ||
87 | /* Catch branch to 0 in real mode */ | |
88 | trap | |
89 | ||
90 | #ifdef CONFIG_PPC_ISERIES | |
91 | /* | |
92 | * At offset 0x20, there is a pointer to iSeries LPAR data. | |
93 | * This is required by the hypervisor | |
94 | */ | |
95 | . = 0x20 | |
96 | .llong hvReleaseData-KERNELBASE | |
97 | ||
98 | /* | |
99 | * At offset 0x28 and 0x30 are offsets to the mschunks_map | |
100 | * array (used by the iSeries LPAR debugger to do translation | |
101 | * between physical addresses and absolute addresses) and | |
102 | * to the pidhash table (also used by the debugger) | |
103 | */ | |
104 | .llong mschunks_map-KERNELBASE | |
105 | .llong 0 /* pidhash-KERNELBASE SFRXXX */ | |
106 | ||
107 | /* Offset 0x38 - Pointer to start of embedded System.map */ | |
108 | .globl embedded_sysmap_start | |
109 | embedded_sysmap_start: | |
110 | .llong 0 | |
111 | /* Offset 0x40 - Pointer to end of embedded System.map */ | |
112 | .globl embedded_sysmap_end | |
113 | embedded_sysmap_end: | |
114 | .llong 0 | |
115 | ||
116 | #endif /* CONFIG_PPC_ISERIES */ | |
117 | ||
118 | /* Secondary processors spin on this value until it goes to 1. */ | |
119 | .globl __secondary_hold_spinloop | |
120 | __secondary_hold_spinloop: | |
121 | .llong 0x0 | |
122 | ||
123 | /* Secondary processors write this value with their cpu # */ | |
124 | /* after they enter the spin loop immediately below. */ | |
125 | .globl __secondary_hold_acknowledge | |
126 | __secondary_hold_acknowledge: | |
127 | .llong 0x0 | |
128 | ||
129 | . = 0x60 | |
130 | /* | |
131 | * The following code is used on pSeries to hold secondary processors | |
132 | * in a spin loop after they have been freed from OpenFirmware, but | |
133 | * before the bulk of the kernel has been relocated. This code | |
134 | * is relocated to physical address 0x60 before prom_init is run. | |
135 | * All of it must fit below the first exception vector at 0x100. | |
136 | */ | |
137 | _GLOBAL(__secondary_hold) | |
138 | mfmsr r24 | |
139 | ori r24,r24,MSR_RI | |
140 | mtmsrd r24 /* RI on */ | |
141 | ||
142 | /* Grab our linux cpu number */ | |
143 | mr r24,r3 | |
144 | ||
145 | /* Tell the master cpu we're here */ | |
146 | /* Relocation is off & we are located at an address less */ | |
147 | /* than 0x100, so only need to grab low order offset. */ | |
148 | std r24,__secondary_hold_acknowledge@l(0) | |
149 | sync | |
150 | ||
151 | /* All secondary cpus wait here until told to start. */ | |
152 | 100: ld r4,__secondary_hold_spinloop@l(0) | |
153 | cmpdi 0,r4,1 | |
154 | bne 100b | |
155 | ||
156 | #ifdef CONFIG_HMT | |
e58c3495 | 157 | SET_REG_IMMEDIATE(r4, .hmt_init) |
758438a7 ME |
158 | mtctr r4 |
159 | bctr | |
8fca9270 | 160 | #elif defined(CONFIG_SMP) || defined(CONFIG_KEXEC) |
e58c3495 | 161 | LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init) |
758438a7 | 162 | mtctr r4 |
14cf11af | 163 | mr r3,r24 |
758438a7 | 164 | bctr |
14cf11af PM |
165 | #else |
166 | BUG_OPCODE | |
167 | #endif | |
14cf11af PM |
168 | |
169 | /* This value is used to mark exception frames on the stack. */ | |
170 | .section ".toc","aw" | |
171 | exception_marker: | |
172 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
173 | .text | |
174 | ||
175 | /* | |
176 | * The following macros define the code that appears as | |
177 | * the prologue to each of the exception handlers. They | |
178 | * are split into two parts to allow a single kernel binary | |
179 | * to be used for pSeries and iSeries. | |
180 | * LOL. One day... - paulus | |
181 | */ | |
182 | ||
183 | /* | |
184 | * We make as much of the exception code common between native | |
185 | * exception handlers (including pSeries LPAR) and iSeries LPAR | |
186 | * implementations as possible. | |
187 | */ | |
188 | ||
189 | /* | |
190 | * This is the start of the interrupt handlers for pSeries | |
191 | * This code runs with relocation off. | |
192 | */ | |
193 | #define EX_R9 0 | |
194 | #define EX_R10 8 | |
195 | #define EX_R11 16 | |
196 | #define EX_R12 24 | |
197 | #define EX_R13 32 | |
198 | #define EX_SRR0 40 | |
14cf11af | 199 | #define EX_DAR 48 |
14cf11af PM |
200 | #define EX_DSISR 56 |
201 | #define EX_CCR 60 | |
3c726f8d BH |
202 | #define EX_R3 64 |
203 | #define EX_LR 72 | |
14cf11af | 204 | |
758438a7 | 205 | /* |
e58c3495 DG |
206 | * We're short on space and time in the exception prolog, so we can't |
207 | * use the normal SET_REG_IMMEDIATE macro. Normally we just need the | |
208 | * low halfword of the address, but for Kdump we need the whole low | |
209 | * word. | |
758438a7 ME |
210 | */ |
211 | #ifdef CONFIG_CRASH_DUMP | |
212 | #define LOAD_HANDLER(reg, label) \ | |
213 | oris reg,reg,(label)@h; /* virt addr of handler ... */ \ | |
214 | ori reg,reg,(label)@l; /* .. and the rest */ | |
215 | #else | |
216 | #define LOAD_HANDLER(reg, label) \ | |
217 | ori reg,reg,(label)@l; /* virt addr of handler ... */ | |
218 | #endif | |
219 | ||
14cf11af | 220 | #define EXCEPTION_PROLOG_PSERIES(area, label) \ |
b5bbeb23 | 221 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
14cf11af PM |
222 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
223 | std r10,area+EX_R10(r13); \ | |
224 | std r11,area+EX_R11(r13); \ | |
225 | std r12,area+EX_R12(r13); \ | |
b5bbeb23 | 226 | mfspr r9,SPRN_SPRG1; \ |
14cf11af PM |
227 | std r9,area+EX_R13(r13); \ |
228 | mfcr r9; \ | |
229 | clrrdi r12,r13,32; /* get high part of &label */ \ | |
230 | mfmsr r10; \ | |
b5bbeb23 | 231 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ |
758438a7 | 232 | LOAD_HANDLER(r12,label) \ |
14cf11af | 233 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ |
b5bbeb23 PM |
234 | mtspr SPRN_SRR0,r12; \ |
235 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ | |
236 | mtspr SPRN_SRR1,r10; \ | |
14cf11af PM |
237 | rfid; \ |
238 | b . /* prevent speculative execution */ | |
239 | ||
240 | /* | |
241 | * This is the start of the interrupt handlers for iSeries | |
242 | * This code runs with relocation on. | |
243 | */ | |
244 | #define EXCEPTION_PROLOG_ISERIES_1(area) \ | |
b5bbeb23 | 245 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
14cf11af PM |
246 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
247 | std r10,area+EX_R10(r13); \ | |
248 | std r11,area+EX_R11(r13); \ | |
249 | std r12,area+EX_R12(r13); \ | |
b5bbeb23 | 250 | mfspr r9,SPRN_SPRG1; \ |
14cf11af PM |
251 | std r9,area+EX_R13(r13); \ |
252 | mfcr r9 | |
253 | ||
254 | #define EXCEPTION_PROLOG_ISERIES_2 \ | |
255 | mfmsr r10; \ | |
3356bb9f DG |
256 | ld r12,PACALPPACAPTR(r13); \ |
257 | ld r11,LPPACASRR0(r12); \ | |
258 | ld r12,LPPACASRR1(r12); \ | |
14cf11af PM |
259 | ori r10,r10,MSR_RI; \ |
260 | mtmsrd r10,1 | |
261 | ||
262 | /* | |
263 | * The common exception prolog is used for all except a few exceptions | |
264 | * such as a segment miss on a kernel address. We have to be prepared | |
265 | * to take another exception from the point where we first touch the | |
266 | * kernel stack onwards. | |
267 | * | |
268 | * On entry r13 points to the paca, r9-r13 are saved in the paca, | |
269 | * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and | |
270 | * SRR1, and relocation is on. | |
271 | */ | |
272 | #define EXCEPTION_PROLOG_COMMON(n, area) \ | |
273 | andi. r10,r12,MSR_PR; /* See if coming from user */ \ | |
274 | mr r10,r1; /* Save r1 */ \ | |
275 | subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ | |
276 | beq- 1f; \ | |
277 | ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ | |
278 | 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \ | |
279 | bge- cr1,bad_stack; /* abort if it is */ \ | |
280 | std r9,_CCR(r1); /* save CR in stackframe */ \ | |
281 | std r11,_NIP(r1); /* save SRR0 in stackframe */ \ | |
282 | std r12,_MSR(r1); /* save SRR1 in stackframe */ \ | |
283 | std r10,0(r1); /* make stack chain pointer */ \ | |
284 | std r0,GPR0(r1); /* save r0 in stackframe */ \ | |
285 | std r10,GPR1(r1); /* save r1 in stackframe */ \ | |
286 | std r2,GPR2(r1); /* save r2 in stackframe */ \ | |
287 | SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ | |
288 | SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ | |
289 | ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ | |
290 | ld r10,area+EX_R10(r13); \ | |
291 | std r9,GPR9(r1); \ | |
292 | std r10,GPR10(r1); \ | |
293 | ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ | |
294 | ld r10,area+EX_R12(r13); \ | |
295 | ld r11,area+EX_R13(r13); \ | |
296 | std r9,GPR11(r1); \ | |
297 | std r10,GPR12(r1); \ | |
298 | std r11,GPR13(r1); \ | |
299 | ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ | |
300 | mflr r9; /* save LR in stackframe */ \ | |
301 | std r9,_LINK(r1); \ | |
302 | mfctr r10; /* save CTR in stackframe */ \ | |
303 | std r10,_CTR(r1); \ | |
b5bbeb23 | 304 | mfspr r11,SPRN_XER; /* save XER in stackframe */ \ |
14cf11af PM |
305 | std r11,_XER(r1); \ |
306 | li r9,(n)+1; \ | |
307 | std r9,_TRAP(r1); /* set trap number */ \ | |
308 | li r10,0; \ | |
309 | ld r11,exception_marker@toc(r2); \ | |
310 | std r10,RESULT(r1); /* clear regs->result */ \ | |
311 | std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ | |
312 | ||
313 | /* | |
314 | * Exception vectors. | |
315 | */ | |
316 | #define STD_EXCEPTION_PSERIES(n, label) \ | |
317 | . = n; \ | |
318 | .globl label##_pSeries; \ | |
319 | label##_pSeries: \ | |
320 | HMT_MEDIUM; \ | |
b5bbeb23 | 321 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
322 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) |
323 | ||
324 | #define STD_EXCEPTION_ISERIES(n, label, area) \ | |
325 | .globl label##_iSeries; \ | |
326 | label##_iSeries: \ | |
327 | HMT_MEDIUM; \ | |
b5bbeb23 | 328 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
329 | EXCEPTION_PROLOG_ISERIES_1(area); \ |
330 | EXCEPTION_PROLOG_ISERIES_2; \ | |
331 | b label##_common | |
332 | ||
333 | #define MASKABLE_EXCEPTION_ISERIES(n, label) \ | |
334 | .globl label##_iSeries; \ | |
335 | label##_iSeries: \ | |
336 | HMT_MEDIUM; \ | |
b5bbeb23 | 337 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
14cf11af PM |
338 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ |
339 | lbz r10,PACAPROCENABLED(r13); \ | |
340 | cmpwi 0,r10,0; \ | |
341 | beq- label##_iSeries_masked; \ | |
342 | EXCEPTION_PROLOG_ISERIES_2; \ | |
343 | b label##_common; \ | |
344 | ||
345 | #ifdef DO_SOFT_DISABLE | |
346 | #define DISABLE_INTS \ | |
347 | lbz r10,PACAPROCENABLED(r13); \ | |
348 | li r11,0; \ | |
349 | std r10,SOFTE(r1); \ | |
350 | mfmsr r10; \ | |
351 | stb r11,PACAPROCENABLED(r13); \ | |
352 | ori r10,r10,MSR_EE; \ | |
353 | mtmsrd r10,1 | |
354 | ||
355 | #define ENABLE_INTS \ | |
356 | lbz r10,PACAPROCENABLED(r13); \ | |
357 | mfmsr r11; \ | |
358 | std r10,SOFTE(r1); \ | |
359 | ori r11,r11,MSR_EE; \ | |
360 | mtmsrd r11,1 | |
361 | ||
362 | #else /* hard enable/disable interrupts */ | |
363 | #define DISABLE_INTS | |
364 | ||
365 | #define ENABLE_INTS \ | |
366 | ld r12,_MSR(r1); \ | |
367 | mfmsr r11; \ | |
368 | rlwimi r11,r12,0,MSR_EE; \ | |
369 | mtmsrd r11,1 | |
370 | ||
371 | #endif | |
372 | ||
373 | #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ | |
374 | .align 7; \ | |
375 | .globl label##_common; \ | |
376 | label##_common: \ | |
377 | EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ | |
378 | DISABLE_INTS; \ | |
379 | bl .save_nvgprs; \ | |
380 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
381 | bl hdlr; \ | |
382 | b .ret_from_except | |
383 | ||
384 | #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \ | |
385 | .align 7; \ | |
386 | .globl label##_common; \ | |
387 | label##_common: \ | |
388 | EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ | |
389 | DISABLE_INTS; \ | |
cb2c9b27 | 390 | bl .ppc64_runlatch_on; \ |
14cf11af PM |
391 | addi r3,r1,STACK_FRAME_OVERHEAD; \ |
392 | bl hdlr; \ | |
393 | b .ret_from_except_lite | |
394 | ||
395 | /* | |
396 | * Start of pSeries system interrupt routines | |
397 | */ | |
398 | . = 0x100 | |
399 | .globl __start_interrupts | |
400 | __start_interrupts: | |
401 | ||
402 | STD_EXCEPTION_PSERIES(0x100, system_reset) | |
403 | ||
404 | . = 0x200 | |
405 | _machine_check_pSeries: | |
406 | HMT_MEDIUM | |
b5bbeb23 | 407 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
14cf11af PM |
408 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) |
409 | ||
410 | . = 0x300 | |
411 | .globl data_access_pSeries | |
412 | data_access_pSeries: | |
413 | HMT_MEDIUM | |
b5bbeb23 | 414 | mtspr SPRN_SPRG1,r13 |
14cf11af | 415 | BEGIN_FTR_SECTION |
b5bbeb23 PM |
416 | mtspr SPRN_SPRG2,r12 |
417 | mfspr r13,SPRN_DAR | |
418 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
419 | srdi r13,r13,60 |
420 | rlwimi r13,r12,16,0x20 | |
421 | mfcr r12 | |
422 | cmpwi r13,0x2c | |
423 | beq .do_stab_bolted_pSeries | |
424 | mtcrf 0x80,r12 | |
b5bbeb23 | 425 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
426 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
427 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) | |
428 | ||
429 | . = 0x380 | |
430 | .globl data_access_slb_pSeries | |
431 | data_access_slb_pSeries: | |
432 | HMT_MEDIUM | |
b5bbeb23 | 433 | mtspr SPRN_SPRG1,r13 |
b5bbeb23 | 434 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
435 | std r3,PACA_EXSLB+EX_R3(r13) |
436 | mfspr r3,SPRN_DAR | |
14cf11af | 437 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
438 | mfcr r9 |
439 | #ifdef __DISABLED__ | |
440 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
441 | cmpdi r3,0 | |
442 | bge slb_miss_user_pseries | |
443 | #endif /* __DISABLED__ */ | |
14cf11af PM |
444 | std r10,PACA_EXSLB+EX_R10(r13) |
445 | std r11,PACA_EXSLB+EX_R11(r13) | |
446 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
447 | mfspr r10,SPRN_SPRG1 |
448 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 449 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 450 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af PM |
451 | |
452 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | |
453 | ||
454 | . = 0x480 | |
455 | .globl instruction_access_slb_pSeries | |
456 | instruction_access_slb_pSeries: | |
457 | HMT_MEDIUM | |
b5bbeb23 | 458 | mtspr SPRN_SPRG1,r13 |
b5bbeb23 | 459 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
3c726f8d BH |
460 | std r3,PACA_EXSLB+EX_R3(r13) |
461 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
14cf11af | 462 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
3c726f8d BH |
463 | mfcr r9 |
464 | #ifdef __DISABLED__ | |
465 | /* Keep that around for when we re-implement dynamic VSIDs */ | |
466 | cmpdi r3,0 | |
467 | bge slb_miss_user_pseries | |
468 | #endif /* __DISABLED__ */ | |
14cf11af PM |
469 | std r10,PACA_EXSLB+EX_R10(r13) |
470 | std r11,PACA_EXSLB+EX_R11(r13) | |
471 | std r12,PACA_EXSLB+EX_R12(r13) | |
3c726f8d BH |
472 | mfspr r10,SPRN_SPRG1 |
473 | std r10,PACA_EXSLB+EX_R13(r13) | |
b5bbeb23 | 474 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
3c726f8d | 475 | b .slb_miss_realmode /* Rel. branch works in real mode */ |
14cf11af PM |
476 | |
477 | STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) | |
478 | STD_EXCEPTION_PSERIES(0x600, alignment) | |
479 | STD_EXCEPTION_PSERIES(0x700, program_check) | |
480 | STD_EXCEPTION_PSERIES(0x800, fp_unavailable) | |
481 | STD_EXCEPTION_PSERIES(0x900, decrementer) | |
482 | STD_EXCEPTION_PSERIES(0xa00, trap_0a) | |
483 | STD_EXCEPTION_PSERIES(0xb00, trap_0b) | |
484 | ||
485 | . = 0xc00 | |
486 | .globl system_call_pSeries | |
487 | system_call_pSeries: | |
488 | HMT_MEDIUM | |
14cf11af PM |
489 | mr r9,r13 |
490 | mfmsr r10 | |
b5bbeb23 PM |
491 | mfspr r13,SPRN_SPRG3 |
492 | mfspr r11,SPRN_SRR0 | |
14cf11af PM |
493 | clrrdi r12,r13,32 |
494 | oris r12,r12,system_call_common@h | |
495 | ori r12,r12,system_call_common@l | |
b5bbeb23 | 496 | mtspr SPRN_SRR0,r12 |
14cf11af | 497 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI |
b5bbeb23 PM |
498 | mfspr r12,SPRN_SRR1 |
499 | mtspr SPRN_SRR1,r10 | |
14cf11af PM |
500 | rfid |
501 | b . /* prevent speculative execution */ | |
502 | ||
503 | STD_EXCEPTION_PSERIES(0xd00, single_step) | |
504 | STD_EXCEPTION_PSERIES(0xe00, trap_0e) | |
505 | ||
506 | /* We need to deal with the Altivec unavailable exception | |
507 | * here which is at 0xf20, thus in the middle of the | |
508 | * prolog code of the PerformanceMonitor one. A little | |
509 | * trickery is thus necessary | |
510 | */ | |
511 | . = 0xf00 | |
512 | b performance_monitor_pSeries | |
513 | ||
514 | STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable) | |
515 | ||
516 | STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) | |
517 | STD_EXCEPTION_PSERIES(0x1700, altivec_assist) | |
518 | ||
519 | . = 0x3000 | |
520 | ||
521 | /*** pSeries interrupt support ***/ | |
522 | ||
523 | /* moved from 0xf00 */ | |
524 | STD_EXCEPTION_PSERIES(., performance_monitor) | |
525 | ||
526 | .align 7 | |
527 | _GLOBAL(do_stab_bolted_pSeries) | |
528 | mtcrf 0x80,r12 | |
b5bbeb23 | 529 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
530 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) |
531 | ||
3c726f8d BH |
532 | /* |
533 | * We have some room here we use that to put | |
534 | * the peries slb miss user trampoline code so it's reasonably | |
535 | * away from slb_miss_user_common to avoid problems with rfid | |
536 | * | |
537 | * This is used for when the SLB miss handler has to go virtual, | |
538 | * which doesn't happen for now anymore but will once we re-implement | |
539 | * dynamic VSIDs for shared page tables | |
540 | */ | |
541 | #ifdef __DISABLED__ | |
542 | slb_miss_user_pseries: | |
543 | std r10,PACA_EXGEN+EX_R10(r13) | |
544 | std r11,PACA_EXGEN+EX_R11(r13) | |
545 | std r12,PACA_EXGEN+EX_R12(r13) | |
546 | mfspr r10,SPRG1 | |
547 | ld r11,PACA_EXSLB+EX_R9(r13) | |
548 | ld r12,PACA_EXSLB+EX_R3(r13) | |
549 | std r10,PACA_EXGEN+EX_R13(r13) | |
550 | std r11,PACA_EXGEN+EX_R9(r13) | |
551 | std r12,PACA_EXGEN+EX_R3(r13) | |
552 | clrrdi r12,r13,32 | |
553 | mfmsr r10 | |
554 | mfspr r11,SRR0 /* save SRR0 */ | |
555 | ori r12,r12,slb_miss_user_common@l /* virt addr of handler */ | |
556 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | |
557 | mtspr SRR0,r12 | |
558 | mfspr r12,SRR1 /* and SRR1 */ | |
559 | mtspr SRR1,r10 | |
560 | rfid | |
561 | b . /* prevent spec. execution */ | |
562 | #endif /* __DISABLED__ */ | |
563 | ||
14cf11af PM |
564 | /* |
565 | * Vectors for the FWNMI option. Share common code. | |
566 | */ | |
b5bbeb23 | 567 | .globl system_reset_fwnmi |
8c4f1f29 | 568 | .align 7 |
14cf11af | 569 | system_reset_fwnmi: |
b5bbeb23 PM |
570 | HMT_MEDIUM |
571 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
b5bbeb23 | 572 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) |
14cf11af | 573 | |
b5bbeb23 | 574 | .globl machine_check_fwnmi |
8c4f1f29 | 575 | .align 7 |
14cf11af | 576 | machine_check_fwnmi: |
b5bbeb23 PM |
577 | HMT_MEDIUM |
578 | mtspr SPRN_SPRG1,r13 /* save r13 */ | |
b5bbeb23 | 579 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) |
14cf11af PM |
580 | |
581 | #ifdef CONFIG_PPC_ISERIES | |
582 | /*** ISeries-LPAR interrupt handlers ***/ | |
583 | ||
584 | STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC) | |
585 | ||
586 | .globl data_access_iSeries | |
587 | data_access_iSeries: | |
b5bbeb23 | 588 | mtspr SPRN_SPRG1,r13 |
14cf11af | 589 | BEGIN_FTR_SECTION |
b5bbeb23 PM |
590 | mtspr SPRN_SPRG2,r12 |
591 | mfspr r13,SPRN_DAR | |
592 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
593 | srdi r13,r13,60 |
594 | rlwimi r13,r12,16,0x20 | |
595 | mfcr r12 | |
596 | cmpwi r13,0x2c | |
597 | beq .do_stab_bolted_iSeries | |
598 | mtcrf 0x80,r12 | |
b5bbeb23 | 599 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
600 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
601 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) | |
602 | EXCEPTION_PROLOG_ISERIES_2 | |
603 | b data_access_common | |
604 | ||
605 | .do_stab_bolted_iSeries: | |
606 | mtcrf 0x80,r12 | |
b5bbeb23 | 607 | mfspr r12,SPRN_SPRG2 |
14cf11af PM |
608 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) |
609 | EXCEPTION_PROLOG_ISERIES_2 | |
610 | b .do_stab_bolted | |
611 | ||
612 | .globl data_access_slb_iSeries | |
613 | data_access_slb_iSeries: | |
b5bbeb23 | 614 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
3c726f8d | 615 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
14cf11af | 616 | std r3,PACA_EXSLB+EX_R3(r13) |
b5bbeb23 | 617 | mfspr r3,SPRN_DAR |
3c726f8d BH |
618 | std r9,PACA_EXSLB+EX_R9(r13) |
619 | mfcr r9 | |
620 | #ifdef __DISABLED__ | |
621 | cmpdi r3,0 | |
622 | bge slb_miss_user_iseries | |
623 | #endif | |
624 | std r10,PACA_EXSLB+EX_R10(r13) | |
625 | std r11,PACA_EXSLB+EX_R11(r13) | |
626 | std r12,PACA_EXSLB+EX_R12(r13) | |
627 | mfspr r10,SPRN_SPRG1 | |
628 | std r10,PACA_EXSLB+EX_R13(r13) | |
3356bb9f DG |
629 | ld r12,PACALPPACAPTR(r13) |
630 | ld r12,LPPACASRR1(r12) | |
3c726f8d | 631 | b .slb_miss_realmode |
14cf11af PM |
632 | |
633 | STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) | |
634 | ||
635 | .globl instruction_access_slb_iSeries | |
636 | instruction_access_slb_iSeries: | |
b5bbeb23 | 637 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
3c726f8d | 638 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
14cf11af | 639 | std r3,PACA_EXSLB+EX_R3(r13) |
3356bb9f DG |
640 | ld r3,PACALPPACAPTR(r13) |
641 | ld r3,LPPACASRR0(r3) /* get SRR0 value */ | |
3c726f8d BH |
642 | std r9,PACA_EXSLB+EX_R9(r13) |
643 | mfcr r9 | |
644 | #ifdef __DISABLED__ | |
645 | cmpdi r3,0 | |
646 | bge .slb_miss_user_iseries | |
647 | #endif | |
648 | std r10,PACA_EXSLB+EX_R10(r13) | |
649 | std r11,PACA_EXSLB+EX_R11(r13) | |
650 | std r12,PACA_EXSLB+EX_R12(r13) | |
651 | mfspr r10,SPRN_SPRG1 | |
652 | std r10,PACA_EXSLB+EX_R13(r13) | |
3356bb9f DG |
653 | ld r12,PACALPPACAPTR(r13) |
654 | ld r12,LPPACASRR1(r12) | |
3c726f8d BH |
655 | b .slb_miss_realmode |
656 | ||
657 | #ifdef __DISABLED__ | |
658 | slb_miss_user_iseries: | |
659 | std r10,PACA_EXGEN+EX_R10(r13) | |
660 | std r11,PACA_EXGEN+EX_R11(r13) | |
661 | std r12,PACA_EXGEN+EX_R12(r13) | |
662 | mfspr r10,SPRG1 | |
663 | ld r11,PACA_EXSLB+EX_R9(r13) | |
664 | ld r12,PACA_EXSLB+EX_R3(r13) | |
665 | std r10,PACA_EXGEN+EX_R13(r13) | |
666 | std r11,PACA_EXGEN+EX_R9(r13) | |
667 | std r12,PACA_EXGEN+EX_R3(r13) | |
668 | EXCEPTION_PROLOG_ISERIES_2 | |
669 | b slb_miss_user_common | |
670 | #endif | |
14cf11af PM |
671 | |
672 | MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt) | |
673 | STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN) | |
674 | STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN) | |
675 | STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN) | |
676 | MASKABLE_EXCEPTION_ISERIES(0x900, decrementer) | |
677 | STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN) | |
678 | STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN) | |
679 | ||
680 | .globl system_call_iSeries | |
681 | system_call_iSeries: | |
682 | mr r9,r13 | |
b5bbeb23 | 683 | mfspr r13,SPRN_SPRG3 |
14cf11af PM |
684 | EXCEPTION_PROLOG_ISERIES_2 |
685 | b system_call_common | |
686 | ||
687 | STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN) | |
688 | STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN) | |
689 | STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN) | |
690 | ||
691 | .globl system_reset_iSeries | |
692 | system_reset_iSeries: | |
b5bbeb23 | 693 | mfspr r13,SPRN_SPRG3 /* Get paca address */ |
14cf11af PM |
694 | mfmsr r24 |
695 | ori r24,r24,MSR_RI | |
696 | mtmsrd r24 /* RI on */ | |
697 | lhz r24,PACAPACAINDEX(r13) /* Get processor # */ | |
698 | cmpwi 0,r24,0 /* Are we processor 0? */ | |
699 | beq .__start_initialization_iSeries /* Start up the first processor */ | |
700 | mfspr r4,SPRN_CTRLF | |
701 | li r5,CTRL_RUNLATCH /* Turn off the run light */ | |
702 | andc r4,r4,r5 | |
703 | mtspr SPRN_CTRLT,r4 | |
704 | ||
705 | 1: | |
706 | HMT_LOW | |
707 | #ifdef CONFIG_SMP | |
708 | lbz r23,PACAPROCSTART(r13) /* Test if this processor | |
709 | * should start */ | |
710 | sync | |
e58c3495 | 711 | LOAD_REG_IMMEDIATE(r3,current_set) |
14cf11af PM |
712 | sldi r28,r24,3 /* get current_set[cpu#] */ |
713 | ldx r3,r3,r28 | |
714 | addi r1,r3,THREAD_SIZE | |
715 | subi r1,r1,STACK_FRAME_OVERHEAD | |
716 | ||
717 | cmpwi 0,r23,0 | |
718 | beq iSeries_secondary_smp_loop /* Loop until told to go */ | |
719 | bne .__secondary_start /* Loop until told to go */ | |
720 | iSeries_secondary_smp_loop: | |
721 | /* Let the Hypervisor know we are alive */ | |
722 | /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */ | |
723 | lis r3,0x8002 | |
724 | rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */ | |
725 | #else /* CONFIG_SMP */ | |
726 | /* Yield the processor. This is required for non-SMP kernels | |
727 | which are running on multi-threaded machines. */ | |
728 | lis r3,0x8000 | |
729 | rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */ | |
730 | addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */ | |
731 | li r4,0 /* "yield timed" */ | |
732 | li r5,-1 /* "yield forever" */ | |
733 | #endif /* CONFIG_SMP */ | |
734 | li r0,-1 /* r0=-1 indicates a Hypervisor call */ | |
735 | sc /* Invoke the hypervisor via a system call */ | |
b5bbeb23 | 736 | mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ |
14cf11af PM |
737 | b 1b /* If SMP not configured, secondaries |
738 | * loop forever */ | |
739 | ||
740 | .globl decrementer_iSeries_masked | |
741 | decrementer_iSeries_masked: | |
f9b4045d | 742 | /* We may not have a valid TOC pointer in here. */ |
14cf11af | 743 | li r11,1 |
3356bb9f DG |
744 | ld r12,PACALPPACAPTR(r13) |
745 | stb r11,LPPACADECRINT(r12) | |
f9b4045d ME |
746 | LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy) |
747 | lwz r12,0(r12) | |
14cf11af PM |
748 | mtspr SPRN_DEC,r12 |
749 | /* fall through */ | |
750 | ||
751 | .globl hardware_interrupt_iSeries_masked | |
752 | hardware_interrupt_iSeries_masked: | |
753 | mtcrf 0x80,r9 /* Restore regs */ | |
3356bb9f DG |
754 | ld r12,PACALPPACAPTR(r13) |
755 | ld r11,LPPACASRR0(r12) | |
756 | ld r12,LPPACASRR1(r12) | |
b5bbeb23 PM |
757 | mtspr SPRN_SRR0,r11 |
758 | mtspr SPRN_SRR1,r12 | |
14cf11af PM |
759 | ld r9,PACA_EXGEN+EX_R9(r13) |
760 | ld r10,PACA_EXGEN+EX_R10(r13) | |
761 | ld r11,PACA_EXGEN+EX_R11(r13) | |
762 | ld r12,PACA_EXGEN+EX_R12(r13) | |
763 | ld r13,PACA_EXGEN+EX_R13(r13) | |
764 | rfid | |
765 | b . /* prevent speculative execution */ | |
766 | #endif /* CONFIG_PPC_ISERIES */ | |
767 | ||
768 | /*** Common interrupt handlers ***/ | |
769 | ||
770 | STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception) | |
771 | ||
772 | /* | |
773 | * Machine check is different because we use a different | |
774 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
775 | */ | |
776 | .align 7 | |
777 | .globl machine_check_common | |
778 | machine_check_common: | |
779 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) | |
780 | DISABLE_INTS | |
781 | bl .save_nvgprs | |
782 | addi r3,r1,STACK_FRAME_OVERHEAD | |
783 | bl .machine_check_exception | |
784 | b .ret_from_except | |
785 | ||
786 | STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt) | |
787 | STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception) | |
788 | STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) | |
789 | STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) | |
790 | STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) | |
791 | STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception) | |
792 | STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception) | |
793 | #ifdef CONFIG_ALTIVEC | |
794 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception) | |
795 | #else | |
796 | STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception) | |
797 | #endif | |
798 | ||
799 | /* | |
800 | * Here we have detected that the kernel stack pointer is bad. | |
801 | * R9 contains the saved CR, r13 points to the paca, | |
802 | * r10 contains the (bad) kernel stack pointer, | |
803 | * r11 and r12 contain the saved SRR0 and SRR1. | |
804 | * We switch to using an emergency stack, save the registers there, | |
805 | * and call kernel_bad_stack(), which panics. | |
806 | */ | |
807 | bad_stack: | |
808 | ld r1,PACAEMERGSP(r13) | |
809 | subi r1,r1,64+INT_FRAME_SIZE | |
810 | std r9,_CCR(r1) | |
811 | std r10,GPR1(r1) | |
812 | std r11,_NIP(r1) | |
813 | std r12,_MSR(r1) | |
b5bbeb23 PM |
814 | mfspr r11,SPRN_DAR |
815 | mfspr r12,SPRN_DSISR | |
14cf11af PM |
816 | std r11,_DAR(r1) |
817 | std r12,_DSISR(r1) | |
818 | mflr r10 | |
819 | mfctr r11 | |
820 | mfxer r12 | |
821 | std r10,_LINK(r1) | |
822 | std r11,_CTR(r1) | |
823 | std r12,_XER(r1) | |
824 | SAVE_GPR(0,r1) | |
825 | SAVE_GPR(2,r1) | |
826 | SAVE_4GPRS(3,r1) | |
827 | SAVE_2GPRS(7,r1) | |
828 | SAVE_10GPRS(12,r1) | |
829 | SAVE_10GPRS(22,r1) | |
830 | addi r11,r1,INT_FRAME_SIZE | |
831 | std r11,0(r1) | |
832 | li r12,0 | |
833 | std r12,0(r11) | |
834 | ld r2,PACATOC(r13) | |
835 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
836 | bl .kernel_bad_stack | |
837 | b 1b | |
838 | ||
839 | /* | |
840 | * Return from an exception with minimal checks. | |
841 | * The caller is assumed to have done EXCEPTION_PROLOG_COMMON. | |
842 | * If interrupts have been enabled, or anything has been | |
843 | * done that might have changed the scheduling status of | |
844 | * any task or sent any task a signal, you should use | |
845 | * ret_from_except or ret_from_except_lite instead of this. | |
846 | */ | |
40ef8cbc | 847 | .globl fast_exception_return |
14cf11af PM |
848 | fast_exception_return: |
849 | ld r12,_MSR(r1) | |
850 | ld r11,_NIP(r1) | |
851 | andi. r3,r12,MSR_RI /* check if RI is set */ | |
852 | beq- unrecov_fer | |
853 | ld r3,_CCR(r1) | |
854 | ld r4,_LINK(r1) | |
855 | ld r5,_CTR(r1) | |
856 | ld r6,_XER(r1) | |
857 | mtcr r3 | |
858 | mtlr r4 | |
859 | mtctr r5 | |
860 | mtxer r6 | |
861 | REST_GPR(0, r1) | |
862 | REST_8GPRS(2, r1) | |
863 | ||
864 | mfmsr r10 | |
865 | clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ | |
866 | mtmsrd r10,1 | |
867 | ||
b5bbeb23 PM |
868 | mtspr SPRN_SRR1,r12 |
869 | mtspr SPRN_SRR0,r11 | |
14cf11af PM |
870 | REST_4GPRS(10, r1) |
871 | ld r1,GPR1(r1) | |
872 | rfid | |
873 | b . /* prevent speculative execution */ | |
874 | ||
875 | unrecov_fer: | |
876 | bl .save_nvgprs | |
877 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
878 | bl .unrecoverable_exception | |
879 | b 1b | |
880 | ||
881 | /* | |
882 | * Here r13 points to the paca, r9 contains the saved CR, | |
883 | * SRR0 and SRR1 are saved in r11 and r12, | |
884 | * r9 - r13 are saved in paca->exgen. | |
885 | */ | |
886 | .align 7 | |
887 | .globl data_access_common | |
888 | data_access_common: | |
b5bbeb23 | 889 | mfspr r10,SPRN_DAR |
14cf11af | 890 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 891 | mfspr r10,SPRN_DSISR |
14cf11af PM |
892 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
893 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
894 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
895 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
896 | li r5,0x300 | |
897 | b .do_hash_page /* Try to handle as hpte fault */ | |
898 | ||
899 | .align 7 | |
900 | .globl instruction_access_common | |
901 | instruction_access_common: | |
902 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) | |
903 | ld r3,_NIP(r1) | |
904 | andis. r4,r12,0x5820 | |
905 | li r5,0x400 | |
906 | b .do_hash_page /* Try to handle as hpte fault */ | |
907 | ||
3c726f8d BH |
908 | /* |
909 | * Here is the common SLB miss user that is used when going to virtual | |
910 | * mode for SLB misses, that is currently not used | |
911 | */ | |
912 | #ifdef __DISABLED__ | |
913 | .align 7 | |
914 | .globl slb_miss_user_common | |
915 | slb_miss_user_common: | |
916 | mflr r10 | |
917 | std r3,PACA_EXGEN+EX_DAR(r13) | |
918 | stw r9,PACA_EXGEN+EX_CCR(r13) | |
919 | std r10,PACA_EXGEN+EX_LR(r13) | |
920 | std r11,PACA_EXGEN+EX_SRR0(r13) | |
921 | bl .slb_allocate_user | |
922 | ||
923 | ld r10,PACA_EXGEN+EX_LR(r13) | |
924 | ld r3,PACA_EXGEN+EX_R3(r13) | |
925 | lwz r9,PACA_EXGEN+EX_CCR(r13) | |
926 | ld r11,PACA_EXGEN+EX_SRR0(r13) | |
927 | mtlr r10 | |
928 | beq- slb_miss_fault | |
929 | ||
930 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
931 | beq- unrecov_user_slb | |
932 | mfmsr r10 | |
933 | ||
934 | .machine push | |
935 | .machine "power4" | |
936 | mtcrf 0x80,r9 | |
937 | .machine pop | |
938 | ||
939 | clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */ | |
940 | mtmsrd r10,1 | |
941 | ||
942 | mtspr SRR0,r11 | |
943 | mtspr SRR1,r12 | |
944 | ||
945 | ld r9,PACA_EXGEN+EX_R9(r13) | |
946 | ld r10,PACA_EXGEN+EX_R10(r13) | |
947 | ld r11,PACA_EXGEN+EX_R11(r13) | |
948 | ld r12,PACA_EXGEN+EX_R12(r13) | |
949 | ld r13,PACA_EXGEN+EX_R13(r13) | |
950 | rfid | |
951 | b . | |
952 | ||
953 | slb_miss_fault: | |
954 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN) | |
955 | ld r4,PACA_EXGEN+EX_DAR(r13) | |
956 | li r5,0 | |
957 | std r4,_DAR(r1) | |
958 | std r5,_DSISR(r1) | |
959 | b .handle_page_fault | |
960 | ||
961 | unrecov_user_slb: | |
962 | EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN) | |
963 | DISABLE_INTS | |
964 | bl .save_nvgprs | |
965 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
966 | bl .unrecoverable_exception | |
967 | b 1b | |
968 | ||
969 | #endif /* __DISABLED__ */ | |
970 | ||
971 | ||
972 | /* | |
973 | * r13 points to the PACA, r9 contains the saved CR, | |
974 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
975 | * r3 has the faulting address | |
976 | * r9 - r13 are saved in paca->exslb. | |
977 | * r3 is saved in paca->slb_r3 | |
978 | * We assume we aren't going to take any exceptions during this procedure. | |
979 | */ | |
980 | _GLOBAL(slb_miss_realmode) | |
981 | mflr r10 | |
982 | ||
983 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
984 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
985 | ||
986 | bl .slb_allocate_realmode | |
987 | ||
988 | /* All done -- return from exception. */ | |
989 | ||
990 | ld r10,PACA_EXSLB+EX_LR(r13) | |
991 | ld r3,PACA_EXSLB+EX_R3(r13) | |
992 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
993 | #ifdef CONFIG_PPC_ISERIES | |
3356bb9f DG |
994 | ld r11,PACALPPACAPTR(r13) |
995 | ld r11,LPPACASRR0(r11) /* get SRR0 value */ | |
3c726f8d BH |
996 | #endif /* CONFIG_PPC_ISERIES */ |
997 | ||
998 | mtlr r10 | |
999 | ||
1000 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ | |
1001 | beq- unrecov_slb | |
1002 | ||
1003 | .machine push | |
1004 | .machine "power4" | |
1005 | mtcrf 0x80,r9 | |
1006 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ | |
1007 | .machine pop | |
1008 | ||
1009 | #ifdef CONFIG_PPC_ISERIES | |
1010 | mtspr SPRN_SRR0,r11 | |
1011 | mtspr SPRN_SRR1,r12 | |
1012 | #endif /* CONFIG_PPC_ISERIES */ | |
1013 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1014 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1015 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1016 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1017 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1018 | rfid | |
1019 | b . /* prevent speculative execution */ | |
1020 | ||
1021 | unrecov_slb: | |
1022 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1023 | DISABLE_INTS | |
1024 | bl .save_nvgprs | |
1025 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1026 | bl .unrecoverable_exception | |
1027 | b 1b | |
1028 | ||
14cf11af PM |
1029 | .align 7 |
1030 | .globl hardware_interrupt_common | |
1031 | .globl hardware_interrupt_entry | |
1032 | hardware_interrupt_common: | |
1033 | EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN) | |
1034 | hardware_interrupt_entry: | |
1035 | DISABLE_INTS | |
cb2c9b27 | 1036 | bl .ppc64_runlatch_on |
14cf11af PM |
1037 | addi r3,r1,STACK_FRAME_OVERHEAD |
1038 | bl .do_IRQ | |
1039 | b .ret_from_except_lite | |
1040 | ||
1041 | .align 7 | |
1042 | .globl alignment_common | |
1043 | alignment_common: | |
b5bbeb23 | 1044 | mfspr r10,SPRN_DAR |
14cf11af | 1045 | std r10,PACA_EXGEN+EX_DAR(r13) |
b5bbeb23 | 1046 | mfspr r10,SPRN_DSISR |
14cf11af PM |
1047 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
1048 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
1049 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1050 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1051 | std r3,_DAR(r1) | |
1052 | std r4,_DSISR(r1) | |
1053 | bl .save_nvgprs | |
1054 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1055 | ENABLE_INTS | |
1056 | bl .alignment_exception | |
1057 | b .ret_from_except | |
1058 | ||
1059 | .align 7 | |
1060 | .globl program_check_common | |
1061 | program_check_common: | |
1062 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) | |
1063 | bl .save_nvgprs | |
1064 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1065 | ENABLE_INTS | |
1066 | bl .program_check_exception | |
1067 | b .ret_from_except | |
1068 | ||
1069 | .align 7 | |
1070 | .globl fp_unavailable_common | |
1071 | fp_unavailable_common: | |
1072 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) | |
1073 | bne .load_up_fpu /* if from user, just load it up */ | |
1074 | bl .save_nvgprs | |
1075 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1076 | ENABLE_INTS | |
1077 | bl .kernel_fp_unavailable_exception | |
1078 | BUG_OPCODE | |
1079 | ||
14cf11af PM |
1080 | .align 7 |
1081 | .globl altivec_unavailable_common | |
1082 | altivec_unavailable_common: | |
1083 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) | |
1084 | #ifdef CONFIG_ALTIVEC | |
1085 | BEGIN_FTR_SECTION | |
1086 | bne .load_up_altivec /* if from user, just load it up */ | |
1087 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1088 | #endif | |
1089 | bl .save_nvgprs | |
1090 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1091 | ENABLE_INTS | |
1092 | bl .altivec_unavailable_exception | |
1093 | b .ret_from_except | |
1094 | ||
1095 | #ifdef CONFIG_ALTIVEC | |
1096 | /* | |
1097 | * load_up_altivec(unused, unused, tsk) | |
1098 | * Disable VMX for the task which had it previously, | |
1099 | * and save its vector registers in its thread_struct. | |
1100 | * Enables the VMX for use in the kernel on return. | |
1101 | * On SMP we know the VMX is free, since we give it up every | |
1102 | * switch (ie, no lazy save of the vector registers). | |
1103 | * On entry: r13 == 'current' && last_task_used_altivec != 'current' | |
1104 | */ | |
1105 | _STATIC(load_up_altivec) | |
1106 | mfmsr r5 /* grab the current MSR */ | |
1107 | oris r5,r5,MSR_VEC@h | |
1108 | mtmsrd r5 /* enable use of VMX now */ | |
1109 | isync | |
1110 | ||
1111 | /* | |
1112 | * For SMP, we don't do lazy VMX switching because it just gets too | |
1113 | * horrendously complex, especially when a task switches from one CPU | |
1114 | * to another. Instead we call giveup_altvec in switch_to. | |
1115 | * VRSAVE isn't dealt with here, that is done in the normal context | |
1116 | * switch code. Note that we could rely on vrsave value to eventually | |
1117 | * avoid saving all of the VREGs here... | |
1118 | */ | |
1119 | #ifndef CONFIG_SMP | |
1120 | ld r3,last_task_used_altivec@got(r2) | |
1121 | ld r4,0(r3) | |
1122 | cmpdi 0,r4,0 | |
1123 | beq 1f | |
1124 | /* Save VMX state to last_task_used_altivec's THREAD struct */ | |
1125 | addi r4,r4,THREAD | |
1126 | SAVE_32VRS(0,r5,r4) | |
1127 | mfvscr vr0 | |
1128 | li r10,THREAD_VSCR | |
1129 | stvx vr0,r10,r4 | |
1130 | /* Disable VMX for last_task_used_altivec */ | |
1131 | ld r5,PT_REGS(r4) | |
1132 | ld r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1133 | lis r6,MSR_VEC@h | |
1134 | andc r4,r4,r6 | |
1135 | std r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1136 | 1: | |
1137 | #endif /* CONFIG_SMP */ | |
1138 | /* Hack: if we get an altivec unavailable trap with VRSAVE | |
1139 | * set to all zeros, we assume this is a broken application | |
1140 | * that fails to set it properly, and thus we switch it to | |
1141 | * all 1's | |
1142 | */ | |
1143 | mfspr r4,SPRN_VRSAVE | |
1144 | cmpdi 0,r4,0 | |
1145 | bne+ 1f | |
1146 | li r4,-1 | |
1147 | mtspr SPRN_VRSAVE,r4 | |
1148 | 1: | |
1149 | /* enable use of VMX after return */ | |
1150 | ld r4,PACACURRENT(r13) | |
1151 | addi r5,r4,THREAD /* Get THREAD */ | |
1152 | oris r12,r12,MSR_VEC@h | |
1153 | std r12,_MSR(r1) | |
1154 | li r4,1 | |
1155 | li r10,THREAD_VSCR | |
1156 | stw r4,THREAD_USED_VR(r5) | |
1157 | lvx vr0,r10,r5 | |
1158 | mtvscr vr0 | |
1159 | REST_32VRS(0,r4,r5) | |
1160 | #ifndef CONFIG_SMP | |
1161 | /* Update last_task_used_math to 'current' */ | |
1162 | subi r4,r5,THREAD /* Back to 'current' */ | |
1163 | std r4,0(r3) | |
1164 | #endif /* CONFIG_SMP */ | |
1165 | /* restore registers and return */ | |
1166 | b fast_exception_return | |
1167 | #endif /* CONFIG_ALTIVEC */ | |
1168 | ||
1169 | /* | |
1170 | * Hash table stuff | |
1171 | */ | |
1172 | .align 7 | |
1173 | _GLOBAL(do_hash_page) | |
1174 | std r3,_DAR(r1) | |
1175 | std r4,_DSISR(r1) | |
1176 | ||
1177 | andis. r0,r4,0xa450 /* weird error? */ | |
1178 | bne- .handle_page_fault /* if not, try to insert a HPTE */ | |
1179 | BEGIN_FTR_SECTION | |
1180 | andis. r0,r4,0x0020 /* Is it a segment table fault? */ | |
1181 | bne- .do_ste_alloc /* If so handle it */ | |
1182 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | |
1183 | ||
1184 | /* | |
1185 | * We need to set the _PAGE_USER bit if MSR_PR is set or if we are | |
1186 | * accessing a userspace segment (even from the kernel). We assume | |
1187 | * kernel addresses always have the high bit set. | |
1188 | */ | |
1189 | rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */ | |
1190 | rotldi r0,r3,15 /* Move high bit into MSR_PR posn */ | |
1191 | orc r0,r12,r0 /* MSR_PR | ~high_bit */ | |
1192 | rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */ | |
1193 | ori r4,r4,1 /* add _PAGE_PRESENT */ | |
1194 | rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */ | |
1195 | ||
1196 | /* | |
1197 | * On iSeries, we soft-disable interrupts here, then | |
1198 | * hard-enable interrupts so that the hash_page code can spin on | |
1199 | * the hash_table_lock without problems on a shared processor. | |
1200 | */ | |
1201 | DISABLE_INTS | |
1202 | ||
1203 | /* | |
1204 | * r3 contains the faulting address | |
1205 | * r4 contains the required access permissions | |
1206 | * r5 contains the trap number | |
1207 | * | |
1208 | * at return r3 = 0 for success | |
1209 | */ | |
1210 | bl .hash_page /* build HPTE if possible */ | |
1211 | cmpdi r3,0 /* see if hash_page succeeded */ | |
1212 | ||
1213 | #ifdef DO_SOFT_DISABLE | |
1214 | /* | |
1215 | * If we had interrupts soft-enabled at the point where the | |
1216 | * DSI/ISI occurred, and an interrupt came in during hash_page, | |
1217 | * handle it now. | |
1218 | * We jump to ret_from_except_lite rather than fast_exception_return | |
1219 | * because ret_from_except_lite will check for and handle pending | |
1220 | * interrupts if necessary. | |
1221 | */ | |
1222 | beq .ret_from_except_lite | |
1223 | /* For a hash failure, we don't bother re-enabling interrupts */ | |
1224 | ble- 12f | |
1225 | ||
1226 | /* | |
1227 | * hash_page couldn't handle it, set soft interrupt enable back | |
1228 | * to what it was before the trap. Note that .local_irq_restore | |
1229 | * handles any interrupts pending at this point. | |
1230 | */ | |
1231 | ld r3,SOFTE(r1) | |
1232 | bl .local_irq_restore | |
1233 | b 11f | |
1234 | #else | |
1235 | beq fast_exception_return /* Return from exception on success */ | |
1236 | ble- 12f /* Failure return from hash_page */ | |
1237 | ||
1238 | /* fall through */ | |
1239 | #endif | |
1240 | ||
1241 | /* Here we have a page fault that hash_page can't handle. */ | |
1242 | _GLOBAL(handle_page_fault) | |
1243 | ENABLE_INTS | |
1244 | 11: ld r4,_DAR(r1) | |
1245 | ld r5,_DSISR(r1) | |
1246 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1247 | bl .do_page_fault | |
1248 | cmpdi r3,0 | |
1249 | beq+ .ret_from_except_lite | |
1250 | bl .save_nvgprs | |
1251 | mr r5,r3 | |
1252 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1253 | lwz r4,_DAR(r1) | |
1254 | bl .bad_page_fault | |
1255 | b .ret_from_except | |
1256 | ||
1257 | /* We have a page fault that hash_page could handle but HV refused | |
1258 | * the PTE insertion | |
1259 | */ | |
1260 | 12: bl .save_nvgprs | |
1261 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1262 | lwz r4,_DAR(r1) | |
1263 | bl .low_hash_fault | |
1264 | b .ret_from_except | |
1265 | ||
1266 | /* here we have a segment miss */ | |
1267 | _GLOBAL(do_ste_alloc) | |
1268 | bl .ste_allocate /* try to insert stab entry */ | |
1269 | cmpdi r3,0 | |
1270 | beq+ fast_exception_return | |
1271 | b .handle_page_fault | |
1272 | ||
1273 | /* | |
1274 | * r13 points to the PACA, r9 contains the saved CR, | |
1275 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1276 | * r9 - r13 are saved in paca->exslb. | |
1277 | * We assume we aren't going to take any exceptions during this procedure. | |
1278 | * We assume (DAR >> 60) == 0xc. | |
1279 | */ | |
1280 | .align 7 | |
1281 | _GLOBAL(do_stab_bolted) | |
1282 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1283 | std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */ | |
1284 | ||
1285 | /* Hash to the primary group */ | |
1286 | ld r10,PACASTABVIRT(r13) | |
b5bbeb23 | 1287 | mfspr r11,SPRN_DAR |
14cf11af PM |
1288 | srdi r11,r11,28 |
1289 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | |
1290 | ||
1291 | /* Calculate VSID */ | |
1292 | /* This is a kernel address, so protovsid = ESID */ | |
1293 | ASM_VSID_SCRAMBLE(r11, r9) | |
1294 | rldic r9,r11,12,16 /* r9 = vsid << 12 */ | |
1295 | ||
1296 | /* Search the primary group for a free entry */ | |
1297 | 1: ld r11,0(r10) /* Test valid bit of the current ste */ | |
1298 | andi. r11,r11,0x80 | |
1299 | beq 2f | |
1300 | addi r10,r10,16 | |
1301 | andi. r11,r10,0x70 | |
1302 | bne 1b | |
1303 | ||
1304 | /* Stick for only searching the primary group for now. */ | |
1305 | /* At least for now, we use a very simple random castout scheme */ | |
1306 | /* Use the TB as a random number ; OR in 1 to avoid entry 0 */ | |
1307 | mftb r11 | |
1308 | rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */ | |
1309 | ori r11,r11,0x10 | |
1310 | ||
1311 | /* r10 currently points to an ste one past the group of interest */ | |
1312 | /* make it point to the randomly selected entry */ | |
1313 | subi r10,r10,128 | |
1314 | or r10,r10,r11 /* r10 is the entry to invalidate */ | |
1315 | ||
1316 | isync /* mark the entry invalid */ | |
1317 | ld r11,0(r10) | |
1318 | rldicl r11,r11,56,1 /* clear the valid bit */ | |
1319 | rotldi r11,r11,8 | |
1320 | std r11,0(r10) | |
1321 | sync | |
1322 | ||
1323 | clrrdi r11,r11,28 /* Get the esid part of the ste */ | |
1324 | slbie r11 | |
1325 | ||
1326 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | |
1327 | eieio | |
1328 | ||
b5bbeb23 | 1329 | mfspr r11,SPRN_DAR /* Get the new esid */ |
14cf11af PM |
1330 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ |
1331 | ori r11,r11,0x90 /* Turn on valid and kp */ | |
1332 | std r11,0(r10) /* Put new entry back into the stab */ | |
1333 | ||
1334 | sync | |
1335 | ||
1336 | /* All done -- return from exception. */ | |
1337 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
1338 | ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */ | |
1339 | ||
1340 | andi. r10,r12,MSR_RI | |
1341 | beq- unrecov_slb | |
1342 | ||
1343 | mtcrf 0x80,r9 /* restore CR */ | |
1344 | ||
1345 | mfmsr r10 | |
1346 | clrrdi r10,r10,2 | |
1347 | mtmsrd r10,1 | |
1348 | ||
b5bbeb23 PM |
1349 | mtspr SPRN_SRR0,r11 |
1350 | mtspr SPRN_SRR1,r12 | |
14cf11af PM |
1351 | ld r9,PACA_EXSLB+EX_R9(r13) |
1352 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1353 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1354 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1355 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1356 | rfid | |
1357 | b . /* prevent speculative execution */ | |
1358 | ||
14cf11af PM |
1359 | /* |
1360 | * Space for CPU0's segment table. | |
1361 | * | |
1362 | * On iSeries, the hypervisor must fill in at least one entry before | |
1363 | * we get control (with relocate on). The address is give to the hv | |
ee400b63 | 1364 | * as a page number (see xLparMap in lpardata.c), so this must be at a |
14cf11af PM |
1365 | * fixed address (the linker can't compute (u64)&initial_stab >> |
1366 | * PAGE_SHIFT). | |
1367 | */ | |
758438a7 | 1368 | . = STAB0_OFFSET /* 0x6000 */ |
14cf11af PM |
1369 | .globl initial_stab |
1370 | initial_stab: | |
1371 | .space 4096 | |
1372 | ||
1373 | /* | |
1374 | * Data area reserved for FWNMI option. | |
1375 | * This address (0x7000) is fixed by the RPA. | |
1376 | */ | |
1377 | .= 0x7000 | |
1378 | .globl fwnmi_data_area | |
1379 | fwnmi_data_area: | |
1380 | ||
1381 | /* iSeries does not use the FWNMI stuff, so it is safe to put | |
1382 | * this here, even if we later allow kernels that will boot on | |
1383 | * both pSeries and iSeries */ | |
1384 | #ifdef CONFIG_PPC_ISERIES | |
1385 | . = LPARMAP_PHYS | |
1386 | #include "lparmap.s" | |
1387 | /* | |
1388 | * This ".text" is here for old compilers that generate a trailing | |
1389 | * .note section when compiling .c files to .s | |
1390 | */ | |
1391 | .text | |
1392 | #endif /* CONFIG_PPC_ISERIES */ | |
1393 | ||
1394 | . = 0x8000 | |
1395 | ||
1396 | /* | |
1397 | * On pSeries, secondary processors spin in the following code. | |
1398 | * At entry, r3 = this processor's number (physical cpu id) | |
1399 | */ | |
1400 | _GLOBAL(pSeries_secondary_smp_init) | |
1401 | mr r24,r3 | |
1402 | ||
1403 | /* turn on 64-bit mode */ | |
1404 | bl .enable_64b_mode | |
1405 | isync | |
1406 | ||
1407 | /* Copy some CPU settings from CPU 0 */ | |
1408 | bl .__restore_cpu_setup | |
1409 | ||
1410 | /* Set up a paca value for this processor. Since we have the | |
1411 | * physical cpu id in r24, we need to search the pacas to find | |
1412 | * which logical id maps to our physical one. | |
1413 | */ | |
e58c3495 | 1414 | LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1415 | li r5,0 /* logical cpu id */ |
1416 | 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
1417 | cmpw r6,r24 /* Compare to our id */ | |
1418 | beq 2f | |
1419 | addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */ | |
1420 | addi r5,r5,1 | |
1421 | cmpwi r5,NR_CPUS | |
1422 | blt 1b | |
1423 | ||
1424 | mr r3,r24 /* not found, copy phys to r3 */ | |
1425 | b .kexec_wait /* next kernel might do better */ | |
1426 | ||
b5bbeb23 | 1427 | 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1428 | /* From now on, r24 is expected to be logical cpuid */ |
1429 | mr r24,r5 | |
1430 | 3: HMT_LOW | |
1431 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ | |
1432 | /* start. */ | |
1433 | sync | |
1434 | ||
1435 | /* Create a temp kernel stack for use before relocation is on. */ | |
1436 | ld r1,PACAEMERGSP(r13) | |
1437 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1438 | ||
1439 | cmpwi 0,r23,0 | |
1440 | #ifdef CONFIG_SMP | |
1441 | bne .__secondary_start | |
1442 | #endif | |
1443 | b 3b /* Loop until told to go */ | |
1444 | ||
1445 | #ifdef CONFIG_PPC_ISERIES | |
1446 | _STATIC(__start_initialization_iSeries) | |
1447 | /* Clear out the BSS */ | |
e58c3495 DG |
1448 | LOAD_REG_IMMEDIATE(r11,__bss_stop) |
1449 | LOAD_REG_IMMEDIATE(r8,__bss_start) | |
14cf11af PM |
1450 | sub r11,r11,r8 /* bss size */ |
1451 | addi r11,r11,7 /* round up to an even double word */ | |
1452 | rldicl. r11,r11,61,3 /* shift right by 3 */ | |
1453 | beq 4f | |
1454 | addi r8,r8,-8 | |
1455 | li r0,0 | |
1456 | mtctr r11 /* zero this many doublewords */ | |
1457 | 3: stdu r0,8(r8) | |
1458 | bdnz 3b | |
1459 | 4: | |
e58c3495 | 1460 | LOAD_REG_IMMEDIATE(r1,init_thread_union) |
14cf11af PM |
1461 | addi r1,r1,THREAD_SIZE |
1462 | li r0,0 | |
1463 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1464 | ||
e58c3495 DG |
1465 | LOAD_REG_IMMEDIATE(r3,cpu_specs) |
1466 | LOAD_REG_IMMEDIATE(r4,cur_cpu_spec) | |
14cf11af PM |
1467 | li r5,0 |
1468 | bl .identify_cpu | |
1469 | ||
e58c3495 | 1470 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1471 | addi r2,r2,0x4000 |
1472 | addi r2,r2,0x4000 | |
1473 | ||
1474 | bl .iSeries_early_setup | |
ee400b63 | 1475 | bl .early_setup |
14cf11af PM |
1476 | |
1477 | /* relocation is on at this point */ | |
1478 | ||
1479 | b .start_here_common | |
1480 | #endif /* CONFIG_PPC_ISERIES */ | |
1481 | ||
1482 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1483 | ||
1484 | _STATIC(__mmu_off) | |
1485 | mfmsr r3 | |
1486 | andi. r0,r3,MSR_IR|MSR_DR | |
1487 | beqlr | |
1488 | andc r3,r3,r0 | |
1489 | mtspr SPRN_SRR0,r4 | |
1490 | mtspr SPRN_SRR1,r3 | |
1491 | sync | |
1492 | rfid | |
1493 | b . /* prevent speculative execution */ | |
1494 | ||
1495 | ||
1496 | /* | |
1497 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
1498 | * depending on the value of r5. | |
1499 | * | |
1500 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
1501 | * in r3...r7 | |
1502 | * | |
1503 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
1504 | * DT block, r4 is a physical pointer to the kernel itself | |
1505 | * | |
1506 | */ | |
1507 | _GLOBAL(__start_initialization_multiplatform) | |
be42d5fa | 1508 | #ifdef CONFIG_PPC_MULTIPLATFORM |
14cf11af PM |
1509 | /* |
1510 | * Are we booted from a PROM Of-type client-interface ? | |
1511 | */ | |
1512 | cmpldi cr0,r5,0 | |
1513 | bne .__boot_from_prom /* yes -> prom */ | |
be42d5fa | 1514 | #endif |
14cf11af PM |
1515 | |
1516 | /* Save parameters */ | |
1517 | mr r31,r3 | |
1518 | mr r30,r4 | |
1519 | ||
1520 | /* Make sure we are running in 64 bits mode */ | |
1521 | bl .enable_64b_mode | |
1522 | ||
1523 | /* Setup some critical 970 SPRs before switching MMU off */ | |
1524 | bl .__970_cpu_preinit | |
1525 | ||
1526 | /* cpu # */ | |
1527 | li r24,0 | |
1528 | ||
1529 | /* Switch off MMU if not already */ | |
e58c3495 | 1530 | LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE) |
14cf11af PM |
1531 | add r4,r4,r30 |
1532 | bl .__mmu_off | |
1533 | b .__after_prom_start | |
1534 | ||
be42d5fa | 1535 | #ifdef CONFIG_PPC_MULTIPLATFORM |
14cf11af PM |
1536 | _STATIC(__boot_from_prom) |
1537 | /* Save parameters */ | |
1538 | mr r31,r3 | |
1539 | mr r30,r4 | |
1540 | mr r29,r5 | |
1541 | mr r28,r6 | |
1542 | mr r27,r7 | |
1543 | ||
1544 | /* Make sure we are running in 64 bits mode */ | |
1545 | bl .enable_64b_mode | |
1546 | ||
1547 | /* put a relocation offset into r3 */ | |
1548 | bl .reloc_offset | |
1549 | ||
e58c3495 | 1550 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1551 | addi r2,r2,0x4000 |
1552 | addi r2,r2,0x4000 | |
1553 | ||
1554 | /* Relocate the TOC from a virt addr to a real addr */ | |
5a408329 | 1555 | add r2,r2,r3 |
14cf11af PM |
1556 | |
1557 | /* Restore parameters */ | |
1558 | mr r3,r31 | |
1559 | mr r4,r30 | |
1560 | mr r5,r29 | |
1561 | mr r6,r28 | |
1562 | mr r7,r27 | |
1563 | ||
1564 | /* Do all of the interaction with OF client interface */ | |
1565 | bl .prom_init | |
1566 | /* We never return */ | |
1567 | trap | |
be42d5fa | 1568 | #endif |
14cf11af PM |
1569 | |
1570 | /* | |
1571 | * At this point, r3 contains the physical address we are running at, | |
1572 | * returned by prom_init() | |
1573 | */ | |
1574 | _STATIC(__after_prom_start) | |
1575 | ||
1576 | /* | |
758438a7 | 1577 | * We need to run with __start at physical address PHYSICAL_START. |
14cf11af PM |
1578 | * This will leave some code in the first 256B of |
1579 | * real memory, which are reserved for software use. | |
1580 | * The remainder of the first page is loaded with the fixed | |
1581 | * interrupt vectors. The next two pages are filled with | |
1582 | * unknown exception placeholders. | |
1583 | * | |
1584 | * Note: This process overwrites the OF exception vectors. | |
1585 | * r26 == relocation offset | |
1586 | * r27 == KERNELBASE | |
1587 | */ | |
1588 | bl .reloc_offset | |
1589 | mr r26,r3 | |
e58c3495 | 1590 | LOAD_REG_IMMEDIATE(r27, KERNELBASE) |
14cf11af | 1591 | |
e58c3495 | 1592 | LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */ |
14cf11af PM |
1593 | |
1594 | // XXX FIXME: Use phys returned by OF (r30) | |
5a408329 | 1595 | add r4,r27,r26 /* source addr */ |
14cf11af PM |
1596 | /* current address of _start */ |
1597 | /* i.e. where we are running */ | |
1598 | /* the source addr */ | |
1599 | ||
e58c3495 | 1600 | LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */ |
14cf11af PM |
1601 | sub r5,r5,r27 |
1602 | ||
1603 | li r6,0x100 /* Start offset, the first 0x100 */ | |
1604 | /* bytes were copied earlier. */ | |
1605 | ||
1606 | bl .copy_and_flush /* copy the first n bytes */ | |
1607 | /* this includes the code being */ | |
1608 | /* executed here. */ | |
1609 | ||
e58c3495 | 1610 | LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */ |
14cf11af PM |
1611 | mtctr r0 /* that we just made/relocated */ |
1612 | bctr | |
1613 | ||
e58c3495 | 1614 | 4: LOAD_REG_IMMEDIATE(r5,klimit) |
5a408329 | 1615 | add r5,r5,r26 |
14cf11af PM |
1616 | ld r5,0(r5) /* get the value of klimit */ |
1617 | sub r5,r5,r27 | |
1618 | bl .copy_and_flush /* copy the rest */ | |
1619 | b .start_here_multiplatform | |
1620 | ||
1621 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
1622 | ||
1623 | /* | |
1624 | * Copy routine used to copy the kernel to start at physical address 0 | |
1625 | * and flush and invalidate the caches as needed. | |
1626 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
1627 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
1628 | * | |
1629 | * Note: this routine *only* clobbers r0, r6 and lr | |
1630 | */ | |
1631 | _GLOBAL(copy_and_flush) | |
1632 | addi r5,r5,-8 | |
1633 | addi r6,r6,-8 | |
1634 | 4: li r0,16 /* Use the least common */ | |
1635 | /* denominator cache line */ | |
1636 | /* size. This results in */ | |
1637 | /* extra cache line flushes */ | |
1638 | /* but operation is correct. */ | |
1639 | /* Can't get cache line size */ | |
1640 | /* from NACA as it is being */ | |
1641 | /* moved too. */ | |
1642 | ||
1643 | mtctr r0 /* put # words/line in ctr */ | |
1644 | 3: addi r6,r6,8 /* copy a cache line */ | |
1645 | ldx r0,r6,r4 | |
1646 | stdx r0,r6,r3 | |
1647 | bdnz 3b | |
1648 | dcbst r6,r3 /* write it to memory */ | |
1649 | sync | |
1650 | icbi r6,r3 /* flush the icache line */ | |
1651 | cmpld 0,r6,r5 | |
1652 | blt 4b | |
1653 | sync | |
1654 | addi r5,r5,8 | |
1655 | addi r6,r6,8 | |
1656 | blr | |
1657 | ||
1658 | .align 8 | |
1659 | copy_to_here: | |
1660 | ||
1661 | #ifdef CONFIG_SMP | |
1662 | #ifdef CONFIG_PPC_PMAC | |
1663 | /* | |
1664 | * On PowerMac, secondary processors starts from the reset vector, which | |
1665 | * is temporarily turned into a call to one of the functions below. | |
1666 | */ | |
1667 | .section ".text"; | |
1668 | .align 2 ; | |
1669 | ||
35499c01 PM |
1670 | .globl __secondary_start_pmac_0 |
1671 | __secondary_start_pmac_0: | |
1672 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
1673 | li r24,0 | |
1674 | b 1f | |
1675 | li r24,1 | |
1676 | b 1f | |
1677 | li r24,2 | |
1678 | b 1f | |
1679 | li r24,3 | |
1680 | 1: | |
14cf11af PM |
1681 | |
1682 | _GLOBAL(pmac_secondary_start) | |
1683 | /* turn on 64-bit mode */ | |
1684 | bl .enable_64b_mode | |
1685 | isync | |
1686 | ||
1687 | /* Copy some CPU settings from CPU 0 */ | |
1688 | bl .__restore_cpu_setup | |
1689 | ||
1690 | /* pSeries do that early though I don't think we really need it */ | |
1691 | mfmsr r3 | |
1692 | ori r3,r3,MSR_RI | |
1693 | mtmsrd r3 /* RI on */ | |
1694 | ||
1695 | /* Set up a paca value for this processor. */ | |
e58c3495 | 1696 | LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1697 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
1698 | add r13,r13,r4 /* for this processor. */ | |
b5bbeb23 | 1699 | mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
14cf11af PM |
1700 | |
1701 | /* Create a temp kernel stack for use before relocation is on. */ | |
1702 | ld r1,PACAEMERGSP(r13) | |
1703 | subi r1,r1,STACK_FRAME_OVERHEAD | |
1704 | ||
1705 | b .__secondary_start | |
1706 | ||
1707 | #endif /* CONFIG_PPC_PMAC */ | |
1708 | ||
1709 | /* | |
1710 | * This function is called after the master CPU has released the | |
1711 | * secondary processors. The execution environment is relocation off. | |
1712 | * The paca for this processor has the following fields initialized at | |
1713 | * this point: | |
1714 | * 1. Processor number | |
1715 | * 2. Segment table pointer (virtual address) | |
1716 | * On entry the following are set: | |
1717 | * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries | |
1718 | * r24 = cpu# (in Linux terms) | |
1719 | * r13 = paca virtual address | |
1720 | * SPRG3 = paca virtual address | |
1721 | */ | |
1722 | _GLOBAL(__secondary_start) | |
799d6046 PM |
1723 | /* Set thread priority to MEDIUM */ |
1724 | HMT_MEDIUM | |
14cf11af | 1725 | |
799d6046 | 1726 | /* Load TOC */ |
14cf11af | 1727 | ld r2,PACATOC(r13) |
799d6046 PM |
1728 | |
1729 | /* Do early setup for that CPU (stab, slb, hash table pointer) */ | |
1730 | bl .early_setup_secondary | |
14cf11af PM |
1731 | |
1732 | /* Initialize the kernel stack. Just a repeat for iSeries. */ | |
e58c3495 | 1733 | LOAD_REG_ADDR(r3, current_set) |
14cf11af PM |
1734 | sldi r28,r24,3 /* get current_set[cpu#] */ |
1735 | ldx r1,r3,r28 | |
1736 | addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
1737 | std r1,PACAKSAVE(r13) | |
1738 | ||
799d6046 | 1739 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
1740 | li r7,0 |
1741 | mtlr r7 | |
1742 | ||
1743 | /* enable MMU and jump to start_secondary */ | |
e58c3495 DG |
1744 | LOAD_REG_ADDR(r3, .start_secondary_prolog) |
1745 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
14cf11af PM |
1746 | #ifdef DO_SOFT_DISABLE |
1747 | ori r4,r4,MSR_EE | |
1748 | #endif | |
b5bbeb23 PM |
1749 | mtspr SPRN_SRR0,r3 |
1750 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1751 | rfid |
1752 | b . /* prevent speculative execution */ | |
1753 | ||
1754 | /* | |
1755 | * Running with relocation on at this point. All we want to do is | |
1756 | * zero the stack back-chain pointer before going into C code. | |
1757 | */ | |
1758 | _GLOBAL(start_secondary_prolog) | |
1759 | li r3,0 | |
1760 | std r3,0(r1) /* Zero the stack frame pointer */ | |
1761 | bl .start_secondary | |
799d6046 | 1762 | b . |
14cf11af PM |
1763 | #endif |
1764 | ||
1765 | /* | |
1766 | * This subroutine clobbers r11 and r12 | |
1767 | */ | |
1768 | _GLOBAL(enable_64b_mode) | |
1769 | mfmsr r11 /* grab the current MSR */ | |
1770 | li r12,1 | |
1771 | rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG) | |
1772 | or r11,r11,r12 | |
1773 | li r12,1 | |
1774 | rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG) | |
1775 | or r11,r11,r12 | |
1776 | mtmsrd r11 | |
1777 | isync | |
1778 | blr | |
1779 | ||
1780 | #ifdef CONFIG_PPC_MULTIPLATFORM | |
1781 | /* | |
1782 | * This is where the main kernel code starts. | |
1783 | */ | |
1784 | _STATIC(start_here_multiplatform) | |
1785 | /* get a new offset, now that the kernel has moved. */ | |
1786 | bl .reloc_offset | |
1787 | mr r26,r3 | |
1788 | ||
1789 | /* Clear out the BSS. It may have been done in prom_init, | |
1790 | * already but that's irrelevant since prom_init will soon | |
1791 | * be detached from the kernel completely. Besides, we need | |
1792 | * to clear it now for kexec-style entry. | |
1793 | */ | |
e58c3495 DG |
1794 | LOAD_REG_IMMEDIATE(r11,__bss_stop) |
1795 | LOAD_REG_IMMEDIATE(r8,__bss_start) | |
14cf11af PM |
1796 | sub r11,r11,r8 /* bss size */ |
1797 | addi r11,r11,7 /* round up to an even double word */ | |
1798 | rldicl. r11,r11,61,3 /* shift right by 3 */ | |
1799 | beq 4f | |
1800 | addi r8,r8,-8 | |
1801 | li r0,0 | |
1802 | mtctr r11 /* zero this many doublewords */ | |
1803 | 3: stdu r0,8(r8) | |
1804 | bdnz 3b | |
1805 | 4: | |
1806 | ||
1807 | mfmsr r6 | |
1808 | ori r6,r6,MSR_RI | |
1809 | mtmsrd r6 /* RI on */ | |
1810 | ||
1811 | #ifdef CONFIG_HMT | |
1812 | /* Start up the second thread on cpu 0 */ | |
b5bbeb23 | 1813 | mfspr r3,SPRN_PVR |
14cf11af PM |
1814 | srwi r3,r3,16 |
1815 | cmpwi r3,0x34 /* Pulsar */ | |
1816 | beq 90f | |
1817 | cmpwi r3,0x36 /* Icestar */ | |
1818 | beq 90f | |
1819 | cmpwi r3,0x37 /* SStar */ | |
1820 | beq 90f | |
1821 | b 91f /* HMT not supported */ | |
1822 | 90: li r3,0 | |
1823 | bl .hmt_start_secondary | |
1824 | 91: | |
1825 | #endif | |
1826 | ||
1827 | /* The following gets the stack and TOC set up with the regs */ | |
1828 | /* pointing to the real addr of the kernel stack. This is */ | |
1829 | /* all done to support the C function call below which sets */ | |
1830 | /* up the htab. This is done because we have relocated the */ | |
1831 | /* kernel but are still running in real mode. */ | |
1832 | ||
e58c3495 | 1833 | LOAD_REG_IMMEDIATE(r3,init_thread_union) |
5a408329 | 1834 | add r3,r3,r26 |
14cf11af PM |
1835 | |
1836 | /* set up a stack pointer (physical address) */ | |
1837 | addi r1,r3,THREAD_SIZE | |
1838 | li r0,0 | |
1839 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1840 | ||
1841 | /* set up the TOC (physical address) */ | |
e58c3495 | 1842 | LOAD_REG_IMMEDIATE(r2,__toc_start) |
14cf11af PM |
1843 | addi r2,r2,0x4000 |
1844 | addi r2,r2,0x4000 | |
5a408329 | 1845 | add r2,r2,r26 |
14cf11af | 1846 | |
e58c3495 | 1847 | LOAD_REG_IMMEDIATE(r3, cpu_specs) |
5a408329 | 1848 | add r3,r3,r26 |
e58c3495 | 1849 | LOAD_REG_IMMEDIATE(r4,cur_cpu_spec) |
5a408329 | 1850 | add r4,r4,r26 |
14cf11af PM |
1851 | mr r5,r26 |
1852 | bl .identify_cpu | |
1853 | ||
1854 | /* Save some low level config HIDs of CPU0 to be copied to | |
1855 | * other CPUs later on, or used for suspend/resume | |
1856 | */ | |
1857 | bl .__save_cpu_setup | |
1858 | sync | |
1859 | ||
1860 | /* Setup a valid physical PACA pointer in SPRG3 for early_setup | |
1861 | * note that boot_cpuid can always be 0 nowadays since there is | |
1862 | * nowhere it can be initialized differently before we reach this | |
1863 | * code | |
1864 | */ | |
e58c3495 | 1865 | LOAD_REG_IMMEDIATE(r27, boot_cpuid) |
5a408329 | 1866 | add r27,r27,r26 |
14cf11af PM |
1867 | lwz r27,0(r27) |
1868 | ||
e58c3495 | 1869 | LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1870 | mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ |
1871 | add r13,r13,r24 /* for this processor. */ | |
5a408329 | 1872 | add r13,r13,r26 /* convert to physical addr */ |
448b2719 | 1873 | mtspr SPRN_SPRG3,r13 |
14cf11af PM |
1874 | |
1875 | /* Do very early kernel initializations, including initial hash table, | |
1876 | * stab and slb setup before we turn on relocation. */ | |
1877 | ||
1878 | /* Restore parameters passed from prom_init/kexec */ | |
1879 | mr r3,r31 | |
1880 | bl .early_setup | |
1881 | ||
e58c3495 DG |
1882 | LOAD_REG_IMMEDIATE(r3, .start_here_common) |
1883 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) | |
b5bbeb23 PM |
1884 | mtspr SPRN_SRR0,r3 |
1885 | mtspr SPRN_SRR1,r4 | |
14cf11af PM |
1886 | rfid |
1887 | b . /* prevent speculative execution */ | |
1888 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
1889 | ||
1890 | /* This is where all platforms converge execution */ | |
1891 | _STATIC(start_here_common) | |
1892 | /* relocation is on at this point */ | |
1893 | ||
1894 | /* The following code sets up the SP and TOC now that we are */ | |
1895 | /* running with translation enabled. */ | |
1896 | ||
e58c3495 | 1897 | LOAD_REG_IMMEDIATE(r3,init_thread_union) |
14cf11af PM |
1898 | |
1899 | /* set up the stack */ | |
1900 | addi r1,r3,THREAD_SIZE | |
1901 | li r0,0 | |
1902 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
1903 | ||
1904 | /* Apply the CPUs-specific fixups (nop out sections not relevant | |
1905 | * to this CPU | |
1906 | */ | |
1907 | li r3,0 | |
1908 | bl .do_cpu_ftr_fixups | |
1909 | ||
e58c3495 | 1910 | LOAD_REG_IMMEDIATE(r26, boot_cpuid) |
14cf11af PM |
1911 | lwz r26,0(r26) |
1912 | ||
e58c3495 | 1913 | LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */ |
14cf11af PM |
1914 | mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ |
1915 | add r13,r13,r24 /* for this processor. */ | |
b5bbeb23 | 1916 | mtspr SPRN_SPRG3,r13 |
14cf11af PM |
1917 | |
1918 | /* ptr to current */ | |
e58c3495 | 1919 | LOAD_REG_IMMEDIATE(r4, init_task) |
14cf11af PM |
1920 | std r4,PACACURRENT(r13) |
1921 | ||
1922 | /* Load the TOC */ | |
1923 | ld r2,PACATOC(r13) | |
1924 | std r1,PACAKSAVE(r13) | |
1925 | ||
1926 | bl .setup_system | |
1927 | ||
1928 | /* Load up the kernel context */ | |
1929 | 5: | |
1930 | #ifdef DO_SOFT_DISABLE | |
1931 | li r5,0 | |
1932 | stb r5,PACAPROCENABLED(r13) /* Soft Disabled */ | |
1933 | mfmsr r5 | |
1934 | ori r5,r5,MSR_EE /* Hard Enabled */ | |
1935 | mtmsrd r5 | |
1936 | #endif | |
1937 | ||
1938 | bl .start_kernel | |
1939 | ||
1940 | _GLOBAL(hmt_init) | |
1941 | #ifdef CONFIG_HMT | |
e58c3495 | 1942 | LOAD_REG_IMMEDIATE(r5, hmt_thread_data) |
b5bbeb23 | 1943 | mfspr r7,SPRN_PVR |
14cf11af PM |
1944 | srwi r7,r7,16 |
1945 | cmpwi r7,0x34 /* Pulsar */ | |
1946 | beq 90f | |
1947 | cmpwi r7,0x36 /* Icestar */ | |
1948 | beq 91f | |
1949 | cmpwi r7,0x37 /* SStar */ | |
1950 | beq 91f | |
1951 | b 101f | |
b5bbeb23 | 1952 | 90: mfspr r6,SPRN_PIR |
14cf11af PM |
1953 | andi. r6,r6,0x1f |
1954 | b 92f | |
b5bbeb23 | 1955 | 91: mfspr r6,SPRN_PIR |
14cf11af PM |
1956 | andi. r6,r6,0x3ff |
1957 | 92: sldi r4,r24,3 | |
1958 | stwx r6,r5,r4 | |
1959 | bl .hmt_start_secondary | |
1960 | b 101f | |
1961 | ||
1962 | __hmt_secondary_hold: | |
e58c3495 | 1963 | LOAD_REG_IMMEDIATE(r5, hmt_thread_data) |
14cf11af PM |
1964 | clrldi r5,r5,4 |
1965 | li r7,0 | |
b5bbeb23 PM |
1966 | mfspr r6,SPRN_PIR |
1967 | mfspr r8,SPRN_PVR | |
14cf11af PM |
1968 | srwi r8,r8,16 |
1969 | cmpwi r8,0x34 | |
1970 | bne 93f | |
1971 | andi. r6,r6,0x1f | |
1972 | b 103f | |
1973 | 93: andi. r6,r6,0x3f | |
1974 | ||
1975 | 103: lwzx r8,r5,r7 | |
1976 | cmpw r8,r6 | |
1977 | beq 104f | |
1978 | addi r7,r7,8 | |
1979 | b 103b | |
1980 | ||
1981 | 104: addi r7,r7,4 | |
1982 | lwzx r9,r5,r7 | |
1983 | mr r24,r9 | |
1984 | 101: | |
1985 | #endif | |
1986 | mr r3,r24 | |
1987 | b .pSeries_secondary_smp_init | |
1988 | ||
1989 | #ifdef CONFIG_HMT | |
1990 | _GLOBAL(hmt_start_secondary) | |
e58c3495 | 1991 | LOAD_REG_IMMEDIATE(r4,__hmt_secondary_hold) |
14cf11af | 1992 | clrldi r4,r4,4 |
b5bbeb23 PM |
1993 | mtspr SPRN_NIADORM, r4 |
1994 | mfspr r4, SPRN_MSRDORM | |
14cf11af PM |
1995 | li r5, -65 |
1996 | and r4, r4, r5 | |
b5bbeb23 | 1997 | mtspr SPRN_MSRDORM, r4 |
14cf11af PM |
1998 | lis r4,0xffef |
1999 | ori r4,r4,0x7403 | |
b5bbeb23 | 2000 | mtspr SPRN_TSC, r4 |
14cf11af | 2001 | li r4,0x1f4 |
b5bbeb23 PM |
2002 | mtspr SPRN_TST, r4 |
2003 | mfspr r4, SPRN_HID0 | |
14cf11af | 2004 | ori r4, r4, 0x1 |
b5bbeb23 | 2005 | mtspr SPRN_HID0, r4 |
14cf11af PM |
2006 | mfspr r4, SPRN_CTRLF |
2007 | oris r4, r4, 0x40 | |
2008 | mtspr SPRN_CTRLT, r4 | |
2009 | blr | |
2010 | #endif | |
2011 | ||
14cf11af PM |
2012 | /* |
2013 | * We put a few things here that have to be page-aligned. | |
2014 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
2015 | */ | |
2016 | .section ".bss" | |
2017 | ||
2018 | .align PAGE_SHIFT | |
2019 | ||
2020 | .globl empty_zero_page | |
2021 | empty_zero_page: | |
2022 | .space PAGE_SIZE | |
2023 | ||
2024 | .globl swapper_pg_dir | |
2025 | swapper_pg_dir: | |
2026 | .space PAGE_SIZE | |
2027 | ||
2028 | /* | |
2029 | * This space gets a copy of optional info passed to us by the bootstrap | |
2030 | * Used to pass parameters into the kernel like root=/dev/sda1, etc. | |
2031 | */ | |
2032 | .globl cmd_line | |
2033 | cmd_line: | |
2034 | .space COMMAND_LINE_SIZE |