]>
Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
6 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
7 | * Adapted for Power Macintosh by Paul Mackerras. | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * | |
12 | * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and | |
13 | * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com | |
14 | * | |
0ebc4cda BH |
15 | * This file contains the entry point for the 64-bit kernel along |
16 | * with some early initialization code common to all 64-bit powerpc | |
17 | * variants. | |
14cf11af PM |
18 | * |
19 | * This program is free software; you can redistribute it and/or | |
20 | * modify it under the terms of the GNU General Public License | |
21 | * as published by the Free Software Foundation; either version | |
22 | * 2 of the License, or (at your option) any later version. | |
23 | */ | |
24 | ||
14cf11af | 25 | #include <linux/threads.h> |
c141611f | 26 | #include <linux/init.h> |
b5bbeb23 | 27 | #include <asm/reg.h> |
14cf11af PM |
28 | #include <asm/page.h> |
29 | #include <asm/mmu.h> | |
14cf11af | 30 | #include <asm/ppc_asm.h> |
57f26649 | 31 | #include <asm/head-64.h> |
14cf11af PM |
32 | #include <asm/asm-offsets.h> |
33 | #include <asm/bug.h> | |
34 | #include <asm/cputable.h> | |
35 | #include <asm/setup.h> | |
36 | #include <asm/hvcall.h> | |
6cb7bfeb | 37 | #include <asm/thread_info.h> |
3f639ee8 | 38 | #include <asm/firmware.h> |
16a15a30 | 39 | #include <asm/page_64.h> |
945feb17 | 40 | #include <asm/irqflags.h> |
2191d657 | 41 | #include <asm/kvm_book3s_asm.h> |
46f52210 | 42 | #include <asm/ptrace.h> |
7230c564 | 43 | #include <asm/hw_irq.h> |
6becef7e | 44 | #include <asm/cputhreads.h> |
7a25d912 | 45 | #include <asm/ppc-opcode.h> |
9445aa1a | 46 | #include <asm/export.h> |
14cf11af | 47 | |
25985edc | 48 | /* The physical memory is laid out such that the secondary processor |
0ebc4cda BH |
49 | * spin code sits at 0x0000...0x00ff. On server, the vectors follow |
50 | * using the layout described in exceptions-64s.S | |
14cf11af PM |
51 | */ |
52 | ||
53 | /* | |
54 | * Entering into this code we make the following assumptions: | |
0ebc4cda BH |
55 | * |
56 | * For pSeries or server processors: | |
14cf11af | 57 | * 1. The MMU is off & open firmware is running in real mode. |
339a3293 NP |
58 | * 2. The primary CPU enters at __start. |
59 | * 3. If the RTAS supports "query-cpu-stopped-state", then secondary | |
60 | * CPUs will enter as directed by "start-cpu" RTAS call, which is | |
61 | * generic_secondary_smp_init, with PIR in r3. | |
62 | * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as | |
63 | * directed by the "start-cpu" RTS call, with PIR in r3. | |
27f44888 | 64 | * -or- For OPAL entry: |
339a3293 NP |
65 | * 1. The MMU is off, processor in HV mode. |
66 | * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base | |
67 | * in r8, and entry in r9 for debugging purposes. | |
68 | * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which | |
69 | * is at generic_secondary_smp_init, with PIR in r3. | |
14cf11af | 70 | * |
0ebc4cda BH |
71 | * For Book3E processors: |
72 | * 1. The MMU is on running in AS0 in a state defined in ePAPR | |
73 | * 2. The kernel is entered at __start | |
14cf11af PM |
74 | */ |
75 | ||
57f26649 NP |
76 | OPEN_FIXED_SECTION(first_256B, 0x0, 0x100) |
77 | USE_FIXED_SECTION(first_256B) | |
78 | /* | |
79 | * Offsets are relative from the start of fixed section, and | |
80 | * first_256B starts at 0. Offsets are a bit easier to use here | |
81 | * than the fixed section entry macros. | |
82 | */ | |
83 | . = 0x0 | |
14cf11af PM |
84 | _GLOBAL(__start) |
85 | /* NOP this out unconditionally */ | |
86 | BEGIN_FTR_SECTION | |
5c0484e2 | 87 | FIXUP_ENDIAN |
b1576fec | 88 | b __start_initialization_multiplatform |
14cf11af | 89 | END_FTR_SECTION(0, 1) |
14cf11af PM |
90 | |
91 | /* Catch branch to 0 in real mode */ | |
92 | trap | |
93 | ||
2751b628 AB |
94 | /* Secondary processors spin on this value until it becomes non-zero. |
95 | * When non-zero, it contains the real address of the function the cpu | |
96 | * should jump to. | |
1f6a93e4 | 97 | */ |
7d4151b5 | 98 | .balign 8 |
14cf11af PM |
99 | .globl __secondary_hold_spinloop |
100 | __secondary_hold_spinloop: | |
eb039161 | 101 | .8byte 0x0 |
14cf11af PM |
102 | |
103 | /* Secondary processors write this value with their cpu # */ | |
104 | /* after they enter the spin loop immediately below. */ | |
105 | .globl __secondary_hold_acknowledge | |
106 | __secondary_hold_acknowledge: | |
eb039161 | 107 | .8byte 0x0 |
14cf11af | 108 | |
928a3197 | 109 | #ifdef CONFIG_RELOCATABLE |
8b8b0cc1 MM |
110 | /* This flag is set to 1 by a loader if the kernel should run |
111 | * at the loaded address instead of the linked address. This | |
112 | * is used by kexec-tools to keep the the kdump kernel in the | |
113 | * crash_kernel region. The loader is responsible for | |
114 | * observing the alignment requirement. | |
115 | */ | |
70839d20 NP |
116 | |
117 | #ifdef CONFIG_RELOCATABLE_TEST | |
118 | #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */ | |
119 | #else | |
120 | #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */ | |
121 | #endif | |
122 | ||
8b8b0cc1 MM |
123 | /* Do not move this variable as kexec-tools knows about it. */ |
124 | . = 0x5c | |
125 | .globl __run_at_load | |
126 | __run_at_load: | |
57f26649 | 127 | DEFINE_FIXED_SYMBOL(__run_at_load) |
70839d20 | 128 | .long RUN_AT_LOAD_DEFAULT |
8b8b0cc1 MM |
129 | #endif |
130 | ||
14cf11af PM |
131 | . = 0x60 |
132 | /* | |
75423b7b GL |
133 | * The following code is used to hold secondary processors |
134 | * in a spin loop after they have entered the kernel, but | |
14cf11af PM |
135 | * before the bulk of the kernel has been relocated. This code |
136 | * is relocated to physical address 0x60 before prom_init is run. | |
137 | * All of it must fit below the first exception vector at 0x100. | |
1f6a93e4 PM |
138 | * Use .globl here not _GLOBAL because we want __secondary_hold |
139 | * to be the actual text address, not a descriptor. | |
14cf11af | 140 | */ |
1f6a93e4 PM |
141 | .globl __secondary_hold |
142 | __secondary_hold: | |
5c0484e2 | 143 | FIXUP_ENDIAN |
2d27cfd3 | 144 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
145 | mfmsr r24 |
146 | ori r24,r24,MSR_RI | |
147 | mtmsrd r24 /* RI on */ | |
2d27cfd3 | 148 | #endif |
f1870f77 | 149 | /* Grab our physical cpu number */ |
14cf11af | 150 | mr r24,r3 |
96f013fe JX |
151 | /* stash r4 for book3e */ |
152 | mr r25,r4 | |
14cf11af PM |
153 | |
154 | /* Tell the master cpu we're here */ | |
155 | /* Relocation is off & we are located at an address less */ | |
156 | /* than 0x100, so only need to grab low order offset. */ | |
57f26649 | 157 | std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0) |
14cf11af PM |
158 | sync |
159 | ||
96f013fe JX |
160 | li r26,0 |
161 | #ifdef CONFIG_PPC_BOOK3E | |
162 | tovirt(r26,r26) | |
163 | #endif | |
14cf11af | 164 | /* All secondary cpus wait here until told to start. */ |
57f26649 | 165 | 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26) |
cc7efbf9 | 166 | cmpdi 0,r12,0 |
1f6a93e4 | 167 | beq 100b |
14cf11af | 168 | |
da665885 | 169 | #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE) |
96f013fe | 170 | #ifdef CONFIG_PPC_BOOK3E |
cc7efbf9 | 171 | tovirt(r12,r12) |
cc7efbf9 AB |
172 | #endif |
173 | mtctr r12 | |
14cf11af | 174 | mr r3,r24 |
96f013fe JX |
175 | /* |
176 | * it may be the case that other platforms have r4 right to | |
177 | * begin with, this gives us some safety in case it is not | |
178 | */ | |
179 | #ifdef CONFIG_PPC_BOOK3E | |
180 | mr r4,r25 | |
181 | #else | |
2d27cfd3 | 182 | li r4,0 |
96f013fe | 183 | #endif |
dd797738 BH |
184 | /* Make sure that patched code is visible */ |
185 | isync | |
758438a7 | 186 | bctr |
14cf11af PM |
187 | #else |
188 | BUG_OPCODE | |
189 | #endif | |
57f26649 | 190 | CLOSE_FIXED_SECTION(first_256B) |
14cf11af PM |
191 | |
192 | /* This value is used to mark exception frames on the stack. */ | |
193 | .section ".toc","aw" | |
194 | exception_marker: | |
195 | .tc ID_72656773_68657265[TC],0x7265677368657265 | |
57f26649 | 196 | .previous |
14cf11af | 197 | |
14cf11af | 198 | /* |
0ebc4cda BH |
199 | * On server, we include the exception vectors code here as it |
200 | * relies on absolute addressing which is only possible within | |
201 | * this compilation unit | |
3c726f8d | 202 | */ |
0ebc4cda BH |
203 | #ifdef CONFIG_PPC_BOOK3S |
204 | #include "exceptions-64s.S" | |
57f26649 NP |
205 | #else |
206 | OPEN_TEXT_SECTION(0x100) | |
1f6a93e4 | 207 | #endif |
3c726f8d | 208 | |
57f26649 NP |
209 | USE_TEXT_SECTION() |
210 | ||
e16c8765 | 211 | #ifdef CONFIG_PPC_BOOK3E |
6becef7e | 212 | /* |
213 | * The booting_thread_hwid holds the thread id we want to boot in cpu | |
214 | * hotplug case. It is set by cpu hotplug code, and is invalid by default. | |
215 | * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID] | |
216 | * bit field. | |
217 | */ | |
218 | .globl booting_thread_hwid | |
219 | booting_thread_hwid: | |
220 | .long INVALID_THREAD_HWID | |
221 | .align 3 | |
222 | /* | |
223 | * start a thread in the same core | |
224 | * input parameters: | |
225 | * r3 = the thread physical id | |
226 | * r4 = the entry point where thread starts | |
227 | */ | |
228 | _GLOBAL(book3e_start_thread) | |
229 | LOAD_REG_IMMEDIATE(r5, MSR_KERNEL) | |
f87f253b | 230 | cmpwi r3, 0 |
6becef7e | 231 | beq 10f |
f87f253b | 232 | cmpwi r3, 1 |
6becef7e | 233 | beq 11f |
234 | /* If the thread id is invalid, just exit. */ | |
235 | b 13f | |
236 | 10: | |
7a25d912 SW |
237 | MTTMR(TMRN_IMSR0, 5) |
238 | MTTMR(TMRN_INIA0, 4) | |
6becef7e | 239 | b 12f |
240 | 11: | |
7a25d912 SW |
241 | MTTMR(TMRN_IMSR1, 5) |
242 | MTTMR(TMRN_INIA1, 4) | |
6becef7e | 243 | 12: |
244 | isync | |
245 | li r6, 1 | |
246 | sld r6, r6, r3 | |
247 | mtspr SPRN_TENS, r6 | |
248 | 13: | |
249 | blr | |
250 | ||
d17799f9 | 251 | /* |
252 | * stop a thread in the same core | |
253 | * input parameter: | |
254 | * r3 = the thread physical id | |
255 | */ | |
256 | _GLOBAL(book3e_stop_thread) | |
f87f253b | 257 | cmpwi r3, 0 |
d17799f9 | 258 | beq 10f |
f87f253b | 259 | cmpwi r3, 1 |
d17799f9 | 260 | beq 10f |
261 | /* If the thread id is invalid, just exit. */ | |
262 | b 13f | |
263 | 10: | |
264 | li r4, 1 | |
265 | sld r4, r4, r3 | |
266 | mtspr SPRN_TENC, r4 | |
267 | 13: | |
268 | blr | |
269 | ||
e16c8765 | 270 | _GLOBAL(fsl_secondary_thread_init) |
f34b3e19 SW |
271 | mfspr r4,SPRN_BUCSR |
272 | ||
e16c8765 AF |
273 | /* Enable branch prediction */ |
274 | lis r3,BUCSR_INIT@h | |
275 | ori r3,r3,BUCSR_INIT@l | |
276 | mtspr SPRN_BUCSR,r3 | |
277 | isync | |
278 | ||
279 | /* | |
280 | * Fix PIR to match the linear numbering in the device tree. | |
281 | * | |
282 | * On e6500, the reset value of PIR uses the low three bits for | |
283 | * the thread within a core, and the upper bits for the core | |
284 | * number. There are two threads per core, so shift everything | |
285 | * but the low bit right by two bits so that the cpu numbering is | |
286 | * continuous. | |
f34b3e19 SW |
287 | * |
288 | * If the old value of BUCSR is non-zero, this thread has run | |
289 | * before. Thus, we assume we are coming from kexec or a similar | |
290 | * scenario, and PIR is already set to the correct value. This | |
291 | * is a bit of a hack, but there are limited opportunities for | |
292 | * getting information into the thread and the alternatives | |
293 | * seemed like they'd be overkill. We can't tell just by looking | |
294 | * at the old PIR value which state it's in, since the same value | |
295 | * could be valid for one thread out of reset and for a different | |
296 | * thread in Linux. | |
e16c8765 | 297 | */ |
f34b3e19 | 298 | |
e16c8765 | 299 | mfspr r3, SPRN_PIR |
f34b3e19 SW |
300 | cmpwi r4,0 |
301 | bne 1f | |
e16c8765 AF |
302 | rlwimi r3, r3, 30, 2, 30 |
303 | mtspr SPRN_PIR, r3 | |
f34b3e19 | 304 | 1: |
e16c8765 AF |
305 | #endif |
306 | ||
2d27cfd3 BH |
307 | _GLOBAL(generic_secondary_thread_init) |
308 | mr r24,r3 | |
309 | ||
310 | /* turn on 64-bit mode */ | |
b1576fec | 311 | bl enable_64b_mode |
2d27cfd3 BH |
312 | |
313 | /* get a valid TOC pointer, wherever we're mapped at */ | |
b1576fec | 314 | bl relative_toc |
1fbe9cf2 | 315 | tovirt(r2,r2) |
2d27cfd3 BH |
316 | |
317 | #ifdef CONFIG_PPC_BOOK3E | |
318 | /* Book3E initialization */ | |
319 | mr r3,r24 | |
b1576fec | 320 | bl book3e_secondary_thread_init |
2d27cfd3 BH |
321 | #endif |
322 | b generic_secondary_common_init | |
14cf11af PM |
323 | |
324 | /* | |
f39b7a55 OJ |
325 | * On pSeries and most other platforms, secondary processors spin |
326 | * in the following code. | |
14cf11af | 327 | * At entry, r3 = this processor's number (physical cpu id) |
2d27cfd3 BH |
328 | * |
329 | * On Book3E, r4 = 1 to indicate that the initial TLB entry for | |
330 | * this core already exists (setup via some other mechanism such | |
331 | * as SCOM before entry). | |
14cf11af | 332 | */ |
f39b7a55 | 333 | _GLOBAL(generic_secondary_smp_init) |
5c0484e2 | 334 | FIXUP_ENDIAN |
14cf11af | 335 | mr r24,r3 |
2d27cfd3 BH |
336 | mr r25,r4 |
337 | ||
14cf11af | 338 | /* turn on 64-bit mode */ |
b1576fec | 339 | bl enable_64b_mode |
14cf11af | 340 | |
2d27cfd3 | 341 | /* get a valid TOC pointer, wherever we're mapped at */ |
b1576fec | 342 | bl relative_toc |
1fbe9cf2 | 343 | tovirt(r2,r2) |
e31aa453 | 344 | |
2d27cfd3 BH |
345 | #ifdef CONFIG_PPC_BOOK3E |
346 | /* Book3E initialization */ | |
347 | mr r3,r24 | |
348 | mr r4,r25 | |
b1576fec | 349 | bl book3e_secondary_core_init |
6becef7e | 350 | |
351 | /* | |
352 | * After common core init has finished, check if the current thread is the | |
353 | * one we wanted to boot. If not, start the specified thread and stop the | |
354 | * current thread. | |
355 | */ | |
356 | LOAD_REG_ADDR(r4, booting_thread_hwid) | |
357 | lwz r3, 0(r4) | |
358 | li r5, INVALID_THREAD_HWID | |
359 | cmpw r3, r5 | |
360 | beq 20f | |
361 | ||
362 | /* | |
363 | * The value of booting_thread_hwid has been stored in r3, | |
364 | * so make it invalid. | |
365 | */ | |
366 | stw r5, 0(r4) | |
367 | ||
368 | /* | |
369 | * Get the current thread id and check if it is the one we wanted. | |
370 | * If not, start the one specified in booting_thread_hwid and stop | |
371 | * the current thread. | |
372 | */ | |
373 | mfspr r8, SPRN_TIR | |
374 | cmpw r3, r8 | |
375 | beq 20f | |
376 | ||
377 | /* start the specified thread */ | |
378 | LOAD_REG_ADDR(r5, fsl_secondary_thread_init) | |
379 | ld r4, 0(r5) | |
380 | bl book3e_start_thread | |
381 | ||
382 | /* stop the current thread */ | |
383 | mr r3, r8 | |
384 | bl book3e_stop_thread | |
385 | 10: | |
386 | b 10b | |
387 | 20: | |
2d27cfd3 BH |
388 | #endif |
389 | ||
390 | generic_secondary_common_init: | |
14cf11af PM |
391 | /* Set up a paca value for this processor. Since we have the |
392 | * physical cpu id in r24, we need to search the pacas to find | |
393 | * which logical id maps to our physical one. | |
394 | */ | |
768d18ad | 395 | #ifndef CONFIG_SMP |
b1576fec | 396 | b kexec_wait /* wait for next kernel if !SMP */ |
768d18ad | 397 | #else |
d2e60075 NP |
398 | LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */ |
399 | ld r8,0(r8) /* Get base vaddr of array */ | |
768d18ad MM |
400 | LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */ |
401 | lwz r7,0(r7) /* also the max paca allocated */ | |
14cf11af | 402 | li r5,0 /* logical cpu id */ |
d2e60075 NP |
403 | 1: |
404 | sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */ | |
405 | ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */ | |
406 | lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */ | |
14cf11af PM |
407 | cmpw r6,r24 /* Compare to our id */ |
408 | beq 2f | |
14cf11af | 409 | addi r5,r5,1 |
768d18ad | 410 | cmpw r5,r7 /* Check if more pacas exist */ |
14cf11af PM |
411 | blt 1b |
412 | ||
413 | mr r3,r24 /* not found, copy phys to r3 */ | |
b1576fec | 414 | b kexec_wait /* next kernel might do better */ |
14cf11af | 415 | |
2dd60d79 | 416 | 2: SET_PACA(r13) |
2d27cfd3 BH |
417 | #ifdef CONFIG_PPC_BOOK3E |
418 | addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */ | |
419 | mtspr SPRN_SPRG_TLB_EXFRAME,r12 | |
420 | #endif | |
421 | ||
14cf11af PM |
422 | /* From now on, r24 is expected to be logical cpuid */ |
423 | mr r24,r5 | |
b6f6b98a | 424 | |
f39b7a55 | 425 | /* See if we need to call a cpu state restore handler */ |
e31aa453 | 426 | LOAD_REG_ADDR(r23, cur_cpu_spec) |
f39b7a55 | 427 | ld r23,0(r23) |
2751b628 AB |
428 | ld r12,CPU_SPEC_RESTORE(r23) |
429 | cmpdi 0,r12,0 | |
9d07bc84 | 430 | beq 3f |
f55d9665 | 431 | #ifdef PPC64_ELF_ABI_v1 |
2751b628 AB |
432 | ld r12,0(r12) |
433 | #endif | |
cc7efbf9 | 434 | mtctr r12 |
f39b7a55 OJ |
435 | bctrl |
436 | ||
7ac87abb | 437 | 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */ |
9d07bc84 BH |
438 | lwarx r4,0,r3 |
439 | subi r4,r4,1 | |
440 | stwcx. r4,0,r3 | |
441 | bne 3b | |
442 | isync | |
443 | ||
444 | 4: HMT_LOW | |
ad0693ee BH |
445 | lbz r23,PACAPROCSTART(r13) /* Test if this processor should */ |
446 | /* start. */ | |
ad0693ee | 447 | cmpwi 0,r23,0 |
9d07bc84 | 448 | beq 4b /* Loop until told to go */ |
ad0693ee BH |
449 | |
450 | sync /* order paca.run and cur_cpu_spec */ | |
9d07bc84 | 451 | isync /* In case code patching happened */ |
ad0693ee | 452 | |
9d07bc84 | 453 | /* Create a temp kernel stack for use before relocation is on. */ |
14cf11af PM |
454 | ld r1,PACAEMERGSP(r13) |
455 | subi r1,r1,STACK_FRAME_OVERHEAD | |
456 | ||
c705677e | 457 | b __secondary_start |
768d18ad | 458 | #endif /* SMP */ |
14cf11af | 459 | |
e31aa453 PM |
460 | /* |
461 | * Turn the MMU off. | |
462 | * Assumes we're mapped EA == RA if the MMU is on. | |
463 | */ | |
2d27cfd3 | 464 | #ifdef CONFIG_PPC_BOOK3S |
6a3bab90 | 465 | __mmu_off: |
14cf11af PM |
466 | mfmsr r3 |
467 | andi. r0,r3,MSR_IR|MSR_DR | |
468 | beqlr | |
e31aa453 | 469 | mflr r4 |
14cf11af PM |
470 | andc r3,r3,r0 |
471 | mtspr SPRN_SRR0,r4 | |
472 | mtspr SPRN_SRR1,r3 | |
473 | sync | |
474 | rfid | |
475 | b . /* prevent speculative execution */ | |
2d27cfd3 | 476 | #endif |
14cf11af PM |
477 | |
478 | ||
479 | /* | |
480 | * Here is our main kernel entry point. We support currently 2 kind of entries | |
481 | * depending on the value of r5. | |
482 | * | |
483 | * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content | |
484 | * in r3...r7 | |
485 | * | |
486 | * r5 == NULL -> kexec style entry. r3 is a physical pointer to the | |
487 | * DT block, r4 is a physical pointer to the kernel itself | |
488 | * | |
489 | */ | |
6a3bab90 | 490 | __start_initialization_multiplatform: |
e31aa453 | 491 | /* Make sure we are running in 64 bits mode */ |
b1576fec | 492 | bl enable_64b_mode |
e31aa453 PM |
493 | |
494 | /* Get TOC pointer (current runtime address) */ | |
b1576fec | 495 | bl relative_toc |
e31aa453 PM |
496 | |
497 | /* find out where we are now */ | |
498 | bcl 20,31,$+4 | |
499 | 0: mflr r26 /* r26 = runtime addr here */ | |
500 | addis r26,r26,(_stext - 0b)@ha | |
501 | addi r26,r26,(_stext - 0b)@l /* current runtime base addr */ | |
502 | ||
14cf11af PM |
503 | /* |
504 | * Are we booted from a PROM Of-type client-interface ? | |
505 | */ | |
506 | cmpldi cr0,r5,0 | |
939e60f6 | 507 | beq 1f |
b1576fec | 508 | b __boot_from_prom /* yes -> prom */ |
939e60f6 | 509 | 1: |
14cf11af PM |
510 | /* Save parameters */ |
511 | mr r31,r3 | |
512 | mr r30,r4 | |
daea1175 BH |
513 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
514 | /* Save OPAL entry */ | |
515 | mr r28,r8 | |
516 | mr r29,r9 | |
517 | #endif | |
14cf11af | 518 | |
2d27cfd3 | 519 | #ifdef CONFIG_PPC_BOOK3E |
b1576fec AB |
520 | bl start_initialization_book3e |
521 | b __after_prom_start | |
2d27cfd3 | 522 | #else |
14cf11af | 523 | /* Setup some critical 970 SPRs before switching MMU off */ |
f39b7a55 OJ |
524 | mfspr r0,SPRN_PVR |
525 | srwi r0,r0,16 | |
526 | cmpwi r0,0x39 /* 970 */ | |
527 | beq 1f | |
528 | cmpwi r0,0x3c /* 970FX */ | |
529 | beq 1f | |
530 | cmpwi r0,0x44 /* 970MP */ | |
190a24f5 OJ |
531 | beq 1f |
532 | cmpwi r0,0x45 /* 970GX */ | |
f39b7a55 | 533 | bne 2f |
b1576fec | 534 | 1: bl __cpu_preinit_ppc970 |
f39b7a55 | 535 | 2: |
14cf11af | 536 | |
e31aa453 | 537 | /* Switch off MMU if not already off */ |
b1576fec AB |
538 | bl __mmu_off |
539 | b __after_prom_start | |
2d27cfd3 | 540 | #endif /* CONFIG_PPC_BOOK3E */ |
14cf11af | 541 | |
6a3bab90 | 542 | __boot_from_prom: |
28794d34 | 543 | #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE |
14cf11af PM |
544 | /* Save parameters */ |
545 | mr r31,r3 | |
546 | mr r30,r4 | |
547 | mr r29,r5 | |
548 | mr r28,r6 | |
549 | mr r27,r7 | |
550 | ||
6088857b OH |
551 | /* |
552 | * Align the stack to 16-byte boundary | |
553 | * Depending on the size and layout of the ELF sections in the initial | |
e31aa453 | 554 | * boot binary, the stack pointer may be unaligned on PowerMac |
6088857b | 555 | */ |
c05b4770 LT |
556 | rldicr r1,r1,0,59 |
557 | ||
549e8152 PM |
558 | #ifdef CONFIG_RELOCATABLE |
559 | /* Relocate code for where we are now */ | |
560 | mr r3,r26 | |
b1576fec | 561 | bl relocate |
549e8152 PM |
562 | #endif |
563 | ||
14cf11af PM |
564 | /* Restore parameters */ |
565 | mr r3,r31 | |
566 | mr r4,r30 | |
567 | mr r5,r29 | |
568 | mr r6,r28 | |
569 | mr r7,r27 | |
570 | ||
571 | /* Do all of the interaction with OF client interface */ | |
549e8152 | 572 | mr r8,r26 |
b1576fec | 573 | bl prom_init |
28794d34 BH |
574 | #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */ |
575 | ||
576 | /* We never return. We also hit that trap if trying to boot | |
577 | * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */ | |
14cf11af PM |
578 | trap |
579 | ||
6a3bab90 | 580 | __after_prom_start: |
549e8152 PM |
581 | #ifdef CONFIG_RELOCATABLE |
582 | /* process relocations for the final address of the kernel */ | |
583 | lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */ | |
584 | sldi r25,r25,32 | |
1cb6e064 TC |
585 | #if defined(CONFIG_PPC_BOOK3E) |
586 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ | |
587 | #endif | |
57f26649 | 588 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) |
1cb6e064 TC |
589 | #if defined(CONFIG_PPC_BOOK3E) |
590 | tophys(r26,r26) | |
591 | #endif | |
928a3197 | 592 | cmplwi cr0,r7,1 /* flagged to stay where we are ? */ |
54622f10 MK |
593 | bne 1f |
594 | add r25,r25,r26 | |
54622f10 | 595 | 1: mr r3,r25 |
b1576fec | 596 | bl relocate |
1cb6e064 TC |
597 | #if defined(CONFIG_PPC_BOOK3E) |
598 | /* IVPR needs to be set after relocation. */ | |
599 | bl init_core_book3e | |
600 | #endif | |
549e8152 | 601 | #endif |
14cf11af PM |
602 | |
603 | /* | |
e31aa453 | 604 | * We need to run with _stext at physical address PHYSICAL_START. |
14cf11af PM |
605 | * This will leave some code in the first 256B of |
606 | * real memory, which are reserved for software use. | |
14cf11af PM |
607 | * |
608 | * Note: This process overwrites the OF exception vectors. | |
14cf11af | 609 | */ |
549e8152 | 610 | li r3,0 /* target addr */ |
2d27cfd3 | 611 | #ifdef CONFIG_PPC_BOOK3E |
835c031c | 612 | tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */ |
2d27cfd3 | 613 | #endif |
549e8152 | 614 | mr. r4,r26 /* In some cases the loader may */ |
835c031c TC |
615 | #if defined(CONFIG_PPC_BOOK3E) |
616 | tovirt(r4,r4) | |
617 | #endif | |
e31aa453 | 618 | beq 9f /* have already put us at zero */ |
14cf11af PM |
619 | li r6,0x100 /* Start offset, the first 0x100 */ |
620 | /* bytes were copied earlier. */ | |
621 | ||
11ee7e99 | 622 | #ifdef CONFIG_RELOCATABLE |
54622f10 MK |
623 | /* |
624 | * Check if the kernel has to be running as relocatable kernel based on the | |
8b8b0cc1 | 625 | * variable __run_at_load, if it is set the kernel is treated as relocatable |
54622f10 MK |
626 | * kernel, otherwise it will be moved to PHYSICAL_START |
627 | */ | |
1cb6e064 TC |
628 | #if defined(CONFIG_PPC_BOOK3E) |
629 | tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */ | |
630 | #endif | |
57f26649 | 631 | lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26) |
8b8b0cc1 | 632 | cmplwi cr0,r7,1 |
54622f10 MK |
633 | bne 3f |
634 | ||
1cb6e064 TC |
635 | #ifdef CONFIG_PPC_BOOK3E |
636 | LOAD_REG_ADDR(r5, __end_interrupts) | |
637 | LOAD_REG_ADDR(r11, _stext) | |
638 | sub r5,r5,r11 | |
639 | #else | |
c1fb6816 | 640 | /* just copy interrupts */ |
57f26649 | 641 | LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts)) |
1cb6e064 | 642 | #endif |
54622f10 MK |
643 | b 5f |
644 | 3: | |
645 | #endif | |
57f26649 NP |
646 | /* # bytes of memory to copy */ |
647 | lis r5,(ABS_ADDR(copy_to_here))@ha | |
648 | addi r5,r5,(ABS_ADDR(copy_to_here))@l | |
54622f10 | 649 | |
b1576fec | 650 | bl copy_and_flush /* copy the first n bytes */ |
14cf11af PM |
651 | /* this includes the code being */ |
652 | /* executed here. */ | |
57f26649 NP |
653 | /* Jump to the copy of this code that we just made */ |
654 | addis r8,r3,(ABS_ADDR(4f))@ha | |
655 | addi r12,r8,(ABS_ADDR(4f))@l | |
cc7efbf9 | 656 | mtctr r12 |
14cf11af PM |
657 | bctr |
658 | ||
286e4f90 | 659 | .balign 8 |
eb039161 | 660 | p_end: .8byte _end - copy_to_here |
54622f10 | 661 | |
573819e3 NP |
662 | 4: |
663 | /* | |
664 | * Now copy the rest of the kernel up to _end, add | |
665 | * _end - copy_to_here to the copy limit and run again. | |
666 | */ | |
57f26649 NP |
667 | addis r8,r26,(ABS_ADDR(p_end))@ha |
668 | ld r8,(ABS_ADDR(p_end))@l(r8) | |
573819e3 | 669 | add r5,r5,r8 |
b1576fec | 670 | 5: bl copy_and_flush /* copy the rest */ |
e31aa453 | 671 | |
b1576fec | 672 | 9: b start_here_multiplatform |
e31aa453 | 673 | |
14cf11af PM |
674 | /* |
675 | * Copy routine used to copy the kernel to start at physical address 0 | |
676 | * and flush and invalidate the caches as needed. | |
677 | * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset | |
678 | * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5. | |
679 | * | |
680 | * Note: this routine *only* clobbers r0, r6 and lr | |
681 | */ | |
682 | _GLOBAL(copy_and_flush) | |
683 | addi r5,r5,-8 | |
684 | addi r6,r6,-8 | |
5a2fe38d | 685 | 4: li r0,8 /* Use the smallest common */ |
14cf11af PM |
686 | /* denominator cache line */ |
687 | /* size. This results in */ | |
688 | /* extra cache line flushes */ | |
689 | /* but operation is correct. */ | |
690 | /* Can't get cache line size */ | |
691 | /* from NACA as it is being */ | |
692 | /* moved too. */ | |
693 | ||
694 | mtctr r0 /* put # words/line in ctr */ | |
695 | 3: addi r6,r6,8 /* copy a cache line */ | |
696 | ldx r0,r6,r4 | |
697 | stdx r0,r6,r3 | |
698 | bdnz 3b | |
699 | dcbst r6,r3 /* write it to memory */ | |
700 | sync | |
701 | icbi r6,r3 /* flush the icache line */ | |
702 | cmpld 0,r6,r5 | |
703 | blt 4b | |
704 | sync | |
705 | addi r5,r5,8 | |
706 | addi r6,r6,8 | |
29ce3c50 | 707 | isync |
14cf11af PM |
708 | blr |
709 | ||
710 | .align 8 | |
711 | copy_to_here: | |
712 | ||
713 | #ifdef CONFIG_SMP | |
714 | #ifdef CONFIG_PPC_PMAC | |
715 | /* | |
716 | * On PowerMac, secondary processors starts from the reset vector, which | |
717 | * is temporarily turned into a call to one of the functions below. | |
718 | */ | |
719 | .section ".text"; | |
720 | .align 2 ; | |
721 | ||
35499c01 PM |
722 | .globl __secondary_start_pmac_0 |
723 | __secondary_start_pmac_0: | |
724 | /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */ | |
725 | li r24,0 | |
726 | b 1f | |
727 | li r24,1 | |
728 | b 1f | |
729 | li r24,2 | |
730 | b 1f | |
731 | li r24,3 | |
732 | 1: | |
14cf11af PM |
733 | |
734 | _GLOBAL(pmac_secondary_start) | |
735 | /* turn on 64-bit mode */ | |
b1576fec | 736 | bl enable_64b_mode |
14cf11af | 737 | |
c478b581 BH |
738 | li r0,0 |
739 | mfspr r3,SPRN_HID4 | |
740 | rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */ | |
741 | sync | |
742 | mtspr SPRN_HID4,r3 | |
743 | isync | |
744 | sync | |
745 | slbia | |
746 | ||
e31aa453 | 747 | /* get TOC pointer (real address) */ |
b1576fec | 748 | bl relative_toc |
1fbe9cf2 | 749 | tovirt(r2,r2) |
e31aa453 | 750 | |
14cf11af | 751 | /* Copy some CPU settings from CPU 0 */ |
b1576fec | 752 | bl __restore_cpu_ppc970 |
14cf11af PM |
753 | |
754 | /* pSeries do that early though I don't think we really need it */ | |
755 | mfmsr r3 | |
756 | ori r3,r3,MSR_RI | |
757 | mtmsrd r3 /* RI on */ | |
758 | ||
759 | /* Set up a paca value for this processor. */ | |
d2e60075 NP |
760 | LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */ |
761 | ld r4,0(r4) /* Get base vaddr of paca_ptrs array */ | |
762 | sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */ | |
763 | ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */ | |
2dd60d79 | 764 | SET_PACA(r13) /* Save vaddr of paca in an SPRG*/ |
14cf11af | 765 | |
62cc67b9 BH |
766 | /* Mark interrupts soft and hard disabled (they might be enabled |
767 | * in the PACA when doing hotplug) | |
768 | */ | |
c2e480ba | 769 | li r0,IRQS_DISABLED |
4e26bc4a | 770 | stb r0,PACAIRQSOFTMASK(r13) |
7230c564 BH |
771 | li r0,PACA_IRQ_HARD_DIS |
772 | stb r0,PACAIRQHAPPENED(r13) | |
62cc67b9 | 773 | |
14cf11af PM |
774 | /* Create a temp kernel stack for use before relocation is on. */ |
775 | ld r1,PACAEMERGSP(r13) | |
776 | subi r1,r1,STACK_FRAME_OVERHEAD | |
777 | ||
c705677e | 778 | b __secondary_start |
14cf11af PM |
779 | |
780 | #endif /* CONFIG_PPC_PMAC */ | |
781 | ||
782 | /* | |
783 | * This function is called after the master CPU has released the | |
784 | * secondary processors. The execution environment is relocation off. | |
785 | * The paca for this processor has the following fields initialized at | |
786 | * this point: | |
787 | * 1. Processor number | |
788 | * 2. Segment table pointer (virtual address) | |
789 | * On entry the following are set: | |
4f8cf36f | 790 | * r1 = stack pointer (real addr of temp stack) |
ee43eb78 BH |
791 | * r24 = cpu# (in Linux terms) |
792 | * r13 = paca virtual address | |
793 | * SPRG_PACA = paca virtual address | |
14cf11af | 794 | */ |
2d27cfd3 BH |
795 | .section ".text"; |
796 | .align 2 ; | |
797 | ||
fc68e869 | 798 | .globl __secondary_start |
c705677e | 799 | __secondary_start: |
799d6046 PM |
800 | /* Set thread priority to MEDIUM */ |
801 | HMT_MEDIUM | |
14cf11af | 802 | |
4f8cf36f | 803 | /* Initialize the kernel stack */ |
e58c3495 | 804 | LOAD_REG_ADDR(r3, current_set) |
14cf11af | 805 | sldi r28,r24,3 /* get current_set[cpu#] */ |
54a83404 MN |
806 | ldx r14,r3,r28 |
807 | addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD | |
808 | std r14,PACAKSAVE(r13) | |
14cf11af | 809 | |
376af594 | 810 | /* Do early setup for that CPU (SLB and hash table pointer) */ |
b1576fec | 811 | bl early_setup_secondary |
f761622e | 812 | |
54a83404 MN |
813 | /* |
814 | * setup the new stack pointer, but *don't* use this until | |
815 | * translation is on. | |
816 | */ | |
817 | mr r1, r14 | |
818 | ||
799d6046 | 819 | /* Clear backchain so we get nice backtraces */ |
14cf11af PM |
820 | li r7,0 |
821 | mtlr r7 | |
822 | ||
7230c564 BH |
823 | /* Mark interrupts soft and hard disabled (they might be enabled |
824 | * in the PACA when doing hotplug) | |
825 | */ | |
c2e480ba | 826 | li r7,IRQS_DISABLED |
4e26bc4a | 827 | stb r7,PACAIRQSOFTMASK(r13) |
7230c564 BH |
828 | li r0,PACA_IRQ_HARD_DIS |
829 | stb r0,PACAIRQHAPPENED(r13) | |
4f8cf36f | 830 | |
14cf11af | 831 | /* enable MMU and jump to start_secondary */ |
ad0289e4 | 832 | LOAD_REG_ADDR(r3, start_secondary_prolog) |
e58c3495 | 833 | LOAD_REG_IMMEDIATE(r4, MSR_KERNEL) |
d04c56f7 | 834 | |
b5bbeb23 PM |
835 | mtspr SPRN_SRR0,r3 |
836 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 837 | RFI |
14cf11af PM |
838 | b . /* prevent speculative execution */ |
839 | ||
840 | /* | |
841 | * Running with relocation on at this point. All we want to do is | |
e31aa453 PM |
842 | * zero the stack back-chain pointer and get the TOC virtual address |
843 | * before going into C code. | |
14cf11af | 844 | */ |
ad0289e4 | 845 | start_secondary_prolog: |
e31aa453 | 846 | ld r2,PACATOC(r13) |
14cf11af PM |
847 | li r3,0 |
848 | std r3,0(r1) /* Zero the stack frame pointer */ | |
b1576fec | 849 | bl start_secondary |
799d6046 | 850 | b . |
8dbce53c VS |
851 | /* |
852 | * Reset stack pointer and call start_secondary | |
853 | * to continue with online operation when woken up | |
854 | * from cede in cpu offline. | |
855 | */ | |
856 | _GLOBAL(start_secondary_resume) | |
857 | ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */ | |
858 | li r3,0 | |
859 | std r3,0(r1) /* Zero the stack frame pointer */ | |
b1576fec | 860 | bl start_secondary |
8dbce53c | 861 | b . |
14cf11af PM |
862 | #endif |
863 | ||
864 | /* | |
865 | * This subroutine clobbers r11 and r12 | |
866 | */ | |
6a3bab90 | 867 | enable_64b_mode: |
14cf11af | 868 | mfmsr r11 /* grab the current MSR */ |
2d27cfd3 BH |
869 | #ifdef CONFIG_PPC_BOOK3E |
870 | oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ | |
871 | mtmsr r11 | |
872 | #else /* CONFIG_PPC_BOOK3E */ | |
9f0b0793 | 873 | li r12,(MSR_64BIT | MSR_ISF)@highest |
e31aa453 | 874 | sldi r12,r12,48 |
14cf11af PM |
875 | or r11,r11,r12 |
876 | mtmsrd r11 | |
877 | isync | |
2d27cfd3 | 878 | #endif |
14cf11af PM |
879 | blr |
880 | ||
e31aa453 PM |
881 | /* |
882 | * This puts the TOC pointer into r2, offset by 0x8000 (as expected | |
883 | * by the toolchain). It computes the correct value for wherever we | |
884 | * are running at the moment, using position-independent code. | |
1fbe9cf2 AB |
885 | * |
886 | * Note: The compiler constructs pointers using offsets from the | |
887 | * TOC in -mcmodel=medium mode. After we relocate to 0 but before | |
888 | * the MMU is on we need our TOC to be a virtual address otherwise | |
889 | * these pointers will be real addresses which may get stored and | |
890 | * accessed later with the MMU on. We use tovirt() at the call | |
891 | * sites to handle this. | |
e31aa453 PM |
892 | */ |
893 | _GLOBAL(relative_toc) | |
894 | mflr r0 | |
895 | bcl 20,31,$+4 | |
e550592e BH |
896 | 0: mflr r11 |
897 | ld r2,(p_toc - 0b)(r11) | |
898 | add r2,r2,r11 | |
e31aa453 PM |
899 | mtlr r0 |
900 | blr | |
901 | ||
5b63fee1 | 902 | .balign 8 |
eb039161 | 903 | p_toc: .8byte __toc_start + 0x8000 - 0b |
e31aa453 | 904 | |
14cf11af PM |
905 | /* |
906 | * This is where the main kernel code starts. | |
907 | */ | |
6a3bab90 | 908 | start_here_multiplatform: |
1fbe9cf2 | 909 | /* set up the TOC */ |
b1576fec | 910 | bl relative_toc |
1fbe9cf2 | 911 | tovirt(r2,r2) |
14cf11af PM |
912 | |
913 | /* Clear out the BSS. It may have been done in prom_init, | |
914 | * already but that's irrelevant since prom_init will soon | |
915 | * be detached from the kernel completely. Besides, we need | |
916 | * to clear it now for kexec-style entry. | |
917 | */ | |
e31aa453 PM |
918 | LOAD_REG_ADDR(r11,__bss_stop) |
919 | LOAD_REG_ADDR(r8,__bss_start) | |
14cf11af PM |
920 | sub r11,r11,r8 /* bss size */ |
921 | addi r11,r11,7 /* round up to an even double word */ | |
e31aa453 | 922 | srdi. r11,r11,3 /* shift right by 3 */ |
14cf11af PM |
923 | beq 4f |
924 | addi r8,r8,-8 | |
925 | li r0,0 | |
926 | mtctr r11 /* zero this many doublewords */ | |
927 | 3: stdu r0,8(r8) | |
928 | bdnz 3b | |
929 | 4: | |
930 | ||
daea1175 BH |
931 | #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL |
932 | /* Setup OPAL entry */ | |
ab7f961a | 933 | LOAD_REG_ADDR(r11, opal) |
daea1175 BH |
934 | std r28,0(r11); |
935 | std r29,8(r11); | |
936 | #endif | |
937 | ||
2d27cfd3 | 938 | #ifndef CONFIG_PPC_BOOK3E |
14cf11af PM |
939 | mfmsr r6 |
940 | ori r6,r6,MSR_RI | |
941 | mtmsrd r6 /* RI on */ | |
2d27cfd3 | 942 | #endif |
14cf11af | 943 | |
549e8152 PM |
944 | #ifdef CONFIG_RELOCATABLE |
945 | /* Save the physical address we're running at in kernstart_addr */ | |
946 | LOAD_REG_ADDR(r4, kernstart_addr) | |
947 | clrldi r0,r25,2 | |
948 | std r0,0(r4) | |
949 | #endif | |
950 | ||
e31aa453 | 951 | /* The following gets the stack set up with the regs */ |
14cf11af PM |
952 | /* pointing to the real addr of the kernel stack. This is */ |
953 | /* all done to support the C function call below which sets */ | |
954 | /* up the htab. This is done because we have relocated the */ | |
955 | /* kernel but are still running in real mode. */ | |
956 | ||
e31aa453 | 957 | LOAD_REG_ADDR(r3,init_thread_union) |
14cf11af | 958 | |
e31aa453 | 959 | /* set up a stack pointer */ |
cabed148 HM |
960 | LOAD_REG_IMMEDIATE(r1,THREAD_SIZE) |
961 | add r1,r3,r1 | |
14cf11af PM |
962 | li r0,0 |
963 | stdu r0,-STACK_FRAME_OVERHEAD(r1) | |
964 | ||
376af594 ME |
965 | /* |
966 | * Do very early kernel initializations, including initial hash table | |
967 | * and SLB setup before we turn on relocation. | |
968 | */ | |
14cf11af PM |
969 | |
970 | /* Restore parameters passed from prom_init/kexec */ | |
971 | mr r3,r31 | |
b1576fec | 972 | bl early_setup /* also sets r13 and SPRG_PACA */ |
14cf11af | 973 | |
ad0289e4 | 974 | LOAD_REG_ADDR(r3, start_here_common) |
e31aa453 | 975 | ld r4,PACAKMSR(r13) |
b5bbeb23 PM |
976 | mtspr SPRN_SRR0,r3 |
977 | mtspr SPRN_SRR1,r4 | |
2d27cfd3 | 978 | RFI |
14cf11af | 979 | b . /* prevent speculative execution */ |
fa745a12 | 980 | |
14cf11af | 981 | /* This is where all platforms converge execution */ |
ad0289e4 AB |
982 | |
983 | start_here_common: | |
14cf11af | 984 | /* relocation is on at this point */ |
e31aa453 | 985 | std r1,PACAKSAVE(r13) |
14cf11af | 986 | |
e31aa453 | 987 | /* Load the TOC (virtual address) */ |
14cf11af | 988 | ld r2,PACATOC(r13) |
14cf11af | 989 | |
7230c564 BH |
990 | /* Mark interrupts soft and hard disabled (they might be enabled |
991 | * in the PACA when doing hotplug) | |
992 | */ | |
c2e480ba | 993 | li r0,IRQS_DISABLED |
4e26bc4a | 994 | stb r0,PACAIRQSOFTMASK(r13) |
7230c564 BH |
995 | li r0,PACA_IRQ_HARD_DIS |
996 | stb r0,PACAIRQHAPPENED(r13) | |
14cf11af | 997 | |
7230c564 | 998 | /* Generic kernel entry */ |
b1576fec | 999 | bl start_kernel |
14cf11af | 1000 | |
f1870f77 AB |
1001 | /* Not reached */ |
1002 | BUG_OPCODE | |
14cf11af | 1003 | |
14cf11af PM |
1004 | /* |
1005 | * We put a few things here that have to be page-aligned. | |
1006 | * This stuff goes at the beginning of the bss, which is page-aligned. | |
1007 | */ | |
1008 | .section ".bss" | |
43a5c684 AK |
1009 | /* |
1010 | * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K. | |
1011 | * We will need to find a better way to fix this | |
1012 | */ | |
1013 | .align 16 | |
14cf11af | 1014 | |
43a5c684 AK |
1015 | .globl swapper_pg_dir |
1016 | swapper_pg_dir: | |
1017 | .space PGD_TABLE_SIZE | |
14cf11af PM |
1018 | |
1019 | .globl empty_zero_page | |
1020 | empty_zero_page: | |
1021 | .space PAGE_SIZE | |
9445aa1a | 1022 | EXPORT_SYMBOL(empty_zero_page) |