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[PATCH] powerpc: Cleanup LOADADDR etc. asm macros
[mirror_ubuntu-focal-kernel.git] / arch / powerpc / kernel / head_64.S
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14cf11af
PM		 1/*
2 * arch/ppc64/kernel/head.S
3 *
4 * PowerPC version
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 *
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
13 *
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 *
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
24 */
25
26#include <linux/config.h>
27#include <linux/threads.h>
b5bbeb23 28#include <asm/reg.h>
14cf11af
PM		 29#include <asm/page.h>
30#include <asm/mmu.h>
14cf11af
PM		 31#include <asm/ppc_asm.h>
32#include <asm/asm-offsets.h>
33#include <asm/bug.h>
34#include <asm/cputable.h>
35#include <asm/setup.h>
36#include <asm/hvcall.h>
c43a55ff 37#include <asm/iseries/lpar_map.h>
6cb7bfeb 38#include <asm/thread_info.h>
14cf11af
PM		 39
40#ifdef CONFIG_PPC_ISERIES
41#define DO_SOFT_DISABLE
42#endif
43
44/*
45 * We layout physical memory as follows:
46 * 0x0000 - 0x00ff : Secondary processor spin code
47 * 0x0100 - 0x2fff : pSeries Interrupt prologs
48 * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
49 * 0x6000 - 0x6fff : Initial (CPU0) segment table
50 * 0x7000 - 0x7fff : FWNMI data area
51 * 0x8000 - : Early init and support code
52 */
53
54/*
55 * SPRG Usage
56 *
57 * Register Definition
58 *
59 * SPRG0 reserved for hypervisor
60 * SPRG1 temp - used to save gpr
61 * SPRG2 temp - used to save gpr
62 * SPRG3 virt addr of paca
63 */
64
65/*
66 * Entering into this code we make the following assumptions:
67 * For pSeries:
68 * 1. The MMU is off & open firmware is running in real mode.
69 * 2. The kernel is entered at __start
70 *
71 * For iSeries:
72 * 1. The MMU is on (as it always is for iSeries)
73 * 2. The kernel is entered at system_reset_iSeries
74 */
75
76 .text
77 .globl _stext
78_stext:
79#ifdef CONFIG_PPC_MULTIPLATFORM
80_GLOBAL(__start)
81 /* NOP this out unconditionally */
82BEGIN_FTR_SECTION
b85a046a 83 b .__start_initialization_multiplatform
14cf11af
PM		 84END_FTR_SECTION(0, 1)
85#endif /* CONFIG_PPC_MULTIPLATFORM */
86
87 /* Catch branch to 0 in real mode */
88 trap
89
90#ifdef CONFIG_PPC_ISERIES
91 /*
92 * At offset 0x20, there is a pointer to iSeries LPAR data.
93 * This is required by the hypervisor
94 */
95 . = 0x20
96 .llong hvReleaseData-KERNELBASE
97
98 /*
99 * At offset 0x28 and 0x30 are offsets to the mschunks_map
100 * array (used by the iSeries LPAR debugger to do translation
101 * between physical addresses and absolute addresses) and
102 * to the pidhash table (also used by the debugger)
103 */
104 .llong mschunks_map-KERNELBASE
105 .llong 0 /* pidhash-KERNELBASE SFRXXX */
106
107 /* Offset 0x38 - Pointer to start of embedded System.map */
108 .globl embedded_sysmap_start
109embedded_sysmap_start:
110 .llong 0
111 /* Offset 0x40 - Pointer to end of embedded System.map */
112 .globl embedded_sysmap_end
113embedded_sysmap_end:
114 .llong 0
115
116#endif /* CONFIG_PPC_ISERIES */
117
118 /* Secondary processors spin on this value until it goes to 1. */
119 .globl __secondary_hold_spinloop
120__secondary_hold_spinloop:
121 .llong 0x0
122
123 /* Secondary processors write this value with their cpu # */
124 /* after they enter the spin loop immediately below. */
125 .globl __secondary_hold_acknowledge
126__secondary_hold_acknowledge:
127 .llong 0x0
128
129 . = 0x60
130/*
131 * The following code is used on pSeries to hold secondary processors
132 * in a spin loop after they have been freed from OpenFirmware, but
133 * before the bulk of the kernel has been relocated. This code
134 * is relocated to physical address 0x60 before prom_init is run.
135 * All of it must fit below the first exception vector at 0x100.
136 */
137_GLOBAL(__secondary_hold)
138 mfmsr r24
139 ori r24,r24,MSR_RI
140 mtmsrd r24 /* RI on */
141
142 /* Grab our linux cpu number */
143 mr r24,r3
144
145 /* Tell the master cpu we're here */
146 /* Relocation is off & we are located at an address less */
147 /* than 0x100, so only need to grab low order offset. */
148 std r24,__secondary_hold_acknowledge@l(0)
149 sync
150
151 /* All secondary cpus wait here until told to start. */
152100: ld r4,__secondary_hold_spinloop@l(0)
153 cmpdi 0,r4,1
154 bne 100b
155
156#ifdef CONFIG_HMT
e58c3495 157 SET_REG_IMMEDIATE(r4, .hmt_init)
758438a7
ME		 158 mtctr r4
159 bctr
14cf11af
PM		 160#else
161#ifdef CONFIG_SMP
e58c3495 162 LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
758438a7 163 mtctr r4
14cf11af 164 mr r3,r24
758438a7 165 bctr
14cf11af
PM		 166#else
167 BUG_OPCODE
168#endif
169#endif
170
171/* This value is used to mark exception frames on the stack. */
172 .section ".toc","aw"
173exception_marker:
174 .tc ID_72656773_68657265[TC],0x7265677368657265
175 .text
176
177/*
178 * The following macros define the code that appears as
179 * the prologue to each of the exception handlers. They
180 * are split into two parts to allow a single kernel binary
181 * to be used for pSeries and iSeries.
182 * LOL. One day... - paulus
183 */
184
185/*
186 * We make as much of the exception code common between native
187 * exception handlers (including pSeries LPAR) and iSeries LPAR
188 * implementations as possible.
189 */
190
191/*
192 * This is the start of the interrupt handlers for pSeries
193 * This code runs with relocation off.
194 */
195#define EX_R9 0
196#define EX_R10 8
197#define EX_R11 16
198#define EX_R12 24
199#define EX_R13 32
200#define EX_SRR0 40
14cf11af 201#define EX_DAR 48
14cf11af
PM		 202#define EX_DSISR 56
203#define EX_CCR 60
3c726f8d
BH		 204#define EX_R3 64
205#define EX_LR 72
14cf11af 206
758438a7 207/*
e58c3495
DG		 208 * We're short on space and time in the exception prolog, so we can't
209 * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
210 * low halfword of the address, but for Kdump we need the whole low
211 * word.
758438a7
ME		 212 */
213#ifdef CONFIG_CRASH_DUMP
214#define LOAD_HANDLER(reg, label) \
215 oris reg,reg,(label)@h; /* virt addr of handler ... */ \
216 ori reg,reg,(label)@l; /* .. and the rest */
217#else
218#define LOAD_HANDLER(reg, label) \
219 ori reg,reg,(label)@l; /* virt addr of handler ... */
220#endif
221
14cf11af 222#define EXCEPTION_PROLOG_PSERIES(area, label) \
b5bbeb23 223 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
14cf11af
PM		 224 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
225 std r10,area+EX_R10(r13); \
226 std r11,area+EX_R11(r13); \
227 std r12,area+EX_R12(r13); \
b5bbeb23 228 mfspr r9,SPRN_SPRG1; \
14cf11af
PM		 229 std r9,area+EX_R13(r13); \
230 mfcr r9; \
231 clrrdi r12,r13,32; /* get high part of &label */ \
232 mfmsr r10; \
b5bbeb23 233 mfspr r11,SPRN_SRR0; /* save SRR0 */ \
758438a7 234 LOAD_HANDLER(r12,label) \
14cf11af 235 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
b5bbeb23
PM		 236 mtspr SPRN_SRR0,r12; \
237 mfspr r12,SPRN_SRR1; /* and SRR1 */ \
238 mtspr SPRN_SRR1,r10; \
14cf11af
PM		 239 rfid; \
240 b . /* prevent speculative execution */
241
242/*
243 * This is the start of the interrupt handlers for iSeries
244 * This code runs with relocation on.
245 */
246#define EXCEPTION_PROLOG_ISERIES_1(area) \
b5bbeb23 247 mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \
14cf11af
PM		 248 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
249 std r10,area+EX_R10(r13); \
250 std r11,area+EX_R11(r13); \
251 std r12,area+EX_R12(r13); \
b5bbeb23 252 mfspr r9,SPRN_SPRG1; \
14cf11af
PM		 253 std r9,area+EX_R13(r13); \
254 mfcr r9
255
256#define EXCEPTION_PROLOG_ISERIES_2 \
257 mfmsr r10; \
258 ld r11,PACALPPACA+LPPACASRR0(r13); \
259 ld r12,PACALPPACA+LPPACASRR1(r13); \
260 ori r10,r10,MSR_RI; \
261 mtmsrd r10,1
262
263/*
264 * The common exception prolog is used for all except a few exceptions
265 * such as a segment miss on a kernel address. We have to be prepared
266 * to take another exception from the point where we first touch the
267 * kernel stack onwards.
268 *
269 * On entry r13 points to the paca, r9-r13 are saved in the paca,
270 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
271 * SRR1, and relocation is on.
272 */
273#define EXCEPTION_PROLOG_COMMON(n, area) \
274 andi. r10,r12,MSR_PR; /* See if coming from user */ \
275 mr r10,r1; /* Save r1 */ \
276 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
277 beq- 1f; \
278 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
2791: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
280 bge- cr1,bad_stack; /* abort if it is */ \
281 std r9,_CCR(r1); /* save CR in stackframe */ \
282 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
283 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
284 std r10,0(r1); /* make stack chain pointer */ \
285 std r0,GPR0(r1); /* save r0 in stackframe */ \
286 std r10,GPR1(r1); /* save r1 in stackframe */ \
287 std r2,GPR2(r1); /* save r2 in stackframe */ \
288 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
289 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
290 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
291 ld r10,area+EX_R10(r13); \
292 std r9,GPR9(r1); \
293 std r10,GPR10(r1); \
294 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
295 ld r10,area+EX_R12(r13); \
296 ld r11,area+EX_R13(r13); \
297 std r9,GPR11(r1); \
298 std r10,GPR12(r1); \
299 std r11,GPR13(r1); \
300 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
301 mflr r9; /* save LR in stackframe */ \
302 std r9,_LINK(r1); \
303 mfctr r10; /* save CTR in stackframe */ \
304 std r10,_CTR(r1); \
b5bbeb23 305 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
14cf11af
PM		 306 std r11,_XER(r1); \
307 li r9,(n)+1; \
308 std r9,_TRAP(r1); /* set trap number */ \
309 li r10,0; \
310 ld r11,exception_marker@toc(r2); \
311 std r10,RESULT(r1); /* clear regs->result */ \
312 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
313
314/*
315 * Exception vectors.
316 */
317#define STD_EXCEPTION_PSERIES(n, label) \
318 . = n; \
319 .globl label##_pSeries; \
320label##_pSeries: \
321 HMT_MEDIUM; \
b5bbeb23 322 mtspr SPRN_SPRG1,r13; /* save r13 */ \
14cf11af
PM		 323 RUNLATCH_ON(r13); \
324 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
325
326#define STD_EXCEPTION_ISERIES(n, label, area) \
327 .globl label##_iSeries; \
328label##_iSeries: \
329 HMT_MEDIUM; \
b5bbeb23 330 mtspr SPRN_SPRG1,r13; /* save r13 */ \
14cf11af
PM		 331 RUNLATCH_ON(r13); \
332 EXCEPTION_PROLOG_ISERIES_1(area); \
333 EXCEPTION_PROLOG_ISERIES_2; \
334 b label##_common
335
336#define MASKABLE_EXCEPTION_ISERIES(n, label) \
337 .globl label##_iSeries; \
338label##_iSeries: \
339 HMT_MEDIUM; \
b5bbeb23 340 mtspr SPRN_SPRG1,r13; /* save r13 */ \
14cf11af
PM		 341 RUNLATCH_ON(r13); \
342 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
343 lbz r10,PACAPROCENABLED(r13); \
344 cmpwi 0,r10,0; \
345 beq- label##_iSeries_masked; \
346 EXCEPTION_PROLOG_ISERIES_2; \
347 b label##_common; \
348
349#ifdef DO_SOFT_DISABLE
350#define DISABLE_INTS \
351 lbz r10,PACAPROCENABLED(r13); \
352 li r11,0; \
353 std r10,SOFTE(r1); \
354 mfmsr r10; \
355 stb r11,PACAPROCENABLED(r13); \
356 ori r10,r10,MSR_EE; \
357 mtmsrd r10,1
358
359#define ENABLE_INTS \
360 lbz r10,PACAPROCENABLED(r13); \
361 mfmsr r11; \
362 std r10,SOFTE(r1); \
363 ori r11,r11,MSR_EE; \
364 mtmsrd r11,1
365
366#else /* hard enable/disable interrupts */
367#define DISABLE_INTS
368
369#define ENABLE_INTS \
370 ld r12,_MSR(r1); \
371 mfmsr r11; \
372 rlwimi r11,r12,0,MSR_EE; \
373 mtmsrd r11,1
374
375#endif
376
377#define STD_EXCEPTION_COMMON(trap, label, hdlr) \
378 .align 7; \
379 .globl label##_common; \
380label##_common: \
381 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
382 DISABLE_INTS; \
383 bl .save_nvgprs; \
384 addi r3,r1,STACK_FRAME_OVERHEAD; \
385 bl hdlr; \
386 b .ret_from_except
387
388#define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
389 .align 7; \
390 .globl label##_common; \
391label##_common: \
392 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
393 DISABLE_INTS; \
394 addi r3,r1,STACK_FRAME_OVERHEAD; \
395 bl hdlr; \
396 b .ret_from_except_lite
397
398/*
399 * Start of pSeries system interrupt routines
400 */
401 . = 0x100
402 .globl __start_interrupts
403__start_interrupts:
404
405 STD_EXCEPTION_PSERIES(0x100, system_reset)
406
407 . = 0x200
408_machine_check_pSeries:
409 HMT_MEDIUM
b5bbeb23 410 mtspr SPRN_SPRG1,r13 /* save r13 */
14cf11af
PM		 411 RUNLATCH_ON(r13)
412 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
413
414 . = 0x300
415 .globl data_access_pSeries
416data_access_pSeries:
417 HMT_MEDIUM
b5bbeb23 418 mtspr SPRN_SPRG1,r13
14cf11af 419BEGIN_FTR_SECTION
b5bbeb23
PM		 420 mtspr SPRN_SPRG2,r12
421 mfspr r13,SPRN_DAR
422 mfspr r12,SPRN_DSISR
14cf11af
PM		 423 srdi r13,r13,60
424 rlwimi r13,r12,16,0x20
425 mfcr r12
426 cmpwi r13,0x2c
427 beq .do_stab_bolted_pSeries
428 mtcrf 0x80,r12
b5bbeb23 429 mfspr r12,SPRN_SPRG2
14cf11af
PM		 430END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
431 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
432
433 . = 0x380
434 .globl data_access_slb_pSeries
435data_access_slb_pSeries:
436 HMT_MEDIUM
b5bbeb23 437 mtspr SPRN_SPRG1,r13
14cf11af 438 RUNLATCH_ON(r13)
b5bbeb23 439 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
3c726f8d
BH		 440 std r3,PACA_EXSLB+EX_R3(r13)
441 mfspr r3,SPRN_DAR
14cf11af 442 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
3c726f8d
BH		 443 mfcr r9
444#ifdef __DISABLED__
445 /* Keep that around for when we re-implement dynamic VSIDs */
446 cmpdi r3,0
447 bge slb_miss_user_pseries
448#endif /* __DISABLED__ */
14cf11af
PM		 449 std r10,PACA_EXSLB+EX_R10(r13)
450 std r11,PACA_EXSLB+EX_R11(r13)
451 std r12,PACA_EXSLB+EX_R12(r13)
3c726f8d
BH		 452 mfspr r10,SPRN_SPRG1
453 std r10,PACA_EXSLB+EX_R13(r13)
b5bbeb23 454 mfspr r12,SPRN_SRR1 /* and SRR1 */
3c726f8d 455 b .slb_miss_realmode /* Rel. branch works in real mode */
14cf11af
PM		 456
457 STD_EXCEPTION_PSERIES(0x400, instruction_access)
458
459 . = 0x480
460 .globl instruction_access_slb_pSeries
461instruction_access_slb_pSeries:
462 HMT_MEDIUM
b5bbeb23 463 mtspr SPRN_SPRG1,r13
14cf11af 464 RUNLATCH_ON(r13)
b5bbeb23 465 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
3c726f8d
BH		 466 std r3,PACA_EXSLB+EX_R3(r13)
467 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
14cf11af 468 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
3c726f8d
BH		 469 mfcr r9
470#ifdef __DISABLED__
471 /* Keep that around for when we re-implement dynamic VSIDs */
472 cmpdi r3,0
473 bge slb_miss_user_pseries
474#endif /* __DISABLED__ */
14cf11af
PM		 475 std r10,PACA_EXSLB+EX_R10(r13)
476 std r11,PACA_EXSLB+EX_R11(r13)
477 std r12,PACA_EXSLB+EX_R12(r13)
3c726f8d
BH		 478 mfspr r10,SPRN_SPRG1
479 std r10,PACA_EXSLB+EX_R13(r13)
b5bbeb23 480 mfspr r12,SPRN_SRR1 /* and SRR1 */
3c726f8d 481 b .slb_miss_realmode /* Rel. branch works in real mode */
14cf11af
PM		 482
483 STD_EXCEPTION_PSERIES(0x500, hardware_interrupt)
484 STD_EXCEPTION_PSERIES(0x600, alignment)
485 STD_EXCEPTION_PSERIES(0x700, program_check)
486 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
487 STD_EXCEPTION_PSERIES(0x900, decrementer)
488 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
489 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
490
491 . = 0xc00
492 .globl system_call_pSeries
493system_call_pSeries:
494 HMT_MEDIUM
495 RUNLATCH_ON(r9)
496 mr r9,r13
497 mfmsr r10
b5bbeb23
PM		 498 mfspr r13,SPRN_SPRG3
499 mfspr r11,SPRN_SRR0
14cf11af
PM		 500 clrrdi r12,r13,32
501 oris r12,r12,system_call_common@h
502 ori r12,r12,system_call_common@l
b5bbeb23 503 mtspr SPRN_SRR0,r12
14cf11af 504 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
b5bbeb23
PM		 505 mfspr r12,SPRN_SRR1
506 mtspr SPRN_SRR1,r10
14cf11af
PM		 507 rfid
508 b . /* prevent speculative execution */
509
510 STD_EXCEPTION_PSERIES(0xd00, single_step)
511 STD_EXCEPTION_PSERIES(0xe00, trap_0e)
512
513 /* We need to deal with the Altivec unavailable exception
514 * here which is at 0xf20, thus in the middle of the
515 * prolog code of the PerformanceMonitor one. A little
516 * trickery is thus necessary
517 */
518 . = 0xf00
519 b performance_monitor_pSeries
520
521 STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
522
523 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
524 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
525
526 . = 0x3000
527
528/*** pSeries interrupt support ***/
529
530 /* moved from 0xf00 */
531 STD_EXCEPTION_PSERIES(., performance_monitor)
532
533 .align 7
534_GLOBAL(do_stab_bolted_pSeries)
535 mtcrf 0x80,r12
b5bbeb23 536 mfspr r12,SPRN_SPRG2
14cf11af
PM		 537 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
538
3c726f8d
BH		 539/*
540 * We have some room here we use that to put
541 * the peries slb miss user trampoline code so it's reasonably
542 * away from slb_miss_user_common to avoid problems with rfid
543 *
544 * This is used for when the SLB miss handler has to go virtual,
545 * which doesn't happen for now anymore but will once we re-implement
546 * dynamic VSIDs for shared page tables
547 */
548#ifdef __DISABLED__
549slb_miss_user_pseries:
550 std r10,PACA_EXGEN+EX_R10(r13)
551 std r11,PACA_EXGEN+EX_R11(r13)
552 std r12,PACA_EXGEN+EX_R12(r13)
553 mfspr r10,SPRG1
554 ld r11,PACA_EXSLB+EX_R9(r13)
555 ld r12,PACA_EXSLB+EX_R3(r13)
556 std r10,PACA_EXGEN+EX_R13(r13)
557 std r11,PACA_EXGEN+EX_R9(r13)
558 std r12,PACA_EXGEN+EX_R3(r13)
559 clrrdi r12,r13,32
560 mfmsr r10
561 mfspr r11,SRR0 /* save SRR0 */
562 ori r12,r12,slb_miss_user_common@l /* virt addr of handler */
563 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
564 mtspr SRR0,r12
565 mfspr r12,SRR1 /* and SRR1 */
566 mtspr SRR1,r10
567 rfid
568 b . /* prevent spec. execution */
569#endif /* __DISABLED__ */
570
14cf11af
PM		 571/*
572 * Vectors for the FWNMI option. Share common code.
573 */
b5bbeb23 574 .globl system_reset_fwnmi
8c4f1f29 575 .align 7
14cf11af 576system_reset_fwnmi:
b5bbeb23
PM		 577 HMT_MEDIUM
578 mtspr SPRN_SPRG1,r13 /* save r13 */
579 RUNLATCH_ON(r13)
580 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common)
14cf11af 581
b5bbeb23 582 .globl machine_check_fwnmi
8c4f1f29 583 .align 7
14cf11af 584machine_check_fwnmi:
b5bbeb23
PM		 585 HMT_MEDIUM
586 mtspr SPRN_SPRG1,r13 /* save r13 */
587 RUNLATCH_ON(r13)
588 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
14cf11af
PM		 589
590#ifdef CONFIG_PPC_ISERIES
591/*** ISeries-LPAR interrupt handlers ***/
592
593 STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
594
595 .globl data_access_iSeries
596data_access_iSeries:
b5bbeb23 597 mtspr SPRN_SPRG1,r13
14cf11af 598BEGIN_FTR_SECTION
b5bbeb23
PM		 599 mtspr SPRN_SPRG2,r12
600 mfspr r13,SPRN_DAR
601 mfspr r12,SPRN_DSISR
14cf11af
PM		 602 srdi r13,r13,60
603 rlwimi r13,r12,16,0x20
604 mfcr r12
605 cmpwi r13,0x2c
606 beq .do_stab_bolted_iSeries
607 mtcrf 0x80,r12
b5bbeb23 608 mfspr r12,SPRN_SPRG2
14cf11af
PM		 609END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
610 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
611 EXCEPTION_PROLOG_ISERIES_2
612 b data_access_common
613
614.do_stab_bolted_iSeries:
615 mtcrf 0x80,r12
b5bbeb23 616 mfspr r12,SPRN_SPRG2
14cf11af
PM		 617 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
618 EXCEPTION_PROLOG_ISERIES_2
619 b .do_stab_bolted
620
621 .globl data_access_slb_iSeries
622data_access_slb_iSeries:
b5bbeb23 623 mtspr SPRN_SPRG1,r13 /* save r13 */
3c726f8d 624 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
14cf11af 625 std r3,PACA_EXSLB+EX_R3(r13)
b5bbeb23 626 mfspr r3,SPRN_DAR
3c726f8d
BH		 627 std r9,PACA_EXSLB+EX_R9(r13)
628 mfcr r9
629#ifdef __DISABLED__
630 cmpdi r3,0
631 bge slb_miss_user_iseries
632#endif
633 std r10,PACA_EXSLB+EX_R10(r13)
634 std r11,PACA_EXSLB+EX_R11(r13)
635 std r12,PACA_EXSLB+EX_R12(r13)
636 mfspr r10,SPRN_SPRG1
637 std r10,PACA_EXSLB+EX_R13(r13)
638 ld r12,PACALPPACA+LPPACASRR1(r13);
639 b .slb_miss_realmode
14cf11af
PM		 640
641 STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
642
643 .globl instruction_access_slb_iSeries
644instruction_access_slb_iSeries:
b5bbeb23 645 mtspr SPRN_SPRG1,r13 /* save r13 */
3c726f8d 646 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
14cf11af 647 std r3,PACA_EXSLB+EX_R3(r13)
3c726f8d
BH		 648 ld r3,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
649 std r9,PACA_EXSLB+EX_R9(r13)
650 mfcr r9
651#ifdef __DISABLED__
652 cmpdi r3,0
653 bge .slb_miss_user_iseries
654#endif
655 std r10,PACA_EXSLB+EX_R10(r13)
656 std r11,PACA_EXSLB+EX_R11(r13)
657 std r12,PACA_EXSLB+EX_R12(r13)
658 mfspr r10,SPRN_SPRG1
659 std r10,PACA_EXSLB+EX_R13(r13)
660 ld r12,PACALPPACA+LPPACASRR1(r13);
661 b .slb_miss_realmode
662
663#ifdef __DISABLED__
664slb_miss_user_iseries:
665 std r10,PACA_EXGEN+EX_R10(r13)
666 std r11,PACA_EXGEN+EX_R11(r13)
667 std r12,PACA_EXGEN+EX_R12(r13)
668 mfspr r10,SPRG1
669 ld r11,PACA_EXSLB+EX_R9(r13)
670 ld r12,PACA_EXSLB+EX_R3(r13)
671 std r10,PACA_EXGEN+EX_R13(r13)
672 std r11,PACA_EXGEN+EX_R9(r13)
673 std r12,PACA_EXGEN+EX_R3(r13)
674 EXCEPTION_PROLOG_ISERIES_2
675 b slb_miss_user_common
676#endif
14cf11af
PM		 677
678 MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
679 STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
680 STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
681 STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
682 MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
683 STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
684 STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
685
686 .globl system_call_iSeries
687system_call_iSeries:
688 mr r9,r13
b5bbeb23 689 mfspr r13,SPRN_SPRG3
14cf11af
PM		 690 EXCEPTION_PROLOG_ISERIES_2
691 b system_call_common
692
693 STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
694 STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
695 STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
696
697 .globl system_reset_iSeries
698system_reset_iSeries:
b5bbeb23 699 mfspr r13,SPRN_SPRG3 /* Get paca address */
14cf11af
PM		 700 mfmsr r24
701 ori r24,r24,MSR_RI
702 mtmsrd r24 /* RI on */
703 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
704 cmpwi 0,r24,0 /* Are we processor 0? */
705 beq .__start_initialization_iSeries /* Start up the first processor */
706 mfspr r4,SPRN_CTRLF
707 li r5,CTRL_RUNLATCH /* Turn off the run light */
708 andc r4,r4,r5
709 mtspr SPRN_CTRLT,r4
710
7111:
712 HMT_LOW
713#ifdef CONFIG_SMP
714 lbz r23,PACAPROCSTART(r13) /* Test if this processor
715 * should start */
716 sync
e58c3495 717 LOAD_REG_IMMEDIATE(r3,current_set)
14cf11af
PM		 718 sldi r28,r24,3 /* get current_set[cpu#] */
719 ldx r3,r3,r28
720 addi r1,r3,THREAD_SIZE
721 subi r1,r1,STACK_FRAME_OVERHEAD
722
723 cmpwi 0,r23,0
724 beq iSeries_secondary_smp_loop /* Loop until told to go */
725 bne .__secondary_start /* Loop until told to go */
726iSeries_secondary_smp_loop:
727 /* Let the Hypervisor know we are alive */
728 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
729 lis r3,0x8002
730 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
731#else /* CONFIG_SMP */
732 /* Yield the processor. This is required for non-SMP kernels
733 which are running on multi-threaded machines. */
734 lis r3,0x8000
735 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
736 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
737 li r4,0 /* "yield timed" */
738 li r5,-1 /* "yield forever" */
739#endif /* CONFIG_SMP */
740 li r0,-1 /* r0=-1 indicates a Hypervisor call */
741 sc /* Invoke the hypervisor via a system call */
b5bbeb23 742 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
14cf11af
PM		 743 b 1b /* If SMP not configured, secondaries
744 * loop forever */
745
746 .globl decrementer_iSeries_masked
747decrementer_iSeries_masked:
748 li r11,1
749 stb r11,PACALPPACA+LPPACADECRINT(r13)
e58c3495
DG		 750 LOAD_REG_ADDRBASE(r12,tb_ticks_per_jiffy)
751 lwz r12,ADDROFF(tb_ticks_per_jiffy)(r12)
14cf11af
PM		 752 mtspr SPRN_DEC,r12
753 /* fall through */
754
755 .globl hardware_interrupt_iSeries_masked
756hardware_interrupt_iSeries_masked:
757 mtcrf 0x80,r9 /* Restore regs */
758 ld r11,PACALPPACA+LPPACASRR0(r13)
759 ld r12,PACALPPACA+LPPACASRR1(r13)
b5bbeb23
PM		 760 mtspr SPRN_SRR0,r11
761 mtspr SPRN_SRR1,r12
14cf11af
PM		 762 ld r9,PACA_EXGEN+EX_R9(r13)
763 ld r10,PACA_EXGEN+EX_R10(r13)
764 ld r11,PACA_EXGEN+EX_R11(r13)
765 ld r12,PACA_EXGEN+EX_R12(r13)
766 ld r13,PACA_EXGEN+EX_R13(r13)
767 rfid
768 b . /* prevent speculative execution */
769#endif /* CONFIG_PPC_ISERIES */
770
771/*** Common interrupt handlers ***/
772
773 STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
774
775 /*
776 * Machine check is different because we use a different
777 * save area: PACA_EXMC instead of PACA_EXGEN.
778 */
779 .align 7
780 .globl machine_check_common
781machine_check_common:
782 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
783 DISABLE_INTS
784 bl .save_nvgprs
785 addi r3,r1,STACK_FRAME_OVERHEAD
786 bl .machine_check_exception
787 b .ret_from_except
788
789 STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
790 STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
791 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
792 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
793 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
794 STD_EXCEPTION_COMMON(0xf00, performance_monitor, .performance_monitor_exception)
795 STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
796#ifdef CONFIG_ALTIVEC
797 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
798#else
799 STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
800#endif
801
802/*
803 * Here we have detected that the kernel stack pointer is bad.
804 * R9 contains the saved CR, r13 points to the paca,
805 * r10 contains the (bad) kernel stack pointer,
806 * r11 and r12 contain the saved SRR0 and SRR1.
807 * We switch to using an emergency stack, save the registers there,
808 * and call kernel_bad_stack(), which panics.
809 */
810bad_stack:
811 ld r1,PACAEMERGSP(r13)
812 subi r1,r1,64+INT_FRAME_SIZE
813 std r9,_CCR(r1)
814 std r10,GPR1(r1)
815 std r11,_NIP(r1)
816 std r12,_MSR(r1)
b5bbeb23
PM		 817 mfspr r11,SPRN_DAR
818 mfspr r12,SPRN_DSISR
14cf11af
PM		 819 std r11,_DAR(r1)
820 std r12,_DSISR(r1)
821 mflr r10
822 mfctr r11
823 mfxer r12
824 std r10,_LINK(r1)
825 std r11,_CTR(r1)
826 std r12,_XER(r1)
827 SAVE_GPR(0,r1)
828 SAVE_GPR(2,r1)
829 SAVE_4GPRS(3,r1)
830 SAVE_2GPRS(7,r1)
831 SAVE_10GPRS(12,r1)
832 SAVE_10GPRS(22,r1)
833 addi r11,r1,INT_FRAME_SIZE
834 std r11,0(r1)
835 li r12,0
836 std r12,0(r11)
837 ld r2,PACATOC(r13)
8381: addi r3,r1,STACK_FRAME_OVERHEAD
839 bl .kernel_bad_stack
840 b 1b
841
842/*
843 * Return from an exception with minimal checks.
844 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
845 * If interrupts have been enabled, or anything has been
846 * done that might have changed the scheduling status of
847 * any task or sent any task a signal, you should use
848 * ret_from_except or ret_from_except_lite instead of this.
849 */
40ef8cbc 850 .globl fast_exception_return
14cf11af
PM		 851fast_exception_return:
852 ld r12,_MSR(r1)
853 ld r11,_NIP(r1)
854 andi. r3,r12,MSR_RI /* check if RI is set */
855 beq- unrecov_fer
856 ld r3,_CCR(r1)
857 ld r4,_LINK(r1)
858 ld r5,_CTR(r1)
859 ld r6,_XER(r1)
860 mtcr r3
861 mtlr r4
862 mtctr r5
863 mtxer r6
864 REST_GPR(0, r1)
865 REST_8GPRS(2, r1)
866
867 mfmsr r10
868 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
869 mtmsrd r10,1
870
b5bbeb23
PM		 871 mtspr SPRN_SRR1,r12
872 mtspr SPRN_SRR0,r11
14cf11af
PM		 873 REST_4GPRS(10, r1)
874 ld r1,GPR1(r1)
875 rfid
876 b . /* prevent speculative execution */
877
878unrecov_fer:
879 bl .save_nvgprs
8801: addi r3,r1,STACK_FRAME_OVERHEAD
881 bl .unrecoverable_exception
882 b 1b
883
884/*
885 * Here r13 points to the paca, r9 contains the saved CR,
886 * SRR0 and SRR1 are saved in r11 and r12,
887 * r9 - r13 are saved in paca->exgen.
888 */
889 .align 7
890 .globl data_access_common
891data_access_common:
892 RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */
b5bbeb23 893 mfspr r10,SPRN_DAR
14cf11af 894 std r10,PACA_EXGEN+EX_DAR(r13)
b5bbeb23 895 mfspr r10,SPRN_DSISR
14cf11af
PM		 896 stw r10,PACA_EXGEN+EX_DSISR(r13)
897 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
898 ld r3,PACA_EXGEN+EX_DAR(r13)
899 lwz r4,PACA_EXGEN+EX_DSISR(r13)
900 li r5,0x300
901 b .do_hash_page /* Try to handle as hpte fault */
902
903 .align 7
904 .globl instruction_access_common
905instruction_access_common:
906 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
907 ld r3,_NIP(r1)
908 andis. r4,r12,0x5820
909 li r5,0x400
910 b .do_hash_page /* Try to handle as hpte fault */
911
3c726f8d
BH		 912/*
913 * Here is the common SLB miss user that is used when going to virtual
914 * mode for SLB misses, that is currently not used
915 */
916#ifdef __DISABLED__
917 .align 7
918 .globl slb_miss_user_common
919slb_miss_user_common:
920 mflr r10
921 std r3,PACA_EXGEN+EX_DAR(r13)
922 stw r9,PACA_EXGEN+EX_CCR(r13)
923 std r10,PACA_EXGEN+EX_LR(r13)
924 std r11,PACA_EXGEN+EX_SRR0(r13)
925 bl .slb_allocate_user
926
927 ld r10,PACA_EXGEN+EX_LR(r13)
928 ld r3,PACA_EXGEN+EX_R3(r13)
929 lwz r9,PACA_EXGEN+EX_CCR(r13)
930 ld r11,PACA_EXGEN+EX_SRR0(r13)
931 mtlr r10
932 beq- slb_miss_fault
933
934 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
935 beq- unrecov_user_slb
936 mfmsr r10
937
938.machine push
939.machine "power4"
940 mtcrf 0x80,r9
941.machine pop
942
943 clrrdi r10,r10,2 /* clear RI before setting SRR0/1 */
944 mtmsrd r10,1
945
946 mtspr SRR0,r11
947 mtspr SRR1,r12
948
949 ld r9,PACA_EXGEN+EX_R9(r13)
950 ld r10,PACA_EXGEN+EX_R10(r13)
951 ld r11,PACA_EXGEN+EX_R11(r13)
952 ld r12,PACA_EXGEN+EX_R12(r13)
953 ld r13,PACA_EXGEN+EX_R13(r13)
954 rfid
955 b .
956
957slb_miss_fault:
958 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
959 ld r4,PACA_EXGEN+EX_DAR(r13)
960 li r5,0
961 std r4,_DAR(r1)
962 std r5,_DSISR(r1)
963 b .handle_page_fault
964
965unrecov_user_slb:
966 EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
967 DISABLE_INTS
968 bl .save_nvgprs
9691: addi r3,r1,STACK_FRAME_OVERHEAD
970 bl .unrecoverable_exception
971 b 1b
972
973#endif /* __DISABLED__ */
974
975
976/*
977 * r13 points to the PACA, r9 contains the saved CR,
978 * r12 contain the saved SRR1, SRR0 is still ready for return
979 * r3 has the faulting address
980 * r9 - r13 are saved in paca->exslb.
981 * r3 is saved in paca->slb_r3
982 * We assume we aren't going to take any exceptions during this procedure.
983 */
984_GLOBAL(slb_miss_realmode)
985 mflr r10
986
987 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
988 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
989
990 bl .slb_allocate_realmode
991
992 /* All done -- return from exception. */
993
994 ld r10,PACA_EXSLB+EX_LR(r13)
995 ld r3,PACA_EXSLB+EX_R3(r13)
996 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
997#ifdef CONFIG_PPC_ISERIES
998 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
999#endif /* CONFIG_PPC_ISERIES */
1000
1001 mtlr r10
1002
1003 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1004 beq- unrecov_slb
1005
1006.machine push
1007.machine "power4"
1008 mtcrf 0x80,r9
1009 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1010.machine pop
1011
1012#ifdef CONFIG_PPC_ISERIES
1013 mtspr SPRN_SRR0,r11
1014 mtspr SPRN_SRR1,r12
1015#endif /* CONFIG_PPC_ISERIES */
1016 ld r9,PACA_EXSLB+EX_R9(r13)
1017 ld r10,PACA_EXSLB+EX_R10(r13)
1018 ld r11,PACA_EXSLB+EX_R11(r13)
1019 ld r12,PACA_EXSLB+EX_R12(r13)
1020 ld r13,PACA_EXSLB+EX_R13(r13)
1021 rfid
1022 b . /* prevent speculative execution */
1023
1024unrecov_slb:
1025 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1026 DISABLE_INTS
1027 bl .save_nvgprs
10281: addi r3,r1,STACK_FRAME_OVERHEAD
1029 bl .unrecoverable_exception
1030 b 1b
1031
14cf11af
PM		 1032 .align 7
1033 .globl hardware_interrupt_common
1034 .globl hardware_interrupt_entry
1035hardware_interrupt_common:
1036 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1037hardware_interrupt_entry:
1038 DISABLE_INTS
1039 addi r3,r1,STACK_FRAME_OVERHEAD
1040 bl .do_IRQ
1041 b .ret_from_except_lite
1042
1043 .align 7
1044 .globl alignment_common
1045alignment_common:
b5bbeb23 1046 mfspr r10,SPRN_DAR
14cf11af 1047 std r10,PACA_EXGEN+EX_DAR(r13)
b5bbeb23 1048 mfspr r10,SPRN_DSISR
14cf11af
PM		 1049 stw r10,PACA_EXGEN+EX_DSISR(r13)
1050 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1051 ld r3,PACA_EXGEN+EX_DAR(r13)
1052 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1053 std r3,_DAR(r1)
1054 std r4,_DSISR(r1)
1055 bl .save_nvgprs
1056 addi r3,r1,STACK_FRAME_OVERHEAD
1057 ENABLE_INTS
1058 bl .alignment_exception
1059 b .ret_from_except
1060
1061 .align 7
1062 .globl program_check_common
1063program_check_common:
1064 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1065 bl .save_nvgprs
1066 addi r3,r1,STACK_FRAME_OVERHEAD
1067 ENABLE_INTS
1068 bl .program_check_exception
1069 b .ret_from_except
1070
1071 .align 7
1072 .globl fp_unavailable_common
1073fp_unavailable_common:
1074 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1075 bne .load_up_fpu /* if from user, just load it up */
1076 bl .save_nvgprs
1077 addi r3,r1,STACK_FRAME_OVERHEAD
1078 ENABLE_INTS
1079 bl .kernel_fp_unavailable_exception
1080 BUG_OPCODE
1081
14cf11af
PM		 1082 .align 7
1083 .globl altivec_unavailable_common
1084altivec_unavailable_common:
1085 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1086#ifdef CONFIG_ALTIVEC
1087BEGIN_FTR_SECTION
1088 bne .load_up_altivec /* if from user, just load it up */
1089END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1090#endif
1091 bl .save_nvgprs
1092 addi r3,r1,STACK_FRAME_OVERHEAD
1093 ENABLE_INTS
1094 bl .altivec_unavailable_exception
1095 b .ret_from_except
1096
1097#ifdef CONFIG_ALTIVEC
1098/*
1099 * load_up_altivec(unused, unused, tsk)
1100 * Disable VMX for the task which had it previously,
1101 * and save its vector registers in its thread_struct.
1102 * Enables the VMX for use in the kernel on return.
1103 * On SMP we know the VMX is free, since we give it up every
1104 * switch (ie, no lazy save of the vector registers).
1105 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1106 */
1107_STATIC(load_up_altivec)
1108 mfmsr r5 /* grab the current MSR */
1109 oris r5,r5,MSR_VEC@h
1110 mtmsrd r5 /* enable use of VMX now */
1111 isync
1112
1113/*
1114 * For SMP, we don't do lazy VMX switching because it just gets too
1115 * horrendously complex, especially when a task switches from one CPU
1116 * to another. Instead we call giveup_altvec in switch_to.
1117 * VRSAVE isn't dealt with here, that is done in the normal context
1118 * switch code. Note that we could rely on vrsave value to eventually
1119 * avoid saving all of the VREGs here...
1120 */
1121#ifndef CONFIG_SMP
1122 ld r3,last_task_used_altivec@got(r2)
1123 ld r4,0(r3)
1124 cmpdi 0,r4,0
1125 beq 1f
1126 /* Save VMX state to last_task_used_altivec's THREAD struct */
1127 addi r4,r4,THREAD
1128 SAVE_32VRS(0,r5,r4)
1129 mfvscr vr0
1130 li r10,THREAD_VSCR
1131 stvx vr0,r10,r4
1132 /* Disable VMX for last_task_used_altivec */
1133 ld r5,PT_REGS(r4)
1134 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1135 lis r6,MSR_VEC@h
1136 andc r4,r4,r6
1137 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
11381:
1139#endif /* CONFIG_SMP */
1140 /* Hack: if we get an altivec unavailable trap with VRSAVE
1141 * set to all zeros, we assume this is a broken application
1142 * that fails to set it properly, and thus we switch it to
1143 * all 1's
1144 */
1145 mfspr r4,SPRN_VRSAVE
1146 cmpdi 0,r4,0
1147 bne+ 1f
1148 li r4,-1
1149 mtspr SPRN_VRSAVE,r4
11501:
1151 /* enable use of VMX after return */
1152 ld r4,PACACURRENT(r13)
1153 addi r5,r4,THREAD /* Get THREAD */
1154 oris r12,r12,MSR_VEC@h
1155 std r12,_MSR(r1)
1156 li r4,1
1157 li r10,THREAD_VSCR
1158 stw r4,THREAD_USED_VR(r5)
1159 lvx vr0,r10,r5
1160 mtvscr vr0
1161 REST_32VRS(0,r4,r5)
1162#ifndef CONFIG_SMP
1163 /* Update last_task_used_math to 'current' */
1164 subi r4,r5,THREAD /* Back to 'current' */
1165 std r4,0(r3)
1166#endif /* CONFIG_SMP */
1167 /* restore registers and return */
1168 b fast_exception_return
1169#endif /* CONFIG_ALTIVEC */
1170
1171/*
1172 * Hash table stuff
1173 */
1174 .align 7
1175_GLOBAL(do_hash_page)
1176 std r3,_DAR(r1)
1177 std r4,_DSISR(r1)
1178
1179 andis. r0,r4,0xa450 /* weird error? */
1180 bne- .handle_page_fault /* if not, try to insert a HPTE */
1181BEGIN_FTR_SECTION
1182 andis. r0,r4,0x0020 /* Is it a segment table fault? */
1183 bne- .do_ste_alloc /* If so handle it */
1184END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1185
1186 /*
1187 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1188 * accessing a userspace segment (even from the kernel). We assume
1189 * kernel addresses always have the high bit set.
1190 */
1191 rlwinm r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1192 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
1193 orc r0,r12,r0 /* MSR_PR | ~high_bit */
1194 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
1195 ori r4,r4,1 /* add _PAGE_PRESENT */
1196 rlwimi r4,r5,22+2,31-2,31-2 /* Set _PAGE_EXEC if trap is 0x400 */
1197
1198 /*
1199 * On iSeries, we soft-disable interrupts here, then
1200 * hard-enable interrupts so that the hash_page code can spin on
1201 * the hash_table_lock without problems on a shared processor.
1202 */
1203 DISABLE_INTS
1204
1205 /*
1206 * r3 contains the faulting address
1207 * r4 contains the required access permissions
1208 * r5 contains the trap number
1209 *
1210 * at return r3 = 0 for success
1211 */
1212 bl .hash_page /* build HPTE if possible */
1213 cmpdi r3,0 /* see if hash_page succeeded */
1214
1215#ifdef DO_SOFT_DISABLE
1216 /*
1217 * If we had interrupts soft-enabled at the point where the
1218 * DSI/ISI occurred, and an interrupt came in during hash_page,
1219 * handle it now.
1220 * We jump to ret_from_except_lite rather than fast_exception_return
1221 * because ret_from_except_lite will check for and handle pending
1222 * interrupts if necessary.
1223 */
1224 beq .ret_from_except_lite
1225 /* For a hash failure, we don't bother re-enabling interrupts */
1226 ble- 12f
1227
1228 /*
1229 * hash_page couldn't handle it, set soft interrupt enable back
1230 * to what it was before the trap. Note that .local_irq_restore
1231 * handles any interrupts pending at this point.
1232 */
1233 ld r3,SOFTE(r1)
1234 bl .local_irq_restore
1235 b 11f
1236#else
1237 beq fast_exception_return /* Return from exception on success */
1238 ble- 12f /* Failure return from hash_page */
1239
1240 /* fall through */
1241#endif
1242
1243/* Here we have a page fault that hash_page can't handle. */
1244_GLOBAL(handle_page_fault)
1245 ENABLE_INTS
124611: ld r4,_DAR(r1)
1247 ld r5,_DSISR(r1)
1248 addi r3,r1,STACK_FRAME_OVERHEAD
1249 bl .do_page_fault
1250 cmpdi r3,0
1251 beq+ .ret_from_except_lite
1252 bl .save_nvgprs
1253 mr r5,r3
1254 addi r3,r1,STACK_FRAME_OVERHEAD
1255 lwz r4,_DAR(r1)
1256 bl .bad_page_fault
1257 b .ret_from_except
1258
1259/* We have a page fault that hash_page could handle but HV refused
1260 * the PTE insertion
1261 */
126212: bl .save_nvgprs
1263 addi r3,r1,STACK_FRAME_OVERHEAD
1264 lwz r4,_DAR(r1)
1265 bl .low_hash_fault
1266 b .ret_from_except
1267
1268 /* here we have a segment miss */
1269_GLOBAL(do_ste_alloc)
1270 bl .ste_allocate /* try to insert stab entry */
1271 cmpdi r3,0
1272 beq+ fast_exception_return
1273 b .handle_page_fault
1274
1275/*
1276 * r13 points to the PACA, r9 contains the saved CR,
1277 * r11 and r12 contain the saved SRR0 and SRR1.
1278 * r9 - r13 are saved in paca->exslb.
1279 * We assume we aren't going to take any exceptions during this procedure.
1280 * We assume (DAR >> 60) == 0xc.
1281 */
1282 .align 7
1283_GLOBAL(do_stab_bolted)
1284 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1285 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1286
1287 /* Hash to the primary group */
1288 ld r10,PACASTABVIRT(r13)
b5bbeb23 1289 mfspr r11,SPRN_DAR
14cf11af
PM		 1290 srdi r11,r11,28
1291 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1292
1293 /* Calculate VSID */
1294 /* This is a kernel address, so protovsid = ESID */
1295 ASM_VSID_SCRAMBLE(r11, r9)
1296 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1297
1298 /* Search the primary group for a free entry */
12991: ld r11,0(r10) /* Test valid bit of the current ste */
1300 andi. r11,r11,0x80
1301 beq 2f
1302 addi r10,r10,16
1303 andi. r11,r10,0x70
1304 bne 1b
1305
1306 /* Stick for only searching the primary group for now. */
1307 /* At least for now, we use a very simple random castout scheme */
1308 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1309 mftb r11
1310 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1311 ori r11,r11,0x10
1312
1313 /* r10 currently points to an ste one past the group of interest */
1314 /* make it point to the randomly selected entry */
1315 subi r10,r10,128
1316 or r10,r10,r11 /* r10 is the entry to invalidate */
1317
1318 isync /* mark the entry invalid */
1319 ld r11,0(r10)
1320 rldicl r11,r11,56,1 /* clear the valid bit */
1321 rotldi r11,r11,8
1322 std r11,0(r10)
1323 sync
1324
1325 clrrdi r11,r11,28 /* Get the esid part of the ste */
1326 slbie r11
1327
13282: std r9,8(r10) /* Store the vsid part of the ste */
1329 eieio
1330
b5bbeb23 1331 mfspr r11,SPRN_DAR /* Get the new esid */
14cf11af
PM		 1332 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1333 ori r11,r11,0x90 /* Turn on valid and kp */
1334 std r11,0(r10) /* Put new entry back into the stab */
1335
1336 sync
1337
1338 /* All done -- return from exception. */
1339 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1340 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1341
1342 andi. r10,r12,MSR_RI
1343 beq- unrecov_slb
1344
1345 mtcrf 0x80,r9 /* restore CR */
1346
1347 mfmsr r10
1348 clrrdi r10,r10,2
1349 mtmsrd r10,1
1350
b5bbeb23
PM		 1351 mtspr SPRN_SRR0,r11
1352 mtspr SPRN_SRR1,r12
14cf11af
PM		 1353 ld r9,PACA_EXSLB+EX_R9(r13)
1354 ld r10,PACA_EXSLB+EX_R10(r13)
1355 ld r11,PACA_EXSLB+EX_R11(r13)
1356 ld r12,PACA_EXSLB+EX_R12(r13)
1357 ld r13,PACA_EXSLB+EX_R13(r13)
1358 rfid
1359 b . /* prevent speculative execution */
1360
14cf11af
PM		 1361/*
1362 * Space for CPU0's segment table.
1363 *
1364 * On iSeries, the hypervisor must fill in at least one entry before
1365 * we get control (with relocate on). The address is give to the hv
ee400b63 1366 * as a page number (see xLparMap in lpardata.c), so this must be at a
14cf11af
PM		 1367 * fixed address (the linker can't compute (u64)&initial_stab >>
1368 * PAGE_SHIFT).
1369 */
758438a7 1370 . = STAB0_OFFSET /* 0x6000 */
14cf11af
PM		 1371 .globl initial_stab
1372initial_stab:
1373 .space 4096
1374
1375/*
1376 * Data area reserved for FWNMI option.
1377 * This address (0x7000) is fixed by the RPA.
1378 */
1379 .= 0x7000
1380 .globl fwnmi_data_area
1381fwnmi_data_area:
1382
1383 /* iSeries does not use the FWNMI stuff, so it is safe to put
1384 * this here, even if we later allow kernels that will boot on
1385 * both pSeries and iSeries */
1386#ifdef CONFIG_PPC_ISERIES
1387 . = LPARMAP_PHYS
1388#include "lparmap.s"
1389/*
1390 * This ".text" is here for old compilers that generate a trailing
1391 * .note section when compiling .c files to .s
1392 */
1393 .text
1394#endif /* CONFIG_PPC_ISERIES */
1395
1396 . = 0x8000
1397
1398/*
1399 * On pSeries, secondary processors spin in the following code.
1400 * At entry, r3 = this processor's number (physical cpu id)
1401 */
1402_GLOBAL(pSeries_secondary_smp_init)
1403 mr r24,r3
1404
1405 /* turn on 64-bit mode */
1406 bl .enable_64b_mode
1407 isync
1408
1409 /* Copy some CPU settings from CPU 0 */
1410 bl .__restore_cpu_setup
1411
1412 /* Set up a paca value for this processor. Since we have the
1413 * physical cpu id in r24, we need to search the pacas to find
1414 * which logical id maps to our physical one.
1415 */
e58c3495 1416 LOAD_REG_IMMEDIATE(r13, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1417 li r5,0 /* logical cpu id */
14181: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
1419 cmpw r6,r24 /* Compare to our id */
1420 beq 2f
1421 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
1422 addi r5,r5,1
1423 cmpwi r5,NR_CPUS
1424 blt 1b
1425
1426 mr r3,r24 /* not found, copy phys to r3 */
1427 b .kexec_wait /* next kernel might do better */
1428
b5bbeb23 14292: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
14cf11af
PM		 1430 /* From now on, r24 is expected to be logical cpuid */
1431 mr r24,r5
14323: HMT_LOW
1433 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1434 /* start. */
1435 sync
1436
1437 /* Create a temp kernel stack for use before relocation is on. */
1438 ld r1,PACAEMERGSP(r13)
1439 subi r1,r1,STACK_FRAME_OVERHEAD
1440
1441 cmpwi 0,r23,0
1442#ifdef CONFIG_SMP
1443 bne .__secondary_start
1444#endif
1445 b 3b /* Loop until told to go */
1446
1447#ifdef CONFIG_PPC_ISERIES
1448_STATIC(__start_initialization_iSeries)
1449 /* Clear out the BSS */
e58c3495
DG		 1450 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1451 LOAD_REG_IMMEDIATE(r8,__bss_start)
14cf11af
PM		 1452 sub r11,r11,r8 /* bss size */
1453 addi r11,r11,7 /* round up to an even double word */
1454 rldicl. r11,r11,61,3 /* shift right by 3 */
1455 beq 4f
1456 addi r8,r8,-8
1457 li r0,0
1458 mtctr r11 /* zero this many doublewords */
14593: stdu r0,8(r8)
1460 bdnz 3b
14614:
e58c3495 1462 LOAD_REG_IMMEDIATE(r1,init_thread_union)
14cf11af
PM		 1463 addi r1,r1,THREAD_SIZE
1464 li r0,0
1465 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1466
e58c3495
DG		 1467 LOAD_REG_IMMEDIATE(r3,cpu_specs)
1468 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
14cf11af
PM		 1469 li r5,0
1470 bl .identify_cpu
1471
e58c3495 1472 LOAD_REG_IMMEDIATE(r2,__toc_start)
14cf11af
PM		 1473 addi r2,r2,0x4000
1474 addi r2,r2,0x4000
1475
1476 bl .iSeries_early_setup
ee400b63 1477 bl .early_setup
14cf11af
PM		 1478
1479 /* relocation is on at this point */
1480
1481 b .start_here_common
1482#endif /* CONFIG_PPC_ISERIES */
1483
1484#ifdef CONFIG_PPC_MULTIPLATFORM
1485
1486_STATIC(__mmu_off)
1487 mfmsr r3
1488 andi. r0,r3,MSR_IR|MSR_DR
1489 beqlr
1490 andc r3,r3,r0
1491 mtspr SPRN_SRR0,r4
1492 mtspr SPRN_SRR1,r3
1493 sync
1494 rfid
1495 b . /* prevent speculative execution */
1496
1497
1498/*
1499 * Here is our main kernel entry point. We support currently 2 kind of entries
1500 * depending on the value of r5.
1501 *
1502 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1503 * in r3...r7
1504 *
1505 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1506 * DT block, r4 is a physical pointer to the kernel itself
1507 *
1508 */
1509_GLOBAL(__start_initialization_multiplatform)
be42d5fa 1510#ifdef CONFIG_PPC_MULTIPLATFORM
14cf11af
PM		 1511 /*
1512 * Are we booted from a PROM Of-type client-interface ?
1513 */
1514 cmpldi cr0,r5,0
1515 bne .__boot_from_prom /* yes -> prom */
be42d5fa 1516#endif
14cf11af
PM		 1517
1518 /* Save parameters */
1519 mr r31,r3
1520 mr r30,r4
1521
1522 /* Make sure we are running in 64 bits mode */
1523 bl .enable_64b_mode
1524
1525 /* Setup some critical 970 SPRs before switching MMU off */
1526 bl .__970_cpu_preinit
1527
1528 /* cpu # */
1529 li r24,0
1530
1531 /* Switch off MMU if not already */
e58c3495 1532 LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
14cf11af
PM		 1533 add r4,r4,r30
1534 bl .__mmu_off
1535 b .__after_prom_start
1536
be42d5fa 1537#ifdef CONFIG_PPC_MULTIPLATFORM
14cf11af
PM		 1538_STATIC(__boot_from_prom)
1539 /* Save parameters */
1540 mr r31,r3
1541 mr r30,r4
1542 mr r29,r5
1543 mr r28,r6
1544 mr r27,r7
1545
1546 /* Make sure we are running in 64 bits mode */
1547 bl .enable_64b_mode
1548
1549 /* put a relocation offset into r3 */
1550 bl .reloc_offset
1551
e58c3495 1552 LOAD_REG_IMMEDIATE(r2,__toc_start)
14cf11af
PM		 1553 addi r2,r2,0x4000
1554 addi r2,r2,0x4000
1555
1556 /* Relocate the TOC from a virt addr to a real addr */
5a408329 1557 add r2,r2,r3
14cf11af
PM		 1558
1559 /* Restore parameters */
1560 mr r3,r31
1561 mr r4,r30
1562 mr r5,r29
1563 mr r6,r28
1564 mr r7,r27
1565
1566 /* Do all of the interaction with OF client interface */
1567 bl .prom_init
1568 /* We never return */
1569 trap
be42d5fa 1570#endif
14cf11af
PM		 1571
1572/*
1573 * At this point, r3 contains the physical address we are running at,
1574 * returned by prom_init()
1575 */
1576_STATIC(__after_prom_start)
1577
1578/*
758438a7 1579 * We need to run with __start at physical address PHYSICAL_START.
14cf11af
PM		 1580 * This will leave some code in the first 256B of
1581 * real memory, which are reserved for software use.
1582 * The remainder of the first page is loaded with the fixed
1583 * interrupt vectors. The next two pages are filled with
1584 * unknown exception placeholders.
1585 *
1586 * Note: This process overwrites the OF exception vectors.
1587 * r26 == relocation offset
1588 * r27 == KERNELBASE
1589 */
1590 bl .reloc_offset
1591 mr r26,r3
e58c3495 1592 LOAD_REG_IMMEDIATE(r27, KERNELBASE)
14cf11af 1593
e58c3495 1594 LOAD_REG_IMMEDIATE(r3, PHYSICAL_START) /* target addr */
14cf11af
PM		 1595
1596 // XXX FIXME: Use phys returned by OF (r30)
5a408329 1597 add r4,r27,r26 /* source addr */
14cf11af
PM		 1598 /* current address of _start */
1599 /* i.e. where we are running */
1600 /* the source addr */
1601
e58c3495 1602 LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
14cf11af
PM		 1603 sub r5,r5,r27
1604
1605 li r6,0x100 /* Start offset, the first 0x100 */
1606 /* bytes were copied earlier. */
1607
1608 bl .copy_and_flush /* copy the first n bytes */
1609 /* this includes the code being */
1610 /* executed here. */
1611
e58c3495 1612 LOAD_REG_IMMEDIATE(r0, 4f) /* Jump to the copy of this code */
14cf11af
PM		 1613 mtctr r0 /* that we just made/relocated */
1614 bctr
1615
e58c3495 16164: LOAD_REG_IMMEDIATE(r5,klimit)
5a408329 1617 add r5,r5,r26
14cf11af
PM		 1618 ld r5,0(r5) /* get the value of klimit */
1619 sub r5,r5,r27
1620 bl .copy_and_flush /* copy the rest */
1621 b .start_here_multiplatform
1622
1623#endif /* CONFIG_PPC_MULTIPLATFORM */
1624
1625/*
1626 * Copy routine used to copy the kernel to start at physical address 0
1627 * and flush and invalidate the caches as needed.
1628 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1629 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1630 *
1631 * Note: this routine *only* clobbers r0, r6 and lr
1632 */
1633_GLOBAL(copy_and_flush)
1634 addi r5,r5,-8
1635 addi r6,r6,-8
16364: li r0,16 /* Use the least common */
1637 /* denominator cache line */
1638 /* size. This results in */
1639 /* extra cache line flushes */
1640 /* but operation is correct. */
1641 /* Can't get cache line size */
1642 /* from NACA as it is being */
1643 /* moved too. */
1644
1645 mtctr r0 /* put # words/line in ctr */
16463: addi r6,r6,8 /* copy a cache line */
1647 ldx r0,r6,r4
1648 stdx r0,r6,r3
1649 bdnz 3b
1650 dcbst r6,r3 /* write it to memory */
1651 sync
1652 icbi r6,r3 /* flush the icache line */
1653 cmpld 0,r6,r5
1654 blt 4b
1655 sync
1656 addi r5,r5,8
1657 addi r6,r6,8
1658 blr
1659
1660.align 8
1661copy_to_here:
1662
1663#ifdef CONFIG_SMP
1664#ifdef CONFIG_PPC_PMAC
1665/*
1666 * On PowerMac, secondary processors starts from the reset vector, which
1667 * is temporarily turned into a call to one of the functions below.
1668 */
1669 .section ".text";
1670 .align 2 ;
1671
35499c01
PM		 1672 .globl __secondary_start_pmac_0
1673__secondary_start_pmac_0:
1674 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1675 li r24,0
1676 b 1f
1677 li r24,1
1678 b 1f
1679 li r24,2
1680 b 1f
1681 li r24,3
16821:
14cf11af
PM		 1683
1684_GLOBAL(pmac_secondary_start)
1685 /* turn on 64-bit mode */
1686 bl .enable_64b_mode
1687 isync
1688
1689 /* Copy some CPU settings from CPU 0 */
1690 bl .__restore_cpu_setup
1691
1692 /* pSeries do that early though I don't think we really need it */
1693 mfmsr r3
1694 ori r3,r3,MSR_RI
1695 mtmsrd r3 /* RI on */
1696
1697 /* Set up a paca value for this processor. */
e58c3495 1698 LOAD_REG_IMMEDIATE(r4, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1699 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1700 add r13,r13,r4 /* for this processor. */
b5bbeb23 1701 mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */
14cf11af
PM		 1702
1703 /* Create a temp kernel stack for use before relocation is on. */
1704 ld r1,PACAEMERGSP(r13)
1705 subi r1,r1,STACK_FRAME_OVERHEAD
1706
1707 b .__secondary_start
1708
1709#endif /* CONFIG_PPC_PMAC */
1710
1711/*
1712 * This function is called after the master CPU has released the
1713 * secondary processors. The execution environment is relocation off.
1714 * The paca for this processor has the following fields initialized at
1715 * this point:
1716 * 1. Processor number
1717 * 2. Segment table pointer (virtual address)
1718 * On entry the following are set:
1719 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1720 * r24 = cpu# (in Linux terms)
1721 * r13 = paca virtual address
1722 * SPRG3 = paca virtual address
1723 */
1724_GLOBAL(__secondary_start)
799d6046
PM		 1725 /* Set thread priority to MEDIUM */
1726 HMT_MEDIUM
14cf11af 1727
799d6046 1728 /* Load TOC */
14cf11af 1729 ld r2,PACATOC(r13)
799d6046
PM		 1730
1731 /* Do early setup for that CPU (stab, slb, hash table pointer) */
1732 bl .early_setup_secondary
14cf11af
PM		 1733
1734 /* Initialize the kernel stack. Just a repeat for iSeries. */
e58c3495 1735 LOAD_REG_ADDR(r3, current_set)
14cf11af
PM		 1736 sldi r28,r24,3 /* get current_set[cpu#] */
1737 ldx r1,r3,r28
1738 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1739 std r1,PACAKSAVE(r13)
1740
799d6046 1741 /* Clear backchain so we get nice backtraces */
14cf11af
PM		 1742 li r7,0
1743 mtlr r7
1744
1745 /* enable MMU and jump to start_secondary */
e58c3495
DG		 1746 LOAD_REG_ADDR(r3, .start_secondary_prolog)
1747 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
14cf11af
PM		 1748#ifdef DO_SOFT_DISABLE
1749 ori r4,r4,MSR_EE
1750#endif
b5bbeb23
PM		 1751 mtspr SPRN_SRR0,r3
1752 mtspr SPRN_SRR1,r4
14cf11af
PM		 1753 rfid
1754 b . /* prevent speculative execution */
1755
1756/*
1757 * Running with relocation on at this point. All we want to do is
1758 * zero the stack back-chain pointer before going into C code.
1759 */
1760_GLOBAL(start_secondary_prolog)
1761 li r3,0
1762 std r3,0(r1) /* Zero the stack frame pointer */
1763 bl .start_secondary
799d6046 1764 b .
14cf11af
PM		 1765#endif
1766
1767/*
1768 * This subroutine clobbers r11 and r12
1769 */
1770_GLOBAL(enable_64b_mode)
1771 mfmsr r11 /* grab the current MSR */
1772 li r12,1
1773 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1774 or r11,r11,r12
1775 li r12,1
1776 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1777 or r11,r11,r12
1778 mtmsrd r11
1779 isync
1780 blr
1781
1782#ifdef CONFIG_PPC_MULTIPLATFORM
1783/*
1784 * This is where the main kernel code starts.
1785 */
1786_STATIC(start_here_multiplatform)
1787 /* get a new offset, now that the kernel has moved. */
1788 bl .reloc_offset
1789 mr r26,r3
1790
1791 /* Clear out the BSS. It may have been done in prom_init,
1792 * already but that's irrelevant since prom_init will soon
1793 * be detached from the kernel completely. Besides, we need
1794 * to clear it now for kexec-style entry.
1795 */
e58c3495
DG		 1796 LOAD_REG_IMMEDIATE(r11,__bss_stop)
1797 LOAD_REG_IMMEDIATE(r8,__bss_start)
14cf11af
PM		 1798 sub r11,r11,r8 /* bss size */
1799 addi r11,r11,7 /* round up to an even double word */
1800 rldicl. r11,r11,61,3 /* shift right by 3 */
1801 beq 4f
1802 addi r8,r8,-8
1803 li r0,0
1804 mtctr r11 /* zero this many doublewords */
18053: stdu r0,8(r8)
1806 bdnz 3b
18074:
1808
1809 mfmsr r6
1810 ori r6,r6,MSR_RI
1811 mtmsrd r6 /* RI on */
1812
1813#ifdef CONFIG_HMT
1814 /* Start up the second thread on cpu 0 */
b5bbeb23 1815 mfspr r3,SPRN_PVR
14cf11af
PM		 1816 srwi r3,r3,16
1817 cmpwi r3,0x34 /* Pulsar */
1818 beq 90f
1819 cmpwi r3,0x36 /* Icestar */
1820 beq 90f
1821 cmpwi r3,0x37 /* SStar */
1822 beq 90f
1823 b 91f /* HMT not supported */
182490: li r3,0
1825 bl .hmt_start_secondary
182691:
1827#endif
1828
1829 /* The following gets the stack and TOC set up with the regs */
1830 /* pointing to the real addr of the kernel stack. This is */
1831 /* all done to support the C function call below which sets */
1832 /* up the htab. This is done because we have relocated the */
1833 /* kernel but are still running in real mode. */
1834
e58c3495 1835 LOAD_REG_IMMEDIATE(r3,init_thread_union)
5a408329 1836 add r3,r3,r26
14cf11af
PM		 1837
1838 /* set up a stack pointer (physical address) */
1839 addi r1,r3,THREAD_SIZE
1840 li r0,0
1841 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1842
1843 /* set up the TOC (physical address) */
e58c3495 1844 LOAD_REG_IMMEDIATE(r2,__toc_start)
14cf11af
PM		 1845 addi r2,r2,0x4000
1846 addi r2,r2,0x4000
5a408329 1847 add r2,r2,r26
14cf11af 1848
e58c3495 1849 LOAD_REG_IMMEDIATE(r3, cpu_specs)
5a408329 1850 add r3,r3,r26
e58c3495 1851 LOAD_REG_IMMEDIATE(r4,cur_cpu_spec)
5a408329 1852 add r4,r4,r26
14cf11af
PM		 1853 mr r5,r26
1854 bl .identify_cpu
1855
1856 /* Save some low level config HIDs of CPU0 to be copied to
1857 * other CPUs later on, or used for suspend/resume
1858 */
1859 bl .__save_cpu_setup
1860 sync
1861
1862 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1863 * note that boot_cpuid can always be 0 nowadays since there is
1864 * nowhere it can be initialized differently before we reach this
1865 * code
1866 */
e58c3495 1867 LOAD_REG_IMMEDIATE(r27, boot_cpuid)
5a408329 1868 add r27,r27,r26
14cf11af
PM		 1869 lwz r27,0(r27)
1870
e58c3495 1871 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1872 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1873 add r13,r13,r24 /* for this processor. */
5a408329 1874 add r13,r13,r26 /* convert to physical addr */
448b2719 1875 mtspr SPRN_SPRG3,r13
14cf11af
PM		 1876
1877 /* Do very early kernel initializations, including initial hash table,
1878 * stab and slb setup before we turn on relocation. */
1879
1880 /* Restore parameters passed from prom_init/kexec */
1881 mr r3,r31
1882 bl .early_setup
1883
e58c3495
DG		 1884 LOAD_REG_IMMEDIATE(r3, .start_here_common)
1885 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
b5bbeb23
PM		 1886 mtspr SPRN_SRR0,r3
1887 mtspr SPRN_SRR1,r4
14cf11af
PM		 1888 rfid
1889 b . /* prevent speculative execution */
1890#endif /* CONFIG_PPC_MULTIPLATFORM */
1891
1892 /* This is where all platforms converge execution */
1893_STATIC(start_here_common)
1894 /* relocation is on at this point */
1895
1896 /* The following code sets up the SP and TOC now that we are */
1897 /* running with translation enabled. */
1898
e58c3495 1899 LOAD_REG_IMMEDIATE(r3,init_thread_union)
14cf11af
PM		 1900
1901 /* set up the stack */
1902 addi r1,r3,THREAD_SIZE
1903 li r0,0
1904 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1905
1906 /* Apply the CPUs-specific fixups (nop out sections not relevant
1907 * to this CPU
1908 */
1909 li r3,0
1910 bl .do_cpu_ftr_fixups
1911
e58c3495 1912 LOAD_REG_IMMEDIATE(r26, boot_cpuid)
14cf11af
PM		 1913 lwz r26,0(r26)
1914
e58c3495 1915 LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
14cf11af
PM		 1916 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
1917 add r13,r13,r24 /* for this processor. */
b5bbeb23 1918 mtspr SPRN_SPRG3,r13
14cf11af
PM		 1919
1920 /* ptr to current */
e58c3495 1921 LOAD_REG_IMMEDIATE(r4, init_task)
14cf11af
PM		 1922 std r4,PACACURRENT(r13)
1923
1924 /* Load the TOC */
1925 ld r2,PACATOC(r13)
1926 std r1,PACAKSAVE(r13)
1927
1928 bl .setup_system
1929
1930 /* Load up the kernel context */
19315:
1932#ifdef DO_SOFT_DISABLE
1933 li r5,0
1934 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
1935 mfmsr r5
1936 ori r5,r5,MSR_EE /* Hard Enabled */
1937 mtmsrd r5
1938#endif
1939
1940 bl .start_kernel
1941
1942_GLOBAL(hmt_init)
1943#ifdef CONFIG_HMT
e58c3495 1944 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
b5bbeb23 1945 mfspr r7,SPRN_PVR
14cf11af
PM		 1946 srwi r7,r7,16
1947 cmpwi r7,0x34 /* Pulsar */
1948 beq 90f
1949 cmpwi r7,0x36 /* Icestar */
1950 beq 91f
1951 cmpwi r7,0x37 /* SStar */
1952 beq 91f
1953 b 101f
b5bbeb23 195490: mfspr r6,SPRN_PIR
14cf11af
PM		 1955 andi. r6,r6,0x1f
1956 b 92f
b5bbeb23 195791: mfspr r6,SPRN_PIR
14cf11af
PM		 1958 andi. r6,r6,0x3ff
195992: sldi r4,r24,3
1960 stwx r6,r5,r4
1961 bl .hmt_start_secondary
1962 b 101f
1963
1964__hmt_secondary_hold:
e58c3495 1965 LOAD_REG_IMMEDIATE(r5, hmt_thread_data)
14cf11af
PM		 1966 clrldi r5,r5,4
1967 li r7,0
b5bbeb23
PM		 1968 mfspr r6,SPRN_PIR
1969 mfspr r8,SPRN_PVR
14cf11af
PM		 1970 srwi r8,r8,16
1971 cmpwi r8,0x34
1972 bne 93f
1973 andi. r6,r6,0x1f
1974 b 103f
197593: andi. r6,r6,0x3f
1976
1977103: lwzx r8,r5,r7
1978 cmpw r8,r6
1979 beq 104f
1980 addi r7,r7,8
1981 b 103b
1982
1983104: addi r7,r7,4
1984 lwzx r9,r5,r7
1985 mr r24,r9
1986101:
1987#endif
1988 mr r3,r24
1989 b .pSeries_secondary_smp_init
1990
1991#ifdef CONFIG_HMT
1992_GLOBAL(hmt_start_secondary)
e58c3495 1993 LOAD_REG_IMMEDIATE(r4,__hmt_secondary_hold)
14cf11af 1994 clrldi r4,r4,4
b5bbeb23
PM		 1995 mtspr SPRN_NIADORM, r4
1996 mfspr r4, SPRN_MSRDORM
14cf11af
PM		 1997 li r5, -65
1998 and r4, r4, r5
b5bbeb23 1999 mtspr SPRN_MSRDORM, r4
14cf11af
PM		 2000 lis r4,0xffef
2001 ori r4,r4,0x7403
b5bbeb23 2002 mtspr SPRN_TSC, r4
14cf11af 2003 li r4,0x1f4
b5bbeb23
PM		 2004 mtspr SPRN_TST, r4
2005 mfspr r4, SPRN_HID0
14cf11af 2006 ori r4, r4, 0x1
b5bbeb23 2007 mtspr SPRN_HID0, r4
14cf11af
PM		 2008 mfspr r4, SPRN_CTRLF
2009 oris r4, r4, 0x40
2010 mtspr SPRN_CTRLT, r4
2011 blr
2012#endif
2013
14cf11af
PM		 2014/*
2015 * We put a few things here that have to be page-aligned.
2016 * This stuff goes at the beginning of the bss, which is page-aligned.
2017 */
2018 .section ".bss"
2019
2020 .align PAGE_SHIFT
2021
2022 .globl empty_zero_page
2023empty_zero_page:
2024 .space PAGE_SIZE
2025
2026 .globl swapper_pg_dir
2027swapper_pg_dir:
2028 .space PAGE_SIZE
2029
2030/*
2031 * This space gets a copy of optional info passed to us by the bootstrap
2032 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2033 */
2034 .globl cmd_line
2035cmd_line:
2036 .space COMMAND_LINE_SIZE
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