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1 | /* |
2 | * arch/ppc/kernel/except_8xx.S | |
3 | * | |
4 | * PowerPC version | |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
6 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
7 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
8 | * Low-level exception handlers and MMU support | |
9 | * rewritten by Paul Mackerras. | |
10 | * Copyright (C) 1996 Paul Mackerras. | |
11 | * MPC8xx modifications by Dan Malek | |
12 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
13 | * | |
14 | * This file contains low-level support and setup for PowerPC 8xx | |
15 | * embedded processors, including trap and interrupt dispatch. | |
16 | * | |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License | |
19 | * as published by the Free Software Foundation; either version | |
20 | * 2 of the License, or (at your option) any later version. | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/config.h> | |
25 | #include <asm/processor.h> | |
26 | #include <asm/page.h> | |
27 | #include <asm/mmu.h> | |
28 | #include <asm/cache.h> | |
29 | #include <asm/pgtable.h> | |
30 | #include <asm/cputable.h> | |
31 | #include <asm/thread_info.h> | |
32 | #include <asm/ppc_asm.h> | |
33 | #include <asm/asm-offsets.h> | |
34 | ||
35 | /* Macro to make the code more readable. */ | |
36 | #ifdef CONFIG_8xx_CPU6 | |
37 | #define DO_8xx_CPU6(val, reg) \ | |
38 | li reg, val; \ | |
39 | stw reg, 12(r0); \ | |
40 | lwz reg, 12(r0); | |
41 | #else | |
42 | #define DO_8xx_CPU6(val, reg) | |
43 | #endif | |
44 | .text | |
45 | .globl _stext | |
46 | _stext: | |
47 | .text | |
48 | .globl _start | |
49 | _start: | |
50 | ||
51 | /* MPC8xx | |
52 | * This port was done on an MBX board with an 860. Right now I only | |
53 | * support an ELF compressed (zImage) boot from EPPC-Bug because the | |
54 | * code there loads up some registers before calling us: | |
55 | * r3: ptr to board info data | |
56 | * r4: initrd_start or if no initrd then 0 | |
57 | * r5: initrd_end - unused if r4 is 0 | |
58 | * r6: Start of command line string | |
59 | * r7: End of command line string | |
60 | * | |
61 | * I decided to use conditional compilation instead of checking PVR and | |
62 | * adding more processor specific branches around code I don't need. | |
63 | * Since this is an embedded processor, I also appreciate any memory | |
64 | * savings I can get. | |
65 | * | |
66 | * The MPC8xx does not have any BATs, but it supports large page sizes. | |
67 | * We first initialize the MMU to support 8M byte pages, then load one | |
68 | * entry into each of the instruction and data TLBs to map the first | |
69 | * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to | |
70 | * the "internal" processor registers before MMU_init is called. | |
71 | * | |
72 | * The TLB code currently contains a major hack. Since I use the condition | |
73 | * code register, I have to save and restore it. I am out of registers, so | |
74 | * I just store it in memory location 0 (the TLB handlers are not reentrant). | |
75 | * To avoid making any decisions, I need to use the "segment" valid bit | |
76 | * in the first level table, but that would require many changes to the | |
77 | * Linux page directory/table functions that I don't want to do right now. | |
78 | * | |
79 | * I used to use SPRG2 for a temporary register in the TLB handler, but it | |
80 | * has since been put to other uses. I now use a hack to save a register | |
81 | * and the CCR at memory location 0.....Someday I'll fix this..... | |
82 | * -- Dan | |
83 | */ | |
84 | .globl __start | |
85 | __start: | |
86 | mr r31,r3 /* save parameters */ | |
87 | mr r30,r4 | |
88 | mr r29,r5 | |
89 | mr r28,r6 | |
90 | mr r27,r7 | |
91 | ||
92 | /* We have to turn on the MMU right away so we get cache modes | |
93 | * set correctly. | |
94 | */ | |
95 | bl initial_mmu | |
96 | ||
97 | /* We now have the lower 8 Meg mapped into TLB entries, and the caches | |
98 | * ready to work. | |
99 | */ | |
100 | ||
101 | turn_on_mmu: | |
102 | mfmsr r0 | |
103 | ori r0,r0,MSR_DR|MSR_IR | |
104 | mtspr SPRN_SRR1,r0 | |
105 | lis r0,start_here@h | |
106 | ori r0,r0,start_here@l | |
107 | mtspr SPRN_SRR0,r0 | |
108 | SYNC | |
109 | rfi /* enables MMU */ | |
110 | ||
111 | /* | |
112 | * Exception entry code. This code runs with address translation | |
113 | * turned off, i.e. using physical addresses. | |
114 | * We assume sprg3 has the physical address of the current | |
115 | * task's thread_struct. | |
116 | */ | |
117 | #define EXCEPTION_PROLOG \ | |
118 | mtspr SPRN_SPRG0,r10; \ | |
119 | mtspr SPRN_SPRG1,r11; \ | |
120 | mfcr r10; \ | |
121 | EXCEPTION_PROLOG_1; \ | |
122 | EXCEPTION_PROLOG_2 | |
123 | ||
124 | #define EXCEPTION_PROLOG_1 \ | |
125 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ | |
126 | andi. r11,r11,MSR_PR; \ | |
127 | tophys(r11,r1); /* use tophys(r1) if kernel */ \ | |
128 | beq 1f; \ | |
129 | mfspr r11,SPRN_SPRG3; \ | |
130 | lwz r11,THREAD_INFO-THREAD(r11); \ | |
131 | addi r11,r11,THREAD_SIZE; \ | |
132 | tophys(r11,r11); \ | |
133 | 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ | |
134 | ||
135 | ||
136 | #define EXCEPTION_PROLOG_2 \ | |
137 | CLR_TOP32(r11); \ | |
138 | stw r10,_CCR(r11); /* save registers */ \ | |
139 | stw r12,GPR12(r11); \ | |
140 | stw r9,GPR9(r11); \ | |
141 | mfspr r10,SPRN_SPRG0; \ | |
142 | stw r10,GPR10(r11); \ | |
143 | mfspr r12,SPRN_SPRG1; \ | |
144 | stw r12,GPR11(r11); \ | |
145 | mflr r10; \ | |
146 | stw r10,_LINK(r11); \ | |
147 | mfspr r12,SPRN_SRR0; \ | |
148 | mfspr r9,SPRN_SRR1; \ | |
149 | stw r1,GPR1(r11); \ | |
150 | stw r1,0(r11); \ | |
151 | tovirt(r1,r11); /* set new kernel sp */ \ | |
152 | li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ | |
153 | MTMSRD(r10); /* (except for mach check in rtas) */ \ | |
154 | stw r0,GPR0(r11); \ | |
155 | SAVE_4GPRS(3, r11); \ | |
156 | SAVE_2GPRS(7, r11) | |
157 | ||
158 | /* | |
159 | * Note: code which follows this uses cr0.eq (set if from kernel), | |
160 | * r11, r12 (SRR0), and r9 (SRR1). | |
161 | * | |
162 | * Note2: once we have set r1 we are in a position to take exceptions | |
163 | * again, and we could thus set MSR:RI at that point. | |
164 | */ | |
165 | ||
166 | /* | |
167 | * Exception vectors. | |
168 | */ | |
169 | #define EXCEPTION(n, label, hdlr, xfer) \ | |
170 | . = n; \ | |
171 | label: \ | |
172 | EXCEPTION_PROLOG; \ | |
173 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
174 | xfer(n, hdlr) | |
175 | ||
176 | #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ | |
177 | li r10,trap; \ | |
d73e0c99 | 178 | stw r10,_TRAP(r11); \ |
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179 | li r10,MSR_KERNEL; \ |
180 | copyee(r10, r9); \ | |
181 | bl tfer; \ | |
182 | i##n: \ | |
183 | .long hdlr; \ | |
184 | .long ret | |
185 | ||
186 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 | |
187 | #define NOCOPY(d, s) | |
188 | ||
189 | #define EXC_XFER_STD(n, hdlr) \ | |
190 | EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ | |
191 | ret_from_except_full) | |
192 | ||
193 | #define EXC_XFER_LITE(n, hdlr) \ | |
194 | EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ | |
195 | ret_from_except) | |
196 | ||
197 | #define EXC_XFER_EE(n, hdlr) \ | |
198 | EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ | |
199 | ret_from_except_full) | |
200 | ||
201 | #define EXC_XFER_EE_LITE(n, hdlr) \ | |
202 | EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ | |
203 | ret_from_except) | |
204 | ||
205 | /* System reset */ | |
dc1c1ca3 | 206 | EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) |
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207 | |
208 | /* Machine check */ | |
209 | . = 0x200 | |
210 | MachineCheck: | |
211 | EXCEPTION_PROLOG | |
212 | mfspr r4,SPRN_DAR | |
213 | stw r4,_DAR(r11) | |
214 | mfspr r5,SPRN_DSISR | |
215 | stw r5,_DSISR(r11) | |
216 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 217 | EXC_XFER_STD(0x200, machine_check_exception) |
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218 | |
219 | /* Data access exception. | |
220 | * This is "never generated" by the MPC8xx. We jump to it for other | |
221 | * translation errors. | |
222 | */ | |
223 | . = 0x300 | |
224 | DataAccess: | |
225 | EXCEPTION_PROLOG | |
226 | mfspr r10,SPRN_DSISR | |
227 | stw r10,_DSISR(r11) | |
228 | mr r5,r10 | |
229 | mfspr r4,SPRN_DAR | |
230 | EXC_XFER_EE_LITE(0x300, handle_page_fault) | |
231 | ||
232 | /* Instruction access exception. | |
233 | * This is "never generated" by the MPC8xx. We jump to it for other | |
234 | * translation errors. | |
235 | */ | |
236 | . = 0x400 | |
237 | InstructionAccess: | |
238 | EXCEPTION_PROLOG | |
239 | mr r4,r12 | |
240 | mr r5,r9 | |
241 | EXC_XFER_EE_LITE(0x400, handle_page_fault) | |
242 | ||
243 | /* External interrupt */ | |
244 | EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) | |
245 | ||
246 | /* Alignment exception */ | |
247 | . = 0x600 | |
248 | Alignment: | |
249 | EXCEPTION_PROLOG | |
250 | mfspr r4,SPRN_DAR | |
251 | stw r4,_DAR(r11) | |
252 | mfspr r5,SPRN_DSISR | |
253 | stw r5,_DSISR(r11) | |
254 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 255 | EXC_XFER_EE(0x600, alignment_exception) |
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256 | |
257 | /* Program check exception */ | |
dc1c1ca3 | 258 | EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) |
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259 | |
260 | /* No FPU on MPC8xx. This exception is not supposed to happen. | |
261 | */ | |
dc1c1ca3 | 262 | EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) |
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263 | |
264 | /* Decrementer */ | |
265 | EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) | |
266 | ||
dc1c1ca3 SR |
267 | EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) |
268 | EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) | |
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269 | |
270 | /* System call */ | |
271 | . = 0xc00 | |
272 | SystemCall: | |
273 | EXCEPTION_PROLOG | |
274 | EXC_XFER_EE_LITE(0xc00, DoSyscall) | |
275 | ||
276 | /* Single step - not used on 601 */ | |
dc1c1ca3 SR |
277 | EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) |
278 | EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) | |
279 | EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) | |
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280 | |
281 | /* On the MPC8xx, this is a software emulation interrupt. It occurs | |
282 | * for all unimplemented and illegal instructions. | |
283 | */ | |
284 | EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) | |
285 | ||
286 | . = 0x1100 | |
287 | /* | |
288 | * For the MPC8xx, this is a software tablewalk to load the instruction | |
289 | * TLB. It is modelled after the example in the Motorola manual. The task | |
290 | * switch loads the M_TWB register with the pointer to the first level table. | |
291 | * If we discover there is no second level table (value is zero) or if there | |
292 | * is an invalid pte, we load that into the TLB, which causes another fault | |
293 | * into the TLB Error interrupt where we can handle such problems. | |
294 | * We have to use the MD_xxx registers for the tablewalk because the | |
295 | * equivalent MI_xxx registers only perform the attribute functions. | |
296 | */ | |
297 | InstructionTLBMiss: | |
298 | #ifdef CONFIG_8xx_CPU6 | |
299 | stw r3, 8(r0) | |
300 | #endif | |
301 | DO_8xx_CPU6(0x3f80, r3) | |
302 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
303 | mfcr r10 | |
304 | stw r10, 0(r0) | |
305 | stw r11, 4(r0) | |
306 | mfspr r10, SPRN_SRR0 /* Get effective address of fault */ | |
307 | DO_8xx_CPU6(0x3780, r3) | |
308 | mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ | |
309 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
310 | ||
311 | /* If we are faulting a kernel address, we have to use the | |
312 | * kernel page tables. | |
313 | */ | |
314 | andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ | |
315 | beq 3f | |
316 | lis r11, swapper_pg_dir@h | |
317 | ori r11, r11, swapper_pg_dir@l | |
318 | rlwimi r10, r11, 0, 2, 19 | |
319 | 3: | |
320 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
321 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
322 | beq 2f /* If zero, don't try to find a pte */ | |
323 | ||
324 | /* We have a pte table, so load the MI_TWC with the attributes | |
325 | * for this "segment." | |
326 | */ | |
327 | ori r11,r11,1 /* Set valid bit */ | |
328 | DO_8xx_CPU6(0x2b80, r3) | |
329 | mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ | |
330 | DO_8xx_CPU6(0x3b80, r3) | |
331 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
332 | mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ | |
333 | lwz r10, 0(r11) /* Get the pte */ | |
334 | ||
335 | ori r10, r10, _PAGE_ACCESSED | |
336 | stw r10, 0(r11) | |
337 | ||
338 | /* The Linux PTE won't go exactly into the MMU TLB. | |
339 | * Software indicator bits 21, 22 and 28 must be clear. | |
340 | * Software indicator bits 24, 25, 26, and 27 must be | |
341 | * set. All other Linux PTE bits control the behavior | |
342 | * of the MMU. | |
343 | */ | |
344 | 2: li r11, 0x00f0 | |
345 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ | |
346 | DO_8xx_CPU6(0x2d80, r3) | |
347 | mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ | |
348 | ||
349 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
350 | lwz r11, 0(r0) | |
351 | mtcr r11 | |
352 | lwz r11, 4(r0) | |
353 | #ifdef CONFIG_8xx_CPU6 | |
354 | lwz r3, 8(r0) | |
355 | #endif | |
356 | rfi | |
357 | ||
358 | . = 0x1200 | |
359 | DataStoreTLBMiss: | |
360 | #ifdef CONFIG_8xx_CPU6 | |
361 | stw r3, 8(r0) | |
362 | #endif | |
363 | DO_8xx_CPU6(0x3f80, r3) | |
364 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
365 | mfcr r10 | |
366 | stw r10, 0(r0) | |
367 | stw r11, 4(r0) | |
368 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
369 | ||
370 | /* If we are faulting a kernel address, we have to use the | |
371 | * kernel page tables. | |
372 | */ | |
373 | andi. r11, r10, 0x0800 | |
374 | beq 3f | |
375 | lis r11, swapper_pg_dir@h | |
376 | ori r11, r11, swapper_pg_dir@l | |
377 | rlwimi r10, r11, 0, 2, 19 | |
378 | 3: | |
379 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
380 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
381 | beq 2f /* If zero, don't try to find a pte */ | |
382 | ||
383 | /* We have a pte table, so load fetch the pte from the table. | |
384 | */ | |
385 | ori r11, r11, 1 /* Set valid bit in physical L2 page */ | |
386 | DO_8xx_CPU6(0x3b80, r3) | |
387 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
388 | mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ | |
389 | lwz r10, 0(r10) /* Get the pte */ | |
390 | ||
391 | /* Insert the Guarded flag into the TWC from the Linux PTE. | |
392 | * It is bit 27 of both the Linux PTE and the TWC (at least | |
393 | * I got that right :-). It will be better when we can put | |
394 | * this into the Linux pgd/pmd and load it in the operation | |
395 | * above. | |
396 | */ | |
397 | rlwimi r11, r10, 0, 27, 27 | |
398 | DO_8xx_CPU6(0x3b80, r3) | |
399 | mtspr SPRN_MD_TWC, r11 | |
400 | ||
401 | mfspr r11, SPRN_MD_TWC /* get the pte address again */ | |
402 | ori r10, r10, _PAGE_ACCESSED | |
403 | stw r10, 0(r11) | |
404 | ||
405 | /* The Linux PTE won't go exactly into the MMU TLB. | |
406 | * Software indicator bits 21, 22 and 28 must be clear. | |
407 | * Software indicator bits 24, 25, 26, and 27 must be | |
408 | * set. All other Linux PTE bits control the behavior | |
409 | * of the MMU. | |
410 | */ | |
411 | 2: li r11, 0x00f0 | |
412 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ | |
413 | DO_8xx_CPU6(0x3d80, r3) | |
414 | mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ | |
415 | ||
416 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
417 | lwz r11, 0(r0) | |
418 | mtcr r11 | |
419 | lwz r11, 4(r0) | |
420 | #ifdef CONFIG_8xx_CPU6 | |
421 | lwz r3, 8(r0) | |
422 | #endif | |
423 | rfi | |
424 | ||
425 | /* This is an instruction TLB error on the MPC8xx. This could be due | |
426 | * to many reasons, such as executing guarded memory or illegal instruction | |
427 | * addresses. There is nothing to do but handle a big time error fault. | |
428 | */ | |
429 | . = 0x1300 | |
430 | InstructionTLBError: | |
431 | b InstructionAccess | |
432 | ||
433 | /* This is the data TLB error on the MPC8xx. This could be due to | |
434 | * many reasons, including a dirty update to a pte. We can catch that | |
435 | * one here, but anything else is an error. First, we track down the | |
436 | * Linux pte. If it is valid, write access is allowed, but the | |
437 | * page dirty bit is not set, we will set it and reload the TLB. For | |
438 | * any other case, we bail out to a higher level function that can | |
439 | * handle it. | |
440 | */ | |
441 | . = 0x1400 | |
442 | DataTLBError: | |
443 | #ifdef CONFIG_8xx_CPU6 | |
444 | stw r3, 8(r0) | |
445 | #endif | |
446 | DO_8xx_CPU6(0x3f80, r3) | |
447 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
448 | mfcr r10 | |
449 | stw r10, 0(r0) | |
450 | stw r11, 4(r0) | |
451 | ||
452 | /* First, make sure this was a store operation. | |
453 | */ | |
454 | mfspr r10, SPRN_DSISR | |
455 | andis. r11, r10, 0x0200 /* If set, indicates store op */ | |
456 | beq 2f | |
457 | ||
458 | /* The EA of a data TLB miss is automatically stored in the MD_EPN | |
459 | * register. The EA of a data TLB error is automatically stored in | |
460 | * the DAR, but not the MD_EPN register. We must copy the 20 most | |
461 | * significant bits of the EA from the DAR to MD_EPN before we | |
462 | * start walking the page tables. We also need to copy the CASID | |
463 | * value from the M_CASID register. | |
464 | * Addendum: The EA of a data TLB error is _supposed_ to be stored | |
465 | * in DAR, but it seems that this doesn't happen in some cases, such | |
466 | * as when the error is due to a dcbi instruction to a page with a | |
467 | * TLB that doesn't have the changed bit set. In such cases, there | |
468 | * does not appear to be any way to recover the EA of the error | |
469 | * since it is neither in DAR nor MD_EPN. As a workaround, the | |
470 | * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs | |
471 | * are initialized in mapin_ram(). This will avoid the problem, | |
472 | * assuming we only use the dcbi instruction on kernel addresses. | |
473 | */ | |
474 | mfspr r10, SPRN_DAR | |
475 | rlwinm r11, r10, 0, 0, 19 | |
476 | ori r11, r11, MD_EVALID | |
477 | mfspr r10, SPRN_M_CASID | |
478 | rlwimi r11, r10, 0, 28, 31 | |
479 | DO_8xx_CPU6(0x3780, r3) | |
480 | mtspr SPRN_MD_EPN, r11 | |
481 | ||
482 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
483 | ||
484 | /* If we are faulting a kernel address, we have to use the | |
485 | * kernel page tables. | |
486 | */ | |
487 | andi. r11, r10, 0x0800 | |
488 | beq 3f | |
489 | lis r11, swapper_pg_dir@h | |
490 | ori r11, r11, swapper_pg_dir@l | |
491 | rlwimi r10, r11, 0, 2, 19 | |
492 | 3: | |
493 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
494 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
495 | beq 2f /* If zero, bail */ | |
496 | ||
497 | /* We have a pte table, so fetch the pte from the table. | |
498 | */ | |
499 | ori r11, r11, 1 /* Set valid bit in physical L2 page */ | |
500 | DO_8xx_CPU6(0x3b80, r3) | |
501 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
502 | mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ | |
503 | lwz r10, 0(r11) /* Get the pte */ | |
504 | ||
505 | andi. r11, r10, _PAGE_RW /* Is it writeable? */ | |
506 | beq 2f /* Bail out if not */ | |
507 | ||
508 | /* Update 'changed', among others. | |
509 | */ | |
510 | ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE | |
511 | mfspr r11, SPRN_MD_TWC /* Get pte address again */ | |
512 | stw r10, 0(r11) /* and update pte in table */ | |
513 | ||
514 | /* The Linux PTE won't go exactly into the MMU TLB. | |
515 | * Software indicator bits 21, 22 and 28 must be clear. | |
516 | * Software indicator bits 24, 25, 26, and 27 must be | |
517 | * set. All other Linux PTE bits control the behavior | |
518 | * of the MMU. | |
519 | */ | |
520 | li r11, 0x00f0 | |
521 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ | |
522 | DO_8xx_CPU6(0x3d80, r3) | |
523 | mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ | |
524 | ||
525 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
526 | lwz r11, 0(r0) | |
527 | mtcr r11 | |
528 | lwz r11, 4(r0) | |
529 | #ifdef CONFIG_8xx_CPU6 | |
530 | lwz r3, 8(r0) | |
531 | #endif | |
532 | rfi | |
533 | 2: | |
534 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
535 | lwz r11, 0(r0) | |
536 | mtcr r11 | |
537 | lwz r11, 4(r0) | |
538 | #ifdef CONFIG_8xx_CPU6 | |
539 | lwz r3, 8(r0) | |
540 | #endif | |
541 | b DataAccess | |
542 | ||
dc1c1ca3 SR |
543 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
544 | EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) | |
545 | EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) | |
546 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) | |
547 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) | |
548 | EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) | |
549 | EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
550 | |
551 | /* On the MPC8xx, these next four traps are used for development | |
552 | * support of breakpoints and such. Someday I will get around to | |
553 | * using them. | |
554 | */ | |
dc1c1ca3 SR |
555 | EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) |
556 | EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) | |
557 | EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) | |
558 | EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
559 | |
560 | . = 0x2000 | |
561 | ||
562 | .globl giveup_fpu | |
563 | giveup_fpu: | |
564 | blr | |
565 | ||
566 | /* | |
567 | * This is where the main kernel code starts. | |
568 | */ | |
569 | start_here: | |
570 | /* ptr to current */ | |
571 | lis r2,init_task@h | |
572 | ori r2,r2,init_task@l | |
573 | ||
574 | /* ptr to phys current thread */ | |
575 | tophys(r4,r2) | |
576 | addi r4,r4,THREAD /* init task's THREAD */ | |
577 | mtspr SPRN_SPRG3,r4 | |
578 | li r3,0 | |
579 | mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ | |
580 | ||
581 | /* stack */ | |
582 | lis r1,init_thread_union@ha | |
583 | addi r1,r1,init_thread_union@l | |
584 | li r0,0 | |
585 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
586 | ||
587 | bl early_init /* We have to do this with MMU on */ | |
588 | ||
589 | /* | |
590 | * Decide what sort of machine this is and initialize the MMU. | |
591 | */ | |
592 | mr r3,r31 | |
593 | mr r4,r30 | |
594 | mr r5,r29 | |
595 | mr r6,r28 | |
596 | mr r7,r27 | |
597 | bl machine_init | |
598 | bl MMU_init | |
599 | ||
600 | /* | |
601 | * Go back to running unmapped so we can load up new values | |
602 | * and change to using our exception vectors. | |
603 | * On the 8xx, all we have to do is invalidate the TLB to clear | |
604 | * the old 8M byte TLB mappings and load the page table base register. | |
605 | */ | |
606 | /* The right way to do this would be to track it down through | |
607 | * init's THREAD like the context switch code does, but this is | |
608 | * easier......until someone changes init's static structures. | |
609 | */ | |
610 | lis r6, swapper_pg_dir@h | |
611 | ori r6, r6, swapper_pg_dir@l | |
612 | tophys(r6,r6) | |
613 | #ifdef CONFIG_8xx_CPU6 | |
614 | lis r4, cpu6_errata_word@h | |
615 | ori r4, r4, cpu6_errata_word@l | |
616 | li r3, 0x3980 | |
617 | stw r3, 12(r4) | |
618 | lwz r3, 12(r4) | |
619 | #endif | |
620 | mtspr SPRN_M_TWB, r6 | |
621 | lis r4,2f@h | |
622 | ori r4,r4,2f@l | |
623 | tophys(r4,r4) | |
624 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) | |
625 | mtspr SPRN_SRR0,r4 | |
626 | mtspr SPRN_SRR1,r3 | |
627 | rfi | |
628 | /* Load up the kernel context */ | |
629 | 2: | |
630 | SYNC /* Force all PTE updates to finish */ | |
631 | tlbia /* Clear all TLB entries */ | |
632 | sync /* wait for tlbia/tlbie to finish */ | |
633 | TLBSYNC /* ... on all CPUs */ | |
634 | ||
635 | /* set up the PTE pointers for the Abatron bdiGDB. | |
636 | */ | |
637 | tovirt(r6,r6) | |
638 | lis r5, abatron_pteptrs@h | |
639 | ori r5, r5, abatron_pteptrs@l | |
640 | stw r5, 0xf0(r0) /* Must match your Abatron config file */ | |
641 | tophys(r5,r5) | |
642 | stw r6, 0(r5) | |
643 | ||
644 | /* Now turn on the MMU for real! */ | |
645 | li r4,MSR_KERNEL | |
646 | lis r3,start_kernel@h | |
647 | ori r3,r3,start_kernel@l | |
648 | mtspr SPRN_SRR0,r3 | |
649 | mtspr SPRN_SRR1,r4 | |
650 | rfi /* enable MMU and jump to start_kernel */ | |
651 | ||
652 | /* Set up the initial MMU state so we can do the first level of | |
653 | * kernel initialization. This maps the first 8 MBytes of memory 1:1 | |
654 | * virtual to physical. Also, set the cache mode since that is defined | |
655 | * by TLB entries and perform any additional mapping (like of the IMMR). | |
656 | * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, | |
657 | * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by | |
658 | * these mappings is mapped by page tables. | |
659 | */ | |
660 | initial_mmu: | |
661 | tlbia /* Invalidate all TLB entries */ | |
662 | #ifdef CONFIG_PIN_TLB | |
663 | lis r8, MI_RSV4I@h | |
664 | ori r8, r8, 0x1c00 | |
665 | #else | |
666 | li r8, 0 | |
667 | #endif | |
668 | mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ | |
669 | ||
670 | #ifdef CONFIG_PIN_TLB | |
671 | lis r10, (MD_RSV4I | MD_RESETVAL)@h | |
672 | ori r10, r10, 0x1c00 | |
673 | mr r8, r10 | |
674 | #else | |
675 | lis r10, MD_RESETVAL@h | |
676 | #endif | |
677 | #ifndef CONFIG_8xx_COPYBACK | |
678 | oris r10, r10, MD_WTDEF@h | |
679 | #endif | |
680 | mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ | |
681 | ||
682 | /* Now map the lower 8 Meg into the TLBs. For this quick hack, | |
683 | * we can load the instruction and data TLB registers with the | |
684 | * same values. | |
685 | */ | |
686 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
687 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
688 | mtspr SPRN_MI_EPN, r8 | |
689 | mtspr SPRN_MD_EPN, r8 | |
690 | li r8, MI_PS8MEG /* Set 8M byte page */ | |
691 | ori r8, r8, MI_SVALID /* Make it valid */ | |
692 | mtspr SPRN_MI_TWC, r8 | |
693 | mtspr SPRN_MD_TWC, r8 | |
694 | li r8, MI_BOOTINIT /* Create RPN for address 0 */ | |
695 | mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ | |
696 | mtspr SPRN_MD_RPN, r8 | |
697 | lis r8, MI_Kp@h /* Set the protection mode */ | |
698 | mtspr SPRN_MI_AP, r8 | |
699 | mtspr SPRN_MD_AP, r8 | |
700 | ||
701 | /* Map another 8 MByte at the IMMR to get the processor | |
702 | * internal registers (among other things). | |
703 | */ | |
704 | #ifdef CONFIG_PIN_TLB | |
705 | addi r10, r10, 0x0100 | |
706 | mtspr SPRN_MD_CTR, r10 | |
707 | #endif | |
708 | mfspr r9, 638 /* Get current IMMR */ | |
709 | andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ | |
710 | ||
711 | mr r8, r9 /* Create vaddr for TLB */ | |
712 | ori r8, r8, MD_EVALID /* Mark it valid */ | |
713 | mtspr SPRN_MD_EPN, r8 | |
714 | li r8, MD_PS8MEG /* Set 8M byte page */ | |
715 | ori r8, r8, MD_SVALID /* Make it valid */ | |
716 | mtspr SPRN_MD_TWC, r8 | |
717 | mr r8, r9 /* Create paddr for TLB */ | |
718 | ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ | |
719 | mtspr SPRN_MD_RPN, r8 | |
720 | ||
721 | #ifdef CONFIG_PIN_TLB | |
722 | /* Map two more 8M kernel data pages. | |
723 | */ | |
724 | addi r10, r10, 0x0100 | |
725 | mtspr SPRN_MD_CTR, r10 | |
726 | ||
727 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
728 | addis r8, r8, 0x0080 /* Add 8M */ | |
729 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
730 | mtspr SPRN_MD_EPN, r8 | |
731 | li r9, MI_PS8MEG /* Set 8M byte page */ | |
732 | ori r9, r9, MI_SVALID /* Make it valid */ | |
733 | mtspr SPRN_MD_TWC, r9 | |
734 | li r11, MI_BOOTINIT /* Create RPN for address 0 */ | |
735 | addis r11, r11, 0x0080 /* Add 8M */ | |
736 | mtspr SPRN_MD_RPN, r8 | |
737 | ||
738 | addis r8, r8, 0x0080 /* Add 8M */ | |
739 | mtspr SPRN_MD_EPN, r8 | |
740 | mtspr SPRN_MD_TWC, r9 | |
741 | addis r11, r11, 0x0080 /* Add 8M */ | |
742 | mtspr SPRN_MD_RPN, r8 | |
743 | #endif | |
744 | ||
745 | /* Since the cache is enabled according to the information we | |
746 | * just loaded into the TLB, invalidate and enable the caches here. | |
747 | * We should probably check/set other modes....later. | |
748 | */ | |
749 | lis r8, IDC_INVALL@h | |
750 | mtspr SPRN_IC_CST, r8 | |
751 | mtspr SPRN_DC_CST, r8 | |
752 | lis r8, IDC_ENABLE@h | |
753 | mtspr SPRN_IC_CST, r8 | |
754 | #ifdef CONFIG_8xx_COPYBACK | |
755 | mtspr SPRN_DC_CST, r8 | |
756 | #else | |
757 | /* For a debug option, I left this here to easily enable | |
758 | * the write through cache mode | |
759 | */ | |
760 | lis r8, DC_SFWT@h | |
761 | mtspr SPRN_DC_CST, r8 | |
762 | lis r8, IDC_ENABLE@h | |
763 | mtspr SPRN_DC_CST, r8 | |
764 | #endif | |
765 | blr | |
766 | ||
767 | ||
768 | /* | |
769 | * Set up to use a given MMU context. | |
770 | * r3 is context number, r4 is PGD pointer. | |
771 | * | |
772 | * We place the physical address of the new task page directory loaded | |
773 | * into the MMU base register, and set the ASID compare register with | |
774 | * the new "context." | |
775 | */ | |
776 | _GLOBAL(set_context) | |
777 | ||
778 | #ifdef CONFIG_BDI_SWITCH | |
779 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
780 | * The PGDIR is passed as second argument. | |
781 | */ | |
782 | lis r5, KERNELBASE@h | |
783 | lwz r5, 0xf0(r5) | |
784 | stw r4, 0x4(r5) | |
785 | #endif | |
786 | ||
787 | #ifdef CONFIG_8xx_CPU6 | |
788 | lis r6, cpu6_errata_word@h | |
789 | ori r6, r6, cpu6_errata_word@l | |
790 | tophys (r4, r4) | |
791 | li r7, 0x3980 | |
792 | stw r7, 12(r6) | |
793 | lwz r7, 12(r6) | |
794 | mtspr SPRN_M_TWB, r4 /* Update MMU base address */ | |
795 | li r7, 0x3380 | |
796 | stw r7, 12(r6) | |
797 | lwz r7, 12(r6) | |
798 | mtspr SPRN_M_CASID, r3 /* Update context */ | |
799 | #else | |
800 | mtspr SPRN_M_CASID,r3 /* Update context */ | |
801 | tophys (r4, r4) | |
802 | mtspr SPRN_M_TWB, r4 /* and pgd */ | |
803 | #endif | |
804 | SYNC | |
805 | blr | |
806 | ||
807 | #ifdef CONFIG_8xx_CPU6 | |
808 | /* It's here because it is unique to the 8xx. | |
809 | * It is important we get called with interrupts disabled. I used to | |
810 | * do that, but it appears that all code that calls this already had | |
811 | * interrupt disabled. | |
812 | */ | |
813 | .globl set_dec_cpu6 | |
814 | set_dec_cpu6: | |
815 | lis r7, cpu6_errata_word@h | |
816 | ori r7, r7, cpu6_errata_word@l | |
817 | li r4, 0x2c00 | |
818 | stw r4, 8(r7) | |
819 | lwz r4, 8(r7) | |
820 | mtspr 22, r3 /* Update Decrementer */ | |
821 | SYNC | |
822 | blr | |
823 | #endif | |
824 | ||
825 | /* | |
826 | * We put a few things here that have to be page-aligned. | |
827 | * This stuff goes at the beginning of the data segment, | |
828 | * which is page-aligned. | |
829 | */ | |
830 | .data | |
831 | .globl sdata | |
832 | sdata: | |
833 | .globl empty_zero_page | |
834 | empty_zero_page: | |
835 | .space 4096 | |
836 | ||
837 | .globl swapper_pg_dir | |
838 | swapper_pg_dir: | |
839 | .space 4096 | |
840 | ||
841 | /* | |
842 | * This space gets a copy of optional info passed to us by the bootstrap | |
843 | * Used to pass parameters into the kernel like root=/dev/sda1, etc. | |
844 | */ | |
845 | .globl cmd_line | |
846 | cmd_line: | |
847 | .space 512 | |
848 | ||
849 | /* Room for two PTE table poiners, usually the kernel and current user | |
850 | * pointer to their respective root page table (pgdir). | |
851 | */ | |
852 | abatron_pteptrs: | |
853 | .space 8 | |
854 | ||
855 | #ifdef CONFIG_8xx_CPU6 | |
856 | .globl cpu6_errata_word | |
857 | cpu6_errata_word: | |
858 | .space 16 | |
859 | #endif | |
860 |