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powerpc/8xx: Optimize verification in FixupDAR
[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / kernel / head_8xx.S
CommitLineData
14cf11af 1/*
14cf11af
PM		 2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
21
e7039845 22#include <linux/init.h>
14cf11af
PM		 23#include <asm/processor.h>
24#include <asm/page.h>
25#include <asm/mmu.h>
26#include <asm/cache.h>
27#include <asm/pgtable.h>
28#include <asm/cputable.h>
29#include <asm/thread_info.h>
30#include <asm/ppc_asm.h>
31#include <asm/asm-offsets.h>
46f52210 32#include <asm/ptrace.h>
14cf11af
PM		 33
34/* Macro to make the code more readable. */
35#ifdef CONFIG_8xx_CPU6
36#define DO_8xx_CPU6(val, reg) \
37 li reg, val; \
38 stw reg, 12(r0); \
39 lwz reg, 12(r0);
40#else
41#define DO_8xx_CPU6(val, reg)
42#endif
e7039845 43 __HEAD
748a7683
KG		 44_ENTRY(_stext);
45_ENTRY(_start);
14cf11af
PM		 46
47/* MPC8xx
48 * This port was done on an MBX board with an 860. Right now I only
49 * support an ELF compressed (zImage) boot from EPPC-Bug because the
50 * code there loads up some registers before calling us:
51 * r3: ptr to board info data
52 * r4: initrd_start or if no initrd then 0
53 * r5: initrd_end - unused if r4 is 0
54 * r6: Start of command line string
55 * r7: End of command line string
56 *
57 * I decided to use conditional compilation instead of checking PVR and
58 * adding more processor specific branches around code I don't need.
59 * Since this is an embedded processor, I also appreciate any memory
60 * savings I can get.
61 *
62 * The MPC8xx does not have any BATs, but it supports large page sizes.
63 * We first initialize the MMU to support 8M byte pages, then load one
64 * entry into each of the instruction and data TLBs to map the first
65 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
66 * the "internal" processor registers before MMU_init is called.
67 *
68 * The TLB code currently contains a major hack. Since I use the condition
69 * code register, I have to save and restore it. I am out of registers, so
70 * I just store it in memory location 0 (the TLB handlers are not reentrant).
71 * To avoid making any decisions, I need to use the "segment" valid bit
72 * in the first level table, but that would require many changes to the
73 * Linux page directory/table functions that I don't want to do right now.
74 *
14cf11af
PM		 75 * -- Dan
76 */
77 .globl __start
78__start:
6dece0eb 79 mr r31,r3 /* save device tree ptr */
14cf11af
PM		 80
81 /* We have to turn on the MMU right away so we get cache modes
82 * set correctly.
83 */
84 bl initial_mmu
85
86/* We now have the lower 8 Meg mapped into TLB entries, and the caches
87 * ready to work.
88 */
89
90turn_on_mmu:
91 mfmsr r0
92 ori r0,r0,MSR_DR|MSR_IR
93 mtspr SPRN_SRR1,r0
94 lis r0,start_here@h
95 ori r0,r0,start_here@l
96 mtspr SPRN_SRR0,r0
97 SYNC
98 rfi /* enables MMU */
99
100/*
101 * Exception entry code. This code runs with address translation
102 * turned off, i.e. using physical addresses.
103 * We assume sprg3 has the physical address of the current
104 * task's thread_struct.
105 */
106#define EXCEPTION_PROLOG \
92625d49 107 EXCEPTION_PROLOG_0; \
14cf11af
PM		 108 EXCEPTION_PROLOG_1; \
109 EXCEPTION_PROLOG_2
110
92625d49
LC		 111#define EXCEPTION_PROLOG_0 \
112 mtspr SPRN_SPRG_SCRATCH0,r10; \
113 mtspr SPRN_SPRG_SCRATCH1,r11; \
114 mfcr r10
115
14cf11af
PM		 116#define EXCEPTION_PROLOG_1 \
117 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
118 andi. r11,r11,MSR_PR; \
119 tophys(r11,r1); /* use tophys(r1) if kernel */ \
120 beq 1f; \
ee43eb78 121 mfspr r11,SPRN_SPRG_THREAD; \
14cf11af
PM		 122 lwz r11,THREAD_INFO-THREAD(r11); \
123 addi r11,r11,THREAD_SIZE; \
124 tophys(r11,r11); \
1251: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
126
127
128#define EXCEPTION_PROLOG_2 \
129 CLR_TOP32(r11); \
130 stw r10,_CCR(r11); /* save registers */ \
131 stw r12,GPR12(r11); \
132 stw r9,GPR9(r11); \
ee43eb78 133 mfspr r10,SPRN_SPRG_SCRATCH0; \
14cf11af 134 stw r10,GPR10(r11); \
ee43eb78 135 mfspr r12,SPRN_SPRG_SCRATCH1; \
14cf11af
PM		 136 stw r12,GPR11(r11); \
137 mflr r10; \
138 stw r10,_LINK(r11); \
139 mfspr r12,SPRN_SRR0; \
140 mfspr r9,SPRN_SRR1; \
141 stw r1,GPR1(r11); \
142 stw r1,0(r11); \
143 tovirt(r1,r11); /* set new kernel sp */ \
144 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
145 MTMSRD(r10); /* (except for mach check in rtas) */ \
146 stw r0,GPR0(r11); \
147 SAVE_4GPRS(3, r11); \
148 SAVE_2GPRS(7, r11)
149
92625d49
LC		 150/*
151 * Exception exit code.
152 */
153#define EXCEPTION_EPILOG_0 \
154 mtcr r10; \
155 mfspr r10,SPRN_SPRG_SCRATCH0; \
156 mfspr r11,SPRN_SPRG_SCRATCH1
157
14cf11af
PM		 158/*
159 * Note: code which follows this uses cr0.eq (set if from kernel),
160 * r11, r12 (SRR0), and r9 (SRR1).
161 *
162 * Note2: once we have set r1 we are in a position to take exceptions
163 * again, and we could thus set MSR:RI at that point.
164 */
165
166/*
167 * Exception vectors.
168 */
169#define EXCEPTION(n, label, hdlr, xfer) \
170 . = n; \
171label: \
172 EXCEPTION_PROLOG; \
173 addi r3,r1,STACK_FRAME_OVERHEAD; \
174 xfer(n, hdlr)
175
176#define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
177 li r10,trap; \
d73e0c99 178 stw r10,_TRAP(r11); \
14cf11af
PM		 179 li r10,MSR_KERNEL; \
180 copyee(r10, r9); \
181 bl tfer; \
182i##n: \
183 .long hdlr; \
184 .long ret
185
186#define COPY_EE(d, s) rlwimi d,s,0,16,16
187#define NOCOPY(d, s)
188
189#define EXC_XFER_STD(n, hdlr) \
190 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
191 ret_from_except_full)
192
193#define EXC_XFER_LITE(n, hdlr) \
194 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
195 ret_from_except)
196
197#define EXC_XFER_EE(n, hdlr) \
198 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
199 ret_from_except_full)
200
201#define EXC_XFER_EE_LITE(n, hdlr) \
202 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
203 ret_from_except)
204
205/* System reset */
dc1c1ca3 206 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
14cf11af
PM		 207
208/* Machine check */
209 . = 0x200
210MachineCheck:
211 EXCEPTION_PROLOG
212 mfspr r4,SPRN_DAR
213 stw r4,_DAR(r11)
60e071fe
JT		 214 li r5,0x00f0
215 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
14cf11af
PM		 216 mfspr r5,SPRN_DSISR
217 stw r5,_DSISR(r11)
218 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 219 EXC_XFER_STD(0x200, machine_check_exception)
14cf11af
PM		 220
221/* Data access exception.
222 * This is "never generated" by the MPC8xx. We jump to it for other
223 * translation errors.
224 */
225 . = 0x300
226DataAccess:
227 EXCEPTION_PROLOG
228 mfspr r10,SPRN_DSISR
229 stw r10,_DSISR(r11)
230 mr r5,r10
231 mfspr r4,SPRN_DAR
60e071fe
JT		 232 li r10,0x00f0
233 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
a546498f 234 EXC_XFER_LITE(0x300, handle_page_fault)
14cf11af
PM		 235
236/* Instruction access exception.
237 * This is "never generated" by the MPC8xx. We jump to it for other
238 * translation errors.
239 */
240 . = 0x400
241InstructionAccess:
242 EXCEPTION_PROLOG
243 mr r4,r12
244 mr r5,r9
a546498f 245 EXC_XFER_LITE(0x400, handle_page_fault)
14cf11af
PM		 246
247/* External interrupt */
248 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
249
250/* Alignment exception */
251 . = 0x600
252Alignment:
253 EXCEPTION_PROLOG
254 mfspr r4,SPRN_DAR
255 stw r4,_DAR(r11)
60e071fe
JT		 256 li r5,0x00f0
257 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
14cf11af
PM		 258 mfspr r5,SPRN_DSISR
259 stw r5,_DSISR(r11)
260 addi r3,r1,STACK_FRAME_OVERHEAD
dc1c1ca3 261 EXC_XFER_EE(0x600, alignment_exception)
14cf11af
PM		 262
263/* Program check exception */
dc1c1ca3 264 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
14cf11af
PM		 265
266/* No FPU on MPC8xx. This exception is not supposed to happen.
267*/
dc1c1ca3 268 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
14cf11af
PM		 269
270/* Decrementer */
271 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
272
dc1c1ca3
SR		 273 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
274 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 275
276/* System call */
277 . = 0xc00
278SystemCall:
279 EXCEPTION_PROLOG
280 EXC_XFER_EE_LITE(0xc00, DoSyscall)
281
282/* Single step - not used on 601 */
dc1c1ca3
SR		 283 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
284 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
285 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 286
287/* On the MPC8xx, this is a software emulation interrupt. It occurs
288 * for all unimplemented and illegal instructions.
289 */
290 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
291
292 . = 0x1100
293/*
294 * For the MPC8xx, this is a software tablewalk to load the instruction
295 * TLB. It is modelled after the example in the Motorola manual. The task
296 * switch loads the M_TWB register with the pointer to the first level table.
297 * If we discover there is no second level table (value is zero) or if there
298 * is an invalid pte, we load that into the TLB, which causes another fault
299 * into the TLB Error interrupt where we can handle such problems.
300 * We have to use the MD_xxx registers for the tablewalk because the
301 * equivalent MI_xxx registers only perform the attribute functions.
302 */
303InstructionTLBMiss:
304#ifdef CONFIG_8xx_CPU6
305 stw r3, 8(r0)
306#endif
92625d49
LC		 307 EXCEPTION_PROLOG_0
308 mtspr SPRN_SPRG_SCRATCH2, r10
14cf11af 309 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
74016852
SW		 310#ifdef CONFIG_8xx_CPU15
311 addi r11, r10, 0x1000
312 tlbie r11
313 addi r11, r10, -0x1000
314 tlbie r11
315#endif
14cf11af
PM		 316 DO_8xx_CPU6(0x3780, r3)
317 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
318 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
319
320 /* If we are faulting a kernel address, we have to use the
321 * kernel page tables.
322 */
4afb0be7
JT		 323#ifdef CONFIG_MODULES
324 /* Only modules will cause ITLB Misses as we always
325 * pin the first 8MB of kernel memory */
14cf11af
PM		 326 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
327 beq 3f
328 lis r11, swapper_pg_dir@h
329 ori r11, r11, swapper_pg_dir@l
330 rlwimi r10, r11, 0, 2, 19
3313:
4afb0be7 332#endif
14cf11af
PM		 333 lwz r11, 0(r10) /* Get the level 1 entry */
334 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
335 beq 2f /* If zero, don't try to find a pte */
336
337 /* We have a pte table, so load the MI_TWC with the attributes
338 * for this "segment."
339 */
340 ori r11,r11,1 /* Set valid bit */
341 DO_8xx_CPU6(0x2b80, r3)
342 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
343 DO_8xx_CPU6(0x3b80, r3)
344 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
345 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
346 lwz r10, 0(r11) /* Get the pte */
347
d069cb43 348#ifdef CONFIG_SWAP
fe11dc3f
JT		 349 andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
350 cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
351 bne- cr0, 2f
d069cb43 352#endif
14cf11af 353 /* The Linux PTE won't go exactly into the MMU TLB.
fe1691e3 354 * Software indicator bits 21 and 28 must be clear.
14cf11af
PM		 355 * Software indicator bits 24, 25, 26, and 27 must be
356 * set. All other Linux PTE bits control the behavior
357 * of the MMU.
358 */
fe11dc3f 359 li r11, 0x00f0
fe1691e3 360 rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
14cf11af
PM		 361 DO_8xx_CPU6(0x2d80, r3)
362 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
363
469d62be 364 /* Restore registers */
92625d49 365#ifdef CONFIG_8xx_CPU6
14cf11af
PM		 366 lwz r3, 8(r0)
367#endif
92625d49
LC		 368 mfspr r10, SPRN_SPRG_SCRATCH2
369 EXCEPTION_EPILOG_0
14cf11af 370 rfi
fe11dc3f
JT		 3712:
372 mfspr r11, SPRN_SRR1
373 /* clear all error bits as TLB Miss
374 * sets a few unconditionally
375 */
376 rlwinm r11, r11, 0, 0xffff
377 mtspr SPRN_SRR1, r11
378
469d62be 379 /* Restore registers */
92625d49 380#ifdef CONFIG_8xx_CPU6
fe11dc3f
JT		 381 lwz r3, 8(r0)
382#endif
92625d49
LC		 383 mfspr r10, SPRN_SPRG_SCRATCH2
384 EXCEPTION_EPILOG_0
fe11dc3f 385 b InstructionAccess
14cf11af
PM		 386
387 . = 0x1200
388DataStoreTLBMiss:
389#ifdef CONFIG_8xx_CPU6
390 stw r3, 8(r0)
391#endif
92625d49
LC		 392 EXCEPTION_PROLOG_0
393 mtspr SPRN_SPRG_SCRATCH2, r10
14cf11af
PM		 394 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
395
396 /* If we are faulting a kernel address, we have to use the
397 * kernel page tables.
398 */
399 andi. r11, r10, 0x0800
400 beq 3f
401 lis r11, swapper_pg_dir@h
402 ori r11, r11, swapper_pg_dir@l
403 rlwimi r10, r11, 0, 2, 19
4043:
405 lwz r11, 0(r10) /* Get the level 1 entry */
406 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
407 beq 2f /* If zero, don't try to find a pte */
408
409 /* We have a pte table, so load fetch the pte from the table.
410 */
411 ori r11, r11, 1 /* Set valid bit in physical L2 page */
412 DO_8xx_CPU6(0x3b80, r3)
413 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
414 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
415 lwz r10, 0(r10) /* Get the pte */
416
417 /* Insert the Guarded flag into the TWC from the Linux PTE.
418 * It is bit 27 of both the Linux PTE and the TWC (at least
419 * I got that right :-). It will be better when we can put
420 * this into the Linux pgd/pmd and load it in the operation
421 * above.
422 */
423 rlwimi r11, r10, 0, 27, 27
0c466169
JT		 424 /* Insert the WriteThru flag into the TWC from the Linux PTE.
425 * It is bit 25 in the Linux PTE and bit 30 in the TWC
426 */
427 rlwimi r11, r10, 32-5, 30, 30
14cf11af
PM		 428 DO_8xx_CPU6(0x3b80, r3)
429 mtspr SPRN_MD_TWC, r11
430
fe11dc3f
JT		 431 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
432 * We also need to know if the insn is a load/store, so:
433 * Clear _PAGE_PRESENT and load that which will
434 * trap into DTLB Error with store bit set accordinly.
435 */
436 /* PRESENT=0x1, ACCESSED=0x20
437 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
438 * r10 = (r10 & ~PRESENT) | r11;
439 */
d069cb43 440#ifdef CONFIG_SWAP
990d89c6 441 rlwinm r11, r10, 32-5, _PAGE_PRESENT
fe11dc3f 442 and r11, r11, r10
990d89c6 443 rlwimi r10, r11, 0, _PAGE_PRESENT
d069cb43 444#endif
fe11dc3f 445 /* Honour kernel RO, User NA */
990d89c6 446 /* 0x200 == Extended encoding, bit 22 */
fe1691e3 447 rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */
990d89c6
JT		 448 /* r11 = (r10 & _PAGE_RW) >> 1 */
449 rlwinm r11, r10, 32-1, 0x200
450 or r10, r11, r10
451 /* invert RW and 0x200 bits */
452 xori r10, r10, _PAGE_RW | 0x200
14cf11af
PM		 453
454 /* The Linux PTE won't go exactly into the MMU TLB.
fe11dc3f 455 * Software indicator bits 22 and 28 must be clear.
14cf11af
PM		 456 * Software indicator bits 24, 25, 26, and 27 must be
457 * set. All other Linux PTE bits control the behavior
458 * of the MMU.
459 */
4602: li r11, 0x00f0
461 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
462 DO_8xx_CPU6(0x3d80, r3)
463 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
464
469d62be 465 /* Restore registers */
92625d49 466#ifdef CONFIG_8xx_CPU6
14cf11af
PM		 467 lwz r3, 8(r0)
468#endif
92625d49
LC		 469 mtspr SPRN_DAR, r11 /* Tag DAR */
470 mfspr r10, SPRN_SPRG_SCRATCH2
471 EXCEPTION_EPILOG_0
14cf11af
PM		 472 rfi
473
474/* This is an instruction TLB error on the MPC8xx. This could be due
475 * to many reasons, such as executing guarded memory or illegal instruction
476 * addresses. There is nothing to do but handle a big time error fault.
477 */
478 . = 0x1300
479InstructionTLBError:
480 b InstructionAccess
481
482/* This is the data TLB error on the MPC8xx. This could be due to
140a6a60
LC		 483 * many reasons, including a dirty update to a pte. We bail out to
484 * a higher level function that can handle it.
14cf11af
PM		 485 */
486 . = 0x1400
487DataTLBError:
92625d49 488 EXCEPTION_PROLOG_0
14cf11af 489
5bcbe24f
LC		 490 mfspr r11, SPRN_DAR
491 cmpwi cr0, r11, 0x00f0
0a2ab51f 492 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
3e436403 493DARFixed:/* Return from dcbx instruction bug workaround */
92625d49 494 EXCEPTION_EPILOG_0
14cf11af
PM		 495 b DataAccess
496
dc1c1ca3
SR		 497 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
498 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
499 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
500 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
501 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
502 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
503 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 504
505/* On the MPC8xx, these next four traps are used for development
506 * support of breakpoints and such. Someday I will get around to
507 * using them.
508 */
dc1c1ca3
SR		 509 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
510 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
511 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
512 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
14cf11af
PM		 513
514 . = 0x2000
515
0a2ab51f
JT		 516/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
517 * by decoding the registers used by the dcbx instruction and adding them.
3e436403 518 * DAR is set to the calculated address.
0a2ab51f
JT		 519 */
520 /* define if you don't want to use self modifying code */
521#define NO_SELF_MODIFYING_CODE
522FixupDAR:/* Entry point for dcbx workaround. */
5bcbe24f
LC		 523#ifdef CONFIG_8xx_CPU6
524 stw r3, 8(r0)
525#endif
526 mtspr SPRN_SPRG_SCRATCH2, r10
0a2ab51f
JT		 527 /* fetch instruction from memory. */
528 mfspr r10, SPRN_SRR0
061ec959 529 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
0a2ab51f
JT		 530 DO_8xx_CPU6(0x3780, r3)
531 mtspr SPRN_MD_EPN, r10
532 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
061ec959 533 beq- 3f /* Branch if user space */
0a2ab51f
JT		 534 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
535 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
536 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
5373: lwz r11, 0(r11) /* Get the level 1 entry */
538 DO_8xx_CPU6(0x3b80, r3)
539 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
540 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
541 lwz r11, 0(r11) /* Get the pte */
5bcbe24f
LC		 542#ifdef CONFIG_8xx_CPU6
543 lwz r3, 8(r0) /* restore r3 from memory */
544#endif
0a2ab51f
JT		 545 /* concat physical page address(r11) and page offset(r10) */
546 rlwimi r11, r10, 0, 20, 31
547 lwz r11,0(r11)
548/* Check if it really is a dcbx instruction. */
549/* dcbt and dcbtst does not generate DTLB Misses/Errors,
550 * no need to include them here */
41cacac6
LC		 551 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
552 rlwinm r10, r10, 0, 21, 5
0a2ab51f
JT		 553 cmpwi cr0, r10, 2028 /* Is dcbz? */
554 beq+ 142f
555 cmpwi cr0, r10, 940 /* Is dcbi? */
556 beq+ 142f
557 cmpwi cr0, r10, 108 /* Is dcbst? */
558 beq+ 144f /* Fix up store bit! */
559 cmpwi cr0, r10, 172 /* Is dcbf? */
560 beq+ 142f
561 cmpwi cr0, r10, 1964 /* Is icbi? */
562 beq+ 142f
5bcbe24f
LC		 563141: mfspr r10,SPRN_SPRG_SCRATCH2
564 b DARFixed /* Nope, go back to normal TLB processing */
0a2ab51f
JT		 565
566144: mfspr r10, SPRN_DSISR
567 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
568 mtspr SPRN_DSISR, r10
569142: /* continue, it was a dcbx, dcbi instruction. */
0a2ab51f
JT		 570#ifndef NO_SELF_MODIFYING_CODE
571 andis. r10,r11,0x1f /* test if reg RA is r0 */
572 li r10,modified_instr@l
573 dcbtst r0,r10 /* touch for store */
574 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
575 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
576 ori r11,r11,532
577 stw r11,0(r10) /* store add/and instruction */
578 dcbf 0,r10 /* flush new instr. to memory. */
579 icbi 0,r10 /* invalidate instr. cache line */
92625d49
LC		 580 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
581 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
0a2ab51f
JT		 582 isync /* Wait until new instr is loaded from memory */
583modified_instr:
584 .space 4 /* this is where the add instr. is stored */
585 bne+ 143f
586 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
587143: mtdar r10 /* store faulting EA in DAR */
5bcbe24f 588 mfspr r10,SPRN_SPRG_SCRATCH2
0a2ab51f
JT		 589 b DARFixed /* Go back to normal TLB handling */
590#else
591 mfctr r10
592 mtdar r10 /* save ctr reg in DAR */
593 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
594 addi r10, r10, 150f@l /* add start of table */
595 mtctr r10 /* load ctr with jump address */
596 xor r10, r10, r10 /* sum starts at zero */
597 bctr /* jump into table */
598150:
599 add r10, r10, r0 ;b 151f
600 add r10, r10, r1 ;b 151f
601 add r10, r10, r2 ;b 151f
602 add r10, r10, r3 ;b 151f
603 add r10, r10, r4 ;b 151f
604 add r10, r10, r5 ;b 151f
605 add r10, r10, r6 ;b 151f
606 add r10, r10, r7 ;b 151f
607 add r10, r10, r8 ;b 151f
608 add r10, r10, r9 ;b 151f
609 mtctr r11 ;b 154f /* r10 needs special handling */
610 mtctr r11 ;b 153f /* r11 needs special handling */
611 add r10, r10, r12 ;b 151f
612 add r10, r10, r13 ;b 151f
613 add r10, r10, r14 ;b 151f
614 add r10, r10, r15 ;b 151f
615 add r10, r10, r16 ;b 151f
616 add r10, r10, r17 ;b 151f
617 add r10, r10, r18 ;b 151f
618 add r10, r10, r19 ;b 151f
619 add r10, r10, r20 ;b 151f
620 add r10, r10, r21 ;b 151f
621 add r10, r10, r22 ;b 151f
622 add r10, r10, r23 ;b 151f
623 add r10, r10, r24 ;b 151f
624 add r10, r10, r25 ;b 151f
625 add r10, r10, r26 ;b 151f
626 add r10, r10, r27 ;b 151f
627 add r10, r10, r28 ;b 151f
628 add r10, r10, r29 ;b 151f
629 add r10, r10, r30 ;b 151f
630 add r10, r10, r31
631151:
632 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
633 beq 152f /* if reg RA is zero, don't add it */
634 addi r11, r11, 150b@l /* add start of table */
635 mtctr r11 /* load ctr with jump address */
636 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
637 bctr /* jump into table */
638152:
639 mfdar r11
640 mtctr r11 /* restore ctr reg from DAR */
641 mtdar r10 /* save fault EA to DAR */
5bcbe24f 642 mfspr r10,SPRN_SPRG_SCRATCH2
0a2ab51f
JT		 643 b DARFixed /* Go back to normal TLB handling */
644
645 /* special handling for r10,r11 since these are modified already */
92625d49 646153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
0a2ab51f 647 b 155f
92625d49 648154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
0a2ab51f
JT		 649155: add r10, r10, r11 /* add it */
650 mfctr r11 /* restore r11 */
651 b 151b
652#endif
653
14cf11af
PM		 654/*
655 * This is where the main kernel code starts.
656 */
657start_here:
658 /* ptr to current */
659 lis r2,init_task@h
660 ori r2,r2,init_task@l
661
662 /* ptr to phys current thread */
663 tophys(r4,r2)
664 addi r4,r4,THREAD /* init task's THREAD */
ee43eb78 665 mtspr SPRN_SPRG_THREAD,r4
14cf11af
PM		 666
667 /* stack */
668 lis r1,init_thread_union@ha
669 addi r1,r1,init_thread_union@l
670 li r0,0
671 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
672
673 bl early_init /* We have to do this with MMU on */
674
675/*
676 * Decide what sort of machine this is and initialize the MMU.
677 */
6dece0eb
SW		 678 li r3,0
679 mr r4,r31
14cf11af
PM		 680 bl machine_init
681 bl MMU_init
682
683/*
684 * Go back to running unmapped so we can load up new values
685 * and change to using our exception vectors.
686 * On the 8xx, all we have to do is invalidate the TLB to clear
687 * the old 8M byte TLB mappings and load the page table base register.
688 */
689 /* The right way to do this would be to track it down through
690 * init's THREAD like the context switch code does, but this is
691 * easier......until someone changes init's static structures.
692 */
693 lis r6, swapper_pg_dir@h
694 ori r6, r6, swapper_pg_dir@l
695 tophys(r6,r6)
696#ifdef CONFIG_8xx_CPU6
697 lis r4, cpu6_errata_word@h
698 ori r4, r4, cpu6_errata_word@l
699 li r3, 0x3980
700 stw r3, 12(r4)
701 lwz r3, 12(r4)
702#endif
703 mtspr SPRN_M_TWB, r6
704 lis r4,2f@h
705 ori r4,r4,2f@l
706 tophys(r4,r4)
707 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
708 mtspr SPRN_SRR0,r4
709 mtspr SPRN_SRR1,r3
710 rfi
711/* Load up the kernel context */
7122:
713 SYNC /* Force all PTE updates to finish */
714 tlbia /* Clear all TLB entries */
715 sync /* wait for tlbia/tlbie to finish */
716 TLBSYNC /* ... on all CPUs */
717
718 /* set up the PTE pointers for the Abatron bdiGDB.
719 */
720 tovirt(r6,r6)
721 lis r5, abatron_pteptrs@h
722 ori r5, r5, abatron_pteptrs@l
723 stw r5, 0xf0(r0) /* Must match your Abatron config file */
724 tophys(r5,r5)
725 stw r6, 0(r5)
726
727/* Now turn on the MMU for real! */
728 li r4,MSR_KERNEL
729 lis r3,start_kernel@h
730 ori r3,r3,start_kernel@l
731 mtspr SPRN_SRR0,r3
732 mtspr SPRN_SRR1,r4
733 rfi /* enable MMU and jump to start_kernel */
734
735/* Set up the initial MMU state so we can do the first level of
736 * kernel initialization. This maps the first 8 MBytes of memory 1:1
737 * virtual to physical. Also, set the cache mode since that is defined
738 * by TLB entries and perform any additional mapping (like of the IMMR).
739 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
740 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
741 * these mappings is mapped by page tables.
742 */
743initial_mmu:
744 tlbia /* Invalidate all TLB entries */
9f4f04ba
JT		 745/* Always pin the first 8 MB ITLB to prevent ITLB
746 misses while mucking around with SRR0/SRR1 in asm
747*/
14cf11af
PM		 748 lis r8, MI_RSV4I@h
749 ori r8, r8, 0x1c00
9f4f04ba 750
14cf11af
PM		 751 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
752
753#ifdef CONFIG_PIN_TLB
754 lis r10, (MD_RSV4I | MD_RESETVAL)@h
755 ori r10, r10, 0x1c00
756 mr r8, r10
757#else
758 lis r10, MD_RESETVAL@h
759#endif
760#ifndef CONFIG_8xx_COPYBACK
761 oris r10, r10, MD_WTDEF@h
762#endif
763 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
764
765 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
766 * we can load the instruction and data TLB registers with the
767 * same values.
768 */
769 lis r8, KERNELBASE@h /* Create vaddr for TLB */
770 ori r8, r8, MI_EVALID /* Mark it valid */
771 mtspr SPRN_MI_EPN, r8
772 mtspr SPRN_MD_EPN, r8
773 li r8, MI_PS8MEG /* Set 8M byte page */
774 ori r8, r8, MI_SVALID /* Make it valid */
775 mtspr SPRN_MI_TWC, r8
776 mtspr SPRN_MD_TWC, r8
777 li r8, MI_BOOTINIT /* Create RPN for address 0 */
778 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
779 mtspr SPRN_MD_RPN, r8
780 lis r8, MI_Kp@h /* Set the protection mode */
781 mtspr SPRN_MI_AP, r8
782 mtspr SPRN_MD_AP, r8
783
784 /* Map another 8 MByte at the IMMR to get the processor
785 * internal registers (among other things).
786 */
787#ifdef CONFIG_PIN_TLB
788 addi r10, r10, 0x0100
789 mtspr SPRN_MD_CTR, r10
790#endif
791 mfspr r9, 638 /* Get current IMMR */
792 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
793
794 mr r8, r9 /* Create vaddr for TLB */
795 ori r8, r8, MD_EVALID /* Mark it valid */
796 mtspr SPRN_MD_EPN, r8
797 li r8, MD_PS8MEG /* Set 8M byte page */
798 ori r8, r8, MD_SVALID /* Make it valid */
799 mtspr SPRN_MD_TWC, r8
800 mr r8, r9 /* Create paddr for TLB */
801 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
802 mtspr SPRN_MD_RPN, r8
803
804#ifdef CONFIG_PIN_TLB
805 /* Map two more 8M kernel data pages.
806 */
807 addi r10, r10, 0x0100
808 mtspr SPRN_MD_CTR, r10
809
810 lis r8, KERNELBASE@h /* Create vaddr for TLB */
811 addis r8, r8, 0x0080 /* Add 8M */
812 ori r8, r8, MI_EVALID /* Mark it valid */
813 mtspr SPRN_MD_EPN, r8
814 li r9, MI_PS8MEG /* Set 8M byte page */
815 ori r9, r9, MI_SVALID /* Make it valid */
816 mtspr SPRN_MD_TWC, r9
817 li r11, MI_BOOTINIT /* Create RPN for address 0 */
818 addis r11, r11, 0x0080 /* Add 8M */
ccf0d68e 819 mtspr SPRN_MD_RPN, r11
14cf11af 820
4e591f3c
LC		 821 addi r10, r10, 0x0100
822 mtspr SPRN_MD_CTR, r10
823
14cf11af
PM		 824 addis r8, r8, 0x0080 /* Add 8M */
825 mtspr SPRN_MD_EPN, r8
826 mtspr SPRN_MD_TWC, r9
827 addis r11, r11, 0x0080 /* Add 8M */
ccf0d68e 828 mtspr SPRN_MD_RPN, r11
14cf11af
PM		 829#endif
830
831 /* Since the cache is enabled according to the information we
832 * just loaded into the TLB, invalidate and enable the caches here.
833 * We should probably check/set other modes....later.
834 */
835 lis r8, IDC_INVALL@h
836 mtspr SPRN_IC_CST, r8
837 mtspr SPRN_DC_CST, r8
838 lis r8, IDC_ENABLE@h
839 mtspr SPRN_IC_CST, r8
840#ifdef CONFIG_8xx_COPYBACK
841 mtspr SPRN_DC_CST, r8
842#else
843 /* For a debug option, I left this here to easily enable
844 * the write through cache mode
845 */
846 lis r8, DC_SFWT@h
847 mtspr SPRN_DC_CST, r8
848 lis r8, IDC_ENABLE@h
849 mtspr SPRN_DC_CST, r8
850#endif
851 blr
852
853
854/*
855 * Set up to use a given MMU context.
856 * r3 is context number, r4 is PGD pointer.
857 *
858 * We place the physical address of the new task page directory loaded
859 * into the MMU base register, and set the ASID compare register with
860 * the new "context."
861 */
862_GLOBAL(set_context)
863
864#ifdef CONFIG_BDI_SWITCH
865 /* Context switch the PTE pointer for the Abatron BDI2000.
866 * The PGDIR is passed as second argument.
867 */
868 lis r5, KERNELBASE@h
869 lwz r5, 0xf0(r5)
870 stw r4, 0x4(r5)
871#endif
872
873#ifdef CONFIG_8xx_CPU6
874 lis r6, cpu6_errata_word@h
875 ori r6, r6, cpu6_errata_word@l
876 tophys (r4, r4)
877 li r7, 0x3980
878 stw r7, 12(r6)
879 lwz r7, 12(r6)
880 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
881 li r7, 0x3380
882 stw r7, 12(r6)
883 lwz r7, 12(r6)
884 mtspr SPRN_M_CASID, r3 /* Update context */
885#else
886 mtspr SPRN_M_CASID,r3 /* Update context */
887 tophys (r4, r4)
888 mtspr SPRN_M_TWB, r4 /* and pgd */
889#endif
890 SYNC
891 blr
892
893#ifdef CONFIG_8xx_CPU6
894/* It's here because it is unique to the 8xx.
895 * It is important we get called with interrupts disabled. I used to
896 * do that, but it appears that all code that calls this already had
897 * interrupt disabled.
898 */
899 .globl set_dec_cpu6
900set_dec_cpu6:
901 lis r7, cpu6_errata_word@h
902 ori r7, r7, cpu6_errata_word@l
903 li r4, 0x2c00
904 stw r4, 8(r7)
905 lwz r4, 8(r7)
906 mtspr 22, r3 /* Update Decrementer */
907 SYNC
908 blr
909#endif
910
911/*
912 * We put a few things here that have to be page-aligned.
913 * This stuff goes at the beginning of the data segment,
914 * which is page-aligned.
915 */
916 .data
917 .globl sdata
918sdata:
919 .globl empty_zero_page
920empty_zero_page:
921 .space 4096
922
923 .globl swapper_pg_dir
924swapper_pg_dir:
925 .space 4096
926
14cf11af
PM		 927/* Room for two PTE table poiners, usually the kernel and current user
928 * pointer to their respective root page table (pgdir).
929 */
930abatron_pteptrs:
931 .space 8
932
933#ifdef CONFIG_8xx_CPU6
934 .globl cpu6_errata_word
935cpu6_errata_word:
936 .space 16
937#endif
938
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