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14cf11af | 1 | /* |
14cf11af PM |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
6 | * Low-level exception handlers and MMU support | |
7 | * rewritten by Paul Mackerras. | |
8 | * Copyright (C) 1996 Paul Mackerras. | |
9 | * MPC8xx modifications by Dan Malek | |
10 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
11 | * | |
12 | * This file contains low-level support and setup for PowerPC 8xx | |
13 | * embedded processors, including trap and interrupt dispatch. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | * | |
20 | */ | |
21 | ||
e7039845 | 22 | #include <linux/init.h> |
14cf11af PM |
23 | #include <asm/processor.h> |
24 | #include <asm/page.h> | |
25 | #include <asm/mmu.h> | |
26 | #include <asm/cache.h> | |
27 | #include <asm/pgtable.h> | |
28 | #include <asm/cputable.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/ppc_asm.h> | |
31 | #include <asm/asm-offsets.h> | |
46f52210 | 32 | #include <asm/ptrace.h> |
14cf11af PM |
33 | |
34 | /* Macro to make the code more readable. */ | |
35 | #ifdef CONFIG_8xx_CPU6 | |
d3e40262 LC |
36 | #define SPRN_MI_TWC_ADDR 0x2b80 |
37 | #define SPRN_MI_RPN_ADDR 0x2d80 | |
38 | #define SPRN_MD_TWC_ADDR 0x3b80 | |
39 | #define SPRN_MD_RPN_ADDR 0x3d80 | |
40 | ||
41 | #define MTSPR_CPU6(spr, reg, treg) \ | |
42 | li treg, spr##_ADDR; \ | |
43 | stw treg, 12(r0); \ | |
44 | lwz treg, 12(r0); \ | |
45 | mtspr spr, reg | |
14cf11af | 46 | #else |
d3e40262 LC |
47 | #define MTSPR_CPU6(spr, reg, treg) \ |
48 | mtspr spr, reg | |
14cf11af | 49 | #endif |
ac21951f LC |
50 | |
51 | /* | |
52 | * Value for the bits that have fixed value in RPN entries. | |
53 | * Also used for tagging DAR for DTLBerror. | |
54 | */ | |
959d6173 LC |
55 | #ifdef CONFIG_PPC_16K_PAGES |
56 | #define RPN_PATTERN (0x00f0 | MD_SPS16K) | |
57 | #else | |
ac21951f | 58 | #define RPN_PATTERN 0x00f0 |
959d6173 | 59 | #endif |
ac21951f | 60 | |
e7039845 | 61 | __HEAD |
748a7683 KG |
62 | _ENTRY(_stext); |
63 | _ENTRY(_start); | |
14cf11af PM |
64 | |
65 | /* MPC8xx | |
66 | * This port was done on an MBX board with an 860. Right now I only | |
67 | * support an ELF compressed (zImage) boot from EPPC-Bug because the | |
68 | * code there loads up some registers before calling us: | |
69 | * r3: ptr to board info data | |
70 | * r4: initrd_start or if no initrd then 0 | |
71 | * r5: initrd_end - unused if r4 is 0 | |
72 | * r6: Start of command line string | |
73 | * r7: End of command line string | |
74 | * | |
75 | * I decided to use conditional compilation instead of checking PVR and | |
76 | * adding more processor specific branches around code I don't need. | |
77 | * Since this is an embedded processor, I also appreciate any memory | |
78 | * savings I can get. | |
79 | * | |
80 | * The MPC8xx does not have any BATs, but it supports large page sizes. | |
81 | * We first initialize the MMU to support 8M byte pages, then load one | |
82 | * entry into each of the instruction and data TLBs to map the first | |
83 | * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to | |
84 | * the "internal" processor registers before MMU_init is called. | |
85 | * | |
14cf11af PM |
86 | * -- Dan |
87 | */ | |
88 | .globl __start | |
89 | __start: | |
6dece0eb | 90 | mr r31,r3 /* save device tree ptr */ |
14cf11af PM |
91 | |
92 | /* We have to turn on the MMU right away so we get cache modes | |
93 | * set correctly. | |
94 | */ | |
95 | bl initial_mmu | |
96 | ||
97 | /* We now have the lower 8 Meg mapped into TLB entries, and the caches | |
98 | * ready to work. | |
99 | */ | |
100 | ||
101 | turn_on_mmu: | |
102 | mfmsr r0 | |
103 | ori r0,r0,MSR_DR|MSR_IR | |
104 | mtspr SPRN_SRR1,r0 | |
105 | lis r0,start_here@h | |
106 | ori r0,r0,start_here@l | |
107 | mtspr SPRN_SRR0,r0 | |
108 | SYNC | |
109 | rfi /* enables MMU */ | |
110 | ||
111 | /* | |
112 | * Exception entry code. This code runs with address translation | |
113 | * turned off, i.e. using physical addresses. | |
114 | * We assume sprg3 has the physical address of the current | |
115 | * task's thread_struct. | |
116 | */ | |
117 | #define EXCEPTION_PROLOG \ | |
92625d49 | 118 | EXCEPTION_PROLOG_0; \ |
14cf11af PM |
119 | EXCEPTION_PROLOG_1; \ |
120 | EXCEPTION_PROLOG_2 | |
121 | ||
92625d49 LC |
122 | #define EXCEPTION_PROLOG_0 \ |
123 | mtspr SPRN_SPRG_SCRATCH0,r10; \ | |
124 | mtspr SPRN_SPRG_SCRATCH1,r11; \ | |
125 | mfcr r10 | |
126 | ||
14cf11af PM |
127 | #define EXCEPTION_PROLOG_1 \ |
128 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ | |
129 | andi. r11,r11,MSR_PR; \ | |
130 | tophys(r11,r1); /* use tophys(r1) if kernel */ \ | |
131 | beq 1f; \ | |
ee43eb78 | 132 | mfspr r11,SPRN_SPRG_THREAD; \ |
14cf11af PM |
133 | lwz r11,THREAD_INFO-THREAD(r11); \ |
134 | addi r11,r11,THREAD_SIZE; \ | |
135 | tophys(r11,r11); \ | |
136 | 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ | |
137 | ||
138 | ||
139 | #define EXCEPTION_PROLOG_2 \ | |
140 | CLR_TOP32(r11); \ | |
141 | stw r10,_CCR(r11); /* save registers */ \ | |
142 | stw r12,GPR12(r11); \ | |
143 | stw r9,GPR9(r11); \ | |
ee43eb78 | 144 | mfspr r10,SPRN_SPRG_SCRATCH0; \ |
14cf11af | 145 | stw r10,GPR10(r11); \ |
ee43eb78 | 146 | mfspr r12,SPRN_SPRG_SCRATCH1; \ |
14cf11af PM |
147 | stw r12,GPR11(r11); \ |
148 | mflr r10; \ | |
149 | stw r10,_LINK(r11); \ | |
150 | mfspr r12,SPRN_SRR0; \ | |
151 | mfspr r9,SPRN_SRR1; \ | |
152 | stw r1,GPR1(r11); \ | |
153 | stw r1,0(r11); \ | |
154 | tovirt(r1,r11); /* set new kernel sp */ \ | |
155 | li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ | |
156 | MTMSRD(r10); /* (except for mach check in rtas) */ \ | |
157 | stw r0,GPR0(r11); \ | |
158 | SAVE_4GPRS(3, r11); \ | |
159 | SAVE_2GPRS(7, r11) | |
160 | ||
92625d49 LC |
161 | /* |
162 | * Exception exit code. | |
163 | */ | |
164 | #define EXCEPTION_EPILOG_0 \ | |
165 | mtcr r10; \ | |
166 | mfspr r10,SPRN_SPRG_SCRATCH0; \ | |
167 | mfspr r11,SPRN_SPRG_SCRATCH1 | |
168 | ||
14cf11af PM |
169 | /* |
170 | * Note: code which follows this uses cr0.eq (set if from kernel), | |
171 | * r11, r12 (SRR0), and r9 (SRR1). | |
172 | * | |
173 | * Note2: once we have set r1 we are in a position to take exceptions | |
174 | * again, and we could thus set MSR:RI at that point. | |
175 | */ | |
176 | ||
177 | /* | |
178 | * Exception vectors. | |
179 | */ | |
180 | #define EXCEPTION(n, label, hdlr, xfer) \ | |
181 | . = n; \ | |
182 | label: \ | |
183 | EXCEPTION_PROLOG; \ | |
184 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
185 | xfer(n, hdlr) | |
186 | ||
187 | #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ | |
188 | li r10,trap; \ | |
d73e0c99 | 189 | stw r10,_TRAP(r11); \ |
14cf11af PM |
190 | li r10,MSR_KERNEL; \ |
191 | copyee(r10, r9); \ | |
192 | bl tfer; \ | |
193 | i##n: \ | |
194 | .long hdlr; \ | |
195 | .long ret | |
196 | ||
197 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 | |
198 | #define NOCOPY(d, s) | |
199 | ||
200 | #define EXC_XFER_STD(n, hdlr) \ | |
201 | EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ | |
202 | ret_from_except_full) | |
203 | ||
204 | #define EXC_XFER_LITE(n, hdlr) \ | |
205 | EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ | |
206 | ret_from_except) | |
207 | ||
208 | #define EXC_XFER_EE(n, hdlr) \ | |
209 | EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ | |
210 | ret_from_except_full) | |
211 | ||
212 | #define EXC_XFER_EE_LITE(n, hdlr) \ | |
213 | EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ | |
214 | ret_from_except) | |
215 | ||
216 | /* System reset */ | |
dc1c1ca3 | 217 | EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) |
14cf11af PM |
218 | |
219 | /* Machine check */ | |
220 | . = 0x200 | |
221 | MachineCheck: | |
222 | EXCEPTION_PROLOG | |
223 | mfspr r4,SPRN_DAR | |
224 | stw r4,_DAR(r11) | |
ac21951f | 225 | li r5,RPN_PATTERN |
60e071fe | 226 | mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ |
14cf11af PM |
227 | mfspr r5,SPRN_DSISR |
228 | stw r5,_DSISR(r11) | |
229 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 230 | EXC_XFER_STD(0x200, machine_check_exception) |
14cf11af PM |
231 | |
232 | /* Data access exception. | |
749137a2 | 233 | * This is "never generated" by the MPC8xx. |
14cf11af PM |
234 | */ |
235 | . = 0x300 | |
236 | DataAccess: | |
14cf11af PM |
237 | |
238 | /* Instruction access exception. | |
7439b37e | 239 | * This is "never generated" by the MPC8xx. |
14cf11af PM |
240 | */ |
241 | . = 0x400 | |
242 | InstructionAccess: | |
14cf11af PM |
243 | |
244 | /* External interrupt */ | |
245 | EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) | |
246 | ||
247 | /* Alignment exception */ | |
248 | . = 0x600 | |
249 | Alignment: | |
250 | EXCEPTION_PROLOG | |
251 | mfspr r4,SPRN_DAR | |
252 | stw r4,_DAR(r11) | |
ac21951f | 253 | li r5,RPN_PATTERN |
60e071fe | 254 | mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ |
14cf11af PM |
255 | mfspr r5,SPRN_DSISR |
256 | stw r5,_DSISR(r11) | |
257 | addi r3,r1,STACK_FRAME_OVERHEAD | |
dc1c1ca3 | 258 | EXC_XFER_EE(0x600, alignment_exception) |
14cf11af PM |
259 | |
260 | /* Program check exception */ | |
dc1c1ca3 | 261 | EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) |
14cf11af PM |
262 | |
263 | /* No FPU on MPC8xx. This exception is not supposed to happen. | |
264 | */ | |
dc1c1ca3 | 265 | EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) |
14cf11af PM |
266 | |
267 | /* Decrementer */ | |
268 | EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) | |
269 | ||
dc1c1ca3 SR |
270 | EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) |
271 | EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
272 | |
273 | /* System call */ | |
274 | . = 0xc00 | |
275 | SystemCall: | |
276 | EXCEPTION_PROLOG | |
277 | EXC_XFER_EE_LITE(0xc00, DoSyscall) | |
278 | ||
279 | /* Single step - not used on 601 */ | |
dc1c1ca3 SR |
280 | EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) |
281 | EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) | |
282 | EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
283 | |
284 | /* On the MPC8xx, this is a software emulation interrupt. It occurs | |
285 | * for all unimplemented and illegal instructions. | |
286 | */ | |
287 | EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) | |
288 | ||
289 | . = 0x1100 | |
290 | /* | |
291 | * For the MPC8xx, this is a software tablewalk to load the instruction | |
cbc130f1 LC |
292 | * TLB. The task switch loads the M_TW register with the pointer to the first |
293 | * level table. | |
14cf11af PM |
294 | * If we discover there is no second level table (value is zero) or if there |
295 | * is an invalid pte, we load that into the TLB, which causes another fault | |
296 | * into the TLB Error interrupt where we can handle such problems. | |
297 | * We have to use the MD_xxx registers for the tablewalk because the | |
298 | * equivalent MI_xxx registers only perform the attribute functions. | |
299 | */ | |
300 | InstructionTLBMiss: | |
301 | #ifdef CONFIG_8xx_CPU6 | |
83c17ba3 | 302 | mtspr SPRN_DAR, r3 |
14cf11af | 303 | #endif |
92625d49 LC |
304 | EXCEPTION_PROLOG_0 |
305 | mtspr SPRN_SPRG_SCRATCH2, r10 | |
14cf11af | 306 | mfspr r10, SPRN_SRR0 /* Get effective address of fault */ |
74016852 | 307 | #ifdef CONFIG_8xx_CPU15 |
d1406803 | 308 | addi r11, r10, PAGE_SIZE |
74016852 | 309 | tlbie r11 |
d1406803 | 310 | addi r11, r10, -PAGE_SIZE |
74016852 SW |
311 | tlbie r11 |
312 | #endif | |
14cf11af PM |
313 | |
314 | /* If we are faulting a kernel address, we have to use the | |
315 | * kernel page tables. | |
316 | */ | |
4afb0be7 JT |
317 | #ifdef CONFIG_MODULES |
318 | /* Only modules will cause ITLB Misses as we always | |
319 | * pin the first 8MB of kernel memory */ | |
cbc130f1 LC |
320 | andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ |
321 | #endif | |
322 | mfspr r11, SPRN_M_TW /* Get level 1 table base address */ | |
323 | #ifdef CONFIG_MODULES | |
14cf11af | 324 | beq 3f |
cbc130f1 LC |
325 | lis r11, (swapper_pg_dir-PAGE_OFFSET)@h |
326 | ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l | |
14cf11af | 327 | 3: |
4afb0be7 | 328 | #endif |
d1406803 LC |
329 | /* Extract level 1 index */ |
330 | rlwinm r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 | |
cbc130f1 | 331 | lwzx r11, r10, r11 /* Get the level 1 entry */ |
5ddb75ce | 332 | rlwinm r10, r11,0,0,19 /* Extract page descriptor page address */ |
14cf11af | 333 | |
5ddb75ce | 334 | /* Load the MI_TWC with the attributes for this "segment." */ |
d3e40262 | 335 | MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */ |
33fb845a | 336 | mfspr r11, SPRN_SRR0 /* Get effective address of fault */ |
d1406803 LC |
337 | /* Extract level 2 index */ |
338 | rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 | |
33fb845a | 339 | lwzx r10, r10, r11 /* Get the pte */ |
14cf11af | 340 | |
d069cb43 | 341 | #ifdef CONFIG_SWAP |
5ddb75ce LC |
342 | rlwinm r11, r10, 32-5, _PAGE_PRESENT |
343 | and r11, r11, r10 | |
344 | rlwimi r10, r11, 0, _PAGE_PRESENT | |
d069cb43 | 345 | #endif |
5ddb75ce | 346 | li r11, RPN_PATTERN |
14cf11af | 347 | /* The Linux PTE won't go exactly into the MMU TLB. |
fe1691e3 | 348 | * Software indicator bits 21 and 28 must be clear. |
14cf11af PM |
349 | * Software indicator bits 24, 25, 26, and 27 must be |
350 | * set. All other Linux PTE bits control the behavior | |
351 | * of the MMU. | |
352 | */ | |
fe1691e3 | 353 | rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ |
d3e40262 | 354 | MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */ |
14cf11af | 355 | |
469d62be | 356 | /* Restore registers */ |
92625d49 | 357 | #ifdef CONFIG_8xx_CPU6 |
83c17ba3 LC |
358 | mfspr r3, SPRN_DAR |
359 | mtspr SPRN_DAR, r11 /* Tag DAR */ | |
14cf11af | 360 | #endif |
92625d49 LC |
361 | mfspr r10, SPRN_SPRG_SCRATCH2 |
362 | EXCEPTION_EPILOG_0 | |
14cf11af PM |
363 | rfi |
364 | ||
365 | . = 0x1200 | |
366 | DataStoreTLBMiss: | |
367 | #ifdef CONFIG_8xx_CPU6 | |
83c17ba3 | 368 | mtspr SPRN_DAR, r3 |
14cf11af | 369 | #endif |
92625d49 LC |
370 | EXCEPTION_PROLOG_0 |
371 | mtspr SPRN_SPRG_SCRATCH2, r10 | |
cbc130f1 | 372 | mfspr r10, SPRN_MD_EPN |
14cf11af PM |
373 | |
374 | /* If we are faulting a kernel address, we have to use the | |
375 | * kernel page tables. | |
376 | */ | |
cbc130f1 LC |
377 | andis. r11, r10, 0x8000 |
378 | mfspr r11, SPRN_M_TW /* Get level 1 table base address */ | |
14cf11af | 379 | beq 3f |
cbc130f1 LC |
380 | lis r11, (swapper_pg_dir-PAGE_OFFSET)@h |
381 | ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l | |
14cf11af | 382 | 3: |
d1406803 LC |
383 | /* Extract level 1 index */ |
384 | rlwinm r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 | |
cbc130f1 | 385 | lwzx r11, r10, r11 /* Get the level 1 entry */ |
14cf11af PM |
386 | |
387 | /* We have a pte table, so load fetch the pte from the table. | |
388 | */ | |
33fb845a LC |
389 | mfspr r10, SPRN_MD_EPN /* Get address of fault */ |
390 | /* Extract level 2 index */ | |
d1406803 LC |
391 | rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 |
392 | rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */ | |
14cf11af PM |
393 | lwz r10, 0(r10) /* Get the pte */ |
394 | ||
395 | /* Insert the Guarded flag into the TWC from the Linux PTE. | |
396 | * It is bit 27 of both the Linux PTE and the TWC (at least | |
397 | * I got that right :-). It will be better when we can put | |
398 | * this into the Linux pgd/pmd and load it in the operation | |
399 | * above. | |
400 | */ | |
401 | rlwimi r11, r10, 0, 27, 27 | |
0c466169 JT |
402 | /* Insert the WriteThru flag into the TWC from the Linux PTE. |
403 | * It is bit 25 in the Linux PTE and bit 30 in the TWC | |
404 | */ | |
405 | rlwimi r11, r10, 32-5, 30, 30 | |
d3e40262 | 406 | MTSPR_CPU6(SPRN_MD_TWC, r11, r3) |
14cf11af | 407 | |
fe11dc3f JT |
408 | /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. |
409 | * We also need to know if the insn is a load/store, so: | |
410 | * Clear _PAGE_PRESENT and load that which will | |
411 | * trap into DTLB Error with store bit set accordinly. | |
412 | */ | |
413 | /* PRESENT=0x1, ACCESSED=0x20 | |
414 | * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); | |
415 | * r10 = (r10 & ~PRESENT) | r11; | |
416 | */ | |
d069cb43 | 417 | #ifdef CONFIG_SWAP |
990d89c6 | 418 | rlwinm r11, r10, 32-5, _PAGE_PRESENT |
fe11dc3f | 419 | and r11, r11, r10 |
990d89c6 | 420 | rlwimi r10, r11, 0, _PAGE_PRESENT |
d069cb43 | 421 | #endif |
14cf11af | 422 | /* The Linux PTE won't go exactly into the MMU TLB. |
fe11dc3f | 423 | * Software indicator bits 22 and 28 must be clear. |
14cf11af PM |
424 | * Software indicator bits 24, 25, 26, and 27 must be |
425 | * set. All other Linux PTE bits control the behavior | |
426 | * of the MMU. | |
427 | */ | |
5ddb75ce | 428 | li r11, RPN_PATTERN |
14cf11af | 429 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ |
d3e40262 | 430 | MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */ |
14cf11af | 431 | |
469d62be | 432 | /* Restore registers */ |
92625d49 | 433 | #ifdef CONFIG_8xx_CPU6 |
83c17ba3 | 434 | mfspr r3, SPRN_DAR |
14cf11af | 435 | #endif |
92625d49 LC |
436 | mtspr SPRN_DAR, r11 /* Tag DAR */ |
437 | mfspr r10, SPRN_SPRG_SCRATCH2 | |
438 | EXCEPTION_EPILOG_0 | |
14cf11af PM |
439 | rfi |
440 | ||
441 | /* This is an instruction TLB error on the MPC8xx. This could be due | |
442 | * to many reasons, such as executing guarded memory or illegal instruction | |
443 | * addresses. There is nothing to do but handle a big time error fault. | |
444 | */ | |
445 | . = 0x1300 | |
446 | InstructionTLBError: | |
5ddb75ce | 447 | EXCEPTION_PROLOG |
7439b37e LC |
448 | mr r4,r12 |
449 | mr r5,r9 | |
c51a6821 LC |
450 | andis. r10,r5,0x4000 |
451 | beq+ 1f | |
452 | tlbie r4 | |
7439b37e | 453 | /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ |
c51a6821 | 454 | 1: EXC_XFER_LITE(0x400, handle_page_fault) |
14cf11af PM |
455 | |
456 | /* This is the data TLB error on the MPC8xx. This could be due to | |
140a6a60 LC |
457 | * many reasons, including a dirty update to a pte. We bail out to |
458 | * a higher level function that can handle it. | |
14cf11af PM |
459 | */ |
460 | . = 0x1400 | |
461 | DataTLBError: | |
92625d49 | 462 | EXCEPTION_PROLOG_0 |
14cf11af | 463 | |
5bcbe24f | 464 | mfspr r11, SPRN_DAR |
ac21951f | 465 | cmpwi cr0, r11, RPN_PATTERN |
0a2ab51f | 466 | beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ |
3e436403 | 467 | DARFixed:/* Return from dcbx instruction bug workaround */ |
6cde2b6f LC |
468 | EXCEPTION_PROLOG_1 |
469 | EXCEPTION_PROLOG_2 | |
c51a6821 LC |
470 | mfspr r5,SPRN_DSISR |
471 | stw r5,_DSISR(r11) | |
749137a2 | 472 | mfspr r4,SPRN_DAR |
c51a6821 LC |
473 | andis. r10,r5,0x4000 |
474 | beq+ 1f | |
475 | tlbie r4 | |
476 | 1: li r10,RPN_PATTERN | |
749137a2 LC |
477 | mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ |
478 | /* 0x300 is DataAccess exception, needed by bad_page_fault() */ | |
479 | EXC_XFER_LITE(0x300, handle_page_fault) | |
14cf11af | 480 | |
dc1c1ca3 SR |
481 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
482 | EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) | |
483 | EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) | |
484 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) | |
485 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) | |
486 | EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) | |
487 | EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
488 | |
489 | /* On the MPC8xx, these next four traps are used for development | |
490 | * support of breakpoints and such. Someday I will get around to | |
491 | * using them. | |
492 | */ | |
dc1c1ca3 SR |
493 | EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) |
494 | EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) | |
495 | EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) | |
496 | EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) | |
14cf11af PM |
497 | |
498 | . = 0x2000 | |
499 | ||
0a2ab51f JT |
500 | /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions |
501 | * by decoding the registers used by the dcbx instruction and adding them. | |
3e436403 | 502 | * DAR is set to the calculated address. |
0a2ab51f JT |
503 | */ |
504 | /* define if you don't want to use self modifying code */ | |
505 | #define NO_SELF_MODIFYING_CODE | |
506 | FixupDAR:/* Entry point for dcbx workaround. */ | |
5bcbe24f | 507 | mtspr SPRN_SPRG_SCRATCH2, r10 |
0a2ab51f JT |
508 | /* fetch instruction from memory. */ |
509 | mfspr r10, SPRN_SRR0 | |
061ec959 | 510 | andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ |
cbc130f1 | 511 | mfspr r11, SPRN_M_TW /* Get level 1 table base address */ |
061ec959 | 512 | beq- 3f /* Branch if user space */ |
0a2ab51f JT |
513 | lis r11, (swapper_pg_dir-PAGE_OFFSET)@h |
514 | ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l | |
d1406803 LC |
515 | /* Extract level 1 index */ |
516 | 3: rlwinm r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29 | |
cbc130f1 | 517 | lwzx r11, r10, r11 /* Get the level 1 entry */ |
33fb845a LC |
518 | rlwinm r10, r11,0,0,19 /* Extract page descriptor page address */ |
519 | mfspr r11, SPRN_SRR0 /* Get effective address of fault */ | |
d1406803 LC |
520 | /* Extract level 2 index */ |
521 | rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29 | |
33fb845a | 522 | lwzx r11, r10, r11 /* Get the pte */ |
0a2ab51f | 523 | /* concat physical page address(r11) and page offset(r10) */ |
cbc130f1 | 524 | mfspr r10, SPRN_SRR0 |
d1406803 | 525 | rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31 |
0a2ab51f JT |
526 | lwz r11,0(r11) |
527 | /* Check if it really is a dcbx instruction. */ | |
528 | /* dcbt and dcbtst does not generate DTLB Misses/Errors, | |
529 | * no need to include them here */ | |
41cacac6 LC |
530 | xoris r10, r11, 0x7c00 /* check if major OP code is 31 */ |
531 | rlwinm r10, r10, 0, 21, 5 | |
0a2ab51f JT |
532 | cmpwi cr0, r10, 2028 /* Is dcbz? */ |
533 | beq+ 142f | |
534 | cmpwi cr0, r10, 940 /* Is dcbi? */ | |
535 | beq+ 142f | |
536 | cmpwi cr0, r10, 108 /* Is dcbst? */ | |
537 | beq+ 144f /* Fix up store bit! */ | |
538 | cmpwi cr0, r10, 172 /* Is dcbf? */ | |
539 | beq+ 142f | |
540 | cmpwi cr0, r10, 1964 /* Is icbi? */ | |
541 | beq+ 142f | |
5bcbe24f LC |
542 | 141: mfspr r10,SPRN_SPRG_SCRATCH2 |
543 | b DARFixed /* Nope, go back to normal TLB processing */ | |
0a2ab51f JT |
544 | |
545 | 144: mfspr r10, SPRN_DSISR | |
546 | rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ | |
547 | mtspr SPRN_DSISR, r10 | |
548 | 142: /* continue, it was a dcbx, dcbi instruction. */ | |
0a2ab51f JT |
549 | #ifndef NO_SELF_MODIFYING_CODE |
550 | andis. r10,r11,0x1f /* test if reg RA is r0 */ | |
551 | li r10,modified_instr@l | |
552 | dcbtst r0,r10 /* touch for store */ | |
553 | rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ | |
554 | oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ | |
555 | ori r11,r11,532 | |
556 | stw r11,0(r10) /* store add/and instruction */ | |
557 | dcbf 0,r10 /* flush new instr. to memory. */ | |
558 | icbi 0,r10 /* invalidate instr. cache line */ | |
92625d49 LC |
559 | mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */ |
560 | mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */ | |
0a2ab51f JT |
561 | isync /* Wait until new instr is loaded from memory */ |
562 | modified_instr: | |
563 | .space 4 /* this is where the add instr. is stored */ | |
564 | bne+ 143f | |
565 | subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ | |
566 | 143: mtdar r10 /* store faulting EA in DAR */ | |
5bcbe24f | 567 | mfspr r10,SPRN_SPRG_SCRATCH2 |
0a2ab51f JT |
568 | b DARFixed /* Go back to normal TLB handling */ |
569 | #else | |
570 | mfctr r10 | |
571 | mtdar r10 /* save ctr reg in DAR */ | |
572 | rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ | |
573 | addi r10, r10, 150f@l /* add start of table */ | |
574 | mtctr r10 /* load ctr with jump address */ | |
575 | xor r10, r10, r10 /* sum starts at zero */ | |
576 | bctr /* jump into table */ | |
577 | 150: | |
578 | add r10, r10, r0 ;b 151f | |
579 | add r10, r10, r1 ;b 151f | |
580 | add r10, r10, r2 ;b 151f | |
581 | add r10, r10, r3 ;b 151f | |
582 | add r10, r10, r4 ;b 151f | |
583 | add r10, r10, r5 ;b 151f | |
584 | add r10, r10, r6 ;b 151f | |
585 | add r10, r10, r7 ;b 151f | |
586 | add r10, r10, r8 ;b 151f | |
587 | add r10, r10, r9 ;b 151f | |
588 | mtctr r11 ;b 154f /* r10 needs special handling */ | |
589 | mtctr r11 ;b 153f /* r11 needs special handling */ | |
590 | add r10, r10, r12 ;b 151f | |
591 | add r10, r10, r13 ;b 151f | |
592 | add r10, r10, r14 ;b 151f | |
593 | add r10, r10, r15 ;b 151f | |
594 | add r10, r10, r16 ;b 151f | |
595 | add r10, r10, r17 ;b 151f | |
596 | add r10, r10, r18 ;b 151f | |
597 | add r10, r10, r19 ;b 151f | |
598 | add r10, r10, r20 ;b 151f | |
599 | add r10, r10, r21 ;b 151f | |
600 | add r10, r10, r22 ;b 151f | |
601 | add r10, r10, r23 ;b 151f | |
602 | add r10, r10, r24 ;b 151f | |
603 | add r10, r10, r25 ;b 151f | |
604 | add r10, r10, r26 ;b 151f | |
605 | add r10, r10, r27 ;b 151f | |
606 | add r10, r10, r28 ;b 151f | |
607 | add r10, r10, r29 ;b 151f | |
608 | add r10, r10, r30 ;b 151f | |
609 | add r10, r10, r31 | |
610 | 151: | |
611 | rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ | |
612 | beq 152f /* if reg RA is zero, don't add it */ | |
613 | addi r11, r11, 150b@l /* add start of table */ | |
614 | mtctr r11 /* load ctr with jump address */ | |
615 | rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ | |
616 | bctr /* jump into table */ | |
617 | 152: | |
618 | mfdar r11 | |
619 | mtctr r11 /* restore ctr reg from DAR */ | |
620 | mtdar r10 /* save fault EA to DAR */ | |
5bcbe24f | 621 | mfspr r10,SPRN_SPRG_SCRATCH2 |
0a2ab51f JT |
622 | b DARFixed /* Go back to normal TLB handling */ |
623 | ||
624 | /* special handling for r10,r11 since these are modified already */ | |
92625d49 | 625 | 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */ |
111e32b2 LC |
626 | add r10, r10, r11 /* add it */ |
627 | mfctr r11 /* restore r11 */ | |
628 | b 151b | |
92625d49 | 629 | 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */ |
111e32b2 | 630 | add r10, r10, r11 /* add it */ |
0a2ab51f JT |
631 | mfctr r11 /* restore r11 */ |
632 | b 151b | |
633 | #endif | |
634 | ||
14cf11af PM |
635 | /* |
636 | * This is where the main kernel code starts. | |
637 | */ | |
638 | start_here: | |
639 | /* ptr to current */ | |
640 | lis r2,init_task@h | |
641 | ori r2,r2,init_task@l | |
642 | ||
643 | /* ptr to phys current thread */ | |
644 | tophys(r4,r2) | |
645 | addi r4,r4,THREAD /* init task's THREAD */ | |
ee43eb78 | 646 | mtspr SPRN_SPRG_THREAD,r4 |
14cf11af PM |
647 | |
648 | /* stack */ | |
649 | lis r1,init_thread_union@ha | |
650 | addi r1,r1,init_thread_union@l | |
651 | li r0,0 | |
652 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
653 | ||
654 | bl early_init /* We have to do this with MMU on */ | |
655 | ||
656 | /* | |
657 | * Decide what sort of machine this is and initialize the MMU. | |
658 | */ | |
6dece0eb SW |
659 | li r3,0 |
660 | mr r4,r31 | |
14cf11af PM |
661 | bl machine_init |
662 | bl MMU_init | |
663 | ||
664 | /* | |
665 | * Go back to running unmapped so we can load up new values | |
666 | * and change to using our exception vectors. | |
667 | * On the 8xx, all we have to do is invalidate the TLB to clear | |
668 | * the old 8M byte TLB mappings and load the page table base register. | |
669 | */ | |
670 | /* The right way to do this would be to track it down through | |
671 | * init's THREAD like the context switch code does, but this is | |
672 | * easier......until someone changes init's static structures. | |
673 | */ | |
674 | lis r6, swapper_pg_dir@h | |
675 | ori r6, r6, swapper_pg_dir@l | |
676 | tophys(r6,r6) | |
677 | #ifdef CONFIG_8xx_CPU6 | |
678 | lis r4, cpu6_errata_word@h | |
679 | ori r4, r4, cpu6_errata_word@l | |
cbc130f1 | 680 | li r3, 0x3f80 |
14cf11af PM |
681 | stw r3, 12(r4) |
682 | lwz r3, 12(r4) | |
683 | #endif | |
cbc130f1 | 684 | mtspr SPRN_M_TW, r6 |
14cf11af PM |
685 | lis r4,2f@h |
686 | ori r4,r4,2f@l | |
687 | tophys(r4,r4) | |
688 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) | |
689 | mtspr SPRN_SRR0,r4 | |
690 | mtspr SPRN_SRR1,r3 | |
691 | rfi | |
692 | /* Load up the kernel context */ | |
693 | 2: | |
694 | SYNC /* Force all PTE updates to finish */ | |
695 | tlbia /* Clear all TLB entries */ | |
696 | sync /* wait for tlbia/tlbie to finish */ | |
697 | TLBSYNC /* ... on all CPUs */ | |
698 | ||
699 | /* set up the PTE pointers for the Abatron bdiGDB. | |
700 | */ | |
701 | tovirt(r6,r6) | |
702 | lis r5, abatron_pteptrs@h | |
703 | ori r5, r5, abatron_pteptrs@l | |
704 | stw r5, 0xf0(r0) /* Must match your Abatron config file */ | |
705 | tophys(r5,r5) | |
706 | stw r6, 0(r5) | |
707 | ||
708 | /* Now turn on the MMU for real! */ | |
709 | li r4,MSR_KERNEL | |
710 | lis r3,start_kernel@h | |
711 | ori r3,r3,start_kernel@l | |
712 | mtspr SPRN_SRR0,r3 | |
713 | mtspr SPRN_SRR1,r4 | |
714 | rfi /* enable MMU and jump to start_kernel */ | |
715 | ||
716 | /* Set up the initial MMU state so we can do the first level of | |
717 | * kernel initialization. This maps the first 8 MBytes of memory 1:1 | |
718 | * virtual to physical. Also, set the cache mode since that is defined | |
719 | * by TLB entries and perform any additional mapping (like of the IMMR). | |
720 | * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, | |
721 | * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by | |
722 | * these mappings is mapped by page tables. | |
723 | */ | |
724 | initial_mmu: | |
725 | tlbia /* Invalidate all TLB entries */ | |
9f4f04ba JT |
726 | /* Always pin the first 8 MB ITLB to prevent ITLB |
727 | misses while mucking around with SRR0/SRR1 in asm | |
728 | */ | |
14cf11af PM |
729 | lis r8, MI_RSV4I@h |
730 | ori r8, r8, 0x1c00 | |
9f4f04ba | 731 | |
14cf11af PM |
732 | mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ |
733 | ||
734 | #ifdef CONFIG_PIN_TLB | |
735 | lis r10, (MD_RSV4I | MD_RESETVAL)@h | |
736 | ori r10, r10, 0x1c00 | |
737 | mr r8, r10 | |
738 | #else | |
739 | lis r10, MD_RESETVAL@h | |
740 | #endif | |
741 | #ifndef CONFIG_8xx_COPYBACK | |
742 | oris r10, r10, MD_WTDEF@h | |
743 | #endif | |
744 | mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ | |
745 | ||
746 | /* Now map the lower 8 Meg into the TLBs. For this quick hack, | |
747 | * we can load the instruction and data TLB registers with the | |
748 | * same values. | |
749 | */ | |
750 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
751 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
752 | mtspr SPRN_MI_EPN, r8 | |
753 | mtspr SPRN_MD_EPN, r8 | |
754 | li r8, MI_PS8MEG /* Set 8M byte page */ | |
755 | ori r8, r8, MI_SVALID /* Make it valid */ | |
756 | mtspr SPRN_MI_TWC, r8 | |
757 | mtspr SPRN_MD_TWC, r8 | |
758 | li r8, MI_BOOTINIT /* Create RPN for address 0 */ | |
759 | mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ | |
760 | mtspr SPRN_MD_RPN, r8 | |
761 | lis r8, MI_Kp@h /* Set the protection mode */ | |
762 | mtspr SPRN_MI_AP, r8 | |
763 | mtspr SPRN_MD_AP, r8 | |
764 | ||
765 | /* Map another 8 MByte at the IMMR to get the processor | |
766 | * internal registers (among other things). | |
767 | */ | |
768 | #ifdef CONFIG_PIN_TLB | |
769 | addi r10, r10, 0x0100 | |
770 | mtspr SPRN_MD_CTR, r10 | |
771 | #endif | |
772 | mfspr r9, 638 /* Get current IMMR */ | |
773 | andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ | |
774 | ||
775 | mr r8, r9 /* Create vaddr for TLB */ | |
776 | ori r8, r8, MD_EVALID /* Mark it valid */ | |
777 | mtspr SPRN_MD_EPN, r8 | |
778 | li r8, MD_PS8MEG /* Set 8M byte page */ | |
779 | ori r8, r8, MD_SVALID /* Make it valid */ | |
780 | mtspr SPRN_MD_TWC, r8 | |
781 | mr r8, r9 /* Create paddr for TLB */ | |
782 | ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ | |
783 | mtspr SPRN_MD_RPN, r8 | |
784 | ||
785 | #ifdef CONFIG_PIN_TLB | |
786 | /* Map two more 8M kernel data pages. | |
787 | */ | |
788 | addi r10, r10, 0x0100 | |
789 | mtspr SPRN_MD_CTR, r10 | |
790 | ||
791 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
792 | addis r8, r8, 0x0080 /* Add 8M */ | |
793 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
794 | mtspr SPRN_MD_EPN, r8 | |
795 | li r9, MI_PS8MEG /* Set 8M byte page */ | |
796 | ori r9, r9, MI_SVALID /* Make it valid */ | |
797 | mtspr SPRN_MD_TWC, r9 | |
798 | li r11, MI_BOOTINIT /* Create RPN for address 0 */ | |
799 | addis r11, r11, 0x0080 /* Add 8M */ | |
ccf0d68e | 800 | mtspr SPRN_MD_RPN, r11 |
14cf11af | 801 | |
4e591f3c LC |
802 | addi r10, r10, 0x0100 |
803 | mtspr SPRN_MD_CTR, r10 | |
804 | ||
14cf11af PM |
805 | addis r8, r8, 0x0080 /* Add 8M */ |
806 | mtspr SPRN_MD_EPN, r8 | |
807 | mtspr SPRN_MD_TWC, r9 | |
808 | addis r11, r11, 0x0080 /* Add 8M */ | |
ccf0d68e | 809 | mtspr SPRN_MD_RPN, r11 |
14cf11af PM |
810 | #endif |
811 | ||
812 | /* Since the cache is enabled according to the information we | |
813 | * just loaded into the TLB, invalidate and enable the caches here. | |
814 | * We should probably check/set other modes....later. | |
815 | */ | |
816 | lis r8, IDC_INVALL@h | |
817 | mtspr SPRN_IC_CST, r8 | |
818 | mtspr SPRN_DC_CST, r8 | |
819 | lis r8, IDC_ENABLE@h | |
820 | mtspr SPRN_IC_CST, r8 | |
821 | #ifdef CONFIG_8xx_COPYBACK | |
822 | mtspr SPRN_DC_CST, r8 | |
823 | #else | |
824 | /* For a debug option, I left this here to easily enable | |
825 | * the write through cache mode | |
826 | */ | |
827 | lis r8, DC_SFWT@h | |
828 | mtspr SPRN_DC_CST, r8 | |
829 | lis r8, IDC_ENABLE@h | |
830 | mtspr SPRN_DC_CST, r8 | |
831 | #endif | |
832 | blr | |
833 | ||
834 | ||
835 | /* | |
836 | * Set up to use a given MMU context. | |
837 | * r3 is context number, r4 is PGD pointer. | |
838 | * | |
839 | * We place the physical address of the new task page directory loaded | |
840 | * into the MMU base register, and set the ASID compare register with | |
841 | * the new "context." | |
842 | */ | |
843 | _GLOBAL(set_context) | |
844 | ||
845 | #ifdef CONFIG_BDI_SWITCH | |
846 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
847 | * The PGDIR is passed as second argument. | |
848 | */ | |
849 | lis r5, KERNELBASE@h | |
850 | lwz r5, 0xf0(r5) | |
851 | stw r4, 0x4(r5) | |
852 | #endif | |
853 | ||
854 | #ifdef CONFIG_8xx_CPU6 | |
855 | lis r6, cpu6_errata_word@h | |
856 | ori r6, r6, cpu6_errata_word@l | |
857 | tophys (r4, r4) | |
cbc130f1 | 858 | li r7, 0x3f80 |
14cf11af PM |
859 | stw r7, 12(r6) |
860 | lwz r7, 12(r6) | |
cbc130f1 | 861 | mtspr SPRN_M_TW, r4 /* Update MMU base address */ |
14cf11af PM |
862 | li r7, 0x3380 |
863 | stw r7, 12(r6) | |
864 | lwz r7, 12(r6) | |
865 | mtspr SPRN_M_CASID, r3 /* Update context */ | |
866 | #else | |
867 | mtspr SPRN_M_CASID,r3 /* Update context */ | |
868 | tophys (r4, r4) | |
cbc130f1 | 869 | mtspr SPRN_M_TW, r4 /* and pgd */ |
14cf11af PM |
870 | #endif |
871 | SYNC | |
872 | blr | |
873 | ||
874 | #ifdef CONFIG_8xx_CPU6 | |
875 | /* It's here because it is unique to the 8xx. | |
876 | * It is important we get called with interrupts disabled. I used to | |
877 | * do that, but it appears that all code that calls this already had | |
878 | * interrupt disabled. | |
879 | */ | |
880 | .globl set_dec_cpu6 | |
881 | set_dec_cpu6: | |
882 | lis r7, cpu6_errata_word@h | |
883 | ori r7, r7, cpu6_errata_word@l | |
884 | li r4, 0x2c00 | |
885 | stw r4, 8(r7) | |
886 | lwz r4, 8(r7) | |
887 | mtspr 22, r3 /* Update Decrementer */ | |
888 | SYNC | |
889 | blr | |
890 | #endif | |
891 | ||
892 | /* | |
893 | * We put a few things here that have to be page-aligned. | |
894 | * This stuff goes at the beginning of the data segment, | |
895 | * which is page-aligned. | |
896 | */ | |
897 | .data | |
898 | .globl sdata | |
899 | sdata: | |
900 | .globl empty_zero_page | |
d1406803 | 901 | .align PAGE_SHIFT |
14cf11af | 902 | empty_zero_page: |
d1406803 | 903 | .space PAGE_SIZE |
14cf11af PM |
904 | |
905 | .globl swapper_pg_dir | |
906 | swapper_pg_dir: | |
d1406803 | 907 | .space PGD_TABLE_SIZE |
14cf11af | 908 | |
14cf11af PM |
909 | /* Room for two PTE table poiners, usually the kernel and current user |
910 | * pointer to their respective root page table (pgdir). | |
911 | */ | |
912 | abatron_pteptrs: | |
913 | .space 8 | |
914 | ||
915 | #ifdef CONFIG_8xx_CPU6 | |
916 | .globl cpu6_errata_word | |
917 | cpu6_errata_word: | |
918 | .space 16 | |
919 | #endif | |
920 |