projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 14cf11af | 1 | /* |
| 14cf11af PM |
2 | * PowerPC version |
| 3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
| 4 | * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP | |
| 5 | * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> | |
| 6 | * Low-level exception handlers and MMU support | |
| 7 | * rewritten by Paul Mackerras. | |
| 8 | * Copyright (C) 1996 Paul Mackerras. | |
| 9 | * MPC8xx modifications by Dan Malek | |
| 10 | * Copyright (C) 1997 Dan Malek (dmalek@jlc.net). | |
| 11 | * | |
| 12 | * This file contains low-level support and setup for PowerPC 8xx | |
| 13 | * embedded processors, including trap and interrupt dispatch. | |
| 14 | * | |
| 15 | * This program is free software; you can redistribute it and/or | |
| 16 | * modify it under the terms of the GNU General Public License | |
| 17 | * as published by the Free Software Foundation; either version | |
| 18 | * 2 of the License, or (at your option) any later version. | |
| 19 | * | |
| 20 | */ | |
| 21 | ||
| e7039845 | 22 | #include <linux/init.h> |
| 14cf11af PM |
23 | #include <asm/processor.h> |
| 24 | #include <asm/page.h> | |
| 25 | #include <asm/mmu.h> | |
| 26 | #include <asm/cache.h> | |
| 27 | #include <asm/pgtable.h> | |
| 28 | #include <asm/cputable.h> | |
| 29 | #include <asm/thread_info.h> | |
| 30 | #include <asm/ppc_asm.h> | |
| 31 | #include <asm/asm-offsets.h> | |
| 32 | ||
| 33 | /* Macro to make the code more readable. */ | |
| 34 | #ifdef CONFIG_8xx_CPU6 | |
| 35 | #define DO_8xx_CPU6(val, reg) \ | |
| 36 | li reg, val; \ | |
| 37 | stw reg, 12(r0); \ | |
| 38 | lwz reg, 12(r0); | |
| 39 | #else | |
| 40 | #define DO_8xx_CPU6(val, reg) | |
| 41 | #endif | |
| e7039845 | 42 | __HEAD |
| 748a7683 KG |
43 | _ENTRY(_stext); |
| 44 | _ENTRY(_start); | |
| 14cf11af PM |
45 | |
| 46 | /* MPC8xx | |
| 47 | * This port was done on an MBX board with an 860. Right now I only | |
| 48 | * support an ELF compressed (zImage) boot from EPPC-Bug because the | |
| 49 | * code there loads up some registers before calling us: | |
| 50 | * r3: ptr to board info data | |
| 51 | * r4: initrd_start or if no initrd then 0 | |
| 52 | * r5: initrd_end - unused if r4 is 0 | |
| 53 | * r6: Start of command line string | |
| 54 | * r7: End of command line string | |
| 55 | * | |
| 56 | * I decided to use conditional compilation instead of checking PVR and | |
| 57 | * adding more processor specific branches around code I don't need. | |
| 58 | * Since this is an embedded processor, I also appreciate any memory | |
| 59 | * savings I can get. | |
| 60 | * | |
| 61 | * The MPC8xx does not have any BATs, but it supports large page sizes. | |
| 62 | * We first initialize the MMU to support 8M byte pages, then load one | |
| 63 | * entry into each of the instruction and data TLBs to map the first | |
| 64 | * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to | |
| 65 | * the "internal" processor registers before MMU_init is called. | |
| 66 | * | |
| 67 | * The TLB code currently contains a major hack. Since I use the condition | |
| 68 | * code register, I have to save and restore it. I am out of registers, so | |
| 69 | * I just store it in memory location 0 (the TLB handlers are not reentrant). | |
| 70 | * To avoid making any decisions, I need to use the "segment" valid bit | |
| 71 | * in the first level table, but that would require many changes to the | |
| 72 | * Linux page directory/table functions that I don't want to do right now. | |
| 73 | * | |
| 74 | * I used to use SPRG2 for a temporary register in the TLB handler, but it | |
| 75 | * has since been put to other uses. I now use a hack to save a register | |
| 76 | * and the CCR at memory location 0.....Someday I'll fix this..... | |
| 77 | * -- Dan | |
| 78 | */ | |
| 79 | .globl __start | |
| 80 | __start: | |
| 81 | mr r31,r3 /* save parameters */ | |
| 82 | mr r30,r4 | |
| 83 | mr r29,r5 | |
| 84 | mr r28,r6 | |
| 85 | mr r27,r7 | |
| 86 | ||
| 87 | /* We have to turn on the MMU right away so we get cache modes | |
| 88 | * set correctly. | |
| 89 | */ | |
| 90 | bl initial_mmu | |
| 91 | ||
| 92 | /* We now have the lower 8 Meg mapped into TLB entries, and the caches | |
| 93 | * ready to work. | |
| 94 | */ | |
| 95 | ||
| 96 | turn_on_mmu: | |
| 97 | mfmsr r0 | |
| 98 | ori r0,r0,MSR_DR|MSR_IR | |
| 99 | mtspr SPRN_SRR1,r0 | |
| 100 | lis r0,start_here@h | |
| 101 | ori r0,r0,start_here@l | |
| 102 | mtspr SPRN_SRR0,r0 | |
| 103 | SYNC | |
| 104 | rfi /* enables MMU */ | |
| 105 | ||
| 106 | /* | |
| 107 | * Exception entry code. This code runs with address translation | |
| 108 | * turned off, i.e. using physical addresses. | |
| 109 | * We assume sprg3 has the physical address of the current | |
| 110 | * task's thread_struct. | |
| 111 | */ | |
| 112 | #define EXCEPTION_PROLOG \ | |
| ee43eb78 BH |
113 | mtspr SPRN_SPRG_SCRATCH0,r10; \ |
| 114 | mtspr SPRN_SPRG_SCRATCH1,r11; \ | |
| 14cf11af PM |
115 | mfcr r10; \ |
| 116 | EXCEPTION_PROLOG_1; \ | |
| 117 | EXCEPTION_PROLOG_2 | |
| 118 | ||
| 119 | #define EXCEPTION_PROLOG_1 \ | |
| 120 | mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ | |
| 121 | andi. r11,r11,MSR_PR; \ | |
| 122 | tophys(r11,r1); /* use tophys(r1) if kernel */ \ | |
| 123 | beq 1f; \ | |
| ee43eb78 | 124 | mfspr r11,SPRN_SPRG_THREAD; \ |
| 14cf11af PM |
125 | lwz r11,THREAD_INFO-THREAD(r11); \ |
| 126 | addi r11,r11,THREAD_SIZE; \ | |
| 127 | tophys(r11,r11); \ | |
| 128 | 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */ | |
| 129 | ||
| 130 | ||
| 131 | #define EXCEPTION_PROLOG_2 \ | |
| 132 | CLR_TOP32(r11); \ | |
| 133 | stw r10,_CCR(r11); /* save registers */ \ | |
| 134 | stw r12,GPR12(r11); \ | |
| 135 | stw r9,GPR9(r11); \ | |
| ee43eb78 | 136 | mfspr r10,SPRN_SPRG_SCRATCH0; \ |
| 14cf11af | 137 | stw r10,GPR10(r11); \ |
| ee43eb78 | 138 | mfspr r12,SPRN_SPRG_SCRATCH1; \ |
| 14cf11af PM |
139 | stw r12,GPR11(r11); \ |
| 140 | mflr r10; \ | |
| 141 | stw r10,_LINK(r11); \ | |
| 142 | mfspr r12,SPRN_SRR0; \ | |
| 143 | mfspr r9,SPRN_SRR1; \ | |
| 144 | stw r1,GPR1(r11); \ | |
| 145 | stw r1,0(r11); \ | |
| 146 | tovirt(r1,r11); /* set new kernel sp */ \ | |
| 147 | li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \ | |
| 148 | MTMSRD(r10); /* (except for mach check in rtas) */ \ | |
| 149 | stw r0,GPR0(r11); \ | |
| 150 | SAVE_4GPRS(3, r11); \ | |
| 151 | SAVE_2GPRS(7, r11) | |
| 152 | ||
| 153 | /* | |
| 154 | * Note: code which follows this uses cr0.eq (set if from kernel), | |
| 155 | * r11, r12 (SRR0), and r9 (SRR1). | |
| 156 | * | |
| 157 | * Note2: once we have set r1 we are in a position to take exceptions | |
| 158 | * again, and we could thus set MSR:RI at that point. | |
| 159 | */ | |
| 160 | ||
| 161 | /* | |
| 162 | * Exception vectors. | |
| 163 | */ | |
| 164 | #define EXCEPTION(n, label, hdlr, xfer) \ | |
| 165 | . = n; \ | |
| 166 | label: \ | |
| 167 | EXCEPTION_PROLOG; \ | |
| 168 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | |
| 169 | xfer(n, hdlr) | |
| 170 | ||
| 171 | #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \ | |
| 172 | li r10,trap; \ | |
| d73e0c99 | 173 | stw r10,_TRAP(r11); \ |
| 14cf11af PM |
174 | li r10,MSR_KERNEL; \ |
| 175 | copyee(r10, r9); \ | |
| 176 | bl tfer; \ | |
| 177 | i##n: \ | |
| 178 | .long hdlr; \ | |
| 179 | .long ret | |
| 180 | ||
| 181 | #define COPY_EE(d, s) rlwimi d,s,0,16,16 | |
| 182 | #define NOCOPY(d, s) | |
| 183 | ||
| 184 | #define EXC_XFER_STD(n, hdlr) \ | |
| 185 | EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \ | |
| 186 | ret_from_except_full) | |
| 187 | ||
| 188 | #define EXC_XFER_LITE(n, hdlr) \ | |
| 189 | EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \ | |
| 190 | ret_from_except) | |
| 191 | ||
| 192 | #define EXC_XFER_EE(n, hdlr) \ | |
| 193 | EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \ | |
| 194 | ret_from_except_full) | |
| 195 | ||
| 196 | #define EXC_XFER_EE_LITE(n, hdlr) \ | |
| 197 | EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \ | |
| 198 | ret_from_except) | |
| 199 | ||
| 200 | /* System reset */ | |
| dc1c1ca3 | 201 | EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD) |
| 14cf11af PM |
202 | |
| 203 | /* Machine check */ | |
| 204 | . = 0x200 | |
| 205 | MachineCheck: | |
| 206 | EXCEPTION_PROLOG | |
| 207 | mfspr r4,SPRN_DAR | |
| 208 | stw r4,_DAR(r11) | |
| 60e071fe JT |
209 | li r5,0x00f0 |
| 210 | mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ | |
| 14cf11af PM |
211 | mfspr r5,SPRN_DSISR |
| 212 | stw r5,_DSISR(r11) | |
| 213 | addi r3,r1,STACK_FRAME_OVERHEAD | |
| dc1c1ca3 | 214 | EXC_XFER_STD(0x200, machine_check_exception) |
| 14cf11af PM |
215 | |
| 216 | /* Data access exception. | |
| 217 | * This is "never generated" by the MPC8xx. We jump to it for other | |
| 218 | * translation errors. | |
| 219 | */ | |
| 220 | . = 0x300 | |
| 221 | DataAccess: | |
| 222 | EXCEPTION_PROLOG | |
| 223 | mfspr r10,SPRN_DSISR | |
| 224 | stw r10,_DSISR(r11) | |
| 225 | mr r5,r10 | |
| 226 | mfspr r4,SPRN_DAR | |
| 60e071fe JT |
227 | li r10,0x00f0 |
| 228 | mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */ | |
| 14cf11af PM |
229 | EXC_XFER_EE_LITE(0x300, handle_page_fault) |
| 230 | ||
| 231 | /* Instruction access exception. | |
| 232 | * This is "never generated" by the MPC8xx. We jump to it for other | |
| 233 | * translation errors. | |
| 234 | */ | |
| 235 | . = 0x400 | |
| 236 | InstructionAccess: | |
| 237 | EXCEPTION_PROLOG | |
| 238 | mr r4,r12 | |
| 239 | mr r5,r9 | |
| 240 | EXC_XFER_EE_LITE(0x400, handle_page_fault) | |
| 241 | ||
| 242 | /* External interrupt */ | |
| 243 | EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE) | |
| 244 | ||
| 245 | /* Alignment exception */ | |
| 246 | . = 0x600 | |
| 247 | Alignment: | |
| 248 | EXCEPTION_PROLOG | |
| 249 | mfspr r4,SPRN_DAR | |
| 250 | stw r4,_DAR(r11) | |
| 60e071fe JT |
251 | li r5,0x00f0 |
| 252 | mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */ | |
| 14cf11af PM |
253 | mfspr r5,SPRN_DSISR |
| 254 | stw r5,_DSISR(r11) | |
| 255 | addi r3,r1,STACK_FRAME_OVERHEAD | |
| dc1c1ca3 | 256 | EXC_XFER_EE(0x600, alignment_exception) |
| 14cf11af PM |
257 | |
| 258 | /* Program check exception */ | |
| dc1c1ca3 | 259 | EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD) |
| 14cf11af PM |
260 | |
| 261 | /* No FPU on MPC8xx. This exception is not supposed to happen. | |
| 262 | */ | |
| dc1c1ca3 | 263 | EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD) |
| 14cf11af PM |
264 | |
| 265 | /* Decrementer */ | |
| 266 | EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE) | |
| 267 | ||
| dc1c1ca3 SR |
268 | EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE) |
| 269 | EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE) | |
| 14cf11af PM |
270 | |
| 271 | /* System call */ | |
| 272 | . = 0xc00 | |
| 273 | SystemCall: | |
| 274 | EXCEPTION_PROLOG | |
| 275 | EXC_XFER_EE_LITE(0xc00, DoSyscall) | |
| 276 | ||
| 277 | /* Single step - not used on 601 */ | |
| dc1c1ca3 SR |
278 | EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD) |
| 279 | EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE) | |
| 280 | EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE) | |
| 14cf11af PM |
281 | |
| 282 | /* On the MPC8xx, this is a software emulation interrupt. It occurs | |
| 283 | * for all unimplemented and illegal instructions. | |
| 284 | */ | |
| 285 | EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD) | |
| 286 | ||
| 287 | . = 0x1100 | |
| 288 | /* | |
| 289 | * For the MPC8xx, this is a software tablewalk to load the instruction | |
| 290 | * TLB. It is modelled after the example in the Motorola manual. The task | |
| 291 | * switch loads the M_TWB register with the pointer to the first level table. | |
| 292 | * If we discover there is no second level table (value is zero) or if there | |
| 293 | * is an invalid pte, we load that into the TLB, which causes another fault | |
| 294 | * into the TLB Error interrupt where we can handle such problems. | |
| 295 | * We have to use the MD_xxx registers for the tablewalk because the | |
| 296 | * equivalent MI_xxx registers only perform the attribute functions. | |
| 297 | */ | |
| 298 | InstructionTLBMiss: | |
| 299 | #ifdef CONFIG_8xx_CPU6 | |
| 300 | stw r3, 8(r0) | |
| 301 | #endif | |
| 302 | DO_8xx_CPU6(0x3f80, r3) | |
| 303 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
| 304 | mfcr r10 | |
| 305 | stw r10, 0(r0) | |
| 306 | stw r11, 4(r0) | |
| 307 | mfspr r10, SPRN_SRR0 /* Get effective address of fault */ | |
| 74016852 SW |
308 | #ifdef CONFIG_8xx_CPU15 |
| 309 | addi r11, r10, 0x1000 | |
| 310 | tlbie r11 | |
| 311 | addi r11, r10, -0x1000 | |
| 312 | tlbie r11 | |
| 313 | #endif | |
| 14cf11af PM |
314 | DO_8xx_CPU6(0x3780, r3) |
| 315 | mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ | |
| 316 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
| 317 | ||
| 318 | /* If we are faulting a kernel address, we have to use the | |
| 319 | * kernel page tables. | |
| 320 | */ | |
| 4afb0be7 JT |
321 | #ifdef CONFIG_MODULES |
| 322 | /* Only modules will cause ITLB Misses as we always | |
| 323 | * pin the first 8MB of kernel memory */ | |
| 14cf11af PM |
324 | andi. r11, r10, 0x0800 /* Address >= 0x80000000 */ |
| 325 | beq 3f | |
| 326 | lis r11, swapper_pg_dir@h | |
| 327 | ori r11, r11, swapper_pg_dir@l | |
| 328 | rlwimi r10, r11, 0, 2, 19 | |
| 329 | 3: | |
| 4afb0be7 | 330 | #endif |
| 14cf11af PM |
331 | lwz r11, 0(r10) /* Get the level 1 entry */ |
| 332 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
| 333 | beq 2f /* If zero, don't try to find a pte */ | |
| 334 | ||
| 335 | /* We have a pte table, so load the MI_TWC with the attributes | |
| 336 | * for this "segment." | |
| 337 | */ | |
| 338 | ori r11,r11,1 /* Set valid bit */ | |
| 339 | DO_8xx_CPU6(0x2b80, r3) | |
| 340 | mtspr SPRN_MI_TWC, r11 /* Set segment attributes */ | |
| 341 | DO_8xx_CPU6(0x3b80, r3) | |
| 342 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
| 343 | mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ | |
| 344 | lwz r10, 0(r11) /* Get the pte */ | |
| 345 | ||
| d069cb43 | 346 | #ifdef CONFIG_SWAP |
| fe11dc3f JT |
347 | andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT |
| 348 | cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT | |
| 349 | bne- cr0, 2f | |
| d069cb43 | 350 | #endif |
| 14cf11af | 351 | /* The Linux PTE won't go exactly into the MMU TLB. |
| fe1691e3 | 352 | * Software indicator bits 21 and 28 must be clear. |
| 14cf11af PM |
353 | * Software indicator bits 24, 25, 26, and 27 must be |
| 354 | * set. All other Linux PTE bits control the behavior | |
| 355 | * of the MMU. | |
| 356 | */ | |
| fe11dc3f | 357 | li r11, 0x00f0 |
| fe1691e3 | 358 | rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */ |
| 14cf11af PM |
359 | DO_8xx_CPU6(0x2d80, r3) |
| 360 | mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ | |
| 361 | ||
| 362 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
| 363 | lwz r11, 0(r0) | |
| 364 | mtcr r11 | |
| 365 | lwz r11, 4(r0) | |
| 366 | #ifdef CONFIG_8xx_CPU6 | |
| 367 | lwz r3, 8(r0) | |
| 368 | #endif | |
| 369 | rfi | |
| fe11dc3f JT |
370 | 2: |
| 371 | mfspr r11, SPRN_SRR1 | |
| 372 | /* clear all error bits as TLB Miss | |
| 373 | * sets a few unconditionally | |
| 374 | */ | |
| 375 | rlwinm r11, r11, 0, 0xffff | |
| 376 | mtspr SPRN_SRR1, r11 | |
| 377 | ||
| 378 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
| 379 | lwz r11, 0(r0) | |
| 380 | mtcr r11 | |
| 381 | lwz r11, 4(r0) | |
| 382 | #ifdef CONFIG_8xx_CPU6 | |
| 383 | lwz r3, 8(r0) | |
| 384 | #endif | |
| 385 | b InstructionAccess | |
| 14cf11af PM |
386 | |
| 387 | . = 0x1200 | |
| 388 | DataStoreTLBMiss: | |
| 389 | #ifdef CONFIG_8xx_CPU6 | |
| 390 | stw r3, 8(r0) | |
| 391 | #endif | |
| 392 | DO_8xx_CPU6(0x3f80, r3) | |
| 393 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
| 394 | mfcr r10 | |
| 395 | stw r10, 0(r0) | |
| 396 | stw r11, 4(r0) | |
| 397 | mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ | |
| 398 | ||
| 399 | /* If we are faulting a kernel address, we have to use the | |
| 400 | * kernel page tables. | |
| 401 | */ | |
| 402 | andi. r11, r10, 0x0800 | |
| 403 | beq 3f | |
| 404 | lis r11, swapper_pg_dir@h | |
| 405 | ori r11, r11, swapper_pg_dir@l | |
| 406 | rlwimi r10, r11, 0, 2, 19 | |
| 407 | 3: | |
| 408 | lwz r11, 0(r10) /* Get the level 1 entry */ | |
| 409 | rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */ | |
| 410 | beq 2f /* If zero, don't try to find a pte */ | |
| 411 | ||
| 412 | /* We have a pte table, so load fetch the pte from the table. | |
| 413 | */ | |
| 414 | ori r11, r11, 1 /* Set valid bit in physical L2 page */ | |
| 415 | DO_8xx_CPU6(0x3b80, r3) | |
| 416 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
| 417 | mfspr r10, SPRN_MD_TWC /* ....and get the pte address */ | |
| 418 | lwz r10, 0(r10) /* Get the pte */ | |
| 419 | ||
| 420 | /* Insert the Guarded flag into the TWC from the Linux PTE. | |
| 421 | * It is bit 27 of both the Linux PTE and the TWC (at least | |
| 422 | * I got that right :-). It will be better when we can put | |
| 423 | * this into the Linux pgd/pmd and load it in the operation | |
| 424 | * above. | |
| 425 | */ | |
| 426 | rlwimi r11, r10, 0, 27, 27 | |
| 0c466169 JT |
427 | /* Insert the WriteThru flag into the TWC from the Linux PTE. |
| 428 | * It is bit 25 in the Linux PTE and bit 30 in the TWC | |
| 429 | */ | |
| 430 | rlwimi r11, r10, 32-5, 30, 30 | |
| 14cf11af PM |
431 | DO_8xx_CPU6(0x3b80, r3) |
| 432 | mtspr SPRN_MD_TWC, r11 | |
| 433 | ||
| fe11dc3f JT |
434 | /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set. |
| 435 | * We also need to know if the insn is a load/store, so: | |
| 436 | * Clear _PAGE_PRESENT and load that which will | |
| 437 | * trap into DTLB Error with store bit set accordinly. | |
| 438 | */ | |
| 439 | /* PRESENT=0x1, ACCESSED=0x20 | |
| 440 | * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5)); | |
| 441 | * r10 = (r10 & ~PRESENT) | r11; | |
| 442 | */ | |
| d069cb43 | 443 | #ifdef CONFIG_SWAP |
| 990d89c6 | 444 | rlwinm r11, r10, 32-5, _PAGE_PRESENT |
| fe11dc3f | 445 | and r11, r11, r10 |
| 990d89c6 | 446 | rlwimi r10, r11, 0, _PAGE_PRESENT |
| d069cb43 | 447 | #endif |
| fe11dc3f | 448 | /* Honour kernel RO, User NA */ |
| 990d89c6 | 449 | /* 0x200 == Extended encoding, bit 22 */ |
| fe1691e3 | 450 | rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */ |
| 990d89c6 JT |
451 | /* r11 = (r10 & _PAGE_RW) >> 1 */ |
| 452 | rlwinm r11, r10, 32-1, 0x200 | |
| 453 | or r10, r11, r10 | |
| 454 | /* invert RW and 0x200 bits */ | |
| 455 | xori r10, r10, _PAGE_RW | 0x200 | |
| 14cf11af PM |
456 | |
| 457 | /* The Linux PTE won't go exactly into the MMU TLB. | |
| fe11dc3f | 458 | * Software indicator bits 22 and 28 must be clear. |
| 14cf11af PM |
459 | * Software indicator bits 24, 25, 26, and 27 must be |
| 460 | * set. All other Linux PTE bits control the behavior | |
| 461 | * of the MMU. | |
| 462 | */ | |
| 463 | 2: li r11, 0x00f0 | |
| 60e071fe | 464 | mtspr SPRN_DAR,r11 /* Tag DAR */ |
| 14cf11af PM |
465 | rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ |
| 466 | DO_8xx_CPU6(0x3d80, r3) | |
| 467 | mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ | |
| 468 | ||
| 469 | mfspr r10, SPRN_M_TW /* Restore registers */ | |
| 470 | lwz r11, 0(r0) | |
| 471 | mtcr r11 | |
| 472 | lwz r11, 4(r0) | |
| 473 | #ifdef CONFIG_8xx_CPU6 | |
| 474 | lwz r3, 8(r0) | |
| 475 | #endif | |
| 476 | rfi | |
| 477 | ||
| 478 | /* This is an instruction TLB error on the MPC8xx. This could be due | |
| 479 | * to many reasons, such as executing guarded memory or illegal instruction | |
| 480 | * addresses. There is nothing to do but handle a big time error fault. | |
| 481 | */ | |
| 482 | . = 0x1300 | |
| 483 | InstructionTLBError: | |
| 484 | b InstructionAccess | |
| 485 | ||
| 486 | /* This is the data TLB error on the MPC8xx. This could be due to | |
| 487 | * many reasons, including a dirty update to a pte. We can catch that | |
| 488 | * one here, but anything else is an error. First, we track down the | |
| 489 | * Linux pte. If it is valid, write access is allowed, but the | |
| 490 | * page dirty bit is not set, we will set it and reload the TLB. For | |
| 491 | * any other case, we bail out to a higher level function that can | |
| 492 | * handle it. | |
| 493 | */ | |
| 494 | . = 0x1400 | |
| 495 | DataTLBError: | |
| 496 | #ifdef CONFIG_8xx_CPU6 | |
| 497 | stw r3, 8(r0) | |
| 498 | #endif | |
| 499 | DO_8xx_CPU6(0x3f80, r3) | |
| 500 | mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ | |
| 501 | mfcr r10 | |
| 502 | stw r10, 0(r0) | |
| 503 | stw r11, 4(r0) | |
| 504 | ||
| 60e071fe JT |
505 | mfspr r10, SPRN_DAR |
| 506 | cmpwi cr0, r10, 0x00f0 | |
| 0a2ab51f JT |
507 | beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ |
| 508 | DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ | |
| 14cf11af PM |
509 | mfspr r10, SPRN_M_TW /* Restore registers */ |
| 510 | lwz r11, 0(r0) | |
| 511 | mtcr r11 | |
| 512 | lwz r11, 4(r0) | |
| 513 | #ifdef CONFIG_8xx_CPU6 | |
| 514 | lwz r3, 8(r0) | |
| 515 | #endif | |
| 516 | b DataAccess | |
| 517 | ||
| dc1c1ca3 SR |
518 | EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) |
| 519 | EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE) | |
| 520 | EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE) | |
| 521 | EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE) | |
| 522 | EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE) | |
| 523 | EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE) | |
| 524 | EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE) | |
| 14cf11af PM |
525 | |
| 526 | /* On the MPC8xx, these next four traps are used for development | |
| 527 | * support of breakpoints and such. Someday I will get around to | |
| 528 | * using them. | |
| 529 | */ | |
| dc1c1ca3 SR |
530 | EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE) |
| 531 | EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE) | |
| 532 | EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE) | |
| 533 | EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE) | |
| 14cf11af PM |
534 | |
| 535 | . = 0x2000 | |
| 536 | ||
| 0a2ab51f JT |
537 | /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions |
| 538 | * by decoding the registers used by the dcbx instruction and adding them. | |
| 539 | * DAR is set to the calculated address and r10 also holds the EA on exit. | |
| 540 | */ | |
| 541 | /* define if you don't want to use self modifying code */ | |
| 542 | #define NO_SELF_MODIFYING_CODE | |
| 543 | FixupDAR:/* Entry point for dcbx workaround. */ | |
| 544 | /* fetch instruction from memory. */ | |
| 545 | mfspr r10, SPRN_SRR0 | |
| 061ec959 | 546 | andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ |
| 0a2ab51f JT |
547 | DO_8xx_CPU6(0x3780, r3) |
| 548 | mtspr SPRN_MD_EPN, r10 | |
| 549 | mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ | |
| 061ec959 | 550 | beq- 3f /* Branch if user space */ |
| 0a2ab51f JT |
551 | lis r11, (swapper_pg_dir-PAGE_OFFSET)@h |
| 552 | ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l | |
| 553 | rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ | |
| 554 | 3: lwz r11, 0(r11) /* Get the level 1 entry */ | |
| 555 | DO_8xx_CPU6(0x3b80, r3) | |
| 556 | mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ | |
| 557 | mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ | |
| 558 | lwz r11, 0(r11) /* Get the pte */ | |
| 559 | /* concat physical page address(r11) and page offset(r10) */ | |
| 560 | rlwimi r11, r10, 0, 20, 31 | |
| 561 | lwz r11,0(r11) | |
| 562 | /* Check if it really is a dcbx instruction. */ | |
| 563 | /* dcbt and dcbtst does not generate DTLB Misses/Errors, | |
| 564 | * no need to include them here */ | |
| 565 | srwi r10, r11, 26 /* check if major OP code is 31 */ | |
| 566 | cmpwi cr0, r10, 31 | |
| 567 | bne- 141f | |
| 568 | rlwinm r10, r11, 0, 21, 30 | |
| 569 | cmpwi cr0, r10, 2028 /* Is dcbz? */ | |
| 570 | beq+ 142f | |
| 571 | cmpwi cr0, r10, 940 /* Is dcbi? */ | |
| 572 | beq+ 142f | |
| 573 | cmpwi cr0, r10, 108 /* Is dcbst? */ | |
| 574 | beq+ 144f /* Fix up store bit! */ | |
| 575 | cmpwi cr0, r10, 172 /* Is dcbf? */ | |
| 576 | beq+ 142f | |
| 577 | cmpwi cr0, r10, 1964 /* Is icbi? */ | |
| 578 | beq+ 142f | |
| 579 | 141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ | |
| 580 | b DARFixed /* Nope, go back to normal TLB processing */ | |
| 581 | ||
| 582 | 144: mfspr r10, SPRN_DSISR | |
| 583 | rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ | |
| 584 | mtspr SPRN_DSISR, r10 | |
| 585 | 142: /* continue, it was a dcbx, dcbi instruction. */ | |
| 586 | #ifdef CONFIG_8xx_CPU6 | |
| 587 | lwz r3, 8(r0) /* restore r3 from memory */ | |
| 588 | #endif | |
| 589 | #ifndef NO_SELF_MODIFYING_CODE | |
| 590 | andis. r10,r11,0x1f /* test if reg RA is r0 */ | |
| 591 | li r10,modified_instr@l | |
| 592 | dcbtst r0,r10 /* touch for store */ | |
| 593 | rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */ | |
| 594 | oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */ | |
| 595 | ori r11,r11,532 | |
| 596 | stw r11,0(r10) /* store add/and instruction */ | |
| 597 | dcbf 0,r10 /* flush new instr. to memory. */ | |
| 598 | icbi 0,r10 /* invalidate instr. cache line */ | |
| 599 | lwz r11, 4(r0) /* restore r11 from memory */ | |
| 600 | mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ | |
| 601 | isync /* Wait until new instr is loaded from memory */ | |
| 602 | modified_instr: | |
| 603 | .space 4 /* this is where the add instr. is stored */ | |
| 604 | bne+ 143f | |
| 605 | subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ | |
| 606 | 143: mtdar r10 /* store faulting EA in DAR */ | |
| 607 | b DARFixed /* Go back to normal TLB handling */ | |
| 608 | #else | |
| 609 | mfctr r10 | |
| 610 | mtdar r10 /* save ctr reg in DAR */ | |
| 611 | rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */ | |
| 612 | addi r10, r10, 150f@l /* add start of table */ | |
| 613 | mtctr r10 /* load ctr with jump address */ | |
| 614 | xor r10, r10, r10 /* sum starts at zero */ | |
| 615 | bctr /* jump into table */ | |
| 616 | 150: | |
| 617 | add r10, r10, r0 ;b 151f | |
| 618 | add r10, r10, r1 ;b 151f | |
| 619 | add r10, r10, r2 ;b 151f | |
| 620 | add r10, r10, r3 ;b 151f | |
| 621 | add r10, r10, r4 ;b 151f | |
| 622 | add r10, r10, r5 ;b 151f | |
| 623 | add r10, r10, r6 ;b 151f | |
| 624 | add r10, r10, r7 ;b 151f | |
| 625 | add r10, r10, r8 ;b 151f | |
| 626 | add r10, r10, r9 ;b 151f | |
| 627 | mtctr r11 ;b 154f /* r10 needs special handling */ | |
| 628 | mtctr r11 ;b 153f /* r11 needs special handling */ | |
| 629 | add r10, r10, r12 ;b 151f | |
| 630 | add r10, r10, r13 ;b 151f | |
| 631 | add r10, r10, r14 ;b 151f | |
| 632 | add r10, r10, r15 ;b 151f | |
| 633 | add r10, r10, r16 ;b 151f | |
| 634 | add r10, r10, r17 ;b 151f | |
| 635 | add r10, r10, r18 ;b 151f | |
| 636 | add r10, r10, r19 ;b 151f | |
| 637 | add r10, r10, r20 ;b 151f | |
| 638 | add r10, r10, r21 ;b 151f | |
| 639 | add r10, r10, r22 ;b 151f | |
| 640 | add r10, r10, r23 ;b 151f | |
| 641 | add r10, r10, r24 ;b 151f | |
| 642 | add r10, r10, r25 ;b 151f | |
| 643 | add r10, r10, r26 ;b 151f | |
| 644 | add r10, r10, r27 ;b 151f | |
| 645 | add r10, r10, r28 ;b 151f | |
| 646 | add r10, r10, r29 ;b 151f | |
| 647 | add r10, r10, r30 ;b 151f | |
| 648 | add r10, r10, r31 | |
| 649 | 151: | |
| 650 | rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */ | |
| 651 | beq 152f /* if reg RA is zero, don't add it */ | |
| 652 | addi r11, r11, 150b@l /* add start of table */ | |
| 653 | mtctr r11 /* load ctr with jump address */ | |
| 654 | rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */ | |
| 655 | bctr /* jump into table */ | |
| 656 | 152: | |
| 657 | mfdar r11 | |
| 658 | mtctr r11 /* restore ctr reg from DAR */ | |
| 659 | mtdar r10 /* save fault EA to DAR */ | |
| 660 | b DARFixed /* Go back to normal TLB handling */ | |
| 661 | ||
| 662 | /* special handling for r10,r11 since these are modified already */ | |
| 663 | 153: lwz r11, 4(r0) /* load r11 from memory */ | |
| 664 | b 155f | |
| 665 | 154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */ | |
| 666 | 155: add r10, r10, r11 /* add it */ | |
| 667 | mfctr r11 /* restore r11 */ | |
| 668 | b 151b | |
| 669 | #endif | |
| 670 | ||
| 14cf11af PM |
671 | .globl giveup_fpu |
| 672 | giveup_fpu: | |
| 673 | blr | |
| 674 | ||
| 675 | /* | |
| 676 | * This is where the main kernel code starts. | |
| 677 | */ | |
| 678 | start_here: | |
| 679 | /* ptr to current */ | |
| 680 | lis r2,init_task@h | |
| 681 | ori r2,r2,init_task@l | |
| 682 | ||
| 683 | /* ptr to phys current thread */ | |
| 684 | tophys(r4,r2) | |
| 685 | addi r4,r4,THREAD /* init task's THREAD */ | |
| ee43eb78 | 686 | mtspr SPRN_SPRG_THREAD,r4 |
| 14cf11af | 687 | li r3,0 |
| ee43eb78 | 688 | /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */ |
| 14cf11af PM |
689 | mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */ |
| 690 | ||
| 691 | /* stack */ | |
| 692 | lis r1,init_thread_union@ha | |
| 693 | addi r1,r1,init_thread_union@l | |
| 694 | li r0,0 | |
| 695 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
| 696 | ||
| 697 | bl early_init /* We have to do this with MMU on */ | |
| 698 | ||
| 699 | /* | |
| 700 | * Decide what sort of machine this is and initialize the MMU. | |
| 701 | */ | |
| 702 | mr r3,r31 | |
| 703 | mr r4,r30 | |
| 704 | mr r5,r29 | |
| 705 | mr r6,r28 | |
| 706 | mr r7,r27 | |
| 707 | bl machine_init | |
| 708 | bl MMU_init | |
| 709 | ||
| 710 | /* | |
| 711 | * Go back to running unmapped so we can load up new values | |
| 712 | * and change to using our exception vectors. | |
| 713 | * On the 8xx, all we have to do is invalidate the TLB to clear | |
| 714 | * the old 8M byte TLB mappings and load the page table base register. | |
| 715 | */ | |
| 716 | /* The right way to do this would be to track it down through | |
| 717 | * init's THREAD like the context switch code does, but this is | |
| 718 | * easier......until someone changes init's static structures. | |
| 719 | */ | |
| 720 | lis r6, swapper_pg_dir@h | |
| 721 | ori r6, r6, swapper_pg_dir@l | |
| 722 | tophys(r6,r6) | |
| 723 | #ifdef CONFIG_8xx_CPU6 | |
| 724 | lis r4, cpu6_errata_word@h | |
| 725 | ori r4, r4, cpu6_errata_word@l | |
| 726 | li r3, 0x3980 | |
| 727 | stw r3, 12(r4) | |
| 728 | lwz r3, 12(r4) | |
| 729 | #endif | |
| 730 | mtspr SPRN_M_TWB, r6 | |
| 731 | lis r4,2f@h | |
| 732 | ori r4,r4,2f@l | |
| 733 | tophys(r4,r4) | |
| 734 | li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR) | |
| 735 | mtspr SPRN_SRR0,r4 | |
| 736 | mtspr SPRN_SRR1,r3 | |
| 737 | rfi | |
| 738 | /* Load up the kernel context */ | |
| 739 | 2: | |
| 740 | SYNC /* Force all PTE updates to finish */ | |
| 741 | tlbia /* Clear all TLB entries */ | |
| 742 | sync /* wait for tlbia/tlbie to finish */ | |
| 743 | TLBSYNC /* ... on all CPUs */ | |
| 744 | ||
| 745 | /* set up the PTE pointers for the Abatron bdiGDB. | |
| 746 | */ | |
| 747 | tovirt(r6,r6) | |
| 748 | lis r5, abatron_pteptrs@h | |
| 749 | ori r5, r5, abatron_pteptrs@l | |
| 750 | stw r5, 0xf0(r0) /* Must match your Abatron config file */ | |
| 751 | tophys(r5,r5) | |
| 752 | stw r6, 0(r5) | |
| 753 | ||
| 754 | /* Now turn on the MMU for real! */ | |
| 755 | li r4,MSR_KERNEL | |
| 756 | lis r3,start_kernel@h | |
| 757 | ori r3,r3,start_kernel@l | |
| 758 | mtspr SPRN_SRR0,r3 | |
| 759 | mtspr SPRN_SRR1,r4 | |
| 760 | rfi /* enable MMU and jump to start_kernel */ | |
| 761 | ||
| 762 | /* Set up the initial MMU state so we can do the first level of | |
| 763 | * kernel initialization. This maps the first 8 MBytes of memory 1:1 | |
| 764 | * virtual to physical. Also, set the cache mode since that is defined | |
| 765 | * by TLB entries and perform any additional mapping (like of the IMMR). | |
| 766 | * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel, | |
| 767 | * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by | |
| 768 | * these mappings is mapped by page tables. | |
| 769 | */ | |
| 770 | initial_mmu: | |
| 771 | tlbia /* Invalidate all TLB entries */ | |
| 9f4f04ba JT |
772 | /* Always pin the first 8 MB ITLB to prevent ITLB |
| 773 | misses while mucking around with SRR0/SRR1 in asm | |
| 774 | */ | |
| 14cf11af PM |
775 | lis r8, MI_RSV4I@h |
| 776 | ori r8, r8, 0x1c00 | |
| 9f4f04ba | 777 | |
| 14cf11af PM |
778 | mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ |
| 779 | ||
| 780 | #ifdef CONFIG_PIN_TLB | |
| 781 | lis r10, (MD_RSV4I | MD_RESETVAL)@h | |
| 782 | ori r10, r10, 0x1c00 | |
| 783 | mr r8, r10 | |
| 784 | #else | |
| 785 | lis r10, MD_RESETVAL@h | |
| 786 | #endif | |
| 787 | #ifndef CONFIG_8xx_COPYBACK | |
| 788 | oris r10, r10, MD_WTDEF@h | |
| 789 | #endif | |
| 790 | mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ | |
| 791 | ||
| 792 | /* Now map the lower 8 Meg into the TLBs. For this quick hack, | |
| 793 | * we can load the instruction and data TLB registers with the | |
| 794 | * same values. | |
| 795 | */ | |
| 796 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
| 797 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
| 798 | mtspr SPRN_MI_EPN, r8 | |
| 799 | mtspr SPRN_MD_EPN, r8 | |
| 800 | li r8, MI_PS8MEG /* Set 8M byte page */ | |
| 801 | ori r8, r8, MI_SVALID /* Make it valid */ | |
| 802 | mtspr SPRN_MI_TWC, r8 | |
| 803 | mtspr SPRN_MD_TWC, r8 | |
| 804 | li r8, MI_BOOTINIT /* Create RPN for address 0 */ | |
| 805 | mtspr SPRN_MI_RPN, r8 /* Store TLB entry */ | |
| 806 | mtspr SPRN_MD_RPN, r8 | |
| 807 | lis r8, MI_Kp@h /* Set the protection mode */ | |
| 808 | mtspr SPRN_MI_AP, r8 | |
| 809 | mtspr SPRN_MD_AP, r8 | |
| 810 | ||
| 811 | /* Map another 8 MByte at the IMMR to get the processor | |
| 812 | * internal registers (among other things). | |
| 813 | */ | |
| 814 | #ifdef CONFIG_PIN_TLB | |
| 815 | addi r10, r10, 0x0100 | |
| 816 | mtspr SPRN_MD_CTR, r10 | |
| 817 | #endif | |
| 818 | mfspr r9, 638 /* Get current IMMR */ | |
| 819 | andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */ | |
| 820 | ||
| 821 | mr r8, r9 /* Create vaddr for TLB */ | |
| 822 | ori r8, r8, MD_EVALID /* Mark it valid */ | |
| 823 | mtspr SPRN_MD_EPN, r8 | |
| 824 | li r8, MD_PS8MEG /* Set 8M byte page */ | |
| 825 | ori r8, r8, MD_SVALID /* Make it valid */ | |
| 826 | mtspr SPRN_MD_TWC, r8 | |
| 827 | mr r8, r9 /* Create paddr for TLB */ | |
| 828 | ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */ | |
| 829 | mtspr SPRN_MD_RPN, r8 | |
| 830 | ||
| 831 | #ifdef CONFIG_PIN_TLB | |
| 832 | /* Map two more 8M kernel data pages. | |
| 833 | */ | |
| 834 | addi r10, r10, 0x0100 | |
| 835 | mtspr SPRN_MD_CTR, r10 | |
| 836 | ||
| 837 | lis r8, KERNELBASE@h /* Create vaddr for TLB */ | |
| 838 | addis r8, r8, 0x0080 /* Add 8M */ | |
| 839 | ori r8, r8, MI_EVALID /* Mark it valid */ | |
| 840 | mtspr SPRN_MD_EPN, r8 | |
| 841 | li r9, MI_PS8MEG /* Set 8M byte page */ | |
| 842 | ori r9, r9, MI_SVALID /* Make it valid */ | |
| 843 | mtspr SPRN_MD_TWC, r9 | |
| 844 | li r11, MI_BOOTINIT /* Create RPN for address 0 */ | |
| 845 | addis r11, r11, 0x0080 /* Add 8M */ | |
| ccf0d68e | 846 | mtspr SPRN_MD_RPN, r11 |
| 14cf11af PM |
847 | |
| 848 | addis r8, r8, 0x0080 /* Add 8M */ | |
| 849 | mtspr SPRN_MD_EPN, r8 | |
| 850 | mtspr SPRN_MD_TWC, r9 | |
| 851 | addis r11, r11, 0x0080 /* Add 8M */ | |
| ccf0d68e | 852 | mtspr SPRN_MD_RPN, r11 |
| 14cf11af PM |
853 | #endif |
| 854 | ||
| 855 | /* Since the cache is enabled according to the information we | |
| 856 | * just loaded into the TLB, invalidate and enable the caches here. | |
| 857 | * We should probably check/set other modes....later. | |
| 858 | */ | |
| 859 | lis r8, IDC_INVALL@h | |
| 860 | mtspr SPRN_IC_CST, r8 | |
| 861 | mtspr SPRN_DC_CST, r8 | |
| 862 | lis r8, IDC_ENABLE@h | |
| 863 | mtspr SPRN_IC_CST, r8 | |
| 864 | #ifdef CONFIG_8xx_COPYBACK | |
| 865 | mtspr SPRN_DC_CST, r8 | |
| 866 | #else | |
| 867 | /* For a debug option, I left this here to easily enable | |
| 868 | * the write through cache mode | |
| 869 | */ | |
| 870 | lis r8, DC_SFWT@h | |
| 871 | mtspr SPRN_DC_CST, r8 | |
| 872 | lis r8, IDC_ENABLE@h | |
| 873 | mtspr SPRN_DC_CST, r8 | |
| 874 | #endif | |
| 875 | blr | |
| 876 | ||
| 877 | ||
| 878 | /* | |
| 879 | * Set up to use a given MMU context. | |
| 880 | * r3 is context number, r4 is PGD pointer. | |
| 881 | * | |
| 882 | * We place the physical address of the new task page directory loaded | |
| 883 | * into the MMU base register, and set the ASID compare register with | |
| 884 | * the new "context." | |
| 885 | */ | |
| 886 | _GLOBAL(set_context) | |
| 887 | ||
| 888 | #ifdef CONFIG_BDI_SWITCH | |
| 889 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
| 890 | * The PGDIR is passed as second argument. | |
| 891 | */ | |
| 892 | lis r5, KERNELBASE@h | |
| 893 | lwz r5, 0xf0(r5) | |
| 894 | stw r4, 0x4(r5) | |
| 895 | #endif | |
| 896 | ||
| 897 | #ifdef CONFIG_8xx_CPU6 | |
| 898 | lis r6, cpu6_errata_word@h | |
| 899 | ori r6, r6, cpu6_errata_word@l | |
| 900 | tophys (r4, r4) | |
| 901 | li r7, 0x3980 | |
| 902 | stw r7, 12(r6) | |
| 903 | lwz r7, 12(r6) | |
| 904 | mtspr SPRN_M_TWB, r4 /* Update MMU base address */ | |
| 905 | li r7, 0x3380 | |
| 906 | stw r7, 12(r6) | |
| 907 | lwz r7, 12(r6) | |
| 908 | mtspr SPRN_M_CASID, r3 /* Update context */ | |
| 909 | #else | |
| 910 | mtspr SPRN_M_CASID,r3 /* Update context */ | |
| 911 | tophys (r4, r4) | |
| 912 | mtspr SPRN_M_TWB, r4 /* and pgd */ | |
| 913 | #endif | |
| 914 | SYNC | |
| 915 | blr | |
| 916 | ||
| 917 | #ifdef CONFIG_8xx_CPU6 | |
| 918 | /* It's here because it is unique to the 8xx. | |
| 919 | * It is important we get called with interrupts disabled. I used to | |
| 920 | * do that, but it appears that all code that calls this already had | |
| 921 | * interrupt disabled. | |
| 922 | */ | |
| 923 | .globl set_dec_cpu6 | |
| 924 | set_dec_cpu6: | |
| 925 | lis r7, cpu6_errata_word@h | |
| 926 | ori r7, r7, cpu6_errata_word@l | |
| 927 | li r4, 0x2c00 | |
| 928 | stw r4, 8(r7) | |
| 929 | lwz r4, 8(r7) | |
| 930 | mtspr 22, r3 /* Update Decrementer */ | |
| 931 | SYNC | |
| 932 | blr | |
| 933 | #endif | |
| 934 | ||
| 935 | /* | |
| 936 | * We put a few things here that have to be page-aligned. | |
| 937 | * This stuff goes at the beginning of the data segment, | |
| 938 | * which is page-aligned. | |
| 939 | */ | |
| 940 | .data | |
| 941 | .globl sdata | |
| 942 | sdata: | |
| 943 | .globl empty_zero_page | |
| 944 | empty_zero_page: | |
| 945 | .space 4096 | |
| 946 | ||
| 947 | .globl swapper_pg_dir | |
| 948 | swapper_pg_dir: | |
| 949 | .space 4096 | |
| 950 | ||
| 14cf11af PM |
951 | /* Room for two PTE table poiners, usually the kernel and current user |
| 952 | * pointer to their respective root page table (pgdir). | |
| 953 | */ | |
| 954 | abatron_pteptrs: | |
| 955 | .space 8 | |
| 956 | ||
| 957 | #ifdef CONFIG_8xx_CPU6 | |
| 958 | .globl cpu6_errata_word | |
| 959 | cpu6_errata_word: | |
| 960 | .space 16 | |
| 961 | #endif | |
| 962 |