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Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Kernel execution entry point code. |
3 | * | |
4 | * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org> | |
3c5df5c2 | 5 | * Initial PowerPC version. |
14cf11af | 6 | * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu> |
3c5df5c2 | 7 | * Rewritten for PReP |
14cf11af | 8 | * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> |
3c5df5c2 | 9 | * Low-level exception handers, MMU support, and rewrite. |
14cf11af | 10 | * Copyright (c) 1997 Dan Malek <dmalek@jlc.net> |
3c5df5c2 | 11 | * PowerPC 8xx modifications. |
14cf11af | 12 | * Copyright (c) 1998-1999 TiVo, Inc. |
3c5df5c2 | 13 | * PowerPC 403GCX modifications. |
14cf11af | 14 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> |
3c5df5c2 | 15 | * PowerPC 403GCX/405GP modifications. |
14cf11af PM |
16 | * Copyright 2000 MontaVista Software Inc. |
17 | * PPC405 modifications | |
3c5df5c2 KG |
18 | * PowerPC 403GCX/405GP modifications. |
19 | * Author: MontaVista Software, Inc. | |
20 | * frank_rowand@mvista.com or source@mvista.com | |
21 | * debbie_chu@mvista.com | |
14cf11af | 22 | * Copyright 2002-2004 MontaVista Software, Inc. |
3c5df5c2 | 23 | * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org> |
14cf11af | 24 | * Copyright 2004 Freescale Semiconductor, Inc |
3c5df5c2 | 25 | * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org> |
14cf11af PM |
26 | * |
27 | * This program is free software; you can redistribute it and/or modify it | |
28 | * under the terms of the GNU General Public License as published by the | |
29 | * Free Software Foundation; either version 2 of the License, or (at your | |
30 | * option) any later version. | |
31 | */ | |
32 | ||
14cf11af PM |
33 | #include <linux/threads.h> |
34 | #include <asm/processor.h> | |
35 | #include <asm/page.h> | |
36 | #include <asm/mmu.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/cputable.h> | |
39 | #include <asm/thread_info.h> | |
40 | #include <asm/ppc_asm.h> | |
41 | #include <asm/asm-offsets.h> | |
fc4033b2 | 42 | #include <asm/cache.h> |
14cf11af PM |
43 | #include "head_booke.h" |
44 | ||
45 | /* As with the other PowerPC ports, it is expected that when code | |
46 | * execution begins here, the following registers contain valid, yet | |
47 | * optional, information: | |
48 | * | |
49 | * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.) | |
50 | * r4 - Starting address of the init RAM disk | |
51 | * r5 - Ending address of the init RAM disk | |
52 | * r6 - Start of kernel command line string (e.g. "mem=128") | |
53 | * r7 - End of kernel command line string | |
54 | * | |
55 | */ | |
748a7683 KG |
56 | .section .text.head, "ax" |
57 | _ENTRY(_stext); | |
58 | _ENTRY(_start); | |
14cf11af PM |
59 | /* |
60 | * Reserve a word at a fixed location to store the address | |
61 | * of abatron_pteptrs | |
62 | */ | |
63 | nop | |
64 | /* | |
65 | * Save parameters we are passed | |
66 | */ | |
67 | mr r31,r3 | |
68 | mr r30,r4 | |
69 | mr r29,r5 | |
70 | mr r28,r6 | |
71 | mr r27,r7 | |
0aef996b | 72 | li r25,0 /* phys kernel start (low) */ |
14cf11af | 73 | li r24,0 /* CPU number */ |
0aef996b | 74 | li r23,0 /* phys kernel start (high) */ |
14cf11af PM |
75 | |
76 | /* We try to not make any assumptions about how the boot loader | |
77 | * setup or used the TLBs. We invalidate all mappings from the | |
78 | * boot loader and load a single entry in TLB1[0] to map the | |
e8b63761 DF |
79 | * first 64M of kernel memory. Any boot info passed from the |
80 | * bootloader needs to live in this first 64M. | |
14cf11af PM |
81 | * |
82 | * Requirement on bootloader: | |
83 | * - The page we're executing in needs to reside in TLB1 and | |
84 | * have IPROT=1. If not an invalidate broadcast could | |
85 | * evict the entry we're currently executing in. | |
86 | * | |
87 | * r3 = Index of TLB1 were executing in | |
88 | * r4 = Current MSR[IS] | |
89 | * r5 = Index of TLB1 temp mapping | |
90 | * | |
91 | * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0] | |
92 | * if needed | |
93 | */ | |
94 | ||
95 | /* 1. Find the index of the entry we're executing in */ | |
96 | bl invstr /* Find our address */ | |
97 | invstr: mflr r6 /* Make it accessible */ | |
98 | mfmsr r7 | |
99 | rlwinm r4,r7,27,31,31 /* extract MSR[IS] */ | |
100 | mfspr r7, SPRN_PID0 | |
101 | slwi r7,r7,16 | |
102 | or r7,r7,r4 | |
103 | mtspr SPRN_MAS6,r7 | |
104 | tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ | |
105 | #ifndef CONFIG_E200 | |
106 | mfspr r7,SPRN_MAS1 | |
107 | andis. r7,r7,MAS1_VALID@h | |
108 | bne match_TLB | |
109 | mfspr r7,SPRN_PID1 | |
110 | slwi r7,r7,16 | |
111 | or r7,r7,r4 | |
112 | mtspr SPRN_MAS6,r7 | |
113 | tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */ | |
114 | mfspr r7,SPRN_MAS1 | |
115 | andis. r7,r7,MAS1_VALID@h | |
116 | bne match_TLB | |
117 | mfspr r7, SPRN_PID2 | |
118 | slwi r7,r7,16 | |
119 | or r7,r7,r4 | |
120 | mtspr SPRN_MAS6,r7 | |
121 | tlbsx 0,r6 /* Fall through, we had to match */ | |
122 | #endif | |
123 | match_TLB: | |
124 | mfspr r7,SPRN_MAS0 | |
125 | rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ | |
126 | ||
127 | mfspr r7,SPRN_MAS1 /* Insure IPROT set */ | |
128 | oris r7,r7,MAS1_IPROT@h | |
129 | mtspr SPRN_MAS1,r7 | |
130 | tlbwe | |
131 | ||
132 | /* 2. Invalidate all entries except the entry we're executing in */ | |
133 | mfspr r9,SPRN_TLB1CFG | |
134 | andi. r9,r9,0xfff | |
135 | li r6,0 /* Set Entry counter to 0 */ | |
136 | 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
137 | rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ | |
138 | mtspr SPRN_MAS0,r7 | |
139 | tlbre | |
140 | mfspr r7,SPRN_MAS1 | |
141 | rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ | |
142 | cmpw r3,r6 | |
143 | beq skpinv /* Dont update the current execution TLB */ | |
144 | mtspr SPRN_MAS1,r7 | |
145 | tlbwe | |
146 | isync | |
147 | skpinv: addi r6,r6,1 /* Increment */ | |
148 | cmpw r6,r9 /* Are we done? */ | |
149 | bne 1b /* If not, repeat */ | |
150 | ||
151 | /* Invalidate TLB0 */ | |
3c5df5c2 | 152 | li r6,0x04 |
14cf11af PM |
153 | tlbivax 0,r6 |
154 | #ifdef CONFIG_SMP | |
155 | tlbsync | |
156 | #endif | |
157 | /* Invalidate TLB1 */ | |
3c5df5c2 | 158 | li r6,0x0c |
14cf11af PM |
159 | tlbivax 0,r6 |
160 | #ifdef CONFIG_SMP | |
161 | tlbsync | |
162 | #endif | |
163 | msync | |
164 | ||
165 | /* 3. Setup a temp mapping and jump to it */ | |
166 | andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */ | |
167 | addi r5, r5, 0x1 | |
168 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
169 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
170 | mtspr SPRN_MAS0,r7 | |
171 | tlbre | |
172 | ||
0aef996b KG |
173 | /* grab and fixup the RPN */ |
174 | mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ | |
175 | rlwinm r6,r6,25,27,30 | |
176 | li r8,-1 | |
177 | addi r6,r6,10 | |
178 | slw r6,r8,r6 /* convert to mask */ | |
179 | ||
180 | bl 1f /* Find our address */ | |
181 | 1: mflr r7 | |
182 | ||
183 | mfspr r8,SPRN_MAS3 | |
184 | #ifdef CONFIG_PHYS_64BIT | |
185 | mfspr r23,SPRN_MAS7 | |
186 | #endif | |
187 | and r8,r6,r8 | |
188 | subfic r9,r6,-4096 | |
189 | and r9,r9,r7 | |
190 | ||
191 | or r25,r8,r9 | |
192 | ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR) | |
193 | ||
194 | /* Just modify the entry ID and EPN for the temp mapping */ | |
14cf11af PM |
195 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ |
196 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ | |
197 | mtspr SPRN_MAS0,r7 | |
198 | xori r6,r4,1 /* Setup TMP mapping in the other Address space */ | |
199 | slwi r6,r6,12 | |
200 | oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h | |
201 | ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l | |
202 | mtspr SPRN_MAS1,r6 | |
203 | mfspr r6,SPRN_MAS2 | |
0aef996b | 204 | li r7,0 /* temp EPN = 0 */ |
14cf11af PM |
205 | rlwimi r7,r6,0,20,31 |
206 | mtspr SPRN_MAS2,r7 | |
0aef996b | 207 | mtspr SPRN_MAS3,r8 |
14cf11af PM |
208 | tlbwe |
209 | ||
210 | xori r6,r4,1 | |
211 | slwi r6,r6,5 /* setup new context with other address space */ | |
212 | bl 1f /* Find our address */ | |
213 | 1: mflr r9 | |
214 | rlwimi r7,r9,0,20,31 | |
215 | addi r7,r7,24 | |
216 | mtspr SPRN_SRR0,r7 | |
217 | mtspr SPRN_SRR1,r6 | |
218 | rfi | |
219 | ||
220 | /* 4. Clear out PIDs & Search info */ | |
221 | li r6,0 | |
222 | mtspr SPRN_PID0,r6 | |
223 | #ifndef CONFIG_E200 | |
224 | mtspr SPRN_PID1,r6 | |
225 | mtspr SPRN_PID2,r6 | |
226 | #endif | |
227 | mtspr SPRN_MAS6,r6 | |
228 | ||
229 | /* 5. Invalidate mapping we started in */ | |
230 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
231 | rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ | |
232 | mtspr SPRN_MAS0,r7 | |
233 | tlbre | |
8ce0a7df BB |
234 | mfspr r6,SPRN_MAS1 |
235 | rlwinm r6,r6,0,2,0 /* clear IPROT */ | |
14cf11af PM |
236 | mtspr SPRN_MAS1,r6 |
237 | tlbwe | |
238 | /* Invalidate TLB1 */ | |
3c5df5c2 | 239 | li r9,0x0c |
14cf11af PM |
240 | tlbivax 0,r9 |
241 | #ifdef CONFIG_SMP | |
242 | tlbsync | |
243 | #endif | |
244 | msync | |
245 | ||
246 | /* 6. Setup KERNELBASE mapping in TLB1[0] */ | |
247 | lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ | |
248 | mtspr SPRN_MAS0,r6 | |
249 | lis r6,(MAS1_VALID|MAS1_IPROT)@h | |
e8b63761 | 250 | ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l |
14cf11af PM |
251 | mtspr SPRN_MAS1,r6 |
252 | li r7,0 | |
e8b63761 DF |
253 | lis r6,PAGE_OFFSET@h |
254 | ori r6,r6,PAGE_OFFSET@l | |
14cf11af PM |
255 | rlwimi r6,r7,0,20,31 |
256 | mtspr SPRN_MAS2,r6 | |
0aef996b | 257 | mtspr SPRN_MAS3,r8 |
14cf11af PM |
258 | tlbwe |
259 | ||
260 | /* 7. Jump to KERNELBASE mapping */ | |
e8b63761 DF |
261 | lis r6,KERNELBASE@h |
262 | ori r6,r6,KERNELBASE@l | |
263 | rlwimi r6,r7,0,20,31 | |
14cf11af PM |
264 | lis r7,MSR_KERNEL@h |
265 | ori r7,r7,MSR_KERNEL@l | |
266 | bl 1f /* Find our address */ | |
267 | 1: mflr r9 | |
268 | rlwimi r6,r9,0,20,31 | |
269 | addi r6,r6,24 | |
270 | mtspr SPRN_SRR0,r6 | |
271 | mtspr SPRN_SRR1,r7 | |
272 | rfi /* start execution out of TLB1[0] entry */ | |
273 | ||
274 | /* 8. Clear out the temp mapping */ | |
275 | lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ | |
276 | rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */ | |
277 | mtspr SPRN_MAS0,r7 | |
278 | tlbre | |
8ce0a7df BB |
279 | mfspr r8,SPRN_MAS1 |
280 | rlwinm r8,r8,0,2,0 /* clear IPROT */ | |
14cf11af PM |
281 | mtspr SPRN_MAS1,r8 |
282 | tlbwe | |
283 | /* Invalidate TLB1 */ | |
3c5df5c2 | 284 | li r9,0x0c |
14cf11af PM |
285 | tlbivax 0,r9 |
286 | #ifdef CONFIG_SMP | |
287 | tlbsync | |
288 | #endif | |
289 | msync | |
290 | ||
291 | /* Establish the interrupt vector offsets */ | |
292 | SET_IVOR(0, CriticalInput); | |
293 | SET_IVOR(1, MachineCheck); | |
294 | SET_IVOR(2, DataStorage); | |
295 | SET_IVOR(3, InstructionStorage); | |
296 | SET_IVOR(4, ExternalInput); | |
297 | SET_IVOR(5, Alignment); | |
298 | SET_IVOR(6, Program); | |
299 | SET_IVOR(7, FloatingPointUnavailable); | |
300 | SET_IVOR(8, SystemCall); | |
301 | SET_IVOR(9, AuxillaryProcessorUnavailable); | |
302 | SET_IVOR(10, Decrementer); | |
303 | SET_IVOR(11, FixedIntervalTimer); | |
304 | SET_IVOR(12, WatchdogTimer); | |
305 | SET_IVOR(13, DataTLBError); | |
306 | SET_IVOR(14, InstructionTLBError); | |
eb0cd5fd | 307 | SET_IVOR(15, DebugDebug); |
3dfa8773 | 308 | #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC) |
eb0cd5fd KG |
309 | SET_IVOR(15, DebugCrit); |
310 | #endif | |
14cf11af PM |
311 | SET_IVOR(32, SPEUnavailable); |
312 | SET_IVOR(33, SPEFloatingPointData); | |
313 | SET_IVOR(34, SPEFloatingPointRound); | |
314 | #ifndef CONFIG_E200 | |
315 | SET_IVOR(35, PerformanceMonitor); | |
316 | #endif | |
3dfa8773 KG |
317 | #ifdef CONFIG_PPC_E500MC |
318 | SET_IVOR(36, Doorbell); | |
319 | #endif | |
14cf11af PM |
320 | |
321 | /* Establish the interrupt vector base */ | |
322 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | |
323 | mtspr SPRN_IVPR,r4 | |
324 | ||
325 | /* Setup the defaults for TLB entries */ | |
326 | li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l | |
327 | #ifdef CONFIG_E200 | |
328 | oris r2,r2,MAS4_TLBSELD(1)@h | |
329 | #endif | |
3c5df5c2 | 330 | mtspr SPRN_MAS4, r2 |
14cf11af PM |
331 | |
332 | #if 0 | |
333 | /* Enable DOZE */ | |
334 | mfspr r2,SPRN_HID0 | |
335 | oris r2,r2,HID0_DOZE@h | |
336 | mtspr SPRN_HID0, r2 | |
337 | #endif | |
338 | #ifdef CONFIG_E200 | |
339 | /* enable dedicated debug exception handling resources (Debug APU) */ | |
340 | mfspr r2,SPRN_HID0 | |
3c5df5c2 | 341 | ori r2,r2,HID0_DAPUEN@l |
14cf11af PM |
342 | mtspr SPRN_HID0,r2 |
343 | #endif | |
344 | ||
345 | #if !defined(CONFIG_BDI_SWITCH) | |
346 | /* | |
347 | * The Abatron BDI JTAG debugger does not tolerate others | |
348 | * mucking with the debug registers. | |
349 | */ | |
350 | lis r2,DBCR0_IDM@h | |
351 | mtspr SPRN_DBCR0,r2 | |
a7cb0337 | 352 | isync |
14cf11af PM |
353 | /* clear any residual debug events */ |
354 | li r2,-1 | |
355 | mtspr SPRN_DBSR,r2 | |
356 | #endif | |
357 | ||
358 | /* | |
359 | * This is where the main kernel code starts. | |
360 | */ | |
361 | ||
362 | /* ptr to current */ | |
363 | lis r2,init_task@h | |
364 | ori r2,r2,init_task@l | |
365 | ||
366 | /* ptr to current thread */ | |
367 | addi r4,r2,THREAD /* init task's THREAD */ | |
368 | mtspr SPRN_SPRG3,r4 | |
369 | ||
370 | /* stack */ | |
371 | lis r1,init_thread_union@h | |
372 | ori r1,r1,init_thread_union@l | |
373 | li r0,0 | |
374 | stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1) | |
375 | ||
376 | bl early_init | |
377 | ||
37dd2bad KG |
378 | #ifdef CONFIG_RELOCATABLE |
379 | lis r3,kernstart_addr@ha | |
380 | la r3,kernstart_addr@l(r3) | |
381 | #ifdef CONFIG_PHYS_64BIT | |
382 | stw r23,0(r3) | |
383 | stw r25,4(r3) | |
384 | #else | |
385 | stw r25,0(r3) | |
386 | #endif | |
387 | #endif | |
388 | ||
14cf11af PM |
389 | mfspr r3,SPRN_TLB1CFG |
390 | andi. r3,r3,0xfff | |
391 | lis r4,num_tlbcam_entries@ha | |
392 | stw r3,num_tlbcam_entries@l(r4) | |
393 | /* | |
394 | * Decide what sort of machine this is and initialize the MMU. | |
395 | */ | |
396 | mr r3,r31 | |
397 | mr r4,r30 | |
398 | mr r5,r29 | |
399 | mr r6,r28 | |
400 | mr r7,r27 | |
401 | bl machine_init | |
402 | bl MMU_init | |
403 | ||
404 | /* Setup PTE pointers for the Abatron bdiGDB */ | |
405 | lis r6, swapper_pg_dir@h | |
406 | ori r6, r6, swapper_pg_dir@l | |
407 | lis r5, abatron_pteptrs@h | |
408 | ori r5, r5, abatron_pteptrs@l | |
409 | lis r4, KERNELBASE@h | |
410 | ori r4, r4, KERNELBASE@l | |
411 | stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */ | |
412 | stw r6, 0(r5) | |
413 | ||
414 | /* Let's move on */ | |
415 | lis r4,start_kernel@h | |
416 | ori r4,r4,start_kernel@l | |
417 | lis r3,MSR_KERNEL@h | |
418 | ori r3,r3,MSR_KERNEL@l | |
419 | mtspr SPRN_SRR0,r4 | |
420 | mtspr SPRN_SRR1,r3 | |
421 | rfi /* change context and jump to start_kernel */ | |
422 | ||
423 | /* Macros to hide the PTE size differences | |
424 | * | |
425 | * FIND_PTE -- walks the page tables given EA & pgdir pointer | |
426 | * r10 -- EA of fault | |
427 | * r11 -- PGDIR pointer | |
428 | * r12 -- free | |
429 | * label 2: is the bailout case | |
430 | * | |
431 | * if we find the pte (fall through): | |
432 | * r11 is low pte word | |
433 | * r12 is pointer to the pte | |
434 | */ | |
435 | #ifdef CONFIG_PTE_64BIT | |
436 | #define PTE_FLAGS_OFFSET 4 | |
437 | #define FIND_PTE \ | |
3c5df5c2 | 438 | rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \ |
14cf11af PM |
439 | lwzx r11, r12, r11; /* Get pgd/pmd entry */ \ |
440 | rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \ | |
441 | beq 2f; /* Bail if no table */ \ | |
442 | rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \ | |
443 | lwz r11, 4(r12); /* Get pte entry */ | |
444 | #else | |
445 | #define PTE_FLAGS_OFFSET 0 | |
446 | #define FIND_PTE \ | |
447 | rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \ | |
448 | lwz r11, 0(r11); /* Get L1 entry */ \ | |
449 | rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \ | |
450 | beq 2f; /* Bail if no table */ \ | |
451 | rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \ | |
452 | lwz r11, 0(r12); /* Get Linux PTE */ | |
453 | #endif | |
454 | ||
455 | /* | |
456 | * Interrupt vector entry code | |
457 | * | |
458 | * The Book E MMUs are always on so we don't need to handle | |
459 | * interrupts in real mode as with previous PPC processors. In | |
460 | * this case we handle interrupts in the kernel virtual address | |
461 | * space. | |
462 | * | |
463 | * Interrupt vectors are dynamically placed relative to the | |
464 | * interrupt prefix as determined by the address of interrupt_base. | |
465 | * The interrupt vectors offsets are programmed using the labels | |
466 | * for each interrupt vector entry. | |
467 | * | |
468 | * Interrupt vectors must be aligned on a 16 byte boundary. | |
469 | * We align on a 32 byte cache line boundary for good measure. | |
470 | */ | |
471 | ||
472 | interrupt_base: | |
473 | /* Critical Input Interrupt */ | |
dc1c1ca3 | 474 | CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception) |
14cf11af PM |
475 | |
476 | /* Machine Check Interrupt */ | |
477 | #ifdef CONFIG_E200 | |
478 | /* no RFMCI, MCSRRs on E200 */ | |
dc1c1ca3 | 479 | CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af | 480 | #else |
dc1c1ca3 | 481 | MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception) |
14cf11af PM |
482 | #endif |
483 | ||
484 | /* Data Storage Interrupt */ | |
485 | START_EXCEPTION(DataStorage) | |
486 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
487 | mtspr SPRN_SPRG1, r11 | |
488 | mtspr SPRN_SPRG4W, r12 | |
489 | mtspr SPRN_SPRG5W, r13 | |
490 | mfcr r11 | |
491 | mtspr SPRN_SPRG7W, r11 | |
492 | ||
493 | /* | |
494 | * Check if it was a store fault, if not then bail | |
495 | * because a user tried to access a kernel or | |
496 | * read-protected page. Otherwise, get the | |
497 | * offending address and handle it. | |
498 | */ | |
499 | mfspr r10, SPRN_ESR | |
500 | andis. r10, r10, ESR_ST@h | |
501 | beq 2f | |
502 | ||
503 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
504 | ||
505 | /* If we are faulting a kernel address, we have to use the | |
506 | * kernel page tables. | |
507 | */ | |
8a13c4f9 | 508 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
509 | cmplw 0, r10, r11 |
510 | bge 2f | |
511 | ||
512 | /* Get the PGD for the current thread */ | |
513 | 3: | |
514 | mfspr r11,SPRN_SPRG3 | |
515 | lwz r11,PGDIR(r11) | |
516 | 4: | |
517 | FIND_PTE | |
518 | ||
519 | /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */ | |
520 | andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE | |
521 | cmpwi 0, r13, _PAGE_RW|_PAGE_USER | |
522 | bne 2f /* Bail if not */ | |
523 | ||
524 | /* Update 'changed'. */ | |
525 | ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE | |
526 | stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */ | |
527 | ||
528 | /* MAS2 not updated as the entry does exist in the tlb, this | |
529 | fault taken to detect state transition (eg: COW -> DIRTY) | |
530 | */ | |
531 | andi. r11, r11, _PAGE_HWEXEC | |
532 | rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */ | |
3c5df5c2 | 533 | ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */ |
14cf11af PM |
534 | |
535 | /* update search PID in MAS6, AS = 0 */ | |
536 | mfspr r12, SPRN_PID0 | |
537 | slwi r12, r12, 16 | |
538 | mtspr SPRN_MAS6, r12 | |
539 | ||
540 | /* find the TLB index that caused the fault. It has to be here. */ | |
541 | tlbsx 0, r10 | |
542 | ||
543 | /* only update the perm bits, assume the RPN is fine */ | |
544 | mfspr r12, SPRN_MAS3 | |
545 | rlwimi r12, r11, 0, 20, 31 | |
546 | mtspr SPRN_MAS3,r12 | |
547 | tlbwe | |
548 | ||
549 | /* Done...restore registers and get out of here. */ | |
550 | mfspr r11, SPRN_SPRG7R | |
551 | mtcr r11 | |
552 | mfspr r13, SPRN_SPRG5R | |
553 | mfspr r12, SPRN_SPRG4R | |
554 | mfspr r11, SPRN_SPRG1 | |
555 | mfspr r10, SPRN_SPRG0 | |
556 | rfi /* Force context change */ | |
557 | ||
558 | 2: | |
559 | /* | |
560 | * The bailout. Restore registers to pre-exception conditions | |
561 | * and call the heavyweights to help us out. | |
562 | */ | |
563 | mfspr r11, SPRN_SPRG7R | |
564 | mtcr r11 | |
565 | mfspr r13, SPRN_SPRG5R | |
566 | mfspr r12, SPRN_SPRG4R | |
567 | mfspr r11, SPRN_SPRG1 | |
568 | mfspr r10, SPRN_SPRG0 | |
569 | b data_access | |
570 | ||
571 | /* Instruction Storage Interrupt */ | |
572 | INSTRUCTION_STORAGE_EXCEPTION | |
573 | ||
574 | /* External Input Interrupt */ | |
575 | EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE) | |
576 | ||
577 | /* Alignment Interrupt */ | |
578 | ALIGNMENT_EXCEPTION | |
579 | ||
580 | /* Program Interrupt */ | |
581 | PROGRAM_EXCEPTION | |
582 | ||
583 | /* Floating Point Unavailable Interrupt */ | |
584 | #ifdef CONFIG_PPC_FPU | |
585 | FP_UNAVAILABLE_EXCEPTION | |
586 | #else | |
587 | #ifdef CONFIG_E200 | |
588 | /* E200 treats 'normal' floating point instructions as FP Unavail exception */ | |
dc1c1ca3 | 589 | EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE) |
14cf11af | 590 | #else |
dc1c1ca3 | 591 | EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
592 | #endif |
593 | #endif | |
594 | ||
595 | /* System Call Interrupt */ | |
596 | START_EXCEPTION(SystemCall) | |
597 | NORMAL_EXCEPTION_PROLOG | |
598 | EXC_XFER_EE_LITE(0x0c00, DoSyscall) | |
599 | ||
600 | /* Auxillary Processor Unavailable Interrupt */ | |
dc1c1ca3 | 601 | EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
602 | |
603 | /* Decrementer Interrupt */ | |
604 | DECREMENTER_EXCEPTION | |
605 | ||
606 | /* Fixed Internal Timer Interrupt */ | |
607 | /* TODO: Add FIT support */ | |
dc1c1ca3 | 608 | EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
609 | |
610 | /* Watchdog Timer Interrupt */ | |
611 | #ifdef CONFIG_BOOKE_WDT | |
612 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException) | |
613 | #else | |
dc1c1ca3 | 614 | CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception) |
14cf11af PM |
615 | #endif |
616 | ||
617 | /* Data TLB Error Interrupt */ | |
618 | START_EXCEPTION(DataTLBError) | |
619 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
620 | mtspr SPRN_SPRG1, r11 | |
621 | mtspr SPRN_SPRG4W, r12 | |
622 | mtspr SPRN_SPRG5W, r13 | |
623 | mfcr r11 | |
624 | mtspr SPRN_SPRG7W, r11 | |
625 | mfspr r10, SPRN_DEAR /* Get faulting address */ | |
626 | ||
627 | /* If we are faulting a kernel address, we have to use the | |
628 | * kernel page tables. | |
629 | */ | |
8a13c4f9 | 630 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
631 | cmplw 5, r10, r11 |
632 | blt 5, 3f | |
633 | lis r11, swapper_pg_dir@h | |
634 | ori r11, r11, swapper_pg_dir@l | |
635 | ||
636 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
637 | rlwinm r12,r12,0,16,1 | |
638 | mtspr SPRN_MAS1,r12 | |
639 | ||
640 | b 4f | |
641 | ||
642 | /* Get the PGD for the current thread */ | |
643 | 3: | |
644 | mfspr r11,SPRN_SPRG3 | |
645 | lwz r11,PGDIR(r11) | |
646 | ||
647 | 4: | |
648 | FIND_PTE | |
649 | andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ | |
650 | beq 2f /* Bail if not present */ | |
651 | ||
652 | #ifdef CONFIG_PTE_64BIT | |
653 | lwz r13, 0(r12) | |
654 | #endif | |
655 | ori r11, r11, _PAGE_ACCESSED | |
656 | stw r11, PTE_FLAGS_OFFSET(r12) | |
657 | ||
658 | /* Jump to common tlb load */ | |
659 | b finish_tlb_load | |
660 | 2: | |
661 | /* The bailout. Restore registers to pre-exception conditions | |
662 | * and call the heavyweights to help us out. | |
663 | */ | |
664 | mfspr r11, SPRN_SPRG7R | |
665 | mtcr r11 | |
666 | mfspr r13, SPRN_SPRG5R | |
667 | mfspr r12, SPRN_SPRG4R | |
668 | mfspr r11, SPRN_SPRG1 | |
669 | mfspr r10, SPRN_SPRG0 | |
670 | b data_access | |
671 | ||
672 | /* Instruction TLB Error Interrupt */ | |
673 | /* | |
674 | * Nearly the same as above, except we get our | |
675 | * information from different registers and bailout | |
676 | * to a different point. | |
677 | */ | |
678 | START_EXCEPTION(InstructionTLBError) | |
679 | mtspr SPRN_SPRG0, r10 /* Save some working registers */ | |
680 | mtspr SPRN_SPRG1, r11 | |
681 | mtspr SPRN_SPRG4W, r12 | |
682 | mtspr SPRN_SPRG5W, r13 | |
683 | mfcr r11 | |
684 | mtspr SPRN_SPRG7W, r11 | |
685 | mfspr r10, SPRN_SRR0 /* Get faulting address */ | |
686 | ||
687 | /* If we are faulting a kernel address, we have to use the | |
688 | * kernel page tables. | |
689 | */ | |
8a13c4f9 | 690 | lis r11, PAGE_OFFSET@h |
14cf11af PM |
691 | cmplw 5, r10, r11 |
692 | blt 5, 3f | |
693 | lis r11, swapper_pg_dir@h | |
694 | ori r11, r11, swapper_pg_dir@l | |
695 | ||
696 | mfspr r12,SPRN_MAS1 /* Set TID to 0 */ | |
697 | rlwinm r12,r12,0,16,1 | |
698 | mtspr SPRN_MAS1,r12 | |
699 | ||
700 | b 4f | |
701 | ||
702 | /* Get the PGD for the current thread */ | |
703 | 3: | |
704 | mfspr r11,SPRN_SPRG3 | |
705 | lwz r11,PGDIR(r11) | |
706 | ||
707 | 4: | |
708 | FIND_PTE | |
709 | andi. r13, r11, _PAGE_PRESENT /* Is the page present? */ | |
710 | beq 2f /* Bail if not present */ | |
711 | ||
712 | #ifdef CONFIG_PTE_64BIT | |
713 | lwz r13, 0(r12) | |
714 | #endif | |
715 | ori r11, r11, _PAGE_ACCESSED | |
716 | stw r11, PTE_FLAGS_OFFSET(r12) | |
717 | ||
718 | /* Jump to common TLB load point */ | |
719 | b finish_tlb_load | |
720 | ||
721 | 2: | |
722 | /* The bailout. Restore registers to pre-exception conditions | |
723 | * and call the heavyweights to help us out. | |
724 | */ | |
725 | mfspr r11, SPRN_SPRG7R | |
726 | mtcr r11 | |
727 | mfspr r13, SPRN_SPRG5R | |
728 | mfspr r12, SPRN_SPRG4R | |
729 | mfspr r11, SPRN_SPRG1 | |
730 | mfspr r10, SPRN_SPRG0 | |
731 | b InstructionStorage | |
732 | ||
733 | #ifdef CONFIG_SPE | |
734 | /* SPE Unavailable */ | |
735 | START_EXCEPTION(SPEUnavailable) | |
736 | NORMAL_EXCEPTION_PROLOG | |
737 | bne load_up_spe | |
3c5df5c2 | 738 | addi r3,r1,STACK_FRAME_OVERHEAD |
14cf11af PM |
739 | EXC_XFER_EE_LITE(0x2010, KernelSPE) |
740 | #else | |
dc1c1ca3 | 741 | EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
742 | #endif /* CONFIG_SPE */ |
743 | ||
744 | /* SPE Floating Point Data */ | |
745 | #ifdef CONFIG_SPE | |
746 | EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE); | |
747 | #else | |
dc1c1ca3 | 748 | EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
749 | #endif /* CONFIG_SPE */ |
750 | ||
751 | /* SPE Floating Point Round */ | |
dc1c1ca3 | 752 | EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE) |
14cf11af PM |
753 | |
754 | /* Performance Monitor */ | |
dc1c1ca3 | 755 | EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD) |
14cf11af | 756 | |
3dfa8773 KG |
757 | #ifdef CONFIG_PPC_E500MC |
758 | EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_EE) | |
759 | #endif | |
14cf11af PM |
760 | |
761 | /* Debug Interrupt */ | |
eb0cd5fd | 762 | DEBUG_DEBUG_EXCEPTION |
3dfa8773 | 763 | #if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC) |
eb0cd5fd KG |
764 | DEBUG_CRIT_EXCEPTION |
765 | #endif | |
14cf11af PM |
766 | |
767 | /* | |
768 | * Local functions | |
769 | */ | |
770 | ||
771 | /* | |
772 | * Data TLB exceptions will bail out to this point | |
773 | * if they can't resolve the lightweight TLB fault. | |
774 | */ | |
775 | data_access: | |
776 | NORMAL_EXCEPTION_PROLOG | |
777 | mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */ | |
778 | stw r5,_ESR(r11) | |
779 | mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */ | |
780 | andis. r10,r5,(ESR_ILK|ESR_DLK)@h | |
781 | bne 1f | |
782 | EXC_XFER_EE_LITE(0x0300, handle_page_fault) | |
783 | 1: | |
784 | addi r3,r1,STACK_FRAME_OVERHEAD | |
785 | EXC_XFER_EE_LITE(0x0300, CacheLockingException) | |
786 | ||
787 | /* | |
788 | ||
789 | * Both the instruction and data TLB miss get to this | |
790 | * point to load the TLB. | |
3c5df5c2 KG |
791 | * r10 - EA of fault |
792 | * r11 - TLB (info from Linux PTE) | |
793 | * r12, r13 - available to use | |
8a13c4f9 | 794 | * CR5 - results of addr >= PAGE_OFFSET |
14cf11af PM |
795 | * MAS0, MAS1 - loaded with proper value when we get here |
796 | * MAS2, MAS3 - will need additional info from Linux PTE | |
797 | * Upon exit, we reload everything and RFI. | |
798 | */ | |
799 | finish_tlb_load: | |
800 | /* | |
801 | * We set execute, because we don't have the granularity to | |
802 | * properly set this at the page level (Linux problem). | |
803 | * Many of these bits are software only. Bits we don't set | |
804 | * here we (properly should) assume have the appropriate value. | |
805 | */ | |
806 | ||
807 | mfspr r12, SPRN_MAS2 | |
808 | #ifdef CONFIG_PTE_64BIT | |
809 | rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */ | |
810 | #else | |
811 | rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */ | |
812 | #endif | |
813 | mtspr SPRN_MAS2, r12 | |
814 | ||
815 | bge 5, 1f | |
816 | ||
817 | /* is user addr */ | |
818 | andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC) | |
819 | andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */ | |
820 | srwi r10, r12, 1 | |
821 | or r12, r12, r10 /* Copy user perms into supervisor */ | |
822 | iseleq r12, 0, r12 | |
823 | b 2f | |
824 | ||
825 | /* is kernel addr */ | |
826 | 1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */ | |
827 | ori r12, r12, (MAS3_SX | MAS3_SR) | |
828 | ||
829 | #ifdef CONFIG_PTE_64BIT | |
830 | 2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */ | |
831 | rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */ | |
832 | mtspr SPRN_MAS3, r12 | |
833 | BEGIN_FTR_SECTION | |
834 | srwi r10, r13, 8 /* grab RPN[8:31] */ | |
835 | mtspr SPRN_MAS7, r10 | |
836 | END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS) | |
837 | #else | |
838 | 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ | |
839 | mtspr SPRN_MAS3, r11 | |
840 | #endif | |
841 | #ifdef CONFIG_E200 | |
842 | /* Round robin TLB1 entries assignment */ | |
843 | mfspr r12, SPRN_MAS0 | |
844 | ||
845 | /* Extract TLB1CFG(NENTRY) */ | |
846 | mfspr r11, SPRN_TLB1CFG | |
847 | andi. r11, r11, 0xfff | |
848 | ||
849 | /* Extract MAS0(NV) */ | |
850 | andi. r13, r12, 0xfff | |
851 | addi r13, r13, 1 | |
852 | cmpw 0, r13, r11 | |
853 | addi r12, r12, 1 | |
854 | ||
855 | /* check if we need to wrap */ | |
856 | blt 7f | |
857 | ||
858 | /* wrap back to first free tlbcam entry */ | |
859 | lis r13, tlbcam_index@ha | |
860 | lwz r13, tlbcam_index@l(r13) | |
861 | rlwimi r12, r13, 0, 20, 31 | |
862 | 7: | |
3c5df5c2 | 863 | mtspr SPRN_MAS0,r12 |
14cf11af PM |
864 | #endif /* CONFIG_E200 */ |
865 | ||
866 | tlbwe | |
867 | ||
868 | /* Done...restore registers and get out of here. */ | |
869 | mfspr r11, SPRN_SPRG7R | |
870 | mtcr r11 | |
871 | mfspr r13, SPRN_SPRG5R | |
872 | mfspr r12, SPRN_SPRG4R | |
873 | mfspr r11, SPRN_SPRG1 | |
874 | mfspr r10, SPRN_SPRG0 | |
875 | rfi /* Force context change */ | |
876 | ||
877 | #ifdef CONFIG_SPE | |
878 | /* Note that the SPE support is closely modeled after the AltiVec | |
879 | * support. Changes to one are likely to be applicable to the | |
880 | * other! */ | |
881 | load_up_spe: | |
882 | /* | |
883 | * Disable SPE for the task which had SPE previously, | |
884 | * and save its SPE registers in its thread_struct. | |
885 | * Enables SPE for use in the kernel on return. | |
886 | * On SMP we know the SPE units are free, since we give it up every | |
887 | * switch. -- Kumar | |
888 | */ | |
889 | mfmsr r5 | |
890 | oris r5,r5,MSR_SPE@h | |
891 | mtmsr r5 /* enable use of SPE now */ | |
892 | isync | |
893 | /* | |
894 | * For SMP, we don't do lazy SPE switching because it just gets too | |
895 | * horrendously complex, especially when a task switches from one CPU | |
896 | * to another. Instead we call giveup_spe in switch_to. | |
897 | */ | |
898 | #ifndef CONFIG_SMP | |
899 | lis r3,last_task_used_spe@ha | |
900 | lwz r4,last_task_used_spe@l(r3) | |
901 | cmpi 0,r4,0 | |
902 | beq 1f | |
903 | addi r4,r4,THREAD /* want THREAD of last_task_used_spe */ | |
904 | SAVE_32EVRS(0,r10,r4) | |
3c5df5c2 | 905 | evxor evr10, evr10, evr10 /* clear out evr10 */ |
14cf11af PM |
906 | evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */ |
907 | li r5,THREAD_ACC | |
3c5df5c2 | 908 | evstddx evr10, r4, r5 /* save off accumulator */ |
14cf11af PM |
909 | lwz r5,PT_REGS(r4) |
910 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
911 | lis r10,MSR_SPE@h | |
912 | andc r4,r4,r10 /* disable SPE for previous task */ | |
913 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
914 | 1: | |
3c5df5c2 | 915 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
916 | /* enable use of SPE after return */ |
917 | oris r9,r9,MSR_SPE@h | |
918 | mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */ | |
919 | li r4,1 | |
920 | li r10,THREAD_ACC | |
921 | stw r4,THREAD_USED_SPE(r5) | |
922 | evlddx evr4,r10,r5 | |
923 | evmra evr4,evr4 | |
924 | REST_32EVRS(0,r10,r5) | |
925 | #ifndef CONFIG_SMP | |
926 | subi r4,r5,THREAD | |
927 | stw r4,last_task_used_spe@l(r3) | |
3c5df5c2 | 928 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
929 | /* restore registers and return */ |
930 | 2: REST_4GPRS(3, r11) | |
931 | lwz r10,_CCR(r11) | |
932 | REST_GPR(1, r11) | |
933 | mtcr r10 | |
934 | lwz r10,_LINK(r11) | |
935 | mtlr r10 | |
936 | REST_GPR(10, r11) | |
937 | mtspr SPRN_SRR1,r9 | |
938 | mtspr SPRN_SRR0,r12 | |
939 | REST_GPR(9, r11) | |
940 | REST_GPR(12, r11) | |
941 | lwz r11,GPR11(r11) | |
14cf11af PM |
942 | rfi |
943 | ||
944 | /* | |
945 | * SPE unavailable trap from kernel - print a message, but let | |
946 | * the task use SPE in the kernel until it returns to user mode. | |
947 | */ | |
948 | KernelSPE: | |
949 | lwz r3,_MSR(r1) | |
950 | oris r3,r3,MSR_SPE@h | |
951 | stw r3,_MSR(r1) /* enable use of SPE after return */ | |
952 | lis r3,87f@h | |
953 | ori r3,r3,87f@l | |
954 | mr r4,r2 /* current */ | |
955 | lwz r5,_NIP(r1) | |
956 | bl printk | |
957 | b ret_from_except | |
958 | 87: .string "SPE used in kernel (task=%p, pc=%x) \n" | |
959 | .align 4,0 | |
960 | ||
961 | #endif /* CONFIG_SPE */ | |
962 | ||
963 | /* | |
964 | * Global functions | |
965 | */ | |
966 | ||
967 | /* | |
968 | * extern void loadcam_entry(unsigned int index) | |
969 | * | |
970 | * Load TLBCAM[index] entry in to the L2 CAM MMU | |
971 | */ | |
972 | _GLOBAL(loadcam_entry) | |
973 | lis r4,TLBCAM@ha | |
974 | addi r4,r4,TLBCAM@l | |
975 | mulli r5,r3,20 | |
976 | add r3,r5,r4 | |
977 | lwz r4,0(r3) | |
978 | mtspr SPRN_MAS0,r4 | |
979 | lwz r4,4(r3) | |
980 | mtspr SPRN_MAS1,r4 | |
981 | lwz r4,8(r3) | |
982 | mtspr SPRN_MAS2,r4 | |
983 | lwz r4,12(r3) | |
984 | mtspr SPRN_MAS3,r4 | |
985 | tlbwe | |
986 | isync | |
987 | blr | |
988 | ||
989 | /* | |
990 | * extern void giveup_altivec(struct task_struct *prev) | |
991 | * | |
992 | * The e500 core does not have an AltiVec unit. | |
993 | */ | |
994 | _GLOBAL(giveup_altivec) | |
995 | blr | |
996 | ||
997 | #ifdef CONFIG_SPE | |
998 | /* | |
999 | * extern void giveup_spe(struct task_struct *prev) | |
1000 | * | |
1001 | */ | |
1002 | _GLOBAL(giveup_spe) | |
1003 | mfmsr r5 | |
1004 | oris r5,r5,MSR_SPE@h | |
14cf11af PM |
1005 | mtmsr r5 /* enable use of SPE now */ |
1006 | isync | |
1007 | cmpi 0,r3,0 | |
1008 | beqlr- /* if no previous owner, done */ | |
1009 | addi r3,r3,THREAD /* want THREAD of task */ | |
1010 | lwz r5,PT_REGS(r3) | |
1011 | cmpi 0,r5,0 | |
1012 | SAVE_32EVRS(0, r4, r3) | |
3c5df5c2 | 1013 | evxor evr6, evr6, evr6 /* clear out evr6 */ |
14cf11af PM |
1014 | evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */ |
1015 | li r4,THREAD_ACC | |
3c5df5c2 | 1016 | evstddx evr6, r4, r3 /* save off accumulator */ |
14cf11af PM |
1017 | mfspr r6,SPRN_SPEFSCR |
1018 | stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */ | |
1019 | beq 1f | |
1020 | lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1021 | lis r3,MSR_SPE@h | |
1022 | andc r4,r4,r3 /* disable SPE for previous task */ | |
1023 | stw r4,_MSR-STACK_FRAME_OVERHEAD(r5) | |
1024 | 1: | |
1025 | #ifndef CONFIG_SMP | |
1026 | li r5,0 | |
1027 | lis r4,last_task_used_spe@ha | |
1028 | stw r5,last_task_used_spe@l(r4) | |
3c5df5c2 | 1029 | #endif /* !CONFIG_SMP */ |
14cf11af PM |
1030 | blr |
1031 | #endif /* CONFIG_SPE */ | |
1032 | ||
1033 | /* | |
1034 | * extern void giveup_fpu(struct task_struct *prev) | |
1035 | * | |
1036 | * Not all FSL Book-E cores have an FPU | |
1037 | */ | |
1038 | #ifndef CONFIG_PPC_FPU | |
1039 | _GLOBAL(giveup_fpu) | |
1040 | blr | |
1041 | #endif | |
1042 | ||
1043 | /* | |
1044 | * extern void abort(void) | |
1045 | * | |
1046 | * At present, this routine just applies a system reset. | |
1047 | */ | |
1048 | _GLOBAL(abort) | |
1049 | li r13,0 | |
3c5df5c2 | 1050 | mtspr SPRN_DBCR0,r13 /* disable all debug events */ |
a7cb0337 | 1051 | isync |
14cf11af PM |
1052 | mfmsr r13 |
1053 | ori r13,r13,MSR_DE@l /* Enable Debug Events */ | |
1054 | mtmsr r13 | |
a7cb0337 | 1055 | isync |
3c5df5c2 KG |
1056 | mfspr r13,SPRN_DBCR0 |
1057 | lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h | |
1058 | mtspr SPRN_DBCR0,r13 | |
a7cb0337 | 1059 | isync |
14cf11af PM |
1060 | |
1061 | _GLOBAL(set_context) | |
1062 | ||
1063 | #ifdef CONFIG_BDI_SWITCH | |
1064 | /* Context switch the PTE pointer for the Abatron BDI2000. | |
1065 | * The PGDIR is the second parameter. | |
1066 | */ | |
1067 | lis r5, abatron_pteptrs@h | |
1068 | ori r5, r5, abatron_pteptrs@l | |
1069 | stw r4, 0x4(r5) | |
1070 | #endif | |
1071 | mtspr SPRN_PID,r3 | |
1072 | isync /* Force context change */ | |
1073 | blr | |
1074 | ||
fc4033b2 KG |
1075 | _GLOBAL(flush_dcache_L1) |
1076 | mfspr r3,SPRN_L1CFG0 | |
1077 | ||
1078 | rlwinm r5,r3,9,3 /* Extract cache block size */ | |
1079 | twlgti r5,1 /* Only 32 and 64 byte cache blocks | |
1080 | * are currently defined. | |
1081 | */ | |
1082 | li r4,32 | |
1083 | subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) - | |
1084 | * log2(number of ways) | |
1085 | */ | |
1086 | slw r5,r4,r5 /* r5 = cache block size */ | |
1087 | ||
1088 | rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */ | |
1089 | mulli r7,r7,13 /* An 8-way cache will require 13 | |
1090 | * loads per set. | |
1091 | */ | |
1092 | slw r7,r7,r6 | |
1093 | ||
1094 | /* save off HID0 and set DCFA */ | |
1095 | mfspr r8,SPRN_HID0 | |
1096 | ori r9,r8,HID0_DCFA@l | |
1097 | mtspr SPRN_HID0,r9 | |
1098 | isync | |
1099 | ||
1100 | lis r4,KERNELBASE@h | |
1101 | mtctr r7 | |
1102 | ||
1103 | 1: lwz r3,0(r4) /* Load... */ | |
1104 | add r4,r4,r5 | |
1105 | bdnz 1b | |
1106 | ||
1107 | msync | |
1108 | lis r4,KERNELBASE@h | |
1109 | mtctr r7 | |
1110 | ||
1111 | 1: dcbf 0,r4 /* ...and flush. */ | |
1112 | add r4,r4,r5 | |
1113 | bdnz 1b | |
1114 | ||
1115 | /* restore HID0 */ | |
1116 | mtspr SPRN_HID0,r8 | |
1117 | isync | |
1118 | ||
1119 | blr | |
1120 | ||
14cf11af PM |
1121 | /* |
1122 | * We put a few things here that have to be page-aligned. This stuff | |
1123 | * goes at the beginning of the data segment, which is page-aligned. | |
1124 | */ | |
1125 | .data | |
ea703ce2 KG |
1126 | .align 12 |
1127 | .globl sdata | |
1128 | sdata: | |
1129 | .globl empty_zero_page | |
1130 | empty_zero_page: | |
14cf11af | 1131 | .space 4096 |
ea703ce2 KG |
1132 | .globl swapper_pg_dir |
1133 | swapper_pg_dir: | |
bee86f14 | 1134 | .space PGD_TABLE_SIZE |
14cf11af | 1135 | |
14cf11af PM |
1136 | /* |
1137 | * Room for two PTE pointers, usually the kernel and current user pointers | |
1138 | * to their respective root page table. | |
1139 | */ | |
1140 | abatron_pteptrs: | |
1141 | .space 8 |