[mirror_ubuntu-bionic-kernel.git] / arch / powerpc / kernel / hw_breakpoint.c

/*
 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
 * using the CPU's debug registers. Derived from
 * "arch/x86/kernel/hw_breakpoint.c"
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright 2010 IBM Corporation
 * Author: K.Prasad <prasad@linux.vnet.ibm.com>
 *
 */

#include <linux/hw_breakpoint.h>
#include <linux/notifier.h>
#include <linux/kprobes.h>
#include <linux/percpu.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/smp.h>

#include <asm/hw_breakpoint.h>
#include <asm/processor.h>
#include <asm/sstep.h>
#include <asm/uaccess.h>

/*
 * Stores the breakpoints currently in use on each breakpoint address
 * register for every cpu
 */
static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);

/*
 * Returns total number of data or instruction breakpoints available.
 */
int hw_breakpoint_slots(int type)
{
	if (type == TYPE_DATA)
		return HBP_NUM;
	return 0;		/* no instruction breakpoints available */
}

/*
 * Install a perf counter breakpoint.
 *
 * We seek a free debug address register and use it for this
 * breakpoint.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
int arch_install_hw_breakpoint(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	struct perf_event **slot = &__get_cpu_var(bp_per_reg);

	*slot = bp;

	/*
	 * Do not install DABR values if the instruction must be single-stepped.
	 * If so, DABR will be populated in single_step_dabr_instruction().
	 */
	if (current->thread.last_hit_ubp != bp)
		set_breakpoint(info);

	return 0;
}

/*
 * Uninstall the breakpoint contained in the given counter.
 *
 * First we search the debug address register it uses and then we disable
 * it.
 *
 * Atomic: we hold the counter->ctx->lock and we only handle variables
 * and registers local to this cpu.
 */
void arch_uninstall_hw_breakpoint(struct perf_event *bp)
{
	struct perf_event **slot = &__get_cpu_var(bp_per_reg);

	if (*slot != bp) {
		WARN_ONCE(1, "Can't find the breakpoint");
		return;
	}

	*slot = NULL;
	hw_breakpoint_disable();
}

/*
 * Perform cleanup of arch-specific counters during unregistration
 * of the perf-event
 */
void arch_unregister_hw_breakpoint(struct perf_event *bp)
{
	/*
	 * If the breakpoint is unregistered between a hw_breakpoint_handler()
	 * and the single_step_dabr_instruction(), then cleanup the breakpoint
	 * restoration variables to prevent dangling pointers.
	 */
	if (bp->ctx && bp->ctx->task)
		bp->ctx->task->thread.last_hit_ubp = NULL;
}

/*
 * Check for virtual address in kernel space.
 */
int arch_check_bp_in_kernelspace(struct perf_event *bp)
{
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	return is_kernel_addr(info->address);
}

int arch_bp_generic_fields(int type, int *gen_bp_type)
{
	*gen_bp_type = 0;
	if (type & HW_BRK_TYPE_READ)
		*gen_bp_type |= HW_BREAKPOINT_R;
	if (type & HW_BRK_TYPE_WRITE)
		*gen_bp_type |= HW_BREAKPOINT_W;
	if (*gen_bp_type == 0)
		return -EINVAL;
	return 0;
}

/*
 * Validate the arch-specific HW Breakpoint register settings
 */
int arch_validate_hwbkpt_settings(struct perf_event *bp)
{
	int ret = -EINVAL;
	struct arch_hw_breakpoint *info = counter_arch_bp(bp);

	if (!bp)
		return ret;

	info->type = HW_BRK_TYPE_TRANSLATE;
	if (bp->attr.bp_type & HW_BREAKPOINT_R)
		info->type |= HW_BRK_TYPE_READ;
	if (bp->attr.bp_type & HW_BREAKPOINT_W)
		info->type |= HW_BRK_TYPE_WRITE;
	if (info->type == HW_BRK_TYPE_TRANSLATE)
		/* must set alteast read or write */
		return ret;
	if (!(bp->attr.exclude_user))
		info->type |= HW_BRK_TYPE_USER;
	if (!(bp->attr.exclude_kernel))
		info->type |= HW_BRK_TYPE_KERNEL;
	if (!(bp->attr.exclude_hv))
		info->type |= HW_BRK_TYPE_HYP;
	info->address = bp->attr.bp_addr;
	info->len = bp->attr.bp_len;

	/*
	 * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
	 * and breakpoint addresses are aligned to nearest double-word
	 * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
	 * 'symbolsize' should satisfy the check below.
	 */
	if (info->len >
	    (HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
		return -EINVAL;
	return 0;
}

/*
 * Restores the breakpoint on the debug registers.
 * Invoke this function if it is known that the execution context is
 * about to change to cause loss of MSR_SE settings.
 */
void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
{
	struct arch_hw_breakpoint *info;

	if (likely(!tsk->thread.last_hit_ubp))
		return;

	info = counter_arch_bp(tsk->thread.last_hit_ubp);
	regs->msr &= ~MSR_SE;
	set_breakpoint(info);
	tsk->thread.last_hit_ubp = NULL;
}

/*
 * Handle debug exception notifications.
 */
int __kprobes hw_breakpoint_handler(struct die_args *args)
{
	int rc = NOTIFY_STOP;
	struct perf_event *bp;
	struct pt_regs *regs = args->regs;
	int stepped = 1;
	struct arch_hw_breakpoint *info;
	unsigned int instr;
	unsigned long dar = regs->dar;

	/* Disable breakpoints during exception handling */
	hw_breakpoint_disable();

	/*
	 * The counter may be concurrently released but that can only
	 * occur from a call_rcu() path. We can then safely fetch
	 * the breakpoint, use its callback, touch its counter
	 * while we are in an rcu_read_lock() path.
	 */
	rcu_read_lock();

	bp = __get_cpu_var(bp_per_reg);
	if (!bp)
		goto out;
	info = counter_arch_bp(bp);

	/*
	 * Return early after invoking user-callback function without restoring
	 * DABR if the breakpoint is from ptrace which always operates in
	 * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
	 * generated in do_dabr().
	 */
	if (bp->overflow_handler == ptrace_triggered) {
		perf_bp_event(bp, regs);
		rc = NOTIFY_DONE;
		goto out;
	}

	/*
	 * Verify if dar lies within the address range occupied by the symbol
	 * being watched to filter extraneous exceptions.  If it doesn't,
	 * we still need to single-step the instruction, but we don't
	 * generate an event.
	 */
	if (!((bp->attr.bp_addr <= dar) &&
	      (dar - bp->attr.bp_addr < bp->attr.bp_len)))
		info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;

	/* Do not emulate user-space instructions, instead single-step them */
	if (user_mode(regs)) {
		current->thread.last_hit_ubp = bp;
		regs->msr |= MSR_SE;
		goto out;
	}

	stepped = 0;
	instr = 0;
	if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
		stepped = emulate_step(regs, instr);

	/*
	 * emulate_step() could not execute it. We've failed in reliably
	 * handling the hw-breakpoint. Unregister it and throw a warning
	 * message to let the user know about it.
	 */
	if (!stepped) {
		WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
			"0x%lx will be disabled.", info->address);
		perf_event_disable(bp);
		goto out;
	}
	/*
	 * As a policy, the callback is invoked in a 'trigger-after-execute'
	 * fashion
	 */
	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
		perf_bp_event(bp, regs);

	set_breakpoint(info);
out:
	rcu_read_unlock();
	return rc;
}

/*
 * Handle single-step exceptions following a DABR hit.
 */
int __kprobes single_step_dabr_instruction(struct die_args *args)
{
	struct pt_regs *regs = args->regs;
	struct perf_event *bp = NULL;
	struct arch_hw_breakpoint *info;

	bp = current->thread.last_hit_ubp;
	/*
	 * Check if we are single-stepping as a result of a
	 * previous HW Breakpoint exception
	 */
	if (!bp)
		return NOTIFY_DONE;

	info = counter_arch_bp(bp);

	/*
	 * We shall invoke the user-defined callback function in the single
	 * stepping handler to confirm to 'trigger-after-execute' semantics
	 */
	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
		perf_bp_event(bp, regs);

	set_breakpoint(info);
	current->thread.last_hit_ubp = NULL;

	/*
	 * If the process was being single-stepped by ptrace, let the
	 * other single-step actions occur (e.g. generate SIGTRAP).
	 */
	if (test_thread_flag(TIF_SINGLESTEP))
		return NOTIFY_DONE;

	return NOTIFY_STOP;
}

/*
 * Handle debug exception notifications.
 */
int __kprobes hw_breakpoint_exceptions_notify(
		struct notifier_block *unused, unsigned long val, void *data)
{
	int ret = NOTIFY_DONE;

	switch (val) {
	case DIE_DABR_MATCH:
		ret = hw_breakpoint_handler(data);
		break;
	case DIE_SSTEP:
		ret = single_step_dabr_instruction(data);
		break;
	}

	return ret;
}

/*
 * Release the user breakpoints used by ptrace
 */
void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
{
	struct thread_struct *t = &tsk->thread;

	unregister_hw_breakpoint(t->ptrace_bps[0]);
	t->ptrace_bps[0] = NULL;
}

void hw_breakpoint_pmu_read(struct perf_event *bp)
{
	/* TODO */
}
Commit	Line	Data
5aae8a53 P	1	/*
	2	* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
	3	* using the CPU's debug registers. Derived from
	4	* "arch/x86/kernel/hw_breakpoint.c"
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	19	*
	20	* Copyright 2010 IBM Corporation
	21	* Author: K.Prasad <prasad@linux.vnet.ibm.com>
	22	*
	23	*/
	24
	25	#include <linux/hw_breakpoint.h>
	26	#include <linux/notifier.h>
	27	#include <linux/kprobes.h>
	28	#include <linux/percpu.h>
	29	#include <linux/kernel.h>
5aae8a53 P	30	#include <linux/sched.h>
	31	#include <linux/init.h>
	32	#include <linux/smp.h>
	33
	34	#include <asm/hw_breakpoint.h>
	35	#include <asm/processor.h>
	36	#include <asm/sstep.h>
	37	#include <asm/uaccess.h>
	38
	39	/*
	40	* Stores the breakpoints currently in use on each breakpoint address
	41	* register for every cpu
	42	*/
	43	static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
	44
d09ec738 PM	45	/*
	46	* Returns total number of data or instruction breakpoints available.
	47	*/
	48	int hw_breakpoint_slots(int type)
	49	{
	50	if (type == TYPE_DATA)
	51	return HBP_NUM;
	52	return 0; /* no instruction breakpoints available */
	53	}
	54
5aae8a53 P	55	/*
	56	* Install a perf counter breakpoint.
	57	*
	58	* We seek a free debug address register and use it for this
	59	* breakpoint.
	60	*
	61	* Atomic: we hold the counter->ctx->lock and we only handle variables
	62	* and registers local to this cpu.
	63	*/
	64	int arch_install_hw_breakpoint(struct perf_event *bp)
	65	{
	66	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	67	struct perf_event **slot = &__get_cpu_var(bp_per_reg);
	68
	69	*slot = bp;
	70
	71	/*
	72	* Do not install DABR values if the instruction must be single-stepped.
	73	* If so, DABR will be populated in single_step_dabr_instruction().
	74	*/
	75	if (current->thread.last_hit_ubp != bp)
b9818c33	76	set_breakpoint(info);
5aae8a53 P	77
	78	return 0;
	79	}
	80
	81	/*
	82	* Uninstall the breakpoint contained in the given counter.
	83	*
	84	* First we search the debug address register it uses and then we disable
	85	* it.
	86	*
	87	* Atomic: we hold the counter->ctx->lock and we only handle variables
	88	* and registers local to this cpu.
	89	*/
	90	void arch_uninstall_hw_breakpoint(struct perf_event *bp)
	91	{
	92	struct perf_event **slot = &__get_cpu_var(bp_per_reg);
	93
	94	if (*slot != bp) {
	95	WARN_ONCE(1, "Can't find the breakpoint");
	96	return;
	97	}
	98
	99	*slot = NULL;
9422de3e	100	hw_breakpoint_disable();
5aae8a53 P	101	}
	102
	103	/*
	104	* Perform cleanup of arch-specific counters during unregistration
	105	* of the perf-event
	106	*/
	107	void arch_unregister_hw_breakpoint(struct perf_event *bp)
	108	{
	109	/*
	110	* If the breakpoint is unregistered between a hw_breakpoint_handler()
	111	* and the single_step_dabr_instruction(), then cleanup the breakpoint
	112	* restoration variables to prevent dangling pointers.
	113	*/
ac84aa2b	114	if (bp->ctx && bp->ctx->task)
5aae8a53 P	115	bp->ctx->task->thread.last_hit_ubp = NULL;
	116	}
	117
	118	/*
	119	* Check for virtual address in kernel space.
	120	*/
	121	int arch_check_bp_in_kernelspace(struct perf_event *bp)
	122	{
	123	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	124
	125	return is_kernel_addr(info->address);
	126	}
	127
	128	int arch_bp_generic_fields(int type, int *gen_bp_type)
	129	{
9422de3e MN	130	*gen_bp_type = 0;
	131	if (type & HW_BRK_TYPE_READ)
	132	*gen_bp_type \|= HW_BREAKPOINT_R;
	133	if (type & HW_BRK_TYPE_WRITE)
	134	*gen_bp_type \|= HW_BREAKPOINT_W;
	135	if (*gen_bp_type == 0)
5aae8a53	136	return -EINVAL;
5aae8a53 P	137	return 0;
	138	}
	139
	140	/*
	141	* Validate the arch-specific HW Breakpoint register settings
	142	*/
	143	int arch_validate_hwbkpt_settings(struct perf_event *bp)
	144	{
	145	int ret = -EINVAL;
	146	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
	147
	148	if (!bp)
	149	return ret;
	150
9422de3e MN	151	info->type = HW_BRK_TYPE_TRANSLATE;
	152	if (bp->attr.bp_type & HW_BREAKPOINT_R)
	153	info->type \|= HW_BRK_TYPE_READ;
	154	if (bp->attr.bp_type & HW_BREAKPOINT_W)
	155	info->type \|= HW_BRK_TYPE_WRITE;
	156	if (info->type == HW_BRK_TYPE_TRANSLATE)
	157	/* must set alteast read or write */
5aae8a53	158	return ret;
9422de3e MN	159	if (!(bp->attr.exclude_user))
	160	info->type \|= HW_BRK_TYPE_USER;
	161	if (!(bp->attr.exclude_kernel))
	162	info->type \|= HW_BRK_TYPE_KERNEL;
	163	if (!(bp->attr.exclude_hv))
	164	info->type \|= HW_BRK_TYPE_HYP;
5aae8a53 P	165	info->address = bp->attr.bp_addr;
	166	info->len = bp->attr.bp_len;
	167
	168	/*
	169	* Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
	170	* and breakpoint addresses are aligned to nearest double-word
	171	* HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
	172	* 'symbolsize' should satisfy the check below.
	173	*/
	174	if (info->len >
	175	(HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
	176	return -EINVAL;
	177	return 0;
	178	}
	179
06532a67 P	180	/*
	181	* Restores the breakpoint on the debug registers.
	182	* Invoke this function if it is known that the execution context is
	183	* about to change to cause loss of MSR_SE settings.
	184	*/
	185	void thread_change_pc(struct task_struct tsk, struct pt_regs regs)
	186	{
	187	struct arch_hw_breakpoint *info;
	188
	189	if (likely(!tsk->thread.last_hit_ubp))
	190	return;
	191
	192	info = counter_arch_bp(tsk->thread.last_hit_ubp);
	193	regs->msr &= ~MSR_SE;
b9818c33	194	set_breakpoint(info);
06532a67 P	195	tsk->thread.last_hit_ubp = NULL;
	196	}
	197
5aae8a53 P	198	/*
	199	* Handle debug exception notifications.
	200	*/
	201	int __kprobes hw_breakpoint_handler(struct die_args *args)
	202	{
5aae8a53 P	203	int rc = NOTIFY_STOP;
	204	struct perf_event *bp;
	205	struct pt_regs *regs = args->regs;
	206	int stepped = 1;
	207	struct arch_hw_breakpoint *info;
	208	unsigned int instr;
e3e94084	209	unsigned long dar = regs->dar;
5aae8a53 P	210
5aae8a53 P	211	/* Disable breakpoints during exception handling */
9422de3e	212	hw_breakpoint_disable();
574cb248	213
5aae8a53 P	214	/*
	215	* The counter may be concurrently released but that can only
	216	* occur from a call_rcu() path. We can then safely fetch
	217	* the breakpoint, use its callback, touch its counter
	218	* while we are in an rcu_read_lock() path.
	219	*/
	220	rcu_read_lock();
	221
	222	bp = __get_cpu_var(bp_per_reg);
	223	if (!bp)
	224	goto out;
	225	info = counter_arch_bp(bp);
5aae8a53 P	226
	227	/*
	228	* Return early after invoking user-callback function without restoring
	229	* DABR if the breakpoint is from ptrace which always operates in
	230	* one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
	231	* generated in do_dabr().
	232	*/
574cb248	233	if (bp->overflow_handler == ptrace_triggered) {
5aae8a53 P	234	perf_bp_event(bp, regs);
	235	rc = NOTIFY_DONE;
	236	goto out;
	237	}
	238
e3e94084 P	239	/*
e3e94084 P	240	* Verify if dar lies within the address range occupied by the symbol
574cb248 PM	241	* being watched to filter extraneous exceptions. If it doesn't,
	242	* we still need to single-step the instruction, but we don't
	243	* generate an event.
e3e94084	244	*/
9422de3e MN	245	if (!((bp->attr.bp_addr <= dar) &&
	246	(dar - bp->attr.bp_addr < bp->attr.bp_len)))
	247	info->type \|= HW_BRK_TYPE_EXTRANEOUS_IRQ;
e3e94084	248
5aae8a53 P	249	/* Do not emulate user-space instructions, instead single-step them */
5aae8a53 P	250	if (user_mode(regs)) {
6d9c00c6	251	current->thread.last_hit_ubp = bp;
5aae8a53 P	252	regs->msr \|= MSR_SE;
	253	goto out;
	254	}
	255
	256	stepped = 0;
	257	instr = 0;
	258	if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
	259	stepped = emulate_step(regs, instr);
	260
	261	/*
	262	* emulate_step() could not execute it. We've failed in reliably
	263	* handling the hw-breakpoint. Unregister it and throw a warning
	264	* message to let the user know about it.
	265	*/
	266	if (!stepped) {
	267	WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
	268	"0x%lx will be disabled.", info->address);
	269	perf_event_disable(bp);
	270	goto out;
	271	}
	272	/*
	273	* As a policy, the callback is invoked in a 'trigger-after-execute'
	274	* fashion
	275	*/
9422de3e	276	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
e3e94084	277	perf_bp_event(bp, regs);
5aae8a53	278
b9818c33	279	set_breakpoint(info);
5aae8a53 P	280	out:
	281	rcu_read_unlock();
	282	return rc;
	283	}
	284
	285	/*
	286	* Handle single-step exceptions following a DABR hit.
	287	*/
	288	int __kprobes single_step_dabr_instruction(struct die_args *args)
	289	{
	290	struct pt_regs *regs = args->regs;
	291	struct perf_event *bp = NULL;
3f4693ee	292	struct arch_hw_breakpoint *info;
5aae8a53 P	293
	294	bp = current->thread.last_hit_ubp;
	295	/*
	296	* Check if we are single-stepping as a result of a
	297	* previous HW Breakpoint exception
	298	*/
	299	if (!bp)
	300	return NOTIFY_DONE;
	301
3f4693ee	302	info = counter_arch_bp(bp);
5aae8a53 P	303
	304	/*
	305	* We shall invoke the user-defined callback function in the single
	306	* stepping handler to confirm to 'trigger-after-execute' semantics
	307	*/
9422de3e	308	if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
e3e94084	309	perf_bp_event(bp, regs);
5aae8a53	310
b9818c33	311	set_breakpoint(info);
76b0f133 PM	312	current->thread.last_hit_ubp = NULL;
76b0f133 PM	313
5aae8a53	314	/*
76b0f133 PM	315	* If the process was being single-stepped by ptrace, let the
76b0f133 PM	316	* other single-step actions occur (e.g. generate SIGTRAP).
5aae8a53	317	*/
76b0f133 PM	318	if (test_thread_flag(TIF_SINGLESTEP))
76b0f133 PM	319	return NOTIFY_DONE;
5aae8a53	320
5aae8a53 P	321	return NOTIFY_STOP;
	322	}
	323
	324	/*
	325	* Handle debug exception notifications.
	326	*/
	327	int __kprobes hw_breakpoint_exceptions_notify(
	328	struct notifier_block unused, unsigned long val, void data)
	329	{
	330	int ret = NOTIFY_DONE;
	331
	332	switch (val) {
	333	case DIE_DABR_MATCH:
	334	ret = hw_breakpoint_handler(data);
	335	break;
	336	case DIE_SSTEP:
	337	ret = single_step_dabr_instruction(data);
	338	break;
	339	}
	340
	341	return ret;
	342	}
	343
	344	/*
	345	* Release the user breakpoints used by ptrace
	346	*/
	347	void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
	348	{
	349	struct thread_struct *t = &tsk->thread;
	350
	351	unregister_hw_breakpoint(t->ptrace_bps[0]);
	352	t->ptrace_bps[0] = NULL;
	353	}
	354
	355	void hw_breakpoint_pmu_read(struct perf_event *bp)
	356	{
	357	/* TODO */
	358	}