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Commit | Line | Data |
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948cf67c | 1 | /* |
5fa6b6bd SP |
2 | * This file contains idle entry/exit functions for POWER7 and |
3 | * POWER8 CPUs. | |
948cf67c BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version | |
8 | * 2 of the License, or (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #include <linux/threads.h> | |
12 | #include <asm/processor.h> | |
13 | #include <asm/page.h> | |
14 | #include <asm/cputable.h> | |
15 | #include <asm/thread_info.h> | |
16 | #include <asm/ppc_asm.h> | |
17 | #include <asm/asm-offsets.h> | |
18 | #include <asm/ppc-opcode.h> | |
7230c564 | 19 | #include <asm/hw_irq.h> |
f0888f70 | 20 | #include <asm/kvm_book3s_asm.h> |
97eb001f | 21 | #include <asm/opal.h> |
7cba160a | 22 | #include <asm/cpuidle.h> |
f64e8084 | 23 | #include <asm/book3s/64/mmu-hash.h> |
948cf67c BH |
24 | |
25 | #undef DEBUG | |
26 | ||
77b54e9f SP |
27 | /* |
28 | * Use unused space in the interrupt stack to save and restore | |
29 | * registers for winkle support. | |
30 | */ | |
31 | #define _SDR1 GPR3 | |
32 | #define _RPR GPR4 | |
33 | #define _SPURR GPR5 | |
34 | #define _PURR GPR6 | |
35 | #define _TSCR GPR7 | |
36 | #define _DSCR GPR8 | |
37 | #define _AMOR GPR9 | |
38 | #define _WORT GPR10 | |
39 | #define _WORC GPR11 | |
40 | ||
aca79d2b | 41 | /* Idle state entry routines */ |
948cf67c | 42 | |
aca79d2b VS |
43 | #define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ |
44 | /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ | |
45 | std r0,0(r1); \ | |
46 | ptesync; \ | |
47 | ld r0,0(r1); \ | |
48 | 1: cmp cr0,r0,r0; \ | |
49 | bne 1b; \ | |
50 | IDLE_INST; \ | |
51 | b . | |
948cf67c | 52 | |
aca79d2b VS |
53 | .text |
54 | ||
0dfffb48 SP |
55 | /* |
56 | * Used by threads before entering deep idle states. Saves SPRs | |
57 | * in interrupt stack frame | |
58 | */ | |
59 | save_sprs_to_stack: | |
60 | /* | |
61 | * Note all register i.e per-core, per-subcore or per-thread is saved | |
62 | * here since any thread in the core might wake up first | |
63 | */ | |
64 | mfspr r3,SPRN_SDR1 | |
65 | std r3,_SDR1(r1) | |
66 | mfspr r3,SPRN_RPR | |
67 | std r3,_RPR(r1) | |
68 | mfspr r3,SPRN_SPURR | |
69 | std r3,_SPURR(r1) | |
70 | mfspr r3,SPRN_PURR | |
71 | std r3,_PURR(r1) | |
72 | mfspr r3,SPRN_TSCR | |
73 | std r3,_TSCR(r1) | |
74 | mfspr r3,SPRN_DSCR | |
75 | std r3,_DSCR(r1) | |
76 | mfspr r3,SPRN_AMOR | |
77 | std r3,_AMOR(r1) | |
78 | mfspr r3,SPRN_WORT | |
79 | std r3,_WORT(r1) | |
80 | mfspr r3,SPRN_WORC | |
81 | std r3,_WORC(r1) | |
82 | ||
83 | blr | |
84 | ||
b32aadc1 SP |
85 | /* |
86 | * Used by threads when the lock bit of core_idle_state is set. | |
87 | * Threads will spin in HMT_LOW until the lock bit is cleared. | |
88 | * r14 - pointer to core_idle_state | |
89 | * r15 - used to load contents of core_idle_state | |
90 | */ | |
91 | ||
92 | core_idle_lock_held: | |
93 | HMT_LOW | |
94 | 3: lwz r15,0(r14) | |
95 | andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT | |
96 | bne 3b | |
97 | HMT_MEDIUM | |
98 | lwarx r15,0,r14 | |
99 | blr | |
100 | ||
aca79d2b VS |
101 | /* |
102 | * Pass requested state in r3: | |
7cba160a | 103 | * r3 - PNV_THREAD_NAP/SLEEP/WINKLE |
8d6f7c5a ME |
104 | * |
105 | * To check IRQ_HAPPENED in r4 | |
106 | * 0 - don't check | |
107 | * 1 - check | |
4eae2c9a SP |
108 | * |
109 | * Address to 'rfid' to in r5 | |
aca79d2b | 110 | */ |
5fa6b6bd | 111 | _GLOBAL(pnv_powersave_common) |
aca79d2b | 112 | /* Use r3 to pass state nap/sleep/winkle */ |
948cf67c BH |
113 | /* NAP is a state loss, we create a regs frame on the |
114 | * stack, fill it up with the state we care about and | |
115 | * stick a pointer to it in PACAR1. We really only | |
116 | * need to save PC, some CR bits and the NV GPRs, | |
117 | * but for now an interrupt frame will do. | |
118 | */ | |
119 | mflr r0 | |
120 | std r0,16(r1) | |
121 | stdu r1,-INT_FRAME_SIZE(r1) | |
122 | std r0,_LINK(r1) | |
123 | std r0,_NIP(r1) | |
124 | ||
948cf67c BH |
125 | /* Hard disable interrupts */ |
126 | mfmsr r9 | |
127 | rldicl r9,r9,48,1 | |
128 | rotldi r9,r9,16 | |
129 | mtmsrd r9,1 /* hard-disable interrupts */ | |
7230c564 BH |
130 | |
131 | /* Check if something happened while soft-disabled */ | |
132 | lbz r0,PACAIRQHAPPENED(r13) | |
d6a4f709 | 133 | andi. r0,r0,~PACA_IRQ_HARD_DIS@l |
7230c564 | 134 | beq 1f |
8d6f7c5a ME |
135 | cmpwi cr0,r4,0 |
136 | beq 1f | |
7230c564 BH |
137 | addi r1,r1,INT_FRAME_SIZE |
138 | ld r0,16(r1) | |
f57333a7 | 139 | li r3,0 /* Return 0 (no nap) */ |
7230c564 BH |
140 | mtlr r0 |
141 | blr | |
142 | ||
143 | 1: /* We mark irqs hard disabled as this is the state we'll | |
144 | * be in when returning and we need to tell arch_local_irq_restore() | |
145 | * about it | |
146 | */ | |
147 | li r0,PACA_IRQ_HARD_DIS | |
148 | stb r0,PACAIRQHAPPENED(r13) | |
149 | ||
150 | /* We haven't lost state ... yet */ | |
948cf67c | 151 | li r0,0 |
2fde6d20 | 152 | stb r0,PACA_NAPSTATELOST(r13) |
948cf67c BH |
153 | |
154 | /* Continue saving state */ | |
155 | SAVE_GPR(2, r1) | |
156 | SAVE_NVGPRS(r1) | |
aca79d2b VS |
157 | mfcr r4 |
158 | std r4,_CCR(r1) | |
948cf67c BH |
159 | std r9,_MSR(r1) |
160 | std r1,PACAR1(r13) | |
161 | ||
4eae2c9a SP |
162 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
163 | /* Tell KVM we're entering idle */ | |
164 | li r4,KVM_HWTHREAD_IN_NAP | |
165 | stb r4,HSTATE_HWTHREAD_STATE(r13) | |
166 | #endif | |
167 | ||
8117ac6a PM |
168 | /* |
169 | * Go to real mode to do the nap, as required by the architecture. | |
170 | * Also, we need to be in real mode before setting hwthread_state, | |
171 | * because as soon as we do that, another thread can switch | |
172 | * the MMU context to the guest. | |
173 | */ | |
4eae2c9a | 174 | LOAD_REG_IMMEDIATE(r7, MSR_IDLE) |
8117ac6a PM |
175 | li r6, MSR_RI |
176 | andc r6, r9, r6 | |
8117ac6a | 177 | mtmsrd r6, 1 /* clear RI before setting SRR0/1 */ |
4eae2c9a SP |
178 | mtspr SPRN_SRR0, r5 |
179 | mtspr SPRN_SRR1, r7 | |
8117ac6a PM |
180 | rfid |
181 | ||
5fa6b6bd SP |
182 | .globl pnv_enter_arch207_idle_mode |
183 | pnv_enter_arch207_idle_mode: | |
7cba160a | 184 | stb r3,PACA_THREAD_IDLE_STATE(r13) |
77b54e9f SP |
185 | cmpwi cr3,r3,PNV_THREAD_SLEEP |
186 | bge cr3,2f | |
aca79d2b VS |
187 | IDLE_STATE_ENTER_SEQ(PPC_NAP) |
188 | /* No return */ | |
7cba160a SP |
189 | 2: |
190 | /* Sleep or winkle */ | |
191 | lbz r7,PACA_THREAD_MASK(r13) | |
192 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
193 | lwarx_loop1: | |
194 | lwarx r15,0,r14 | |
b32aadc1 SP |
195 | |
196 | andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT | |
197 | bnel core_idle_lock_held | |
198 | ||
7cba160a SP |
199 | andc r15,r15,r7 /* Clear thread bit */ |
200 | ||
201 | andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS | |
202 | ||
203 | /* | |
204 | * If cr0 = 0, then current thread is the last thread of the core entering | |
205 | * sleep. Last thread needs to execute the hardware bug workaround code if | |
206 | * required by the platform. | |
207 | * Make the workaround call unconditionally here. The below branch call is | |
208 | * patched out when the idle states are discovered if the platform does not | |
209 | * require it. | |
210 | */ | |
211 | .global pnv_fastsleep_workaround_at_entry | |
212 | pnv_fastsleep_workaround_at_entry: | |
213 | beq fastsleep_workaround_at_entry | |
214 | ||
215 | stwcx. r15,0,r14 | |
216 | bne- lwarx_loop1 | |
217 | isync | |
218 | ||
77b54e9f SP |
219 | common_enter: /* common code for all the threads entering sleep or winkle */ |
220 | bgt cr3,enter_winkle | |
7cba160a SP |
221 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) |
222 | ||
223 | fastsleep_workaround_at_entry: | |
224 | ori r15,r15,PNV_CORE_IDLE_LOCK_BIT | |
225 | stwcx. r15,0,r14 | |
226 | bne- lwarx_loop1 | |
227 | isync | |
228 | ||
229 | /* Fast sleep workaround */ | |
230 | li r3,1 | |
231 | li r4,1 | |
232 | li r0,OPAL_CONFIG_CPU_IDLE_STATE | |
233 | bl opal_call_realmode | |
234 | ||
235 | /* Clear Lock bit */ | |
236 | li r0,0 | |
237 | lwsync | |
238 | stw r0,0(r14) | |
239 | b common_enter | |
240 | ||
77b54e9f | 241 | enter_winkle: |
0dfffb48 SP |
242 | bl save_sprs_to_stack |
243 | ||
77b54e9f | 244 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) |
f0888f70 | 245 | |
aca79d2b VS |
246 | _GLOBAL(power7_idle) |
247 | /* Now check if user or arch enabled NAP mode */ | |
248 | LOAD_REG_ADDRBASE(r3,powersave_nap) | |
249 | lwz r4,ADDROFF(powersave_nap)(r3) | |
250 | cmpwi 0,r4,0 | |
251 | beqlr | |
8d6f7c5a | 252 | li r3, 1 |
aca79d2b VS |
253 | /* fall through */ |
254 | ||
255 | _GLOBAL(power7_nap) | |
8d6f7c5a | 256 | mr r4,r3 |
7cba160a | 257 | li r3,PNV_THREAD_NAP |
4eae2c9a | 258 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 259 | b pnv_powersave_common |
aca79d2b VS |
260 | /* No return */ |
261 | ||
262 | _GLOBAL(power7_sleep) | |
7cba160a | 263 | li r3,PNV_THREAD_SLEEP |
c733cf83 | 264 | li r4,1 |
4eae2c9a | 265 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 266 | b pnv_powersave_common |
aca79d2b | 267 | /* No return */ |
948cf67c | 268 | |
77b54e9f | 269 | _GLOBAL(power7_winkle) |
bfd1b7ae | 270 | li r3,PNV_THREAD_WINKLE |
77b54e9f | 271 | li r4,1 |
4eae2c9a | 272 | LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode) |
5fa6b6bd | 273 | b pnv_powersave_common |
77b54e9f SP |
274 | /* No return */ |
275 | ||
bbdb760d MS |
276 | #define CHECK_HMI_INTERRUPT \ |
277 | mfspr r0,SPRN_SRR1; \ | |
278 | BEGIN_FTR_SECTION_NESTED(66); \ | |
279 | rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \ | |
280 | FTR_SECTION_ELSE_NESTED(66); \ | |
281 | rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \ | |
282 | ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \ | |
283 | cmpwi r0,0xa; /* Hypervisor maintenance ? */ \ | |
284 | bne 20f; \ | |
285 | /* Invoke opal call to handle hmi */ \ | |
286 | ld r2,PACATOC(r13); \ | |
287 | ld r1,PACAR1(r13); \ | |
288 | std r3,ORIG_GPR3(r1); /* Save original r3 */ \ | |
7cba160a | 289 | li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \ |
db97efff | 290 | bl opal_call_realmode; \ |
bbdb760d MS |
291 | ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \ |
292 | 20: nop; | |
293 | ||
294 | ||
17065671 SP |
295 | /* |
296 | * Called from reset vector. Check whether we have woken up with | |
297 | * hypervisor state loss. If yes, restore hypervisor state and return | |
298 | * back to reset vector. | |
299 | * | |
300 | * r13 - Contents of HSPRG0 | |
301 | * cr3 - set to gt if waking up with partial/complete hypervisor state loss | |
302 | */ | |
5fa6b6bd | 303 | _GLOBAL(pnv_restore_hyp_resource) |
17065671 SP |
304 | /* |
305 | * Check if last bit of HSPGR0 is set. This indicates whether we are | |
306 | * waking up from winkle. | |
307 | */ | |
308 | clrldi r5,r13,63 | |
309 | clrrdi r13,r13,1 | |
310 | cmpwi cr4,r5,1 | |
311 | mtspr SPRN_HSPRG0,r13 | |
312 | ||
313 | lbz r0,PACA_THREAD_IDLE_STATE(r13) | |
314 | cmpwi cr2,r0,PNV_THREAD_NAP | |
5fa6b6bd | 315 | bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */ |
17065671 SP |
316 | |
317 | /* | |
318 | * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking | |
319 | * up from nap. At this stage CR3 shouldn't contains 'gt' since that | |
320 | * indicates we are waking with hypervisor state loss from nap. | |
321 | */ | |
322 | bgt cr3,. | |
323 | ||
324 | blr /* Return back to System Reset vector from where | |
5fa6b6bd | 325 | pnv_restore_hyp_resource was invoked */ |
17065671 SP |
326 | |
327 | ||
5fa6b6bd | 328 | _GLOBAL(pnv_wakeup_tb_loss) |
97eb001f VS |
329 | ld r2,PACATOC(r13); |
330 | ld r1,PACAR1(r13) | |
7cba160a SP |
331 | /* |
332 | * Before entering any idle state, the NVGPRs are saved in the stack | |
333 | * and they are restored before switching to the process context. Hence | |
334 | * until they are restored, they are free to be used. | |
335 | * | |
17065671 SP |
336 | * Save SRR1 and LR in NVGPRs as they might be clobbered in |
337 | * opal_call_realmode (called in CHECK_HMI_INTERRUPT). SRR1 is required | |
338 | * to determine the wakeup reason if we branch to kvm_start_guest. LR | |
339 | * is required to return back to reset vector after hypervisor state | |
340 | * restore is complete. | |
7cba160a | 341 | */ |
17065671 | 342 | mflr r17 |
7cba160a | 343 | mfspr r16,SPRN_SRR1 |
bbdb760d MS |
344 | BEGIN_FTR_SECTION |
345 | CHECK_HMI_INTERRUPT | |
346 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
7cba160a SP |
347 | |
348 | lbz r7,PACA_THREAD_MASK(r13) | |
349 | ld r14,PACA_CORE_IDLE_STATE_PTR(r13) | |
350 | lwarx_loop2: | |
351 | lwarx r15,0,r14 | |
352 | andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT | |
353 | /* | |
354 | * Lock bit is set in one of the 2 cases- | |
355 | * a. In the sleep/winkle enter path, the last thread is executing | |
356 | * fastsleep workaround code. | |
357 | * b. In the wake up path, another thread is executing fastsleep | |
358 | * workaround undo code or resyncing timebase or restoring context | |
359 | * In either case loop until the lock bit is cleared. | |
360 | */ | |
b32aadc1 | 361 | bnel core_idle_lock_held |
7cba160a SP |
362 | |
363 | cmpwi cr2,r15,0 | |
77b54e9f SP |
364 | lbz r4,PACA_SUBCORE_SIBLING_MASK(r13) |
365 | and r4,r4,r15 | |
366 | cmpwi cr1,r4,0 /* Check if first in subcore */ | |
367 | ||
368 | /* | |
369 | * At this stage | |
370 | * cr1 - 0b0100 if first thread to wakeup in subcore | |
371 | * cr2 - 0b0100 if first thread to wakeup in core | |
372 | * cr3- 0b0010 if waking up from sleep or winkle | |
373 | * cr4 - 0b0100 if waking up from winkle | |
374 | */ | |
375 | ||
7cba160a SP |
376 | or r15,r15,r7 /* Set thread bit */ |
377 | ||
77b54e9f | 378 | beq cr1,first_thread_in_subcore |
7cba160a | 379 | |
77b54e9f | 380 | /* Not first thread in subcore to wake up */ |
7cba160a SP |
381 | stwcx. r15,0,r14 |
382 | bne- lwarx_loop2 | |
383 | isync | |
384 | b common_exit | |
385 | ||
77b54e9f SP |
386 | first_thread_in_subcore: |
387 | /* First thread in subcore to wakeup */ | |
7cba160a SP |
388 | ori r15,r15,PNV_CORE_IDLE_LOCK_BIT |
389 | stwcx. r15,0,r14 | |
390 | bne- lwarx_loop2 | |
391 | isync | |
392 | ||
77b54e9f SP |
393 | /* |
394 | * If waking up from sleep, subcore state is not lost. Hence | |
395 | * skip subcore state restore | |
396 | */ | |
397 | bne cr4,subcore_state_restored | |
398 | ||
399 | /* Restore per-subcore state */ | |
400 | ld r4,_SDR1(r1) | |
401 | mtspr SPRN_SDR1,r4 | |
402 | ld r4,_RPR(r1) | |
403 | mtspr SPRN_RPR,r4 | |
404 | ld r4,_AMOR(r1) | |
405 | mtspr SPRN_AMOR,r4 | |
406 | ||
407 | subcore_state_restored: | |
408 | /* | |
409 | * Check if the thread is also the first thread in the core. If not, | |
410 | * skip to clear_lock. | |
411 | */ | |
412 | bne cr2,clear_lock | |
413 | ||
414 | first_thread_in_core: | |
415 | ||
7cba160a SP |
416 | /* |
417 | * First thread in the core waking up from fastsleep. It needs to | |
418 | * call the fastsleep workaround code if the platform requires it. | |
419 | * Call it unconditionally here. The below branch instruction will | |
420 | * be patched out when the idle states are discovered if platform | |
421 | * does not require workaround. | |
422 | */ | |
423 | .global pnv_fastsleep_workaround_at_exit | |
424 | pnv_fastsleep_workaround_at_exit: | |
425 | b fastsleep_workaround_at_exit | |
426 | ||
427 | timebase_resync: | |
428 | /* Do timebase resync if we are waking up from sleep. Use cr3 value | |
429 | * set in exceptions-64s.S */ | |
430 | ble cr3,clear_lock | |
97eb001f | 431 | /* Time base re-sync */ |
7cba160a | 432 | li r0,OPAL_RESYNC_TIMEBASE |
db97efff | 433 | bl opal_call_realmode; |
97eb001f VS |
434 | /* TODO: Check r3 for failure */ |
435 | ||
77b54e9f SP |
436 | /* |
437 | * If waking up from sleep, per core state is not lost, skip to | |
438 | * clear_lock. | |
439 | */ | |
440 | bne cr4,clear_lock | |
441 | ||
442 | /* Restore per core state */ | |
443 | ld r4,_TSCR(r1) | |
444 | mtspr SPRN_TSCR,r4 | |
445 | ld r4,_WORC(r1) | |
446 | mtspr SPRN_WORC,r4 | |
447 | ||
7cba160a SP |
448 | clear_lock: |
449 | andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS | |
450 | lwsync | |
451 | stw r15,0(r14) | |
452 | ||
453 | common_exit: | |
77b54e9f SP |
454 | /* |
455 | * Common to all threads. | |
456 | * | |
457 | * If waking up from sleep, hypervisor state is not lost. Hence | |
458 | * skip hypervisor state restore. | |
459 | */ | |
460 | bne cr4,hypervisor_state_restored | |
461 | ||
462 | /* Waking up from winkle */ | |
463 | ||
464 | /* Restore per thread state */ | |
465 | bl __restore_cpu_power8 | |
466 | ||
467 | /* Restore SLB from PACA */ | |
468 | ld r8,PACA_SLBSHADOWPTR(r13) | |
469 | ||
470 | .rept SLB_NUM_BOLTED | |
471 | li r3, SLBSHADOW_SAVEAREA | |
472 | LDX_BE r5, r8, r3 | |
473 | addi r3, r3, 8 | |
474 | LDX_BE r6, r8, r3 | |
475 | andis. r7,r5,SLB_ESID_V@h | |
476 | beq 1f | |
477 | slbmte r6,r5 | |
478 | 1: addi r8,r8,16 | |
479 | .endr | |
480 | ||
481 | ld r4,_SPURR(r1) | |
482 | mtspr SPRN_SPURR,r4 | |
483 | ld r4,_PURR(r1) | |
484 | mtspr SPRN_PURR,r4 | |
485 | ld r4,_DSCR(r1) | |
486 | mtspr SPRN_DSCR,r4 | |
487 | ld r4,_WORT(r1) | |
488 | mtspr SPRN_WORT,r4 | |
489 | ||
490 | hypervisor_state_restored: | |
491 | ||
7cba160a | 492 | mtspr SPRN_SRR1,r16 |
17065671 SP |
493 | mtlr r17 |
494 | blr /* Return back to System Reset vector from where | |
5fa6b6bd | 495 | pnv_restore_hyp_resource was invoked */ |
97eb001f | 496 | |
7cba160a SP |
497 | fastsleep_workaround_at_exit: |
498 | li r3,1 | |
499 | li r4,0 | |
500 | li r0,OPAL_CONFIG_CPU_IDLE_STATE | |
501 | bl opal_call_realmode | |
502 | b timebase_resync | |
503 | ||
56548fc0 PM |
504 | /* |
505 | * R3 here contains the value that will be returned to the caller | |
506 | * of power7_nap. | |
507 | */ | |
5fa6b6bd | 508 | _GLOBAL(pnv_wakeup_loss) |
948cf67c | 509 | ld r1,PACAR1(r13) |
bbdb760d MS |
510 | BEGIN_FTR_SECTION |
511 | CHECK_HMI_INTERRUPT | |
512 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c BH |
513 | REST_NVGPRS(r1) |
514 | REST_GPR(2, r1) | |
56548fc0 | 515 | ld r6,_CCR(r1) |
948cf67c BH |
516 | ld r4,_MSR(r1) |
517 | ld r5,_NIP(r1) | |
518 | addi r1,r1,INT_FRAME_SIZE | |
56548fc0 | 519 | mtcr r6 |
948cf67c BH |
520 | mtspr SPRN_SRR1,r4 |
521 | mtspr SPRN_SRR0,r5 | |
522 | rfid | |
523 | ||
56548fc0 PM |
524 | /* |
525 | * R3 here contains the value that will be returned to the caller | |
526 | * of power7_nap. | |
527 | */ | |
5fa6b6bd | 528 | _GLOBAL(pnv_wakeup_noloss) |
2fde6d20 PM |
529 | lbz r0,PACA_NAPSTATELOST(r13) |
530 | cmpwi r0,0 | |
5fa6b6bd | 531 | bne pnv_wakeup_loss |
bbdb760d MS |
532 | BEGIN_FTR_SECTION |
533 | CHECK_HMI_INTERRUPT | |
534 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | |
948cf67c | 535 | ld r1,PACAR1(r13) |
0aab3747 | 536 | ld r6,_CCR(r1) |
948cf67c BH |
537 | ld r4,_MSR(r1) |
538 | ld r5,_NIP(r1) | |
539 | addi r1,r1,INT_FRAME_SIZE | |
0aab3747 | 540 | mtcr r6 |
948cf67c BH |
541 | mtspr SPRN_SRR1,r4 |
542 | mtspr SPRN_SRR0,r5 | |
543 | rfid |