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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
3 | * | |
4 | * Rewrite, cleanup, new allocation schemes, virtual merging: | |
5 | * Copyright (C) 2004 Olof Johansson, IBM Corporation | |
6 | * and Ben. Herrenschmidt, IBM Corporation | |
7 | * | |
8 | * Dynamic DMA mapping support, bus-independent parts. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | ||
1da177e4 LT |
26 | #include <linux/init.h> |
27 | #include <linux/types.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/string.h> | |
32 | #include <linux/dma-mapping.h> | |
1da177e4 LT |
33 | #include <linux/bitops.h> |
34 | #include <asm/io.h> | |
35 | #include <asm/prom.h> | |
36 | #include <asm/iommu.h> | |
37 | #include <asm/pci-bridge.h> | |
38 | #include <asm/machdep.h> | |
5f50867b | 39 | #include <asm/kdump.h> |
1da177e4 LT |
40 | |
41 | #define DBG(...) | |
42 | ||
43 | #ifdef CONFIG_IOMMU_VMERGE | |
44 | static int novmerge = 0; | |
45 | #else | |
46 | static int novmerge = 1; | |
47 | #endif | |
48 | ||
56997559 JM |
49 | static int protect4gb = 1; |
50 | ||
5d2efba6 LV |
51 | static inline unsigned long iommu_num_pages(unsigned long vaddr, |
52 | unsigned long slen) | |
53 | { | |
54 | unsigned long npages; | |
55 | ||
56 | npages = IOMMU_PAGE_ALIGN(vaddr + slen) - (vaddr & IOMMU_PAGE_MASK); | |
57 | npages >>= IOMMU_PAGE_SHIFT; | |
58 | ||
59 | return npages; | |
60 | } | |
61 | ||
56997559 JM |
62 | static int __init setup_protect4gb(char *str) |
63 | { | |
64 | if (strcmp(str, "on") == 0) | |
65 | protect4gb = 1; | |
66 | else if (strcmp(str, "off") == 0) | |
67 | protect4gb = 0; | |
68 | ||
69 | return 1; | |
70 | } | |
71 | ||
1da177e4 LT |
72 | static int __init setup_iommu(char *str) |
73 | { | |
74 | if (!strcmp(str, "novmerge")) | |
75 | novmerge = 1; | |
76 | else if (!strcmp(str, "vmerge")) | |
77 | novmerge = 0; | |
78 | return 1; | |
79 | } | |
80 | ||
56997559 | 81 | __setup("protect4gb=", setup_protect4gb); |
1da177e4 LT |
82 | __setup("iommu=", setup_iommu); |
83 | ||
84 | static unsigned long iommu_range_alloc(struct iommu_table *tbl, | |
85 | unsigned long npages, | |
86 | unsigned long *handle, | |
7daa411b | 87 | unsigned long mask, |
1da177e4 LT |
88 | unsigned int align_order) |
89 | { | |
90 | unsigned long n, end, i, start; | |
91 | unsigned long limit; | |
92 | int largealloc = npages > 15; | |
93 | int pass = 0; | |
94 | unsigned long align_mask; | |
95 | ||
96 | align_mask = 0xffffffffffffffffl >> (64 - align_order); | |
97 | ||
98 | /* This allocator was derived from x86_64's bit string search */ | |
99 | ||
100 | /* Sanity check */ | |
13a2eea1 | 101 | if (unlikely(npages == 0)) { |
1da177e4 LT |
102 | if (printk_ratelimit()) |
103 | WARN_ON(1); | |
104 | return DMA_ERROR_CODE; | |
105 | } | |
106 | ||
107 | if (handle && *handle) | |
108 | start = *handle; | |
109 | else | |
110 | start = largealloc ? tbl->it_largehint : tbl->it_hint; | |
111 | ||
112 | /* Use only half of the table for small allocs (15 pages or less) */ | |
113 | limit = largealloc ? tbl->it_size : tbl->it_halfpoint; | |
114 | ||
115 | if (largealloc && start < tbl->it_halfpoint) | |
116 | start = tbl->it_halfpoint; | |
117 | ||
118 | /* The case below can happen if we have a small segment appended | |
119 | * to a large, or when the previous alloc was at the very end of | |
120 | * the available space. If so, go back to the initial start. | |
121 | */ | |
122 | if (start >= limit) | |
123 | start = largealloc ? tbl->it_largehint : tbl->it_hint; | |
7daa411b | 124 | |
1da177e4 LT |
125 | again: |
126 | ||
7daa411b OJ |
127 | if (limit + tbl->it_offset > mask) { |
128 | limit = mask - tbl->it_offset + 1; | |
129 | /* If we're constrained on address range, first try | |
130 | * at the masked hint to avoid O(n) search complexity, | |
131 | * but on second pass, start at 0. | |
132 | */ | |
133 | if ((start & mask) >= limit || pass > 0) | |
134 | start = 0; | |
135 | else | |
136 | start &= mask; | |
137 | } | |
138 | ||
1da177e4 LT |
139 | n = find_next_zero_bit(tbl->it_map, limit, start); |
140 | ||
141 | /* Align allocation */ | |
142 | n = (n + align_mask) & ~align_mask; | |
143 | ||
144 | end = n + npages; | |
145 | ||
146 | if (unlikely(end >= limit)) { | |
147 | if (likely(pass < 2)) { | |
148 | /* First failure, just rescan the half of the table. | |
149 | * Second failure, rescan the other half of the table. | |
150 | */ | |
151 | start = (largealloc ^ pass) ? tbl->it_halfpoint : 0; | |
152 | limit = pass ? tbl->it_size : limit; | |
153 | pass++; | |
154 | goto again; | |
155 | } else { | |
156 | /* Third failure, give up */ | |
157 | return DMA_ERROR_CODE; | |
158 | } | |
159 | } | |
160 | ||
161 | for (i = n; i < end; i++) | |
162 | if (test_bit(i, tbl->it_map)) { | |
163 | start = i+1; | |
164 | goto again; | |
165 | } | |
166 | ||
167 | for (i = n; i < end; i++) | |
168 | __set_bit(i, tbl->it_map); | |
169 | ||
170 | /* Bump the hint to a new block for small allocs. */ | |
171 | if (largealloc) { | |
172 | /* Don't bump to new block to avoid fragmentation */ | |
173 | tbl->it_largehint = end; | |
174 | } else { | |
175 | /* Overflow will be taken care of at the next allocation */ | |
176 | tbl->it_hint = (end + tbl->it_blocksize - 1) & | |
177 | ~(tbl->it_blocksize - 1); | |
178 | } | |
179 | ||
180 | /* Update handle for SG allocations */ | |
181 | if (handle) | |
182 | *handle = end; | |
183 | ||
184 | return n; | |
185 | } | |
186 | ||
187 | static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *page, | |
188 | unsigned int npages, enum dma_data_direction direction, | |
7daa411b | 189 | unsigned long mask, unsigned int align_order) |
1da177e4 LT |
190 | { |
191 | unsigned long entry, flags; | |
192 | dma_addr_t ret = DMA_ERROR_CODE; | |
7daa411b | 193 | |
1da177e4 LT |
194 | spin_lock_irqsave(&(tbl->it_lock), flags); |
195 | ||
7daa411b | 196 | entry = iommu_range_alloc(tbl, npages, NULL, mask, align_order); |
1da177e4 LT |
197 | |
198 | if (unlikely(entry == DMA_ERROR_CODE)) { | |
199 | spin_unlock_irqrestore(&(tbl->it_lock), flags); | |
200 | return DMA_ERROR_CODE; | |
201 | } | |
202 | ||
203 | entry += tbl->it_offset; /* Offset into real TCE table */ | |
5d2efba6 | 204 | ret = entry << IOMMU_PAGE_SHIFT; /* Set the return dma address */ |
1da177e4 LT |
205 | |
206 | /* Put the TCEs in the HW table */ | |
5d2efba6 | 207 | ppc_md.tce_build(tbl, entry, npages, (unsigned long)page & IOMMU_PAGE_MASK, |
1da177e4 LT |
208 | direction); |
209 | ||
210 | ||
211 | /* Flush/invalidate TLB caches if necessary */ | |
212 | if (ppc_md.tce_flush) | |
213 | ppc_md.tce_flush(tbl); | |
214 | ||
215 | spin_unlock_irqrestore(&(tbl->it_lock), flags); | |
216 | ||
217 | /* Make sure updates are seen by hardware */ | |
218 | mb(); | |
219 | ||
220 | return ret; | |
221 | } | |
222 | ||
223 | static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
224 | unsigned int npages) | |
225 | { | |
226 | unsigned long entry, free_entry; | |
227 | unsigned long i; | |
228 | ||
5d2efba6 | 229 | entry = dma_addr >> IOMMU_PAGE_SHIFT; |
1da177e4 LT |
230 | free_entry = entry - tbl->it_offset; |
231 | ||
232 | if (((free_entry + npages) > tbl->it_size) || | |
233 | (entry < tbl->it_offset)) { | |
234 | if (printk_ratelimit()) { | |
235 | printk(KERN_INFO "iommu_free: invalid entry\n"); | |
236 | printk(KERN_INFO "\tentry = 0x%lx\n", entry); | |
237 | printk(KERN_INFO "\tdma_addr = 0x%lx\n", (u64)dma_addr); | |
238 | printk(KERN_INFO "\tTable = 0x%lx\n", (u64)tbl); | |
239 | printk(KERN_INFO "\tbus# = 0x%lx\n", (u64)tbl->it_busno); | |
240 | printk(KERN_INFO "\tsize = 0x%lx\n", (u64)tbl->it_size); | |
241 | printk(KERN_INFO "\tstartOff = 0x%lx\n", (u64)tbl->it_offset); | |
242 | printk(KERN_INFO "\tindex = 0x%lx\n", (u64)tbl->it_index); | |
243 | WARN_ON(1); | |
244 | } | |
245 | return; | |
246 | } | |
247 | ||
248 | ppc_md.tce_free(tbl, entry, npages); | |
249 | ||
250 | for (i = 0; i < npages; i++) | |
251 | __clear_bit(free_entry+i, tbl->it_map); | |
252 | } | |
253 | ||
254 | static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, | |
255 | unsigned int npages) | |
256 | { | |
257 | unsigned long flags; | |
258 | ||
259 | spin_lock_irqsave(&(tbl->it_lock), flags); | |
260 | ||
261 | __iommu_free(tbl, dma_addr, npages); | |
262 | ||
263 | /* Make sure TLB cache is flushed if the HW needs it. We do | |
264 | * not do an mb() here on purpose, it is not needed on any of | |
265 | * the current platforms. | |
266 | */ | |
267 | if (ppc_md.tce_flush) | |
268 | ppc_md.tce_flush(tbl); | |
269 | ||
270 | spin_unlock_irqrestore(&(tbl->it_lock), flags); | |
271 | } | |
272 | ||
12d04eef BH |
273 | int iommu_map_sg(struct iommu_table *tbl, struct scatterlist *sglist, |
274 | int nelems, unsigned long mask, | |
275 | enum dma_data_direction direction) | |
1da177e4 LT |
276 | { |
277 | dma_addr_t dma_next = 0, dma_addr; | |
278 | unsigned long flags; | |
279 | struct scatterlist *s, *outs, *segstart; | |
ac9af7cb | 280 | int outcount, incount; |
1da177e4 LT |
281 | unsigned long handle; |
282 | ||
283 | BUG_ON(direction == DMA_NONE); | |
284 | ||
285 | if ((nelems == 0) || !tbl) | |
286 | return 0; | |
287 | ||
288 | outs = s = segstart = &sglist[0]; | |
289 | outcount = 1; | |
ac9af7cb | 290 | incount = nelems; |
1da177e4 LT |
291 | handle = 0; |
292 | ||
293 | /* Init first segment length for backout at failure */ | |
294 | outs->dma_length = 0; | |
295 | ||
5d2efba6 | 296 | DBG("sg mapping %d elements:\n", nelems); |
1da177e4 LT |
297 | |
298 | spin_lock_irqsave(&(tbl->it_lock), flags); | |
299 | ||
300 | for (s = outs; nelems; nelems--, s++) { | |
301 | unsigned long vaddr, npages, entry, slen; | |
302 | ||
303 | slen = s->length; | |
304 | /* Sanity check */ | |
305 | if (slen == 0) { | |
306 | dma_next = 0; | |
307 | continue; | |
308 | } | |
309 | /* Allocate iommu entries for that segment */ | |
310 | vaddr = (unsigned long)page_address(s->page) + s->offset; | |
5d2efba6 LV |
311 | npages = iommu_num_pages(vaddr, slen); |
312 | entry = iommu_range_alloc(tbl, npages, &handle, mask >> IOMMU_PAGE_SHIFT, 0); | |
1da177e4 LT |
313 | |
314 | DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen); | |
315 | ||
316 | /* Handle failure */ | |
317 | if (unlikely(entry == DMA_ERROR_CODE)) { | |
318 | if (printk_ratelimit()) | |
319 | printk(KERN_INFO "iommu_alloc failed, tbl %p vaddr %lx" | |
320 | " npages %lx\n", tbl, vaddr, npages); | |
321 | goto failure; | |
322 | } | |
323 | ||
324 | /* Convert entry to a dma_addr_t */ | |
325 | entry += tbl->it_offset; | |
5d2efba6 LV |
326 | dma_addr = entry << IOMMU_PAGE_SHIFT; |
327 | dma_addr |= (s->offset & ~IOMMU_PAGE_MASK); | |
1da177e4 | 328 | |
5d2efba6 | 329 | DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n", |
1da177e4 LT |
330 | npages, entry, dma_addr); |
331 | ||
332 | /* Insert into HW table */ | |
5d2efba6 | 333 | ppc_md.tce_build(tbl, entry, npages, vaddr & IOMMU_PAGE_MASK, direction); |
1da177e4 LT |
334 | |
335 | /* If we are in an open segment, try merging */ | |
336 | if (segstart != s) { | |
337 | DBG(" - trying merge...\n"); | |
338 | /* We cannot merge if: | |
339 | * - allocated dma_addr isn't contiguous to previous allocation | |
340 | */ | |
341 | if (novmerge || (dma_addr != dma_next)) { | |
342 | /* Can't merge: create a new segment */ | |
343 | segstart = s; | |
344 | outcount++; outs++; | |
345 | DBG(" can't merge, new segment.\n"); | |
346 | } else { | |
347 | outs->dma_length += s->length; | |
5d2efba6 | 348 | DBG(" merged, new len: %ux\n", outs->dma_length); |
1da177e4 LT |
349 | } |
350 | } | |
351 | ||
352 | if (segstart == s) { | |
353 | /* This is a new segment, fill entries */ | |
354 | DBG(" - filling new segment.\n"); | |
355 | outs->dma_address = dma_addr; | |
356 | outs->dma_length = slen; | |
357 | } | |
358 | ||
359 | /* Calculate next page pointer for contiguous check */ | |
360 | dma_next = dma_addr + slen; | |
361 | ||
362 | DBG(" - dma next is: %lx\n", dma_next); | |
363 | } | |
364 | ||
365 | /* Flush/invalidate TLB caches if necessary */ | |
366 | if (ppc_md.tce_flush) | |
367 | ppc_md.tce_flush(tbl); | |
368 | ||
369 | spin_unlock_irqrestore(&(tbl->it_lock), flags); | |
370 | ||
1da177e4 LT |
371 | DBG("mapped %d elements:\n", outcount); |
372 | ||
ac9af7cb | 373 | /* For the sake of iommu_unmap_sg, we clear out the length in the |
1da177e4 LT |
374 | * next entry of the sglist if we didn't fill the list completely |
375 | */ | |
ac9af7cb | 376 | if (outcount < incount) { |
1da177e4 LT |
377 | outs++; |
378 | outs->dma_address = DMA_ERROR_CODE; | |
379 | outs->dma_length = 0; | |
380 | } | |
a958a264 JM |
381 | |
382 | /* Make sure updates are seen by hardware */ | |
383 | mb(); | |
384 | ||
1da177e4 LT |
385 | return outcount; |
386 | ||
387 | failure: | |
388 | for (s = &sglist[0]; s <= outs; s++) { | |
389 | if (s->dma_length != 0) { | |
390 | unsigned long vaddr, npages; | |
391 | ||
5d2efba6 LV |
392 | vaddr = s->dma_address & IOMMU_PAGE_MASK; |
393 | npages = iommu_num_pages(s->dma_address, s->dma_length); | |
1da177e4 | 394 | __iommu_free(tbl, vaddr, npages); |
a958a264 JM |
395 | s->dma_address = DMA_ERROR_CODE; |
396 | s->dma_length = 0; | |
1da177e4 LT |
397 | } |
398 | } | |
399 | spin_unlock_irqrestore(&(tbl->it_lock), flags); | |
400 | return 0; | |
401 | } | |
402 | ||
403 | ||
404 | void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist, | |
405 | int nelems, enum dma_data_direction direction) | |
406 | { | |
407 | unsigned long flags; | |
408 | ||
409 | BUG_ON(direction == DMA_NONE); | |
410 | ||
411 | if (!tbl) | |
412 | return; | |
413 | ||
414 | spin_lock_irqsave(&(tbl->it_lock), flags); | |
415 | ||
416 | while (nelems--) { | |
417 | unsigned int npages; | |
418 | dma_addr_t dma_handle = sglist->dma_address; | |
419 | ||
420 | if (sglist->dma_length == 0) | |
421 | break; | |
5d2efba6 | 422 | npages = iommu_num_pages(dma_handle,sglist->dma_length); |
1da177e4 LT |
423 | __iommu_free(tbl, dma_handle, npages); |
424 | sglist++; | |
425 | } | |
426 | ||
427 | /* Flush/invalidate TLBs if necessary. As for iommu_free(), we | |
428 | * do not do an mb() here, the affected platforms do not need it | |
429 | * when freeing. | |
430 | */ | |
431 | if (ppc_md.tce_flush) | |
432 | ppc_md.tce_flush(tbl); | |
433 | ||
434 | spin_unlock_irqrestore(&(tbl->it_lock), flags); | |
435 | } | |
436 | ||
437 | /* | |
438 | * Build a iommu_table structure. This contains a bit map which | |
439 | * is used to manage allocation of the tce space. | |
440 | */ | |
ca1588e7 | 441 | struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid) |
1da177e4 LT |
442 | { |
443 | unsigned long sz; | |
56997559 JM |
444 | unsigned long start_index, end_index; |
445 | unsigned long entries_per_4g; | |
446 | unsigned long index; | |
1da177e4 | 447 | static int welcomed = 0; |
ca1588e7 | 448 | struct page *page; |
1da177e4 LT |
449 | |
450 | /* Set aside 1/4 of the table for large allocations. */ | |
451 | tbl->it_halfpoint = tbl->it_size * 3 / 4; | |
452 | ||
453 | /* number of bytes needed for the bitmap */ | |
454 | sz = (tbl->it_size + 7) >> 3; | |
455 | ||
ca1588e7 AB |
456 | page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz)); |
457 | if (!page) | |
1da177e4 | 458 | panic("iommu_init_table: Can't allocate %ld bytes\n", sz); |
ca1588e7 | 459 | tbl->it_map = page_address(page); |
1da177e4 LT |
460 | memset(tbl->it_map, 0, sz); |
461 | ||
462 | tbl->it_hint = 0; | |
463 | tbl->it_largehint = tbl->it_halfpoint; | |
464 | spin_lock_init(&tbl->it_lock); | |
465 | ||
5f50867b HM |
466 | #ifdef CONFIG_CRASH_DUMP |
467 | if (ppc_md.tce_get) { | |
56997559 | 468 | unsigned long tceval; |
5f50867b HM |
469 | unsigned long tcecount = 0; |
470 | ||
471 | /* | |
472 | * Reserve the existing mappings left by the first kernel. | |
473 | */ | |
474 | for (index = 0; index < tbl->it_size; index++) { | |
475 | tceval = ppc_md.tce_get(tbl, index + tbl->it_offset); | |
476 | /* | |
477 | * Freed TCE entry contains 0x7fffffffffffffff on JS20 | |
478 | */ | |
479 | if (tceval && (tceval != 0x7fffffffffffffffUL)) { | |
480 | __set_bit(index, tbl->it_map); | |
481 | tcecount++; | |
482 | } | |
483 | } | |
484 | if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) { | |
485 | printk(KERN_WARNING "TCE table is full; "); | |
486 | printk(KERN_WARNING "freeing %d entries for the kdump boot\n", | |
487 | KDUMP_MIN_TCE_ENTRIES); | |
488 | for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES; | |
489 | index < tbl->it_size; index++) | |
490 | __clear_bit(index, tbl->it_map); | |
491 | } | |
492 | } | |
493 | #else | |
d3588ba9 JR |
494 | /* Clear the hardware table in case firmware left allocations in it */ |
495 | ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size); | |
5f50867b | 496 | #endif |
d3588ba9 | 497 | |
56997559 JM |
498 | /* |
499 | * DMA cannot cross 4 GB boundary. Mark last entry of each 4 | |
500 | * GB chunk as reserved. | |
501 | */ | |
502 | if (protect4gb) { | |
503 | entries_per_4g = 0x100000000l >> IOMMU_PAGE_SHIFT; | |
504 | ||
505 | /* Mark the last bit before a 4GB boundary as used */ | |
506 | start_index = tbl->it_offset | (entries_per_4g - 1); | |
507 | start_index -= tbl->it_offset; | |
508 | ||
509 | end_index = tbl->it_size; | |
510 | ||
511 | for (index = start_index; index < end_index - 1; index += entries_per_4g) | |
512 | __set_bit(index, tbl->it_map); | |
513 | } | |
514 | ||
1da177e4 LT |
515 | if (!welcomed) { |
516 | printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n", | |
517 | novmerge ? "disabled" : "enabled"); | |
518 | welcomed = 1; | |
519 | } | |
520 | ||
521 | return tbl; | |
522 | } | |
523 | ||
524 | void iommu_free_table(struct device_node *dn) | |
525 | { | |
1635317f PM |
526 | struct pci_dn *pdn = dn->data; |
527 | struct iommu_table *tbl = pdn->iommu_table; | |
1da177e4 LT |
528 | unsigned long bitmap_sz, i; |
529 | unsigned int order; | |
530 | ||
531 | if (!tbl || !tbl->it_map) { | |
532 | printk(KERN_ERR "%s: expected TCE map for %s\n", __FUNCTION__, | |
533 | dn->full_name); | |
534 | return; | |
535 | } | |
536 | ||
537 | /* verify that table contains no entries */ | |
538 | /* it_size is in entries, and we're examining 64 at a time */ | |
539 | for (i = 0; i < (tbl->it_size/64); i++) { | |
540 | if (tbl->it_map[i] != 0) { | |
541 | printk(KERN_WARNING "%s: Unexpected TCEs for %s\n", | |
542 | __FUNCTION__, dn->full_name); | |
543 | break; | |
544 | } | |
545 | } | |
546 | ||
547 | /* calculate bitmap size in bytes */ | |
548 | bitmap_sz = (tbl->it_size + 7) / 8; | |
549 | ||
550 | /* free bitmap */ | |
551 | order = get_order(bitmap_sz); | |
552 | free_pages((unsigned long) tbl->it_map, order); | |
553 | ||
554 | /* free table */ | |
555 | kfree(tbl); | |
556 | } | |
557 | ||
558 | /* Creates TCEs for a user provided buffer. The user buffer must be | |
559 | * contiguous real kernel storage (not vmalloc). The address of the buffer | |
560 | * passed here is the kernel (virtual) address of the buffer. The buffer | |
561 | * need not be page aligned, the dma_addr_t returned will point to the same | |
562 | * byte within the page as vaddr. | |
563 | */ | |
564 | dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr, | |
7daa411b OJ |
565 | size_t size, unsigned long mask, |
566 | enum dma_data_direction direction) | |
1da177e4 LT |
567 | { |
568 | dma_addr_t dma_handle = DMA_ERROR_CODE; | |
569 | unsigned long uaddr; | |
570 | unsigned int npages; | |
571 | ||
572 | BUG_ON(direction == DMA_NONE); | |
573 | ||
574 | uaddr = (unsigned long)vaddr; | |
5d2efba6 | 575 | npages = iommu_num_pages(uaddr, size); |
1da177e4 LT |
576 | |
577 | if (tbl) { | |
7daa411b | 578 | dma_handle = iommu_alloc(tbl, vaddr, npages, direction, |
5d2efba6 | 579 | mask >> IOMMU_PAGE_SHIFT, 0); |
1da177e4 LT |
580 | if (dma_handle == DMA_ERROR_CODE) { |
581 | if (printk_ratelimit()) { | |
582 | printk(KERN_INFO "iommu_alloc failed, " | |
583 | "tbl %p vaddr %p npages %d\n", | |
584 | tbl, vaddr, npages); | |
585 | } | |
586 | } else | |
5d2efba6 | 587 | dma_handle |= (uaddr & ~IOMMU_PAGE_MASK); |
1da177e4 LT |
588 | } |
589 | ||
590 | return dma_handle; | |
591 | } | |
592 | ||
593 | void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle, | |
594 | size_t size, enum dma_data_direction direction) | |
595 | { | |
5d2efba6 LV |
596 | unsigned int npages; |
597 | ||
1da177e4 LT |
598 | BUG_ON(direction == DMA_NONE); |
599 | ||
5d2efba6 LV |
600 | if (tbl) { |
601 | npages = iommu_num_pages(dma_handle, size); | |
602 | iommu_free(tbl, dma_handle, npages); | |
603 | } | |
1da177e4 LT |
604 | } |
605 | ||
606 | /* Allocates a contiguous real buffer and creates mappings over it. | |
607 | * Returns the virtual address of the buffer and sets dma_handle | |
608 | * to the dma address (mapping) of the first page. | |
609 | */ | |
610 | void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size, | |
8eb6c6e3 | 611 | dma_addr_t *dma_handle, unsigned long mask, gfp_t flag, int node) |
1da177e4 LT |
612 | { |
613 | void *ret = NULL; | |
614 | dma_addr_t mapping; | |
5d2efba6 LV |
615 | unsigned int order; |
616 | unsigned int nio_pages, io_order; | |
8eb6c6e3 | 617 | struct page *page; |
1da177e4 LT |
618 | |
619 | size = PAGE_ALIGN(size); | |
1da177e4 LT |
620 | order = get_order(size); |
621 | ||
622 | /* | |
623 | * Client asked for way too much space. This is checked later | |
624 | * anyway. It is easier to debug here for the drivers than in | |
625 | * the tce tables. | |
626 | */ | |
627 | if (order >= IOMAP_MAX_ORDER) { | |
628 | printk("iommu_alloc_consistent size too large: 0x%lx\n", size); | |
629 | return NULL; | |
630 | } | |
631 | ||
632 | if (!tbl) | |
633 | return NULL; | |
634 | ||
635 | /* Alloc enough pages (and possibly more) */ | |
05061354 | 636 | page = alloc_pages_node(node, flag, order); |
8eb6c6e3 | 637 | if (!page) |
1da177e4 | 638 | return NULL; |
8eb6c6e3 | 639 | ret = page_address(page); |
1da177e4 LT |
640 | memset(ret, 0, size); |
641 | ||
642 | /* Set up tces to cover the allocated range */ | |
5d2efba6 LV |
643 | nio_pages = size >> IOMMU_PAGE_SHIFT; |
644 | io_order = get_iommu_order(size); | |
645 | mapping = iommu_alloc(tbl, ret, nio_pages, DMA_BIDIRECTIONAL, | |
646 | mask >> IOMMU_PAGE_SHIFT, io_order); | |
1da177e4 LT |
647 | if (mapping == DMA_ERROR_CODE) { |
648 | free_pages((unsigned long)ret, order); | |
8eb6c6e3 CH |
649 | return NULL; |
650 | } | |
651 | *dma_handle = mapping; | |
1da177e4 LT |
652 | return ret; |
653 | } | |
654 | ||
655 | void iommu_free_coherent(struct iommu_table *tbl, size_t size, | |
656 | void *vaddr, dma_addr_t dma_handle) | |
657 | { | |
1da177e4 | 658 | if (tbl) { |
5d2efba6 LV |
659 | unsigned int nio_pages; |
660 | ||
661 | size = PAGE_ALIGN(size); | |
662 | nio_pages = size >> IOMMU_PAGE_SHIFT; | |
663 | iommu_free(tbl, dma_handle, nio_pages); | |
1da177e4 | 664 | size = PAGE_ALIGN(size); |
1da177e4 LT |
665 | free_pages((unsigned long)vaddr, get_order(size)); |
666 | } | |
667 | } |