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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Derived from arch/i386/kernel/irq.c |
3 | * Copyright (C) 1992 Linus Torvalds | |
4 | * Adapted from arch/i386 by Gary Thomas | |
5 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
756e7104 SR |
6 | * Updated and modified by Cort Dougan <cort@fsmlabs.com> |
7 | * Copyright (C) 1996-2001 Cort Dougan | |
1da177e4 LT |
8 | * Adapted for Power Macintosh by Paul Mackerras |
9 | * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au) | |
756e7104 | 10 | * |
1da177e4 LT |
11 | * This program is free software; you can redistribute it and/or |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * This file contains the code used by various IRQ handling routines: | |
17 | * asking for different IRQ's should be done through these routines | |
18 | * instead of just grabbing them. Thus setups with different IRQ numbers | |
19 | * shouldn't result in any weird surprises, and installing new handlers | |
20 | * should be easier. | |
756e7104 SR |
21 | * |
22 | * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the | |
23 | * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit | |
24 | * mask register (of which only 16 are defined), hence the weird shifting | |
25 | * and complement of the cached_irq_mask. I want to be able to stuff | |
26 | * this right into the SIU SMASK register. | |
968159c0 | 27 | * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx |
756e7104 | 28 | * to reduce code space and undefined function references. |
1da177e4 LT |
29 | */ |
30 | ||
0ebfff14 BH |
31 | #undef DEBUG |
32 | ||
4b16f8e2 | 33 | #include <linux/export.h> |
1da177e4 LT |
34 | #include <linux/threads.h> |
35 | #include <linux/kernel_stat.h> | |
36 | #include <linux/signal.h> | |
37 | #include <linux/sched.h> | |
756e7104 | 38 | #include <linux/ptrace.h> |
1da177e4 LT |
39 | #include <linux/ioport.h> |
40 | #include <linux/interrupt.h> | |
41 | #include <linux/timex.h> | |
1da177e4 LT |
42 | #include <linux/init.h> |
43 | #include <linux/slab.h> | |
1da177e4 LT |
44 | #include <linux/delay.h> |
45 | #include <linux/irq.h> | |
756e7104 SR |
46 | #include <linux/seq_file.h> |
47 | #include <linux/cpumask.h> | |
1da177e4 LT |
48 | #include <linux/profile.h> |
49 | #include <linux/bitops.h> | |
0ebfff14 BH |
50 | #include <linux/list.h> |
51 | #include <linux/radix-tree.h> | |
52 | #include <linux/mutex.h> | |
45934c47 | 53 | #include <linux/pci.h> |
60b332e7 | 54 | #include <linux/debugfs.h> |
e3873444 GL |
55 | #include <linux/of.h> |
56 | #include <linux/of_irq.h> | |
1da177e4 | 57 | |
7c0f6ba6 | 58 | #include <linux/uaccess.h> |
1da177e4 LT |
59 | #include <asm/io.h> |
60 | #include <asm/pgtable.h> | |
61 | #include <asm/irq.h> | |
62 | #include <asm/cache.h> | |
63 | #include <asm/prom.h> | |
64 | #include <asm/ptrace.h> | |
1da177e4 | 65 | #include <asm/machdep.h> |
0ebfff14 | 66 | #include <asm/udbg.h> |
3e7f45ad | 67 | #include <asm/smp.h> |
5d31a96e | 68 | #include <asm/livepatch.h> |
0545d543 | 69 | #include <asm/asm-prototypes.h> |
89c81797 | 70 | |
d04c56f7 | 71 | #ifdef CONFIG_PPC64 |
1da177e4 | 72 | #include <asm/paca.h> |
d04c56f7 | 73 | #include <asm/firmware.h> |
0874dd40 | 74 | #include <asm/lv1call.h> |
756e7104 | 75 | #endif |
1bf4af16 AB |
76 | #define CREATE_TRACE_POINTS |
77 | #include <asm/trace.h> | |
b92a226e | 78 | #include <asm/cpu_has_feature.h> |
1da177e4 | 79 | |
8c007bfd AB |
80 | DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); |
81 | EXPORT_PER_CPU_SYMBOL(irq_stat); | |
82 | ||
868accb7 | 83 | int __irq_offset_value; |
756e7104 | 84 | |
756e7104 | 85 | #ifdef CONFIG_PPC32 |
b9e5b4e6 BH |
86 | EXPORT_SYMBOL(__irq_offset_value); |
87 | atomic_t ppc_n_lost_interrupts; | |
756e7104 | 88 | |
756e7104 SR |
89 | #ifdef CONFIG_TAU_INT |
90 | extern int tau_initialized; | |
91 | extern int tau_interrupts(int); | |
92 | #endif | |
b9e5b4e6 | 93 | #endif /* CONFIG_PPC32 */ |
756e7104 | 94 | |
756e7104 | 95 | #ifdef CONFIG_PPC64 |
cd015707 | 96 | |
1da177e4 | 97 | int distribute_irqs = 1; |
d04c56f7 | 98 | |
7230c564 | 99 | static inline notrace unsigned long get_irq_happened(void) |
ef2b343e | 100 | { |
7230c564 | 101 | unsigned long happened; |
ef2b343e HD |
102 | |
103 | __asm__ __volatile__("lbz %0,%1(13)" | |
7230c564 | 104 | : "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened))); |
ef2b343e | 105 | |
7230c564 | 106 | return happened; |
ef2b343e HD |
107 | } |
108 | ||
4e491d14 | 109 | static inline notrace void set_soft_enabled(unsigned long enable) |
ef2b343e HD |
110 | { |
111 | __asm__ __volatile__("stb %0,%1(13)" | |
112 | : : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled))); | |
113 | } | |
114 | ||
7230c564 | 115 | static inline notrace int decrementer_check_overflow(void) |
7df10275 | 116 | { |
7230c564 | 117 | u64 now = get_tb_or_rtc(); |
69111bac | 118 | u64 *next_tb = this_cpu_ptr(&decrementers_next_tb); |
7230c564 | 119 | |
7230c564 | 120 | return now >= *next_tb; |
7df10275 AB |
121 | } |
122 | ||
7230c564 | 123 | /* This is called whenever we are re-enabling interrupts |
fe9e1d54 IM |
124 | * and returns either 0 (nothing to do) or 500/900/280/a00/e80 if |
125 | * there's an EE, DEC or DBELL to generate. | |
7230c564 BH |
126 | * |
127 | * This is called in two contexts: From arch_local_irq_restore() | |
128 | * before soft-enabling interrupts, and from the exception exit | |
129 | * path when returning from an interrupt from a soft-disabled to | |
130 | * a soft enabled context. In both case we have interrupts hard | |
131 | * disabled. | |
132 | * | |
133 | * We take care of only clearing the bits we handled in the | |
134 | * PACA irq_happened field since we can only re-emit one at a | |
135 | * time and we don't want to "lose" one. | |
136 | */ | |
137 | notrace unsigned int __check_irq_replay(void) | |
d04c56f7 | 138 | { |
ef2b343e | 139 | /* |
7230c564 BH |
140 | * We use local_paca rather than get_paca() to avoid all |
141 | * the debug_smp_processor_id() business in this low level | |
142 | * function | |
ef2b343e | 143 | */ |
7230c564 | 144 | unsigned char happened = local_paca->irq_happened; |
d04c56f7 | 145 | |
3db40c31 | 146 | if (happened & PACA_IRQ_HARD_DIS) { |
6f881eae NP |
147 | /* Clear bit 0 which we wouldn't clear otherwise */ |
148 | local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; | |
149 | ||
3db40c31 NP |
150 | /* |
151 | * We may have missed a decrementer interrupt if hard disabled. | |
152 | * Check the decrementer register in case we had a rollover | |
153 | * while hard disabled. | |
154 | */ | |
155 | if (!(happened & PACA_IRQ_DEC)) { | |
156 | if (decrementer_check_overflow()) { | |
157 | local_paca->irq_happened |= PACA_IRQ_DEC; | |
158 | happened |= PACA_IRQ_DEC; | |
159 | } | |
160 | } | |
161 | } | |
7230c564 BH |
162 | |
163 | /* | |
164 | * Force the delivery of pending soft-disabled interrupts on PS3. | |
165 | * Any HV call will have this side effect. | |
166 | */ | |
167 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
168 | u64 tmp, tmp2; | |
169 | lv1_get_version_info(&tmp, &tmp2); | |
d04c56f7 PM |
170 | } |
171 | ||
e0e0d6b7 NP |
172 | /* |
173 | * Check if an hypervisor Maintenance interrupt happened. | |
174 | * This is a higher priority interrupt than the others, so | |
175 | * replay it first. | |
176 | */ | |
6f881eae NP |
177 | if (happened & PACA_IRQ_HMI) { |
178 | local_paca->irq_happened &= ~PACA_IRQ_HMI; | |
e0e0d6b7 | 179 | return 0xe60; |
6f881eae | 180 | } |
e0e0d6b7 | 181 | |
6f881eae NP |
182 | if (happened & PACA_IRQ_DEC) { |
183 | local_paca->irq_happened &= ~PACA_IRQ_DEC; | |
7230c564 | 184 | return 0x900; |
6f881eae | 185 | } |
7230c564 | 186 | |
6f881eae NP |
187 | if (happened & PACA_IRQ_EE) { |
188 | local_paca->irq_happened &= ~PACA_IRQ_EE; | |
7230c564 | 189 | return 0x500; |
6f881eae | 190 | } |
7230c564 BH |
191 | |
192 | #ifdef CONFIG_PPC_BOOK3E | |
6f881eae NP |
193 | /* |
194 | * Check if an EPR external interrupt happened this bit is typically | |
195 | * set if we need to handle another "edge" interrupt from within the | |
196 | * MPIC "EPR" handler. | |
ef2b343e | 197 | */ |
6f881eae NP |
198 | if (happened & PACA_IRQ_EE_EDGE) { |
199 | local_paca->irq_happened &= ~PACA_IRQ_EE_EDGE; | |
7230c564 | 200 | return 0x500; |
6f881eae | 201 | } |
7230c564 | 202 | |
6f881eae NP |
203 | if (happened & PACA_IRQ_DBELL) { |
204 | local_paca->irq_happened &= ~PACA_IRQ_DBELL; | |
7230c564 | 205 | return 0x280; |
6f881eae | 206 | } |
fe9e1d54 | 207 | #else |
fe9e1d54 | 208 | if (happened & PACA_IRQ_DBELL) { |
6f881eae | 209 | local_paca->irq_happened &= ~PACA_IRQ_DBELL; |
fe9e1d54 IM |
210 | return 0xa00; |
211 | } | |
7230c564 BH |
212 | #endif /* CONFIG_PPC_BOOK3E */ |
213 | ||
214 | /* There should be nothing left ! */ | |
215 | BUG_ON(local_paca->irq_happened != 0); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
220 | notrace void arch_local_irq_restore(unsigned long en) | |
221 | { | |
222 | unsigned char irq_happened; | |
223 | unsigned int replay; | |
224 | ||
225 | /* Write the new soft-enabled value */ | |
226 | set_soft_enabled(en); | |
227 | if (!en) | |
228 | return; | |
229 | /* | |
230 | * From this point onward, we can take interrupts, preempt, | |
231 | * etc... unless we got hard-disabled. We check if an event | |
232 | * happened. If none happened, we know we can just return. | |
233 | * | |
234 | * We may have preempted before the check below, in which case | |
235 | * we are checking the "new" CPU instead of the old one. This | |
236 | * is only a problem if an event happened on the "old" CPU. | |
237 | * | |
1d9a4731 SR |
238 | * External interrupt events will have caused interrupts to |
239 | * be hard-disabled, so there is no problem, we | |
7230c564 | 240 | * cannot have preempted. |
ef2b343e | 241 | */ |
7230c564 BH |
242 | irq_happened = get_irq_happened(); |
243 | if (!irq_happened) | |
d04c56f7 | 244 | return; |
ef2b343e HD |
245 | |
246 | /* | |
7230c564 BH |
247 | * We need to hard disable to get a trusted value from |
248 | * __check_irq_replay(). We also need to soft-disable | |
249 | * again to avoid warnings in there due to the use of | |
250 | * per-cpu variables. | |
251 | * | |
252 | * We know that if the value in irq_happened is exactly 0x01 | |
253 | * then we are already hard disabled (there are other less | |
254 | * common cases that we'll ignore for now), so we skip the | |
255 | * (expensive) mtmsrd. | |
ef2b343e | 256 | */ |
7230c564 BH |
257 | if (unlikely(irq_happened != PACA_IRQ_HARD_DIS)) |
258 | __hard_irq_disable(); | |
21b2de34 | 259 | #ifdef CONFIG_TRACE_IRQFLAGS |
7c0482e3 BH |
260 | else { |
261 | /* | |
262 | * We should already be hard disabled here. We had bugs | |
263 | * where that wasn't the case so let's dbl check it and | |
264 | * warn if we are wrong. Only do that when IRQ tracing | |
265 | * is enabled as mfmsr() can be costly. | |
266 | */ | |
267 | if (WARN_ON(mfmsr() & MSR_EE)) | |
268 | __hard_irq_disable(); | |
269 | } | |
fa2cff3f | 270 | #endif /* CONFIG_TRACE_IRQFLAGS */ |
7c0482e3 | 271 | |
7230c564 | 272 | set_soft_enabled(0); |
e8775d4a | 273 | |
37fb9a02 | 274 | /* |
7230c564 BH |
275 | * Check if anything needs to be re-emitted. We haven't |
276 | * soft-enabled yet to avoid warnings in decrementer_check_overflow | |
277 | * accessing per-cpu variables | |
e8775d4a | 278 | */ |
7230c564 BH |
279 | replay = __check_irq_replay(); |
280 | ||
281 | /* We can soft-enable now */ | |
282 | set_soft_enabled(1); | |
0874dd40 TS |
283 | |
284 | /* | |
7230c564 BH |
285 | * And replay if we have to. This will return with interrupts |
286 | * hard-enabled. | |
0874dd40 | 287 | */ |
7230c564 BH |
288 | if (replay) { |
289 | __replay_interrupt(replay); | |
290 | return; | |
0874dd40 TS |
291 | } |
292 | ||
7230c564 | 293 | /* Finally, let's ensure we are hard enabled */ |
e1fa2e13 | 294 | __hard_irq_enable(); |
d04c56f7 | 295 | } |
df9ee292 | 296 | EXPORT_SYMBOL(arch_local_irq_restore); |
7230c564 BH |
297 | |
298 | /* | |
299 | * This is specifically called by assembly code to re-enable interrupts | |
300 | * if they are currently disabled. This is typically called before | |
301 | * schedule() or do_signal() when returning to userspace. We do it | |
302 | * in C to avoid the burden of dealing with lockdep etc... | |
56dfa7fa BH |
303 | * |
304 | * NOTE: This is called with interrupts hard disabled but not marked | |
305 | * as such in paca->irq_happened, so we need to resync this. | |
7230c564 | 306 | */ |
2d773aa4 | 307 | void notrace restore_interrupts(void) |
7230c564 | 308 | { |
56dfa7fa BH |
309 | if (irqs_disabled()) { |
310 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; | |
7230c564 | 311 | local_irq_enable(); |
56dfa7fa BH |
312 | } else |
313 | __hard_irq_enable(); | |
7230c564 BH |
314 | } |
315 | ||
be2cf20a BH |
316 | /* |
317 | * This is a helper to use when about to go into idle low-power | |
318 | * when the latter has the side effect of re-enabling interrupts | |
319 | * (such as calling H_CEDE under pHyp). | |
320 | * | |
321 | * You call this function with interrupts soft-disabled (this is | |
322 | * already the case when ppc_md.power_save is called). The function | |
323 | * will return whether to enter power save or just return. | |
324 | * | |
325 | * In the former case, it will have notified lockdep of interrupts | |
326 | * being re-enabled and generally sanitized the lazy irq state, | |
327 | * and in the latter case it will leave with interrupts hard | |
328 | * disabled and marked as such, so the local_irq_enable() call | |
0d2b7ea9 | 329 | * in arch_cpu_idle() will properly re-enable everything. |
be2cf20a BH |
330 | */ |
331 | bool prep_irq_for_idle(void) | |
332 | { | |
333 | /* | |
334 | * First we need to hard disable to ensure no interrupt | |
335 | * occurs before we effectively enter the low power state | |
336 | */ | |
2201f994 NP |
337 | __hard_irq_disable(); |
338 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; | |
be2cf20a BH |
339 | |
340 | /* | |
341 | * If anything happened while we were soft-disabled, | |
342 | * we return now and do not enter the low power state. | |
343 | */ | |
344 | if (lazy_irq_pending()) | |
345 | return false; | |
346 | ||
347 | /* Tell lockdep we are about to re-enable */ | |
348 | trace_hardirqs_on(); | |
349 | ||
350 | /* | |
351 | * Mark interrupts as soft-enabled and clear the | |
352 | * PACA_IRQ_HARD_DIS from the pending mask since we | |
353 | * are about to hard enable as well as a side effect | |
354 | * of entering the low power state. | |
355 | */ | |
356 | local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; | |
357 | local_paca->soft_enabled = 1; | |
358 | ||
359 | /* Tell the caller to enter the low power state */ | |
360 | return true; | |
361 | } | |
362 | ||
771d4304 | 363 | #ifdef CONFIG_PPC_BOOK3S |
2201f994 NP |
364 | /* |
365 | * This is for idle sequences that return with IRQs off, but the | |
366 | * idle state itself wakes on interrupt. Tell the irq tracer that | |
367 | * IRQs are enabled for the duration of idle so it does not get long | |
368 | * off times. Must be paired with fini_irq_for_idle_irqsoff. | |
369 | */ | |
370 | bool prep_irq_for_idle_irqsoff(void) | |
371 | { | |
372 | WARN_ON(!irqs_disabled()); | |
373 | ||
374 | /* | |
375 | * First we need to hard disable to ensure no interrupt | |
376 | * occurs before we effectively enter the low power state | |
377 | */ | |
378 | __hard_irq_disable(); | |
379 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; | |
380 | ||
381 | /* | |
382 | * If anything happened while we were soft-disabled, | |
383 | * we return now and do not enter the low power state. | |
384 | */ | |
385 | if (lazy_irq_pending()) | |
386 | return false; | |
387 | ||
388 | /* Tell lockdep we are about to re-enable */ | |
389 | trace_hardirqs_on(); | |
390 | ||
391 | return true; | |
392 | } | |
393 | ||
771d4304 NP |
394 | /* |
395 | * Take the SRR1 wakeup reason, index into this table to find the | |
396 | * appropriate irq_happened bit. | |
78adf6c2 NP |
397 | * |
398 | * Sytem reset exceptions taken in idle state also come through here, | |
399 | * but they are NMI interrupts so do not need to wait for IRQs to be | |
400 | * restored, and should be taken as early as practical. These are marked | |
401 | * with 0xff in the table. The Power ISA specifies 0100b as the system | |
402 | * reset interrupt reason. | |
771d4304 | 403 | */ |
78adf6c2 NP |
404 | #define IRQ_SYSTEM_RESET 0xff |
405 | ||
771d4304 NP |
406 | static const u8 srr1_to_lazyirq[0x10] = { |
407 | 0, 0, 0, | |
408 | PACA_IRQ_DBELL, | |
78adf6c2 | 409 | IRQ_SYSTEM_RESET, |
771d4304 NP |
410 | PACA_IRQ_DBELL, |
411 | PACA_IRQ_DEC, | |
412 | 0, | |
413 | PACA_IRQ_EE, | |
414 | PACA_IRQ_EE, | |
415 | PACA_IRQ_HMI, | |
416 | 0, 0, 0, 0, 0 }; | |
417 | ||
78adf6c2 NP |
418 | static noinline void replay_system_reset(void) |
419 | { | |
420 | struct pt_regs regs; | |
421 | ||
422 | ppc_save_regs(®s); | |
423 | regs.trap = 0x100; | |
424 | get_paca()->in_nmi = 1; | |
425 | system_reset_exception(®s); | |
426 | get_paca()->in_nmi = 0; | |
427 | } | |
428 | ||
771d4304 NP |
429 | void irq_set_pending_from_srr1(unsigned long srr1) |
430 | { | |
431 | unsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18; | |
78adf6c2 NP |
432 | u8 reason = srr1_to_lazyirq[idx]; |
433 | ||
434 | /* | |
435 | * Take the system reset now, which is immediately after registers | |
436 | * are restored from idle. It's an NMI, so interrupts need not be | |
437 | * re-enabled before it is taken. | |
438 | */ | |
439 | if (unlikely(reason == IRQ_SYSTEM_RESET)) { | |
440 | replay_system_reset(); | |
441 | return; | |
442 | } | |
771d4304 NP |
443 | |
444 | /* | |
445 | * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0, | |
78adf6c2 NP |
446 | * so this can be called unconditionally with the SRR1 wake |
447 | * reason as returned by the idle code, which uses 0 to mean no | |
448 | * interrupt. | |
449 | * | |
450 | * If a future CPU was to designate this as an interrupt reason, | |
451 | * then a new index for no interrupt must be assigned. | |
771d4304 | 452 | */ |
78adf6c2 | 453 | local_paca->irq_happened |= reason; |
771d4304 NP |
454 | } |
455 | #endif /* CONFIG_PPC_BOOK3S */ | |
456 | ||
1d607bb3 BH |
457 | /* |
458 | * Force a replay of the external interrupt handler on this CPU. | |
459 | */ | |
460 | void force_external_irq_replay(void) | |
461 | { | |
462 | /* | |
463 | * This must only be called with interrupts soft-disabled, | |
464 | * the replay will happen when re-enabling. | |
465 | */ | |
466 | WARN_ON(!arch_irqs_disabled()); | |
467 | ||
468 | /* Indicate in the PACA that we have an interrupt to replay */ | |
469 | local_paca->irq_happened |= PACA_IRQ_EE; | |
470 | } | |
471 | ||
756e7104 | 472 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 473 | |
433c9c67 | 474 | int arch_show_interrupts(struct seq_file *p, int prec) |
c86845ed AB |
475 | { |
476 | int j; | |
477 | ||
478 | #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT) | |
479 | if (tau_initialized) { | |
480 | seq_printf(p, "%*s: ", prec, "TAU"); | |
481 | for_each_online_cpu(j) | |
482 | seq_printf(p, "%10u ", tau_interrupts(j)); | |
483 | seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n"); | |
484 | } | |
485 | #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */ | |
486 | ||
89713ed1 AB |
487 | seq_printf(p, "%*s: ", prec, "LOC"); |
488 | for_each_online_cpu(j) | |
c041cfa2 | 489 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event); |
490 | seq_printf(p, " Local timer interrupts for timer event device\n"); | |
491 | ||
492 | seq_printf(p, "%*s: ", prec, "LOC"); | |
493 | for_each_online_cpu(j) | |
494 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others); | |
495 | seq_printf(p, " Local timer interrupts for others\n"); | |
89713ed1 | 496 | |
17081102 AB |
497 | seq_printf(p, "%*s: ", prec, "SPU"); |
498 | for_each_online_cpu(j) | |
499 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs); | |
500 | seq_printf(p, " Spurious interrupts\n"); | |
501 | ||
e8e813ed | 502 | seq_printf(p, "%*s: ", prec, "PMI"); |
89713ed1 AB |
503 | for_each_online_cpu(j) |
504 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs); | |
505 | seq_printf(p, " Performance monitoring interrupts\n"); | |
506 | ||
507 | seq_printf(p, "%*s: ", prec, "MCE"); | |
508 | for_each_online_cpu(j) | |
509 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions); | |
510 | seq_printf(p, " Machine check exceptions\n"); | |
511 | ||
0869b6fd MS |
512 | if (cpu_has_feature(CPU_FTR_HVMODE)) { |
513 | seq_printf(p, "%*s: ", prec, "HMI"); | |
514 | for_each_online_cpu(j) | |
515 | seq_printf(p, "%10u ", | |
516 | per_cpu(irq_stat, j).hmi_exceptions); | |
517 | seq_printf(p, " Hypervisor Maintenance Interrupts\n"); | |
518 | } | |
519 | ||
ca41ad43 NP |
520 | seq_printf(p, "%*s: ", prec, "NMI"); |
521 | for_each_online_cpu(j) | |
522 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).sreset_irqs); | |
523 | seq_printf(p, " System Reset interrupts\n"); | |
524 | ||
04019bf8 NP |
525 | #ifdef CONFIG_PPC_WATCHDOG |
526 | seq_printf(p, "%*s: ", prec, "WDG"); | |
527 | for_each_online_cpu(j) | |
528 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).soft_nmi_irqs); | |
529 | seq_printf(p, " Watchdog soft-NMI interrupts\n"); | |
530 | #endif | |
531 | ||
a6a058e5 IM |
532 | #ifdef CONFIG_PPC_DOORBELL |
533 | if (cpu_has_feature(CPU_FTR_DBELL)) { | |
534 | seq_printf(p, "%*s: ", prec, "DBL"); | |
535 | for_each_online_cpu(j) | |
536 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs); | |
537 | seq_printf(p, " Doorbell interrupts\n"); | |
538 | } | |
539 | #endif | |
540 | ||
c86845ed AB |
541 | return 0; |
542 | } | |
543 | ||
89713ed1 AB |
544 | /* |
545 | * /proc/stat helpers | |
546 | */ | |
547 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
548 | { | |
c041cfa2 | 549 | u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event; |
89713ed1 AB |
550 | |
551 | sum += per_cpu(irq_stat, cpu).pmu_irqs; | |
552 | sum += per_cpu(irq_stat, cpu).mce_exceptions; | |
17081102 | 553 | sum += per_cpu(irq_stat, cpu).spurious_irqs; |
c041cfa2 | 554 | sum += per_cpu(irq_stat, cpu).timer_irqs_others; |
0869b6fd | 555 | sum += per_cpu(irq_stat, cpu).hmi_exceptions; |
ca41ad43 | 556 | sum += per_cpu(irq_stat, cpu).sreset_irqs; |
04019bf8 NP |
557 | #ifdef CONFIG_PPC_WATCHDOG |
558 | sum += per_cpu(irq_stat, cpu).soft_nmi_irqs; | |
559 | #endif | |
a6a058e5 IM |
560 | #ifdef CONFIG_PPC_DOORBELL |
561 | sum += per_cpu(irq_stat, cpu).doorbell_irqs; | |
562 | #endif | |
89713ed1 AB |
563 | |
564 | return sum; | |
565 | } | |
566 | ||
d7cb10d6 ME |
567 | static inline void check_stack_overflow(void) |
568 | { | |
569 | #ifdef CONFIG_DEBUG_STACKOVERFLOW | |
570 | long sp; | |
571 | ||
acf620ec | 572 | sp = current_stack_pointer() & (THREAD_SIZE-1); |
d7cb10d6 ME |
573 | |
574 | /* check for stack overflow: is there less than 2KB free? */ | |
575 | if (unlikely(sp < (sizeof(struct thread_info) + 2048))) { | |
a7696b36 | 576 | pr_err("do_IRQ: stack overflow: %ld\n", |
d7cb10d6 ME |
577 | sp - sizeof(struct thread_info)); |
578 | dump_stack(); | |
579 | } | |
580 | #endif | |
581 | } | |
582 | ||
0366a1c7 | 583 | void __do_irq(struct pt_regs *regs) |
1da177e4 | 584 | { |
0ebfff14 | 585 | unsigned int irq; |
1da177e4 | 586 | |
4b218e9b | 587 | irq_enter(); |
1da177e4 | 588 | |
e72bbbab LZ |
589 | trace_irq_entry(regs); |
590 | ||
d7cb10d6 | 591 | check_stack_overflow(); |
1da177e4 | 592 | |
7230c564 BH |
593 | /* |
594 | * Query the platform PIC for the interrupt & ack it. | |
595 | * | |
596 | * This will typically lower the interrupt line to the CPU | |
597 | */ | |
35a84c2f | 598 | irq = ppc_md.get_irq(); |
1da177e4 | 599 | |
0366a1c7 | 600 | /* We can hard enable interrupts now to allow perf interrupts */ |
7230c564 BH |
601 | may_hard_irq_enable(); |
602 | ||
603 | /* And finally process it */ | |
ef24ba70 | 604 | if (unlikely(!irq)) |
69111bac | 605 | __this_cpu_inc(irq_stat.spurious_irqs); |
a4e04c9f | 606 | else |
0edc2ca9 | 607 | generic_handle_irq(irq); |
e199500c | 608 | |
e72bbbab LZ |
609 | trace_irq_exit(regs); |
610 | ||
4b218e9b | 611 | irq_exit(); |
0366a1c7 BH |
612 | } |
613 | ||
614 | void do_IRQ(struct pt_regs *regs) | |
615 | { | |
616 | struct pt_regs *old_regs = set_irq_regs(regs); | |
8b5ede69 | 617 | struct thread_info *curtp, *irqtp, *sirqtp; |
0366a1c7 BH |
618 | |
619 | /* Switch to the irq stack to handle this */ | |
620 | curtp = current_thread_info(); | |
621 | irqtp = hardirq_ctx[raw_smp_processor_id()]; | |
8b5ede69 | 622 | sirqtp = softirq_ctx[raw_smp_processor_id()]; |
0366a1c7 BH |
623 | |
624 | /* Already there ? */ | |
8b5ede69 | 625 | if (unlikely(curtp == irqtp || curtp == sirqtp)) { |
0366a1c7 BH |
626 | __do_irq(regs); |
627 | set_irq_regs(old_regs); | |
628 | return; | |
629 | } | |
630 | ||
0366a1c7 BH |
631 | /* Prepare the thread_info in the irq stack */ |
632 | irqtp->task = curtp->task; | |
633 | irqtp->flags = 0; | |
634 | ||
635 | /* Copy the preempt_count so that the [soft]irq checks work. */ | |
636 | irqtp->preempt_count = curtp->preempt_count; | |
637 | ||
638 | /* Switch stack and call */ | |
639 | call_do_irq(regs, irqtp); | |
640 | ||
641 | /* Restore stack limit */ | |
0366a1c7 BH |
642 | irqtp->task = NULL; |
643 | ||
644 | /* Copy back updates to the thread_info */ | |
645 | if (irqtp->flags) | |
646 | set_bits(irqtp->flags, &curtp->flags); | |
647 | ||
7d12e780 | 648 | set_irq_regs(old_regs); |
e199500c | 649 | } |
1da177e4 LT |
650 | |
651 | void __init init_IRQ(void) | |
652 | { | |
70584578 SR |
653 | if (ppc_md.init_IRQ) |
654 | ppc_md.init_IRQ(); | |
bcf0b088 KG |
655 | |
656 | exc_lvl_ctx_init(); | |
657 | ||
1da177e4 LT |
658 | irq_ctx_init(); |
659 | } | |
660 | ||
bcf0b088 KG |
661 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
662 | struct thread_info *critirq_ctx[NR_CPUS] __read_mostly; | |
663 | struct thread_info *dbgirq_ctx[NR_CPUS] __read_mostly; | |
664 | struct thread_info *mcheckirq_ctx[NR_CPUS] __read_mostly; | |
665 | ||
666 | void exc_lvl_ctx_init(void) | |
667 | { | |
668 | struct thread_info *tp; | |
ca1769f7 | 669 | int i, cpu_nr; |
bcf0b088 KG |
670 | |
671 | for_each_possible_cpu(i) { | |
ca1769f7 ME |
672 | #ifdef CONFIG_PPC64 |
673 | cpu_nr = i; | |
674 | #else | |
04a34113 | 675 | #ifdef CONFIG_SMP |
ca1769f7 | 676 | cpu_nr = get_hard_smp_processor_id(i); |
04a34113 KH |
677 | #else |
678 | cpu_nr = 0; | |
679 | #endif | |
ca1769f7 | 680 | #endif |
04a34113 | 681 | |
ca1769f7 ME |
682 | memset((void *)critirq_ctx[cpu_nr], 0, THREAD_SIZE); |
683 | tp = critirq_ctx[cpu_nr]; | |
684 | tp->cpu = cpu_nr; | |
bcf0b088 KG |
685 | tp->preempt_count = 0; |
686 | ||
687 | #ifdef CONFIG_BOOKE | |
ca1769f7 ME |
688 | memset((void *)dbgirq_ctx[cpu_nr], 0, THREAD_SIZE); |
689 | tp = dbgirq_ctx[cpu_nr]; | |
690 | tp->cpu = cpu_nr; | |
bcf0b088 KG |
691 | tp->preempt_count = 0; |
692 | ||
ca1769f7 ME |
693 | memset((void *)mcheckirq_ctx[cpu_nr], 0, THREAD_SIZE); |
694 | tp = mcheckirq_ctx[cpu_nr]; | |
695 | tp->cpu = cpu_nr; | |
bcf0b088 KG |
696 | tp->preempt_count = HARDIRQ_OFFSET; |
697 | #endif | |
698 | } | |
699 | } | |
700 | #endif | |
1da177e4 | 701 | |
22722051 AM |
702 | struct thread_info *softirq_ctx[NR_CPUS] __read_mostly; |
703 | struct thread_info *hardirq_ctx[NR_CPUS] __read_mostly; | |
1da177e4 LT |
704 | |
705 | void irq_ctx_init(void) | |
706 | { | |
707 | struct thread_info *tp; | |
708 | int i; | |
709 | ||
0e551954 | 710 | for_each_possible_cpu(i) { |
1da177e4 LT |
711 | memset((void *)softirq_ctx[i], 0, THREAD_SIZE); |
712 | tp = softirq_ctx[i]; | |
713 | tp->cpu = i; | |
5d31a96e | 714 | klp_init_thread_info(tp); |
1da177e4 LT |
715 | |
716 | memset((void *)hardirq_ctx[i], 0, THREAD_SIZE); | |
717 | tp = hardirq_ctx[i]; | |
718 | tp->cpu = i; | |
5d31a96e | 719 | klp_init_thread_info(tp); |
1da177e4 LT |
720 | } |
721 | } | |
722 | ||
7d65f4a6 | 723 | void do_softirq_own_stack(void) |
c6622f63 PM |
724 | { |
725 | struct thread_info *curtp, *irqtp; | |
726 | ||
727 | curtp = current_thread_info(); | |
728 | irqtp = softirq_ctx[smp_processor_id()]; | |
729 | irqtp->task = curtp->task; | |
50d2a422 | 730 | irqtp->flags = 0; |
c6622f63 PM |
731 | call_do_softirq(irqtp); |
732 | irqtp->task = NULL; | |
50d2a422 BH |
733 | |
734 | /* Set any flag that may have been set on the | |
735 | * alternate stack | |
736 | */ | |
737 | if (irqtp->flags) | |
738 | set_bits(irqtp->flags, &curtp->flags); | |
c6622f63 | 739 | } |
1da177e4 | 740 | |
35923f12 OJ |
741 | irq_hw_number_t virq_to_hw(unsigned int virq) |
742 | { | |
4bbdd45a GL |
743 | struct irq_data *irq_data = irq_get_irq_data(virq); |
744 | return WARN_ON(!irq_data) ? 0 : irq_data->hwirq; | |
35923f12 OJ |
745 | } |
746 | EXPORT_SYMBOL_GPL(virq_to_hw); | |
747 | ||
6ec36b58 SY |
748 | #ifdef CONFIG_SMP |
749 | int irq_choose_cpu(const struct cpumask *mask) | |
750 | { | |
751 | int cpuid; | |
752 | ||
2074b1d9 | 753 | if (cpumask_equal(mask, cpu_online_mask)) { |
6ec36b58 SY |
754 | static int irq_rover; |
755 | static DEFINE_RAW_SPINLOCK(irq_rover_lock); | |
756 | unsigned long flags; | |
757 | ||
758 | /* Round-robin distribution... */ | |
759 | do_round_robin: | |
760 | raw_spin_lock_irqsave(&irq_rover_lock, flags); | |
761 | ||
762 | irq_rover = cpumask_next(irq_rover, cpu_online_mask); | |
763 | if (irq_rover >= nr_cpu_ids) | |
764 | irq_rover = cpumask_first(cpu_online_mask); | |
765 | ||
766 | cpuid = irq_rover; | |
767 | ||
768 | raw_spin_unlock_irqrestore(&irq_rover_lock, flags); | |
769 | } else { | |
770 | cpuid = cpumask_first_and(mask, cpu_online_mask); | |
771 | if (cpuid >= nr_cpu_ids) | |
772 | goto do_round_robin; | |
773 | } | |
774 | ||
775 | return get_hard_smp_processor_id(cpuid); | |
776 | } | |
777 | #else | |
778 | int irq_choose_cpu(const struct cpumask *mask) | |
779 | { | |
780 | return hard_smp_processor_id(); | |
781 | } | |
782 | #endif | |
0ebfff14 | 783 | |
cd015707 | 784 | int arch_early_irq_init(void) |
0ebfff14 | 785 | { |
cd015707 | 786 | return 0; |
0ebfff14 BH |
787 | } |
788 | ||
c6622f63 | 789 | #ifdef CONFIG_PPC64 |
1da177e4 LT |
790 | static int __init setup_noirqdistrib(char *str) |
791 | { | |
792 | distribute_irqs = 0; | |
793 | return 1; | |
794 | } | |
795 | ||
796 | __setup("noirqdistrib", setup_noirqdistrib); | |
756e7104 | 797 | #endif /* CONFIG_PPC64 */ |