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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Derived from arch/i386/kernel/irq.c |
4 | * Copyright (C) 1992 Linus Torvalds | |
5 | * Adapted from arch/i386 by Gary Thomas | |
6 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
756e7104 SR |
7 | * Updated and modified by Cort Dougan <cort@fsmlabs.com> |
8 | * Copyright (C) 1996-2001 Cort Dougan | |
1da177e4 LT |
9 | * Adapted for Power Macintosh by Paul Mackerras |
10 | * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au) | |
756e7104 | 11 | * |
1da177e4 LT |
12 | * This file contains the code used by various IRQ handling routines: |
13 | * asking for different IRQ's should be done through these routines | |
14 | * instead of just grabbing them. Thus setups with different IRQ numbers | |
15 | * shouldn't result in any weird surprises, and installing new handlers | |
16 | * should be easier. | |
756e7104 SR |
17 | * |
18 | * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the | |
19 | * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit | |
20 | * mask register (of which only 16 are defined), hence the weird shifting | |
21 | * and complement of the cached_irq_mask. I want to be able to stuff | |
22 | * this right into the SIU SMASK register. | |
968159c0 | 23 | * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx |
756e7104 | 24 | * to reduce code space and undefined function references. |
1da177e4 LT |
25 | */ |
26 | ||
0ebfff14 BH |
27 | #undef DEBUG |
28 | ||
4b16f8e2 | 29 | #include <linux/export.h> |
1da177e4 LT |
30 | #include <linux/threads.h> |
31 | #include <linux/kernel_stat.h> | |
32 | #include <linux/signal.h> | |
33 | #include <linux/sched.h> | |
756e7104 | 34 | #include <linux/ptrace.h> |
1da177e4 LT |
35 | #include <linux/ioport.h> |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/timex.h> | |
1da177e4 LT |
38 | #include <linux/init.h> |
39 | #include <linux/slab.h> | |
1da177e4 LT |
40 | #include <linux/delay.h> |
41 | #include <linux/irq.h> | |
756e7104 SR |
42 | #include <linux/seq_file.h> |
43 | #include <linux/cpumask.h> | |
1da177e4 LT |
44 | #include <linux/profile.h> |
45 | #include <linux/bitops.h> | |
0ebfff14 BH |
46 | #include <linux/list.h> |
47 | #include <linux/radix-tree.h> | |
48 | #include <linux/mutex.h> | |
45934c47 | 49 | #include <linux/pci.h> |
60b332e7 | 50 | #include <linux/debugfs.h> |
e3873444 GL |
51 | #include <linux/of.h> |
52 | #include <linux/of_irq.h> | |
547db12f | 53 | #include <linux/vmalloc.h> |
65fddcfc | 54 | #include <linux/pgtable.h> |
1da177e4 | 55 | |
7c0f6ba6 | 56 | #include <linux/uaccess.h> |
1da177e4 | 57 | #include <asm/io.h> |
1da177e4 LT |
58 | #include <asm/irq.h> |
59 | #include <asm/cache.h> | |
60 | #include <asm/prom.h> | |
61 | #include <asm/ptrace.h> | |
1da177e4 | 62 | #include <asm/machdep.h> |
0ebfff14 | 63 | #include <asm/udbg.h> |
3e7f45ad | 64 | #include <asm/smp.h> |
5d31a96e | 65 | #include <asm/livepatch.h> |
0545d543 | 66 | #include <asm/asm-prototypes.h> |
c2e480ba | 67 | #include <asm/hw_irq.h> |
89c81797 | 68 | |
d04c56f7 | 69 | #ifdef CONFIG_PPC64 |
1da177e4 | 70 | #include <asm/paca.h> |
d04c56f7 | 71 | #include <asm/firmware.h> |
0874dd40 | 72 | #include <asm/lv1call.h> |
3282a3da | 73 | #include <asm/dbell.h> |
756e7104 | 74 | #endif |
1bf4af16 AB |
75 | #define CREATE_TRACE_POINTS |
76 | #include <asm/trace.h> | |
b92a226e | 77 | #include <asm/cpu_has_feature.h> |
1da177e4 | 78 | |
8c007bfd AB |
79 | DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); |
80 | EXPORT_PER_CPU_SYMBOL(irq_stat); | |
81 | ||
756e7104 | 82 | #ifdef CONFIG_PPC32 |
b9e5b4e6 | 83 | atomic_t ppc_n_lost_interrupts; |
756e7104 | 84 | |
756e7104 SR |
85 | #ifdef CONFIG_TAU_INT |
86 | extern int tau_initialized; | |
bd13ac95 | 87 | u32 tau_interrupts(unsigned long cpu); |
756e7104 | 88 | #endif |
b9e5b4e6 | 89 | #endif /* CONFIG_PPC32 */ |
756e7104 | 90 | |
756e7104 | 91 | #ifdef CONFIG_PPC64 |
cd015707 | 92 | |
1da177e4 | 93 | int distribute_irqs = 1; |
d04c56f7 | 94 | |
7230c564 | 95 | static inline notrace unsigned long get_irq_happened(void) |
ef2b343e | 96 | { |
7230c564 | 97 | unsigned long happened; |
ef2b343e HD |
98 | |
99 | __asm__ __volatile__("lbz %0,%1(13)" | |
7230c564 | 100 | : "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened))); |
ef2b343e | 101 | |
7230c564 | 102 | return happened; |
ef2b343e HD |
103 | } |
104 | ||
7230c564 | 105 | static inline notrace int decrementer_check_overflow(void) |
7df10275 | 106 | { |
7230c564 | 107 | u64 now = get_tb_or_rtc(); |
69111bac | 108 | u64 *next_tb = this_cpu_ptr(&decrementers_next_tb); |
7230c564 | 109 | |
7230c564 | 110 | return now >= *next_tb; |
7df10275 AB |
111 | } |
112 | ||
6cc0c16d NP |
113 | #ifdef CONFIG_PPC_BOOK3E |
114 | ||
7230c564 | 115 | /* This is called whenever we are re-enabling interrupts |
fe9e1d54 IM |
116 | * and returns either 0 (nothing to do) or 500/900/280/a00/e80 if |
117 | * there's an EE, DEC or DBELL to generate. | |
7230c564 BH |
118 | * |
119 | * This is called in two contexts: From arch_local_irq_restore() | |
120 | * before soft-enabling interrupts, and from the exception exit | |
121 | * path when returning from an interrupt from a soft-disabled to | |
122 | * a soft enabled context. In both case we have interrupts hard | |
123 | * disabled. | |
124 | * | |
125 | * We take care of only clearing the bits we handled in the | |
126 | * PACA irq_happened field since we can only re-emit one at a | |
127 | * time and we don't want to "lose" one. | |
128 | */ | |
129 | notrace unsigned int __check_irq_replay(void) | |
d04c56f7 | 130 | { |
ef2b343e | 131 | /* |
7230c564 BH |
132 | * We use local_paca rather than get_paca() to avoid all |
133 | * the debug_smp_processor_id() business in this low level | |
134 | * function | |
ef2b343e | 135 | */ |
7230c564 | 136 | unsigned char happened = local_paca->irq_happened; |
d04c56f7 | 137 | |
ff967900 NP |
138 | /* |
139 | * We are responding to the next interrupt, so interrupt-off | |
140 | * latencies should be reset here. | |
141 | */ | |
142 | trace_hardirqs_on(); | |
143 | trace_hardirqs_off(); | |
144 | ||
9b81c021 NP |
145 | /* |
146 | * We are always hard disabled here, but PACA_IRQ_HARD_DIS may | |
147 | * not be set, which means interrupts have only just been hard | |
148 | * disabled as part of the local_irq_restore or interrupt return | |
149 | * code. In that case, skip the decrementr check becaus it's | |
150 | * expensive to read the TB. | |
151 | * | |
152 | * HARD_DIS then gets cleared here, but it's reconciled later. | |
153 | * Either local_irq_disable will replay the interrupt and that | |
154 | * will reconcile state like other hard interrupts. Or interrupt | |
155 | * retur will replay the interrupt and in that case it sets | |
156 | * PACA_IRQ_HARD_DIS by hand (see comments in entry_64.S). | |
157 | */ | |
3db40c31 | 158 | if (happened & PACA_IRQ_HARD_DIS) { |
6f881eae NP |
159 | local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; |
160 | ||
3db40c31 NP |
161 | /* |
162 | * We may have missed a decrementer interrupt if hard disabled. | |
163 | * Check the decrementer register in case we had a rollover | |
164 | * while hard disabled. | |
165 | */ | |
166 | if (!(happened & PACA_IRQ_DEC)) { | |
167 | if (decrementer_check_overflow()) { | |
168 | local_paca->irq_happened |= PACA_IRQ_DEC; | |
169 | happened |= PACA_IRQ_DEC; | |
170 | } | |
171 | } | |
172 | } | |
7230c564 | 173 | |
6f881eae NP |
174 | if (happened & PACA_IRQ_DEC) { |
175 | local_paca->irq_happened &= ~PACA_IRQ_DEC; | |
7230c564 | 176 | return 0x900; |
6f881eae | 177 | } |
7230c564 | 178 | |
6f881eae NP |
179 | if (happened & PACA_IRQ_EE) { |
180 | local_paca->irq_happened &= ~PACA_IRQ_EE; | |
7230c564 | 181 | return 0x500; |
6f881eae | 182 | } |
7230c564 | 183 | |
6f881eae NP |
184 | /* |
185 | * Check if an EPR external interrupt happened this bit is typically | |
186 | * set if we need to handle another "edge" interrupt from within the | |
187 | * MPIC "EPR" handler. | |
ef2b343e | 188 | */ |
6f881eae NP |
189 | if (happened & PACA_IRQ_EE_EDGE) { |
190 | local_paca->irq_happened &= ~PACA_IRQ_EE_EDGE; | |
7230c564 | 191 | return 0x500; |
6f881eae | 192 | } |
7230c564 | 193 | |
6f881eae NP |
194 | if (happened & PACA_IRQ_DBELL) { |
195 | local_paca->irq_happened &= ~PACA_IRQ_DBELL; | |
7230c564 | 196 | return 0x280; |
6f881eae | 197 | } |
7230c564 BH |
198 | |
199 | /* There should be nothing left ! */ | |
200 | BUG_ON(local_paca->irq_happened != 0); | |
201 | ||
202 | return 0; | |
203 | } | |
6cc0c16d | 204 | #endif /* CONFIG_PPC_BOOK3E */ |
7230c564 | 205 | |
6cc0c16d | 206 | void replay_soft_interrupts(void) |
3282a3da NP |
207 | { |
208 | /* | |
209 | * We use local_paca rather than get_paca() to avoid all | |
210 | * the debug_smp_processor_id() business in this low level | |
211 | * function | |
212 | */ | |
213 | unsigned char happened = local_paca->irq_happened; | |
214 | struct pt_regs regs; | |
215 | ||
216 | ppc_save_regs(®s); | |
217 | regs.softe = IRQS_ALL_DISABLED; | |
218 | ||
219 | again: | |
220 | if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) | |
221 | WARN_ON_ONCE(mfmsr() & MSR_EE); | |
222 | ||
223 | if (happened & PACA_IRQ_HARD_DIS) { | |
224 | /* | |
225 | * We may have missed a decrementer interrupt if hard disabled. | |
226 | * Check the decrementer register in case we had a rollover | |
227 | * while hard disabled. | |
228 | */ | |
229 | if (!(happened & PACA_IRQ_DEC)) { | |
230 | if (decrementer_check_overflow()) | |
231 | happened |= PACA_IRQ_DEC; | |
232 | } | |
233 | } | |
234 | ||
235 | /* | |
236 | * Force the delivery of pending soft-disabled interrupts on PS3. | |
237 | * Any HV call will have this side effect. | |
238 | */ | |
239 | if (firmware_has_feature(FW_FEATURE_PS3_LV1)) { | |
240 | u64 tmp, tmp2; | |
241 | lv1_get_version_info(&tmp, &tmp2); | |
242 | } | |
243 | ||
244 | /* | |
245 | * Check if an hypervisor Maintenance interrupt happened. | |
246 | * This is a higher priority interrupt than the others, so | |
247 | * replay it first. | |
248 | */ | |
249 | if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (happened & PACA_IRQ_HMI)) { | |
250 | local_paca->irq_happened &= ~PACA_IRQ_HMI; | |
251 | regs.trap = 0xe60; | |
252 | handle_hmi_exception(®s); | |
253 | if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) | |
254 | hard_irq_disable(); | |
255 | } | |
256 | ||
257 | if (happened & PACA_IRQ_DEC) { | |
258 | local_paca->irq_happened &= ~PACA_IRQ_DEC; | |
259 | regs.trap = 0x900; | |
260 | timer_interrupt(®s); | |
261 | if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) | |
262 | hard_irq_disable(); | |
263 | } | |
264 | ||
265 | if (happened & PACA_IRQ_EE) { | |
266 | local_paca->irq_happened &= ~PACA_IRQ_EE; | |
267 | regs.trap = 0x500; | |
268 | do_IRQ(®s); | |
269 | if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) | |
270 | hard_irq_disable(); | |
271 | } | |
272 | ||
273 | /* | |
274 | * Check if an EPR external interrupt happened this bit is typically | |
275 | * set if we need to handle another "edge" interrupt from within the | |
276 | * MPIC "EPR" handler. | |
277 | */ | |
278 | if (IS_ENABLED(CONFIG_PPC_BOOK3E) && (happened & PACA_IRQ_EE_EDGE)) { | |
279 | local_paca->irq_happened &= ~PACA_IRQ_EE_EDGE; | |
280 | regs.trap = 0x500; | |
281 | do_IRQ(®s); | |
282 | if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) | |
283 | hard_irq_disable(); | |
284 | } | |
285 | ||
286 | if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (happened & PACA_IRQ_DBELL)) { | |
287 | local_paca->irq_happened &= ~PACA_IRQ_DBELL; | |
288 | if (IS_ENABLED(CONFIG_PPC_BOOK3E)) | |
289 | regs.trap = 0x280; | |
290 | else | |
291 | regs.trap = 0xa00; | |
292 | doorbell_exception(®s); | |
293 | if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) | |
294 | hard_irq_disable(); | |
295 | } | |
296 | ||
297 | /* Book3E does not support soft-masking PMI interrupts */ | |
298 | if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (happened & PACA_IRQ_PMI)) { | |
299 | local_paca->irq_happened &= ~PACA_IRQ_PMI; | |
300 | regs.trap = 0xf00; | |
301 | performance_monitor_exception(®s); | |
302 | if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS)) | |
303 | hard_irq_disable(); | |
304 | } | |
305 | ||
306 | happened = local_paca->irq_happened; | |
307 | if (happened & ~PACA_IRQ_HARD_DIS) { | |
308 | /* | |
309 | * We are responding to the next interrupt, so interrupt-off | |
310 | * latencies should be reset here. | |
311 | */ | |
312 | trace_hardirqs_on(); | |
313 | trace_hardirqs_off(); | |
314 | goto again; | |
315 | } | |
316 | } | |
317 | ||
01417c6c | 318 | notrace void arch_local_irq_restore(unsigned long mask) |
7230c564 BH |
319 | { |
320 | unsigned char irq_happened; | |
7230c564 BH |
321 | |
322 | /* Write the new soft-enabled value */ | |
4e26bc4a MS |
323 | irq_soft_mask_set(mask); |
324 | if (mask) | |
7230c564 | 325 | return; |
01417c6c | 326 | |
7230c564 BH |
327 | /* |
328 | * From this point onward, we can take interrupts, preempt, | |
329 | * etc... unless we got hard-disabled. We check if an event | |
330 | * happened. If none happened, we know we can just return. | |
331 | * | |
332 | * We may have preempted before the check below, in which case | |
333 | * we are checking the "new" CPU instead of the old one. This | |
334 | * is only a problem if an event happened on the "old" CPU. | |
335 | * | |
1d9a4731 SR |
336 | * External interrupt events will have caused interrupts to |
337 | * be hard-disabled, so there is no problem, we | |
7230c564 | 338 | * cannot have preempted. |
ef2b343e | 339 | */ |
7230c564 | 340 | irq_happened = get_irq_happened(); |
9b81c021 | 341 | if (!irq_happened) { |
3282a3da NP |
342 | if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) |
343 | WARN_ON_ONCE(!(mfmsr() & MSR_EE)); | |
d04c56f7 | 344 | return; |
9b81c021 | 345 | } |
ef2b343e | 346 | |
3282a3da | 347 | /* We need to hard disable to replay. */ |
9b81c021 | 348 | if (!(irq_happened & PACA_IRQ_HARD_DIS)) { |
3282a3da NP |
349 | if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) |
350 | WARN_ON_ONCE(!(mfmsr() & MSR_EE)); | |
7230c564 | 351 | __hard_irq_disable(); |
9b81c021 | 352 | } else { |
7c0482e3 BH |
353 | /* |
354 | * We should already be hard disabled here. We had bugs | |
355 | * where that wasn't the case so let's dbl check it and | |
356 | * warn if we are wrong. Only do that when IRQ tracing | |
357 | * is enabled as mfmsr() can be costly. | |
358 | */ | |
3282a3da NP |
359 | if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) { |
360 | if (WARN_ON_ONCE(mfmsr() & MSR_EE)) | |
361 | __hard_irq_disable(); | |
362 | } | |
363 | ||
364 | if (irq_happened == PACA_IRQ_HARD_DIS) { | |
365 | local_paca->irq_happened = 0; | |
366 | __hard_irq_enable(); | |
367 | return; | |
368 | } | |
9b81c021 | 369 | } |
7c0482e3 | 370 | |
f442d004 | 371 | irq_soft_mask_set(IRQS_ALL_DISABLED); |
ff967900 | 372 | trace_hardirqs_off(); |
e8775d4a | 373 | |
3282a3da NP |
374 | replay_soft_interrupts(); |
375 | local_paca->irq_happened = 0; | |
7230c564 | 376 | |
ff967900 | 377 | trace_hardirqs_on(); |
4e26bc4a | 378 | irq_soft_mask_set(IRQS_ENABLED); |
e1fa2e13 | 379 | __hard_irq_enable(); |
d04c56f7 | 380 | } |
df9ee292 | 381 | EXPORT_SYMBOL(arch_local_irq_restore); |
7230c564 BH |
382 | |
383 | /* | |
384 | * This is specifically called by assembly code to re-enable interrupts | |
385 | * if they are currently disabled. This is typically called before | |
386 | * schedule() or do_signal() when returning to userspace. We do it | |
387 | * in C to avoid the burden of dealing with lockdep etc... | |
56dfa7fa BH |
388 | * |
389 | * NOTE: This is called with interrupts hard disabled but not marked | |
390 | * as such in paca->irq_happened, so we need to resync this. | |
7230c564 | 391 | */ |
2d773aa4 | 392 | void notrace restore_interrupts(void) |
7230c564 | 393 | { |
56dfa7fa BH |
394 | if (irqs_disabled()) { |
395 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; | |
7230c564 | 396 | local_irq_enable(); |
56dfa7fa BH |
397 | } else |
398 | __hard_irq_enable(); | |
7230c564 BH |
399 | } |
400 | ||
be2cf20a BH |
401 | /* |
402 | * This is a helper to use when about to go into idle low-power | |
403 | * when the latter has the side effect of re-enabling interrupts | |
404 | * (such as calling H_CEDE under pHyp). | |
405 | * | |
406 | * You call this function with interrupts soft-disabled (this is | |
407 | * already the case when ppc_md.power_save is called). The function | |
408 | * will return whether to enter power save or just return. | |
409 | * | |
410 | * In the former case, it will have notified lockdep of interrupts | |
411 | * being re-enabled and generally sanitized the lazy irq state, | |
412 | * and in the latter case it will leave with interrupts hard | |
413 | * disabled and marked as such, so the local_irq_enable() call | |
0d2b7ea9 | 414 | * in arch_cpu_idle() will properly re-enable everything. |
be2cf20a BH |
415 | */ |
416 | bool prep_irq_for_idle(void) | |
417 | { | |
418 | /* | |
419 | * First we need to hard disable to ensure no interrupt | |
420 | * occurs before we effectively enter the low power state | |
421 | */ | |
2201f994 NP |
422 | __hard_irq_disable(); |
423 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; | |
be2cf20a BH |
424 | |
425 | /* | |
426 | * If anything happened while we were soft-disabled, | |
427 | * we return now and do not enter the low power state. | |
428 | */ | |
429 | if (lazy_irq_pending()) | |
430 | return false; | |
431 | ||
432 | /* Tell lockdep we are about to re-enable */ | |
433 | trace_hardirqs_on(); | |
434 | ||
435 | /* | |
436 | * Mark interrupts as soft-enabled and clear the | |
437 | * PACA_IRQ_HARD_DIS from the pending mask since we | |
438 | * are about to hard enable as well as a side effect | |
439 | * of entering the low power state. | |
440 | */ | |
441 | local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; | |
4e26bc4a | 442 | irq_soft_mask_set(IRQS_ENABLED); |
be2cf20a BH |
443 | |
444 | /* Tell the caller to enter the low power state */ | |
445 | return true; | |
446 | } | |
447 | ||
771d4304 | 448 | #ifdef CONFIG_PPC_BOOK3S |
2201f994 NP |
449 | /* |
450 | * This is for idle sequences that return with IRQs off, but the | |
451 | * idle state itself wakes on interrupt. Tell the irq tracer that | |
452 | * IRQs are enabled for the duration of idle so it does not get long | |
453 | * off times. Must be paired with fini_irq_for_idle_irqsoff. | |
454 | */ | |
455 | bool prep_irq_for_idle_irqsoff(void) | |
456 | { | |
457 | WARN_ON(!irqs_disabled()); | |
458 | ||
459 | /* | |
460 | * First we need to hard disable to ensure no interrupt | |
461 | * occurs before we effectively enter the low power state | |
462 | */ | |
463 | __hard_irq_disable(); | |
464 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; | |
465 | ||
466 | /* | |
467 | * If anything happened while we were soft-disabled, | |
468 | * we return now and do not enter the low power state. | |
469 | */ | |
470 | if (lazy_irq_pending()) | |
471 | return false; | |
472 | ||
473 | /* Tell lockdep we are about to re-enable */ | |
474 | trace_hardirqs_on(); | |
475 | ||
476 | return true; | |
477 | } | |
478 | ||
771d4304 NP |
479 | /* |
480 | * Take the SRR1 wakeup reason, index into this table to find the | |
481 | * appropriate irq_happened bit. | |
78adf6c2 NP |
482 | * |
483 | * Sytem reset exceptions taken in idle state also come through here, | |
484 | * but they are NMI interrupts so do not need to wait for IRQs to be | |
485 | * restored, and should be taken as early as practical. These are marked | |
486 | * with 0xff in the table. The Power ISA specifies 0100b as the system | |
487 | * reset interrupt reason. | |
771d4304 | 488 | */ |
78adf6c2 NP |
489 | #define IRQ_SYSTEM_RESET 0xff |
490 | ||
771d4304 NP |
491 | static const u8 srr1_to_lazyirq[0x10] = { |
492 | 0, 0, 0, | |
493 | PACA_IRQ_DBELL, | |
78adf6c2 | 494 | IRQ_SYSTEM_RESET, |
771d4304 NP |
495 | PACA_IRQ_DBELL, |
496 | PACA_IRQ_DEC, | |
497 | 0, | |
498 | PACA_IRQ_EE, | |
499 | PACA_IRQ_EE, | |
500 | PACA_IRQ_HMI, | |
501 | 0, 0, 0, 0, 0 }; | |
502 | ||
6de6638b | 503 | void replay_system_reset(void) |
78adf6c2 NP |
504 | { |
505 | struct pt_regs regs; | |
506 | ||
507 | ppc_save_regs(®s); | |
508 | regs.trap = 0x100; | |
509 | get_paca()->in_nmi = 1; | |
510 | system_reset_exception(®s); | |
511 | get_paca()->in_nmi = 0; | |
512 | } | |
6de6638b | 513 | EXPORT_SYMBOL_GPL(replay_system_reset); |
78adf6c2 | 514 | |
771d4304 NP |
515 | void irq_set_pending_from_srr1(unsigned long srr1) |
516 | { | |
517 | unsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18; | |
78adf6c2 NP |
518 | u8 reason = srr1_to_lazyirq[idx]; |
519 | ||
520 | /* | |
521 | * Take the system reset now, which is immediately after registers | |
522 | * are restored from idle. It's an NMI, so interrupts need not be | |
523 | * re-enabled before it is taken. | |
524 | */ | |
525 | if (unlikely(reason == IRQ_SYSTEM_RESET)) { | |
526 | replay_system_reset(); | |
527 | return; | |
528 | } | |
771d4304 | 529 | |
0c89649a NP |
530 | if (reason == PACA_IRQ_DBELL) { |
531 | /* | |
532 | * When doorbell triggers a system reset wakeup, the message | |
533 | * is not cleared, so if the doorbell interrupt is replayed | |
534 | * and the IPI handled, the doorbell interrupt would still | |
535 | * fire when EE is enabled. | |
536 | * | |
537 | * To avoid taking the superfluous doorbell interrupt, | |
538 | * execute a msgclr here before the interrupt is replayed. | |
539 | */ | |
540 | ppc_msgclr(PPC_DBELL_MSGTYPE); | |
541 | } | |
542 | ||
771d4304 NP |
543 | /* |
544 | * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0, | |
78adf6c2 NP |
545 | * so this can be called unconditionally with the SRR1 wake |
546 | * reason as returned by the idle code, which uses 0 to mean no | |
547 | * interrupt. | |
548 | * | |
549 | * If a future CPU was to designate this as an interrupt reason, | |
550 | * then a new index for no interrupt must be assigned. | |
771d4304 | 551 | */ |
78adf6c2 | 552 | local_paca->irq_happened |= reason; |
771d4304 NP |
553 | } |
554 | #endif /* CONFIG_PPC_BOOK3S */ | |
555 | ||
1d607bb3 BH |
556 | /* |
557 | * Force a replay of the external interrupt handler on this CPU. | |
558 | */ | |
559 | void force_external_irq_replay(void) | |
560 | { | |
561 | /* | |
562 | * This must only be called with interrupts soft-disabled, | |
563 | * the replay will happen when re-enabling. | |
564 | */ | |
565 | WARN_ON(!arch_irqs_disabled()); | |
566 | ||
ff6781fd NP |
567 | /* |
568 | * Interrupts must always be hard disabled before irq_happened is | |
569 | * modified (to prevent lost update in case of interrupt between | |
570 | * load and store). | |
571 | */ | |
572 | __hard_irq_disable(); | |
573 | local_paca->irq_happened |= PACA_IRQ_HARD_DIS; | |
574 | ||
1d607bb3 BH |
575 | /* Indicate in the PACA that we have an interrupt to replay */ |
576 | local_paca->irq_happened |= PACA_IRQ_EE; | |
577 | } | |
578 | ||
756e7104 | 579 | #endif /* CONFIG_PPC64 */ |
1da177e4 | 580 | |
433c9c67 | 581 | int arch_show_interrupts(struct seq_file *p, int prec) |
c86845ed AB |
582 | { |
583 | int j; | |
584 | ||
585 | #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT) | |
586 | if (tau_initialized) { | |
587 | seq_printf(p, "%*s: ", prec, "TAU"); | |
588 | for_each_online_cpu(j) | |
589 | seq_printf(p, "%10u ", tau_interrupts(j)); | |
590 | seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n"); | |
591 | } | |
592 | #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */ | |
593 | ||
89713ed1 AB |
594 | seq_printf(p, "%*s: ", prec, "LOC"); |
595 | for_each_online_cpu(j) | |
c041cfa2 | 596 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event); |
597 | seq_printf(p, " Local timer interrupts for timer event device\n"); | |
598 | ||
e360cd37 NP |
599 | seq_printf(p, "%*s: ", prec, "BCT"); |
600 | for_each_online_cpu(j) | |
601 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).broadcast_irqs_event); | |
602 | seq_printf(p, " Broadcast timer interrupts for timer event device\n"); | |
603 | ||
c041cfa2 | 604 | seq_printf(p, "%*s: ", prec, "LOC"); |
605 | for_each_online_cpu(j) | |
606 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others); | |
607 | seq_printf(p, " Local timer interrupts for others\n"); | |
89713ed1 | 608 | |
17081102 AB |
609 | seq_printf(p, "%*s: ", prec, "SPU"); |
610 | for_each_online_cpu(j) | |
611 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs); | |
612 | seq_printf(p, " Spurious interrupts\n"); | |
613 | ||
e8e813ed | 614 | seq_printf(p, "%*s: ", prec, "PMI"); |
89713ed1 AB |
615 | for_each_online_cpu(j) |
616 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs); | |
617 | seq_printf(p, " Performance monitoring interrupts\n"); | |
618 | ||
619 | seq_printf(p, "%*s: ", prec, "MCE"); | |
620 | for_each_online_cpu(j) | |
621 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions); | |
622 | seq_printf(p, " Machine check exceptions\n"); | |
623 | ||
0869b6fd MS |
624 | if (cpu_has_feature(CPU_FTR_HVMODE)) { |
625 | seq_printf(p, "%*s: ", prec, "HMI"); | |
626 | for_each_online_cpu(j) | |
627 | seq_printf(p, "%10u ", | |
628 | per_cpu(irq_stat, j).hmi_exceptions); | |
629 | seq_printf(p, " Hypervisor Maintenance Interrupts\n"); | |
630 | } | |
631 | ||
ca41ad43 NP |
632 | seq_printf(p, "%*s: ", prec, "NMI"); |
633 | for_each_online_cpu(j) | |
634 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).sreset_irqs); | |
635 | seq_printf(p, " System Reset interrupts\n"); | |
636 | ||
04019bf8 NP |
637 | #ifdef CONFIG_PPC_WATCHDOG |
638 | seq_printf(p, "%*s: ", prec, "WDG"); | |
639 | for_each_online_cpu(j) | |
640 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).soft_nmi_irqs); | |
641 | seq_printf(p, " Watchdog soft-NMI interrupts\n"); | |
642 | #endif | |
643 | ||
a6a058e5 IM |
644 | #ifdef CONFIG_PPC_DOORBELL |
645 | if (cpu_has_feature(CPU_FTR_DBELL)) { | |
646 | seq_printf(p, "%*s: ", prec, "DBL"); | |
647 | for_each_online_cpu(j) | |
648 | seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs); | |
649 | seq_printf(p, " Doorbell interrupts\n"); | |
650 | } | |
651 | #endif | |
652 | ||
c86845ed AB |
653 | return 0; |
654 | } | |
655 | ||
89713ed1 AB |
656 | /* |
657 | * /proc/stat helpers | |
658 | */ | |
659 | u64 arch_irq_stat_cpu(unsigned int cpu) | |
660 | { | |
c041cfa2 | 661 | u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event; |
89713ed1 | 662 | |
e360cd37 | 663 | sum += per_cpu(irq_stat, cpu).broadcast_irqs_event; |
89713ed1 AB |
664 | sum += per_cpu(irq_stat, cpu).pmu_irqs; |
665 | sum += per_cpu(irq_stat, cpu).mce_exceptions; | |
17081102 | 666 | sum += per_cpu(irq_stat, cpu).spurious_irqs; |
c041cfa2 | 667 | sum += per_cpu(irq_stat, cpu).timer_irqs_others; |
0869b6fd | 668 | sum += per_cpu(irq_stat, cpu).hmi_exceptions; |
ca41ad43 | 669 | sum += per_cpu(irq_stat, cpu).sreset_irqs; |
04019bf8 NP |
670 | #ifdef CONFIG_PPC_WATCHDOG |
671 | sum += per_cpu(irq_stat, cpu).soft_nmi_irqs; | |
672 | #endif | |
a6a058e5 IM |
673 | #ifdef CONFIG_PPC_DOORBELL |
674 | sum += per_cpu(irq_stat, cpu).doorbell_irqs; | |
675 | #endif | |
89713ed1 AB |
676 | |
677 | return sum; | |
678 | } | |
679 | ||
d7cb10d6 ME |
680 | static inline void check_stack_overflow(void) |
681 | { | |
d7cb10d6 ME |
682 | long sp; |
683 | ||
0dec6e1c CL |
684 | if (!IS_ENABLED(CONFIG_DEBUG_STACKOVERFLOW)) |
685 | return; | |
686 | ||
84ab1489 | 687 | sp = current_stack_pointer & (THREAD_SIZE - 1); |
d7cb10d6 ME |
688 | |
689 | /* check for stack overflow: is there less than 2KB free? */ | |
a7916a1d CL |
690 | if (unlikely(sp < 2048)) { |
691 | pr_err("do_IRQ: stack overflow: %ld\n", sp); | |
d7cb10d6 ME |
692 | dump_stack(); |
693 | } | |
d7cb10d6 ME |
694 | } |
695 | ||
0366a1c7 | 696 | void __do_irq(struct pt_regs *regs) |
1da177e4 | 697 | { |
0ebfff14 | 698 | unsigned int irq; |
1da177e4 | 699 | |
4b218e9b | 700 | irq_enter(); |
1da177e4 | 701 | |
e72bbbab LZ |
702 | trace_irq_entry(regs); |
703 | ||
7230c564 BH |
704 | /* |
705 | * Query the platform PIC for the interrupt & ack it. | |
706 | * | |
707 | * This will typically lower the interrupt line to the CPU | |
708 | */ | |
35a84c2f | 709 | irq = ppc_md.get_irq(); |
1da177e4 | 710 | |
0366a1c7 | 711 | /* We can hard enable interrupts now to allow perf interrupts */ |
7230c564 BH |
712 | may_hard_irq_enable(); |
713 | ||
714 | /* And finally process it */ | |
ef24ba70 | 715 | if (unlikely(!irq)) |
69111bac | 716 | __this_cpu_inc(irq_stat.spurious_irqs); |
a4e04c9f | 717 | else |
0edc2ca9 | 718 | generic_handle_irq(irq); |
e199500c | 719 | |
e72bbbab LZ |
720 | trace_irq_exit(regs); |
721 | ||
4b218e9b | 722 | irq_exit(); |
0366a1c7 BH |
723 | } |
724 | ||
725 | void do_IRQ(struct pt_regs *regs) | |
726 | { | |
727 | struct pt_regs *old_regs = set_irq_regs(regs); | |
d608898a | 728 | void *cursp, *irqsp, *sirqsp; |
0366a1c7 BH |
729 | |
730 | /* Switch to the irq stack to handle this */ | |
532d43a7 | 731 | cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1)); |
d608898a CL |
732 | irqsp = hardirq_ctx[raw_smp_processor_id()]; |
733 | sirqsp = softirq_ctx[raw_smp_processor_id()]; | |
0366a1c7 | 734 | |
099bc481 CL |
735 | check_stack_overflow(); |
736 | ||
0366a1c7 | 737 | /* Already there ? */ |
d608898a | 738 | if (unlikely(cursp == irqsp || cursp == sirqsp)) { |
0366a1c7 BH |
739 | __do_irq(regs); |
740 | set_irq_regs(old_regs); | |
741 | return; | |
742 | } | |
0366a1c7 | 743 | /* Switch stack and call */ |
d608898a | 744 | call_do_irq(regs, irqsp); |
0366a1c7 | 745 | |
7d12e780 | 746 | set_irq_regs(old_regs); |
e199500c | 747 | } |
1da177e4 | 748 | |
547db12f CL |
749 | static void *__init alloc_vm_stack(void) |
750 | { | |
cb0849a9 CH |
751 | return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP, |
752 | NUMA_NO_NODE, (void *)_RET_IP_); | |
547db12f CL |
753 | } |
754 | ||
755 | static void __init vmap_irqstack_init(void) | |
756 | { | |
757 | int i; | |
758 | ||
759 | for_each_possible_cpu(i) { | |
760 | softirq_ctx[i] = alloc_vm_stack(); | |
761 | hardirq_ctx[i] = alloc_vm_stack(); | |
762 | } | |
763 | } | |
764 | ||
765 | ||
1da177e4 LT |
766 | void __init init_IRQ(void) |
767 | { | |
547db12f CL |
768 | if (IS_ENABLED(CONFIG_VMAP_STACK)) |
769 | vmap_irqstack_init(); | |
770 | ||
70584578 SR |
771 | if (ppc_md.init_IRQ) |
772 | ppc_md.init_IRQ(); | |
1da177e4 LT |
773 | } |
774 | ||
bcf0b088 | 775 | #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
a7916a1d CL |
776 | void *critirq_ctx[NR_CPUS] __read_mostly; |
777 | void *dbgirq_ctx[NR_CPUS] __read_mostly; | |
778 | void *mcheckirq_ctx[NR_CPUS] __read_mostly; | |
bcf0b088 | 779 | #endif |
1da177e4 | 780 | |
a7916a1d CL |
781 | void *softirq_ctx[NR_CPUS] __read_mostly; |
782 | void *hardirq_ctx[NR_CPUS] __read_mostly; | |
1da177e4 | 783 | |
7d65f4a6 | 784 | void do_softirq_own_stack(void) |
c6622f63 | 785 | { |
d608898a | 786 | call_do_softirq(softirq_ctx[smp_processor_id()]); |
c6622f63 | 787 | } |
1da177e4 | 788 | |
35923f12 OJ |
789 | irq_hw_number_t virq_to_hw(unsigned int virq) |
790 | { | |
4bbdd45a GL |
791 | struct irq_data *irq_data = irq_get_irq_data(virq); |
792 | return WARN_ON(!irq_data) ? 0 : irq_data->hwirq; | |
35923f12 OJ |
793 | } |
794 | EXPORT_SYMBOL_GPL(virq_to_hw); | |
795 | ||
6ec36b58 SY |
796 | #ifdef CONFIG_SMP |
797 | int irq_choose_cpu(const struct cpumask *mask) | |
798 | { | |
799 | int cpuid; | |
800 | ||
2074b1d9 | 801 | if (cpumask_equal(mask, cpu_online_mask)) { |
6ec36b58 SY |
802 | static int irq_rover; |
803 | static DEFINE_RAW_SPINLOCK(irq_rover_lock); | |
804 | unsigned long flags; | |
805 | ||
806 | /* Round-robin distribution... */ | |
807 | do_round_robin: | |
808 | raw_spin_lock_irqsave(&irq_rover_lock, flags); | |
809 | ||
810 | irq_rover = cpumask_next(irq_rover, cpu_online_mask); | |
811 | if (irq_rover >= nr_cpu_ids) | |
812 | irq_rover = cpumask_first(cpu_online_mask); | |
813 | ||
814 | cpuid = irq_rover; | |
815 | ||
816 | raw_spin_unlock_irqrestore(&irq_rover_lock, flags); | |
817 | } else { | |
818 | cpuid = cpumask_first_and(mask, cpu_online_mask); | |
819 | if (cpuid >= nr_cpu_ids) | |
820 | goto do_round_robin; | |
821 | } | |
822 | ||
823 | return get_hard_smp_processor_id(cpuid); | |
824 | } | |
825 | #else | |
826 | int irq_choose_cpu(const struct cpumask *mask) | |
827 | { | |
828 | return hard_smp_processor_id(); | |
829 | } | |
830 | #endif | |
0ebfff14 | 831 | |
c6622f63 | 832 | #ifdef CONFIG_PPC64 |
1da177e4 LT |
833 | static int __init setup_noirqdistrib(char *str) |
834 | { | |
835 | distribute_irqs = 0; | |
836 | return 1; | |
837 | } | |
838 | ||
839 | __setup("noirqdistrib", setup_noirqdistrib); | |
756e7104 | 840 | #endif /* CONFIG_PPC64 */ |