projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 9994a338 PM |
1 | /* |
| 2 | * This file contains miscellaneous low-level functions. | |
| 3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
| 4 | * | |
| 5 | * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) | |
| 6 | * and Paul Mackerras. | |
| 7 | * | |
| 3d1229d6 ME |
8 | * kexec bits: |
| 9 | * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com> | |
| 10 | * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz | |
| 11 | * | |
| 9994a338 PM |
12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License | |
| 14 | * as published by the Free Software Foundation; either version | |
| 15 | * 2 of the License, or (at your option) any later version. | |
| 16 | * | |
| 17 | */ | |
| 18 | ||
| 9994a338 PM |
19 | #include <linux/sys.h> |
| 20 | #include <asm/unistd.h> | |
| 21 | #include <asm/errno.h> | |
| 22 | #include <asm/reg.h> | |
| 23 | #include <asm/page.h> | |
| 24 | #include <asm/cache.h> | |
| 25 | #include <asm/cputable.h> | |
| 26 | #include <asm/mmu.h> | |
| 27 | #include <asm/ppc_asm.h> | |
| 28 | #include <asm/thread_info.h> | |
| 29 | #include <asm/asm-offsets.h> | |
| 3d1229d6 ME |
30 | #include <asm/processor.h> |
| 31 | #include <asm/kexec.h> | |
| 9994a338 PM |
32 | |
| 33 | .text | |
| 34 | ||
| f2783c15 PM |
35 | /* |
| 36 | * This returns the high 64 bits of the product of two 64-bit numbers. | |
| 37 | */ | |
| 38 | _GLOBAL(mulhdu) | |
| 39 | cmpwi r6,0 | |
| 40 | cmpwi cr1,r3,0 | |
| 41 | mr r10,r4 | |
| 42 | mulhwu r4,r4,r5 | |
| 43 | beq 1f | |
| 44 | mulhwu r0,r10,r6 | |
| 45 | mullw r7,r10,r5 | |
| 46 | addc r7,r0,r7 | |
| 47 | addze r4,r4 | |
| 48 | 1: beqlr cr1 /* all done if high part of A is 0 */ | |
| 49 | mr r10,r3 | |
| 50 | mullw r9,r3,r5 | |
| 51 | mulhwu r3,r3,r5 | |
| 52 | beq 2f | |
| 53 | mullw r0,r10,r6 | |
| 54 | mulhwu r8,r10,r6 | |
| 55 | addc r7,r0,r7 | |
| 56 | adde r4,r4,r8 | |
| 57 | addze r3,r3 | |
| 58 | 2: addc r4,r4,r9 | |
| 59 | addze r3,r3 | |
| 60 | blr | |
| 61 | ||
| 9994a338 PM |
62 | /* |
| 63 | * sub_reloc_offset(x) returns x - reloc_offset(). | |
| 64 | */ | |
| 65 | _GLOBAL(sub_reloc_offset) | |
| 66 | mflr r0 | |
| 67 | bl 1f | |
| 68 | 1: mflr r5 | |
| 69 | lis r4,1b@ha | |
| 70 | addi r4,r4,1b@l | |
| 71 | subf r5,r4,r5 | |
| 72 | subf r3,r5,r3 | |
| 73 | mtlr r0 | |
| 74 | blr | |
| 75 | ||
| 76 | /* | |
| 77 | * reloc_got2 runs through the .got2 section adding an offset | |
| 78 | * to each entry. | |
| 79 | */ | |
| 80 | _GLOBAL(reloc_got2) | |
| 81 | mflr r11 | |
| 82 | lis r7,__got2_start@ha | |
| 83 | addi r7,r7,__got2_start@l | |
| 84 | lis r8,__got2_end@ha | |
| 85 | addi r8,r8,__got2_end@l | |
| 86 | subf r8,r7,r8 | |
| 87 | srwi. r8,r8,2 | |
| 88 | beqlr | |
| 89 | mtctr r8 | |
| 90 | bl 1f | |
| 91 | 1: mflr r0 | |
| 92 | lis r4,1b@ha | |
| 93 | addi r4,r4,1b@l | |
| 94 | subf r0,r4,r0 | |
| 95 | add r7,r0,r7 | |
| 96 | 2: lwz r0,0(r7) | |
| 97 | add r0,r0,r3 | |
| 98 | stw r0,0(r7) | |
| 99 | addi r7,r7,4 | |
| 100 | bdnz 2b | |
| 101 | mtlr r11 | |
| 102 | blr | |
| 103 | ||
| 9994a338 PM |
104 | /* |
| 105 | * call_setup_cpu - call the setup_cpu function for this cpu | |
| 106 | * r3 = data offset, r24 = cpu number | |
| 107 | * | |
| 108 | * Setup function is called with: | |
| 109 | * r3 = data offset | |
| 110 | * r4 = ptr to CPU spec (relocated) | |
| 111 | */ | |
| 112 | _GLOBAL(call_setup_cpu) | |
| 113 | addis r4,r3,cur_cpu_spec@ha | |
| 114 | addi r4,r4,cur_cpu_spec@l | |
| 115 | lwz r4,0(r4) | |
| 116 | add r4,r4,r3 | |
| 117 | lwz r5,CPU_SPEC_SETUP(r4) | |
| b26f100d | 118 | cmpwi 0,r5,0 |
| 9994a338 PM |
119 | add r5,r5,r3 |
| 120 | beqlr | |
| 121 | mtctr r5 | |
| 122 | bctr | |
| 123 | ||
| 124 | #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx) | |
| 125 | ||
| 126 | /* This gets called by via-pmu.c to switch the PLL selection | |
| 127 | * on 750fx CPU. This function should really be moved to some | |
| 128 | * other place (as most of the cpufreq code in via-pmu | |
| 129 | */ | |
| 130 | _GLOBAL(low_choose_750fx_pll) | |
| 131 | /* Clear MSR:EE */ | |
| 132 | mfmsr r7 | |
| 133 | rlwinm r0,r7,0,17,15 | |
| 134 | mtmsr r0 | |
| 135 | ||
| 136 | /* If switching to PLL1, disable HID0:BTIC */ | |
| 137 | cmplwi cr0,r3,0 | |
| 138 | beq 1f | |
| 139 | mfspr r5,SPRN_HID0 | |
| 140 | rlwinm r5,r5,0,27,25 | |
| 141 | sync | |
| 142 | mtspr SPRN_HID0,r5 | |
| 143 | isync | |
| 144 | sync | |
| 145 | ||
| 146 | 1: | |
| 147 | /* Calc new HID1 value */ | |
| 148 | mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */ | |
| 149 | rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */ | |
| 150 | rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */ | |
| 151 | or r4,r4,r5 | |
| 152 | mtspr SPRN_HID1,r4 | |
| 153 | ||
| 154 | /* Store new HID1 image */ | |
| 155 | rlwinm r6,r1,0,0,18 | |
| 156 | lwz r6,TI_CPU(r6) | |
| 157 | slwi r6,r6,2 | |
| 158 | addis r6,r6,nap_save_hid1@ha | |
| 159 | stw r4,nap_save_hid1@l(r6) | |
| 160 | ||
| 161 | /* If switching to PLL0, enable HID0:BTIC */ | |
| 162 | cmplwi cr0,r3,0 | |
| 163 | bne 1f | |
| 164 | mfspr r5,SPRN_HID0 | |
| 165 | ori r5,r5,HID0_BTIC | |
| 166 | sync | |
| 167 | mtspr SPRN_HID0,r5 | |
| 168 | isync | |
| 169 | sync | |
| 170 | ||
| 171 | 1: | |
| 172 | /* Return */ | |
| 173 | mtmsr r7 | |
| 174 | blr | |
| 175 | ||
| 176 | _GLOBAL(low_choose_7447a_dfs) | |
| 177 | /* Clear MSR:EE */ | |
| 178 | mfmsr r7 | |
| 179 | rlwinm r0,r7,0,17,15 | |
| 180 | mtmsr r0 | |
| 181 | ||
| 182 | /* Calc new HID1 value */ | |
| 183 | mfspr r4,SPRN_HID1 | |
| 184 | insrwi r4,r3,1,9 /* insert parameter into bit 9 */ | |
| 185 | sync | |
| 186 | mtspr SPRN_HID1,r4 | |
| 187 | sync | |
| 188 | isync | |
| 189 | ||
| 190 | /* Return */ | |
| 191 | mtmsr r7 | |
| 192 | blr | |
| 193 | ||
| 194 | #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */ | |
| 195 | ||
| 196 | /* | |
| 197 | * complement mask on the msr then "or" some values on. | |
| 198 | * _nmask_and_or_msr(nmask, value_to_or) | |
| 199 | */ | |
| 200 | _GLOBAL(_nmask_and_or_msr) | |
| 201 | mfmsr r0 /* Get current msr */ | |
| 202 | andc r0,r0,r3 /* And off the bits set in r3 (first parm) */ | |
| 203 | or r0,r0,r4 /* Or on the bits in r4 (second parm) */ | |
| 204 | SYNC /* Some chip revs have problems here... */ | |
| 205 | mtmsr r0 /* Update machine state */ | |
| 206 | isync | |
| 207 | blr /* Done */ | |
| 208 | ||
| 9dae8afd BH |
209 | #ifdef CONFIG_40x |
| 210 | ||
| 211 | /* | |
| 212 | * Do an IO access in real mode | |
| 213 | */ | |
| 214 | _GLOBAL(real_readb) | |
| 215 | mfmsr r7 | |
| 216 | ori r0,r7,MSR_DR | |
| 217 | xori r0,r0,MSR_DR | |
| 218 | sync | |
| 219 | mtmsr r0 | |
| 220 | sync | |
| 221 | isync | |
| 222 | lbz r3,0(r3) | |
| 223 | sync | |
| 224 | mtmsr r7 | |
| 225 | sync | |
| 226 | isync | |
| 227 | blr | |
| 228 | ||
| 229 | /* | |
| 230 | * Do an IO access in real mode | |
| 231 | */ | |
| 232 | _GLOBAL(real_writeb) | |
| 233 | mfmsr r7 | |
| 234 | ori r0,r7,MSR_DR | |
| 235 | xori r0,r0,MSR_DR | |
| 236 | sync | |
| 237 | mtmsr r0 | |
| 238 | sync | |
| 239 | isync | |
| 240 | stb r3,0(r4) | |
| 241 | sync | |
| 242 | mtmsr r7 | |
| 243 | sync | |
| 244 | isync | |
| 245 | blr | |
| 246 | ||
| 247 | #endif /* CONFIG_40x */ | |
| 9994a338 PM |
248 | |
| 249 | /* | |
| 250 | * Flush MMU TLB | |
| 251 | */ | |
| 252 | _GLOBAL(_tlbia) | |
| 253 | #if defined(CONFIG_40x) | |
| 254 | sync /* Flush to memory before changing mapping */ | |
| 255 | tlbia | |
| 256 | isync /* Flush shadow TLB */ | |
| 257 | #elif defined(CONFIG_44x) | |
| 258 | li r3,0 | |
| 259 | sync | |
| 260 | ||
| 261 | /* Load high watermark */ | |
| 262 | lis r4,tlb_44x_hwater@ha | |
| 263 | lwz r5,tlb_44x_hwater@l(r4) | |
| 264 | ||
| 265 | 1: tlbwe r3,r3,PPC44x_TLB_PAGEID | |
| 266 | addi r3,r3,1 | |
| 267 | cmpw 0,r3,r5 | |
| 268 | ble 1b | |
| 269 | ||
| 270 | isync | |
| 271 | #elif defined(CONFIG_FSL_BOOKE) | |
| 272 | /* Invalidate all entries in TLB0 */ | |
| 273 | li r3, 0x04 | |
| 274 | tlbivax 0,3 | |
| 275 | /* Invalidate all entries in TLB1 */ | |
| 276 | li r3, 0x0c | |
| 277 | tlbivax 0,3 | |
| 278 | /* Invalidate all entries in TLB2 */ | |
| 279 | li r3, 0x14 | |
| 280 | tlbivax 0,3 | |
| 281 | /* Invalidate all entries in TLB3 */ | |
| 282 | li r3, 0x1c | |
| 283 | tlbivax 0,3 | |
| 284 | msync | |
| 285 | #ifdef CONFIG_SMP | |
| 286 | tlbsync | |
| 287 | #endif /* CONFIG_SMP */ | |
| 288 | #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ | |
| 289 | #if defined(CONFIG_SMP) | |
| 290 | rlwinm r8,r1,0,0,18 | |
| 291 | lwz r8,TI_CPU(r8) | |
| 292 | oris r8,r8,10 | |
| 293 | mfmsr r10 | |
| 294 | SYNC | |
| 295 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
| 296 | rlwinm r0,r0,0,28,26 /* clear DR */ | |
| 297 | mtmsr r0 | |
| 298 | SYNC_601 | |
| 299 | isync | |
| 300 | lis r9,mmu_hash_lock@h | |
| 301 | ori r9,r9,mmu_hash_lock@l | |
| 302 | tophys(r9,r9) | |
| 303 | 10: lwarx r7,0,r9 | |
| 304 | cmpwi 0,r7,0 | |
| 305 | bne- 10b | |
| 306 | stwcx. r8,0,r9 | |
| 307 | bne- 10b | |
| 308 | sync | |
| 309 | tlbia | |
| 310 | sync | |
| 311 | TLBSYNC | |
| 312 | li r0,0 | |
| 313 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
| 314 | mtmsr r10 | |
| 315 | SYNC_601 | |
| 316 | isync | |
| 317 | #else /* CONFIG_SMP */ | |
| 318 | sync | |
| 319 | tlbia | |
| 320 | sync | |
| 321 | #endif /* CONFIG_SMP */ | |
| 322 | #endif /* ! defined(CONFIG_40x) */ | |
| 323 | blr | |
| 324 | ||
| 325 | /* | |
| 326 | * Flush MMU TLB for a particular address | |
| 327 | */ | |
| 328 | _GLOBAL(_tlbie) | |
| 329 | #if defined(CONFIG_40x) | |
| e701d269 BH |
330 | /* We run the search with interrupts disabled because we have to change |
| 331 | * the PID and I don't want to preempt when that happens. | |
| 332 | */ | |
| 333 | mfmsr r5 | |
| 334 | mfspr r6,SPRN_PID | |
| 335 | wrteei 0 | |
| 336 | mtspr SPRN_PID,r4 | |
| 9994a338 | 337 | tlbsx. r3, 0, r3 |
| e701d269 BH |
338 | mtspr SPRN_PID,r6 |
| 339 | wrtee r5 | |
| 9994a338 PM |
340 | bne 10f |
| 341 | sync | |
| 342 | /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear. | |
| 343 | * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate | |
| 344 | * the TLB entry. */ | |
| 345 | tlbwe r3, r3, TLB_TAG | |
| 346 | isync | |
| 347 | 10: | |
| e701d269 | 348 | |
| 9994a338 | 349 | #elif defined(CONFIG_44x) |
| e701d269 BH |
350 | mfspr r5,SPRN_MMUCR |
| 351 | rlwimi r5,r4,0,24,31 /* Set TID */ | |
| 9994a338 | 352 | |
| aa1cf632 DG |
353 | /* We have to run the search with interrupts disabled, even critical |
| 354 | * and debug interrupts (in fact the only critical exceptions we have | |
| 355 | * are debug and machine check). Otherwise an interrupt which causes | |
| 356 | * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ | |
| e701d269 | 357 | mfmsr r4 |
| aa1cf632 DG |
358 | lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha |
| 359 | addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l | |
| e701d269 | 360 | andc r6,r4,r6 |
| aa1cf632 | 361 | mtmsr r6 |
| e701d269 | 362 | mtspr SPRN_MMUCR,r5 |
| 9994a338 | 363 | tlbsx. r3, 0, r3 |
| e701d269 | 364 | mtmsr r4 |
| 9994a338 PM |
365 | bne 10f |
| 366 | sync | |
| 367 | /* There are only 64 TLB entries, so r3 < 64, | |
| 368 | * which means bit 22, is clear. Since 22 is | |
| 369 | * the V bit in the TLB_PAGEID, loading this | |
| 370 | * value will invalidate the TLB entry. | |
| 371 | */ | |
| 372 | tlbwe r3, r3, PPC44x_TLB_PAGEID | |
| 373 | isync | |
| 374 | 10: | |
| 375 | #elif defined(CONFIG_FSL_BOOKE) | |
| 376 | rlwinm r4, r3, 0, 0, 19 | |
| 377 | ori r5, r4, 0x08 /* TLBSEL = 1 */ | |
| 378 | ori r6, r4, 0x10 /* TLBSEL = 2 */ | |
| 379 | ori r7, r4, 0x18 /* TLBSEL = 3 */ | |
| 380 | tlbivax 0, r4 | |
| 381 | tlbivax 0, r5 | |
| 382 | tlbivax 0, r6 | |
| 383 | tlbivax 0, r7 | |
| 384 | msync | |
| 385 | #if defined(CONFIG_SMP) | |
| 386 | tlbsync | |
| 387 | #endif /* CONFIG_SMP */ | |
| 388 | #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */ | |
| 389 | #if defined(CONFIG_SMP) | |
| 390 | rlwinm r8,r1,0,0,18 | |
| 391 | lwz r8,TI_CPU(r8) | |
| 392 | oris r8,r8,11 | |
| 393 | mfmsr r10 | |
| 394 | SYNC | |
| 395 | rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */ | |
| 396 | rlwinm r0,r0,0,28,26 /* clear DR */ | |
| 397 | mtmsr r0 | |
| 398 | SYNC_601 | |
| 399 | isync | |
| 400 | lis r9,mmu_hash_lock@h | |
| 401 | ori r9,r9,mmu_hash_lock@l | |
| 402 | tophys(r9,r9) | |
| 403 | 10: lwarx r7,0,r9 | |
| 404 | cmpwi 0,r7,0 | |
| 405 | bne- 10b | |
| 406 | stwcx. r8,0,r9 | |
| 407 | bne- 10b | |
| 408 | eieio | |
| 409 | tlbie r3 | |
| 410 | sync | |
| 411 | TLBSYNC | |
| 412 | li r0,0 | |
| 413 | stw r0,0(r9) /* clear mmu_hash_lock */ | |
| 414 | mtmsr r10 | |
| 415 | SYNC_601 | |
| 416 | isync | |
| 417 | #else /* CONFIG_SMP */ | |
| 418 | tlbie r3 | |
| 419 | sync | |
| 420 | #endif /* CONFIG_SMP */ | |
| 421 | #endif /* ! CONFIG_40x */ | |
| 422 | blr | |
| 423 | ||
| 424 | /* | |
| 425 | * Flush instruction cache. | |
| 426 | * This is a no-op on the 601. | |
| 427 | */ | |
| 428 | _GLOBAL(flush_instruction_cache) | |
| 429 | #if defined(CONFIG_8xx) | |
| 430 | isync | |
| 431 | lis r5, IDC_INVALL@h | |
| 432 | mtspr SPRN_IC_CST, r5 | |
| 433 | #elif defined(CONFIG_4xx) | |
| 434 | #ifdef CONFIG_403GCX | |
| 435 | li r3, 512 | |
| 436 | mtctr r3 | |
| 437 | lis r4, KERNELBASE@h | |
| 438 | 1: iccci 0, r4 | |
| 439 | addi r4, r4, 16 | |
| 440 | bdnz 1b | |
| 441 | #else | |
| 442 | lis r3, KERNELBASE@h | |
| 443 | iccci 0,r3 | |
| 444 | #endif | |
| 445 | #elif CONFIG_FSL_BOOKE | |
| 446 | BEGIN_FTR_SECTION | |
| 447 | mfspr r3,SPRN_L1CSR0 | |
| 448 | ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC | |
| 449 | /* msync; isync recommended here */ | |
| 450 | mtspr SPRN_L1CSR0,r3 | |
| 451 | isync | |
| 452 | blr | |
| 4508dc21 | 453 | END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) |
| 9994a338 PM |
454 | mfspr r3,SPRN_L1CSR1 |
| 455 | ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR | |
| 456 | mtspr SPRN_L1CSR1,r3 | |
| 457 | #else | |
| 458 | mfspr r3,SPRN_PVR | |
| 459 | rlwinm r3,r3,16,16,31 | |
| 460 | cmpwi 0,r3,1 | |
| 461 | beqlr /* for 601, do nothing */ | |
| 462 | /* 603/604 processor - use invalidate-all bit in HID0 */ | |
| 463 | mfspr r3,SPRN_HID0 | |
| 464 | ori r3,r3,HID0_ICFI | |
| 465 | mtspr SPRN_HID0,r3 | |
| 466 | #endif /* CONFIG_8xx/4xx */ | |
| 467 | isync | |
| 468 | blr | |
| 469 | ||
| 470 | /* | |
| 471 | * Write any modified data cache blocks out to memory | |
| 472 | * and invalidate the corresponding instruction cache blocks. | |
| 473 | * This is a no-op on the 601. | |
| 474 | * | |
| 475 | * flush_icache_range(unsigned long start, unsigned long stop) | |
| 476 | */ | |
| 26ef5c09 | 477 | _GLOBAL(__flush_icache_range) |
| 9994a338 PM |
478 | BEGIN_FTR_SECTION |
| 479 | blr /* for 601, do nothing */ | |
| 4508dc21 | 480 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) |
| 7dffb720 | 481 | li r5,L1_CACHE_BYTES-1 |
| 9994a338 PM |
482 | andc r3,r3,r5 |
| 483 | subf r4,r3,r4 | |
| 484 | add r4,r4,r5 | |
| 7dffb720 | 485 | srwi. r4,r4,L1_CACHE_SHIFT |
| 9994a338 PM |
486 | beqlr |
| 487 | mtctr r4 | |
| 488 | mr r6,r3 | |
| 489 | 1: dcbst 0,r3 | |
| 7dffb720 | 490 | addi r3,r3,L1_CACHE_BYTES |
| 9994a338 PM |
491 | bdnz 1b |
| 492 | sync /* wait for dcbst's to get to ram */ | |
| 493 | mtctr r4 | |
| 494 | 2: icbi 0,r6 | |
| 7dffb720 | 495 | addi r6,r6,L1_CACHE_BYTES |
| 9994a338 PM |
496 | bdnz 2b |
| 497 | sync /* additional sync needed on g4 */ | |
| 498 | isync | |
| 499 | blr | |
| 500 | /* | |
| 501 | * Write any modified data cache blocks out to memory. | |
| 502 | * Does not invalidate the corresponding cache lines (especially for | |
| 503 | * any corresponding instruction cache). | |
| 504 | * | |
| 505 | * clean_dcache_range(unsigned long start, unsigned long stop) | |
| 506 | */ | |
| 507 | _GLOBAL(clean_dcache_range) | |
| 7dffb720 | 508 | li r5,L1_CACHE_BYTES-1 |
| 9994a338 PM |
509 | andc r3,r3,r5 |
| 510 | subf r4,r3,r4 | |
| 511 | add r4,r4,r5 | |
| 7dffb720 | 512 | srwi. r4,r4,L1_CACHE_SHIFT |
| 9994a338 PM |
513 | beqlr |
| 514 | mtctr r4 | |
| 515 | ||
| 516 | 1: dcbst 0,r3 | |
| 7dffb720 | 517 | addi r3,r3,L1_CACHE_BYTES |
| 9994a338 PM |
518 | bdnz 1b |
| 519 | sync /* wait for dcbst's to get to ram */ | |
| 520 | blr | |
| 521 | ||
| 522 | /* | |
| 523 | * Write any modified data cache blocks out to memory and invalidate them. | |
| 524 | * Does not invalidate the corresponding instruction cache blocks. | |
| 525 | * | |
| 526 | * flush_dcache_range(unsigned long start, unsigned long stop) | |
| 527 | */ | |
| 528 | _GLOBAL(flush_dcache_range) | |
| 7dffb720 | 529 | li r5,L1_CACHE_BYTES-1 |
| 9994a338 PM |
530 | andc r3,r3,r5 |
| 531 | subf r4,r3,r4 | |
| 532 | add r4,r4,r5 | |
| 7dffb720 | 533 | srwi. r4,r4,L1_CACHE_SHIFT |
| 9994a338 PM |
534 | beqlr |
| 535 | mtctr r4 | |
| 536 | ||
| 537 | 1: dcbf 0,r3 | |
| 7dffb720 | 538 | addi r3,r3,L1_CACHE_BYTES |
| 9994a338 PM |
539 | bdnz 1b |
| 540 | sync /* wait for dcbst's to get to ram */ | |
| 541 | blr | |
| 542 | ||
| 543 | /* | |
| 544 | * Like above, but invalidate the D-cache. This is used by the 8xx | |
| 545 | * to invalidate the cache so the PPC core doesn't get stale data | |
| 546 | * from the CPM (no cache snooping here :-). | |
| 547 | * | |
| 548 | * invalidate_dcache_range(unsigned long start, unsigned long stop) | |
| 549 | */ | |
| 550 | _GLOBAL(invalidate_dcache_range) | |
| 7dffb720 | 551 | li r5,L1_CACHE_BYTES-1 |
| 9994a338 PM |
552 | andc r3,r3,r5 |
| 553 | subf r4,r3,r4 | |
| 554 | add r4,r4,r5 | |
| 7dffb720 | 555 | srwi. r4,r4,L1_CACHE_SHIFT |
| 9994a338 PM |
556 | beqlr |
| 557 | mtctr r4 | |
| 558 | ||
| 559 | 1: dcbi 0,r3 | |
| 7dffb720 | 560 | addi r3,r3,L1_CACHE_BYTES |
| 9994a338 PM |
561 | bdnz 1b |
| 562 | sync /* wait for dcbi's to get to ram */ | |
| 563 | blr | |
| 564 | ||
| 9994a338 PM |
565 | /* |
| 566 | * Flush a particular page from the data cache to RAM. | |
| 567 | * Note: this is necessary because the instruction cache does *not* | |
| 568 | * snoop from the data cache. | |
| 569 | * This is a no-op on the 601 which has a unified cache. | |
| 570 | * | |
| 571 | * void __flush_dcache_icache(void *page) | |
| 572 | */ | |
| 573 | _GLOBAL(__flush_dcache_icache) | |
| 574 | BEGIN_FTR_SECTION | |
| 4508dc21 DG |
575 | blr |
| 576 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) | |
| 9994a338 | 577 | rlwinm r3,r3,0,0,19 /* Get page base address */ |
| 7dffb720 | 578 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ |
| 9994a338 PM |
579 | mtctr r4 |
| 580 | mr r6,r3 | |
| 581 | 0: dcbst 0,r3 /* Write line to ram */ | |
| 7dffb720 | 582 | addi r3,r3,L1_CACHE_BYTES |
| 9994a338 PM |
583 | bdnz 0b |
| 584 | sync | |
| b98ac05d BH |
585 | #ifndef CONFIG_44x |
| 586 | /* We don't flush the icache on 44x. Those have a virtual icache | |
| 587 | * and we don't have access to the virtual address here (it's | |
| 588 | * not the page vaddr but where it's mapped in user space). The | |
| 589 | * flushing of the icache on these is handled elsewhere, when | |
| 590 | * a change in the address space occurs, before returning to | |
| 591 | * user space | |
| 592 | */ | |
| 9994a338 PM |
593 | mtctr r4 |
| 594 | 1: icbi 0,r6 | |
| 7dffb720 | 595 | addi r6,r6,L1_CACHE_BYTES |
| 9994a338 PM |
596 | bdnz 1b |
| 597 | sync | |
| 598 | isync | |
| b98ac05d | 599 | #endif /* CONFIG_44x */ |
| 9994a338 PM |
600 | blr |
| 601 | ||
| 602 | /* | |
| 603 | * Flush a particular page from the data cache to RAM, identified | |
| 604 | * by its physical address. We turn off the MMU so we can just use | |
| 605 | * the physical address (this may be a highmem page without a kernel | |
| 606 | * mapping). | |
| 607 | * | |
| 608 | * void __flush_dcache_icache_phys(unsigned long physaddr) | |
| 609 | */ | |
| 610 | _GLOBAL(__flush_dcache_icache_phys) | |
| 611 | BEGIN_FTR_SECTION | |
| 612 | blr /* for 601, do nothing */ | |
| 4508dc21 | 613 | END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) |
| 9994a338 PM |
614 | mfmsr r10 |
| 615 | rlwinm r0,r10,0,28,26 /* clear DR */ | |
| 616 | mtmsr r0 | |
| 617 | isync | |
| 618 | rlwinm r3,r3,0,0,19 /* Get page base address */ | |
| 7dffb720 | 619 | li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */ |
| 9994a338 PM |
620 | mtctr r4 |
| 621 | mr r6,r3 | |
| 622 | 0: dcbst 0,r3 /* Write line to ram */ | |
| 7dffb720 | 623 | addi r3,r3,L1_CACHE_BYTES |
| 9994a338 PM |
624 | bdnz 0b |
| 625 | sync | |
| 626 | mtctr r4 | |
| 627 | 1: icbi 0,r6 | |
| 7dffb720 | 628 | addi r6,r6,L1_CACHE_BYTES |
| 9994a338 PM |
629 | bdnz 1b |
| 630 | sync | |
| 631 | mtmsr r10 /* restore DR */ | |
| 632 | isync | |
| 633 | blr | |
| 634 | ||
| 635 | /* | |
| 636 | * Clear pages using the dcbz instruction, which doesn't cause any | |
| 637 | * memory traffic (except to write out any cache lines which get | |
| 638 | * displaced). This only works on cacheable memory. | |
| 639 | * | |
| 640 | * void clear_pages(void *page, int order) ; | |
| 641 | */ | |
| 642 | _GLOBAL(clear_pages) | |
| 7dffb720 | 643 | li r0,4096/L1_CACHE_BYTES |
| 9994a338 PM |
644 | slw r0,r0,r4 |
| 645 | mtctr r0 | |
| 646 | #ifdef CONFIG_8xx | |
| 647 | li r4, 0 | |
| 648 | 1: stw r4, 0(r3) | |
| 649 | stw r4, 4(r3) | |
| 650 | stw r4, 8(r3) | |
| 651 | stw r4, 12(r3) | |
| 652 | #else | |
| 653 | 1: dcbz 0,r3 | |
| 654 | #endif | |
| 7dffb720 | 655 | addi r3,r3,L1_CACHE_BYTES |
| 9994a338 PM |
656 | bdnz 1b |
| 657 | blr | |
| 658 | ||
| 659 | /* | |
| 660 | * Copy a whole page. We use the dcbz instruction on the destination | |
| 661 | * to reduce memory traffic (it eliminates the unnecessary reads of | |
| 662 | * the destination into cache). This requires that the destination | |
| 663 | * is cacheable. | |
| 664 | */ | |
| 665 | #define COPY_16_BYTES \ | |
| 666 | lwz r6,4(r4); \ | |
| 667 | lwz r7,8(r4); \ | |
| 668 | lwz r8,12(r4); \ | |
| 669 | lwzu r9,16(r4); \ | |
| 670 | stw r6,4(r3); \ | |
| 671 | stw r7,8(r3); \ | |
| 672 | stw r8,12(r3); \ | |
| 673 | stwu r9,16(r3) | |
| 674 | ||
| 675 | _GLOBAL(copy_page) | |
| 676 | addi r3,r3,-4 | |
| 677 | addi r4,r4,-4 | |
| 678 | ||
| 679 | #ifdef CONFIG_8xx | |
| 680 | /* don't use prefetch on 8xx */ | |
| 7dffb720 | 681 | li r0,4096/L1_CACHE_BYTES |
| 9994a338 PM |
682 | mtctr r0 |
| 683 | 1: COPY_16_BYTES | |
| 684 | bdnz 1b | |
| 685 | blr | |
| 686 | ||
| 687 | #else /* not 8xx, we can prefetch */ | |
| 688 | li r5,4 | |
| 689 | ||
| 690 | #if MAX_COPY_PREFETCH > 1 | |
| 691 | li r0,MAX_COPY_PREFETCH | |
| 692 | li r11,4 | |
| 693 | mtctr r0 | |
| 694 | 11: dcbt r11,r4 | |
| 7dffb720 | 695 | addi r11,r11,L1_CACHE_BYTES |
| 9994a338 PM |
696 | bdnz 11b |
| 697 | #else /* MAX_COPY_PREFETCH == 1 */ | |
| 698 | dcbt r5,r4 | |
| 7dffb720 | 699 | li r11,L1_CACHE_BYTES+4 |
| 9994a338 | 700 | #endif /* MAX_COPY_PREFETCH */ |
| 7dffb720 | 701 | li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH |
| 9994a338 PM |
702 | crclr 4*cr0+eq |
| 703 | 2: | |
| 704 | mtctr r0 | |
| 705 | 1: | |
| 706 | dcbt r11,r4 | |
| 707 | dcbz r5,r3 | |
| 708 | COPY_16_BYTES | |
| 7dffb720 | 709 | #if L1_CACHE_BYTES >= 32 |
| 9994a338 | 710 | COPY_16_BYTES |
| 7dffb720 | 711 | #if L1_CACHE_BYTES >= 64 |
| 9994a338 PM |
712 | COPY_16_BYTES |
| 713 | COPY_16_BYTES | |
| 7dffb720 | 714 | #if L1_CACHE_BYTES >= 128 |
| 9994a338 PM |
715 | COPY_16_BYTES |
| 716 | COPY_16_BYTES | |
| 717 | COPY_16_BYTES | |
| 718 | COPY_16_BYTES | |
| 719 | #endif | |
| 720 | #endif | |
| 721 | #endif | |
| 722 | bdnz 1b | |
| 723 | beqlr | |
| 724 | crnot 4*cr0+eq,4*cr0+eq | |
| 725 | li r0,MAX_COPY_PREFETCH | |
| 726 | li r11,4 | |
| 727 | b 2b | |
| 728 | #endif /* CONFIG_8xx */ | |
| 729 | ||
| 730 | /* | |
| 731 | * void atomic_clear_mask(atomic_t mask, atomic_t *addr) | |
| 732 | * void atomic_set_mask(atomic_t mask, atomic_t *addr); | |
| 733 | */ | |
| 734 | _GLOBAL(atomic_clear_mask) | |
| 735 | 10: lwarx r5,0,r4 | |
| 736 | andc r5,r5,r3 | |
| 737 | PPC405_ERR77(0,r4) | |
| 738 | stwcx. r5,0,r4 | |
| 739 | bne- 10b | |
| 740 | blr | |
| 741 | _GLOBAL(atomic_set_mask) | |
| 742 | 10: lwarx r5,0,r4 | |
| 743 | or r5,r5,r3 | |
| 744 | PPC405_ERR77(0,r4) | |
| 745 | stwcx. r5,0,r4 | |
| 746 | bne- 10b | |
| 747 | blr | |
| 748 | ||
| 9994a338 PM |
749 | /* |
| 750 | * Extended precision shifts. | |
| 751 | * | |
| 752 | * Updated to be valid for shift counts from 0 to 63 inclusive. | |
| 753 | * -- Gabriel | |
| 754 | * | |
| 755 | * R3/R4 has 64 bit value | |
| 756 | * R5 has shift count | |
| 757 | * result in R3/R4 | |
| 758 | * | |
| 759 | * ashrdi3: arithmetic right shift (sign propagation) | |
| 760 | * lshrdi3: logical right shift | |
| 761 | * ashldi3: left shift | |
| 762 | */ | |
| 763 | _GLOBAL(__ashrdi3) | |
| 764 | subfic r6,r5,32 | |
| 765 | srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count | |
| 766 | addi r7,r5,32 # could be xori, or addi with -32 | |
| 767 | slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) | |
| 768 | rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0 | |
| 769 | sraw r7,r3,r7 # t2 = MSW >> (count-32) | |
| 770 | or r4,r4,r6 # LSW |= t1 | |
| 771 | slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2 | |
| 772 | sraw r3,r3,r5 # MSW = MSW >> count | |
| 773 | or r4,r4,r7 # LSW |= t2 | |
| 774 | blr | |
| 775 | ||
| 776 | _GLOBAL(__ashldi3) | |
| 777 | subfic r6,r5,32 | |
| 778 | slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count | |
| 779 | addi r7,r5,32 # could be xori, or addi with -32 | |
| 780 | srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count) | |
| 781 | slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32) | |
| 782 | or r3,r3,r6 # MSW |= t1 | |
| 783 | slw r4,r4,r5 # LSW = LSW << count | |
| 784 | or r3,r3,r7 # MSW |= t2 | |
| 785 | blr | |
| 786 | ||
| 787 | _GLOBAL(__lshrdi3) | |
| 788 | subfic r6,r5,32 | |
| 789 | srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count | |
| 790 | addi r7,r5,32 # could be xori, or addi with -32 | |
| 791 | slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count) | |
| 792 | srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32) | |
| 793 | or r4,r4,r6 # LSW |= t1 | |
| 794 | srw r3,r3,r5 # MSW = MSW >> count | |
| 795 | or r4,r4,r7 # LSW |= t2 | |
| 796 | blr | |
| 797 | ||
| 798 | _GLOBAL(abs) | |
| 799 | srawi r4,r3,31 | |
| 800 | xor r3,r3,r4 | |
| 801 | sub r3,r3,r4 | |
| 802 | blr | |
| 803 | ||
| 9994a338 PM |
804 | /* |
| 805 | * Create a kernel thread | |
| 806 | * kernel_thread(fn, arg, flags) | |
| 807 | */ | |
| 808 | _GLOBAL(kernel_thread) | |
| 809 | stwu r1,-16(r1) | |
| 810 | stw r30,8(r1) | |
| 811 | stw r31,12(r1) | |
| 812 | mr r30,r3 /* function */ | |
| 813 | mr r31,r4 /* argument */ | |
| 814 | ori r3,r5,CLONE_VM /* flags */ | |
| 815 | oris r3,r3,CLONE_UNTRACED>>16 | |
| 816 | li r4,0 /* new sp (unused) */ | |
| 817 | li r0,__NR_clone | |
| 818 | sc | |
| 819 | cmpwi 0,r3,0 /* parent or child? */ | |
| 820 | bne 1f /* return if parent */ | |
| 821 | li r0,0 /* make top-level stack frame */ | |
| 822 | stwu r0,-16(r1) | |
| 823 | mtlr r30 /* fn addr in lr */ | |
| 824 | mr r3,r31 /* load arg and call fn */ | |
| 825 | PPC440EP_ERR42 | |
| 826 | blrl | |
| 827 | li r0,__NR_exit /* exit if function returns */ | |
| 828 | li r3,0 | |
| 829 | sc | |
| 830 | 1: lwz r30,8(r1) | |
| 831 | lwz r31,12(r1) | |
| 832 | addi r1,r1,16 | |
| 833 | blr | |
| 834 | ||
| 9994a338 PM |
835 | /* |
| 836 | * This routine is just here to keep GCC happy - sigh... | |
| 837 | */ | |
| 838 | _GLOBAL(__main) | |
| 839 | blr | |
| 3d1229d6 ME |
840 | |
| 841 | #ifdef CONFIG_KEXEC | |
| 842 | /* | |
| 843 | * Must be relocatable PIC code callable as a C function. | |
| 844 | */ | |
| 845 | .globl relocate_new_kernel | |
| 846 | relocate_new_kernel: | |
| 847 | /* r3 = page_list */ | |
| 848 | /* r4 = reboot_code_buffer */ | |
| 849 | /* r5 = start_address */ | |
| 850 | ||
| 851 | li r0, 0 | |
| 852 | ||
| 853 | /* | |
| 854 | * Set Machine Status Register to a known status, | |
| 855 | * switch the MMU off and jump to 1: in a single step. | |
| 856 | */ | |
| 857 | ||
| 858 | mr r8, r0 | |
| 859 | ori r8, r8, MSR_RI|MSR_ME | |
| 860 | mtspr SPRN_SRR1, r8 | |
| 861 | addi r8, r4, 1f - relocate_new_kernel | |
| 862 | mtspr SPRN_SRR0, r8 | |
| 863 | sync | |
| 864 | rfi | |
| 865 | ||
| 866 | 1: | |
| 867 | /* from this point address translation is turned off */ | |
| 868 | /* and interrupts are disabled */ | |
| 869 | ||
| 870 | /* set a new stack at the bottom of our page... */ | |
| 871 | /* (not really needed now) */ | |
| 872 | addi r1, r4, KEXEC_CONTROL_CODE_SIZE - 8 /* for LR Save+Back Chain */ | |
| 873 | stw r0, 0(r1) | |
| 874 | ||
| 875 | /* Do the copies */ | |
| 876 | li r6, 0 /* checksum */ | |
| 877 | mr r0, r3 | |
| 878 | b 1f | |
| 879 | ||
| 880 | 0: /* top, read another word for the indirection page */ | |
| 881 | lwzu r0, 4(r3) | |
| 882 | ||
| 883 | 1: | |
| 884 | /* is it a destination page? (r8) */ | |
| 885 | rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */ | |
| 886 | beq 2f | |
| 887 | ||
| 888 | rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
| 889 | b 0b | |
| 890 | ||
| 891 | 2: /* is it an indirection page? (r3) */ | |
| 892 | rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */ | |
| 893 | beq 2f | |
| 894 | ||
| 895 | rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
| 896 | subi r3, r3, 4 | |
| 897 | b 0b | |
| 898 | ||
| 899 | 2: /* are we done? */ | |
| 900 | rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */ | |
| 901 | beq 2f | |
| 902 | b 3f | |
| 903 | ||
| 904 | 2: /* is it a source page? (r9) */ | |
| 905 | rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */ | |
| 906 | beq 0b | |
| 907 | ||
| 908 | rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */ | |
| 909 | ||
| 910 | li r7, PAGE_SIZE / 4 | |
| 911 | mtctr r7 | |
| 912 | subi r9, r9, 4 | |
| 913 | subi r8, r8, 4 | |
| 914 | 9: | |
| 915 | lwzu r0, 4(r9) /* do the copy */ | |
| 916 | xor r6, r6, r0 | |
| 917 | stwu r0, 4(r8) | |
| 918 | dcbst 0, r8 | |
| 919 | sync | |
| 920 | icbi 0, r8 | |
| 921 | bdnz 9b | |
| 922 | ||
| 923 | addi r9, r9, 4 | |
| 924 | addi r8, r8, 4 | |
| 925 | b 0b | |
| 926 | ||
| 927 | 3: | |
| 928 | ||
| 929 | /* To be certain of avoiding problems with self-modifying code | |
| 930 | * execute a serializing instruction here. | |
| 931 | */ | |
| 932 | isync | |
| 933 | sync | |
| 934 | ||
| 935 | /* jump to the entry point, usually the setup routine */ | |
| 936 | mtlr r5 | |
| 937 | blrl | |
| 938 | ||
| 939 | 1: b 1b | |
| 940 | ||
| 941 | relocate_new_kernel_end: | |
| 942 | ||
| 943 | .globl relocate_new_kernel_size | |
| 944 | relocate_new_kernel_size: | |
| 945 | .long relocate_new_kernel_end - relocate_new_kernel | |
| 946 | #endif |