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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
5516b540 KG |
2 | /* |
3 | * Contains common pci routines for ALL ppc platform | |
cf1d8a8a KG |
4 | * (based on pci_32.c and pci_64.c) |
5 | * | |
6 | * Port for PPC64 David Engebretsen, IBM Corp. | |
7 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
8 | * | |
9 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
10 | * Rework, based on alpha PCI code. | |
11 | * | |
12 | * Common pmac/prep/chrp pci routines. -- Cort | |
5516b540 KG |
13 | */ |
14 | ||
5516b540 KG |
15 | #include <linux/kernel.h> |
16 | #include <linux/pci.h> | |
17 | #include <linux/string.h> | |
18 | #include <linux/init.h> | |
d92a208d | 19 | #include <linux/delay.h> |
66b15db6 | 20 | #include <linux/export.h> |
22ae782f | 21 | #include <linux/of_address.h> |
04bea68b | 22 | #include <linux/of_pci.h> |
5516b540 | 23 | #include <linux/mm.h> |
3a4f8a0b | 24 | #include <linux/shmem_fs.h> |
5516b540 KG |
25 | #include <linux/list.h> |
26 | #include <linux/syscalls.h> | |
27 | #include <linux/irq.h> | |
28 | #include <linux/vmalloc.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
c2e1d845 | 30 | #include <linux/vgaarb.h> |
98fa15f3 | 31 | #include <linux/numa.h> |
5516b540 KG |
32 | |
33 | #include <asm/processor.h> | |
34 | #include <asm/io.h> | |
35 | #include <asm/prom.h> | |
36 | #include <asm/pci-bridge.h> | |
37 | #include <asm/byteorder.h> | |
38 | #include <asm/machdep.h> | |
39 | #include <asm/ppc-pci.h> | |
8b8da358 | 40 | #include <asm/eeh.h> |
5516b540 | 41 | |
44bda4b7 HV |
42 | #include "../../../drivers/pci/pci.h" |
43 | ||
63a72284 | 44 | /* hose_spinlock protects accesses to the the phb_bitmap. */ |
a4c9e328 | 45 | static DEFINE_SPINLOCK(hose_spinlock); |
c3bd517d | 46 | LIST_HEAD(hose_list); |
a4c9e328 | 47 | |
63a72284 GP |
48 | /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */ |
49 | #define MAX_PHBS 0x10000 | |
50 | ||
51 | /* | |
52 | * For dynamic PHB numbering: used/free PHBs tracking bitmap. | |
53 | * Accesses to this bitmap should be protected by hose_spinlock. | |
54 | */ | |
55 | static DECLARE_BITMAP(phb_bitmap, MAX_PHBS); | |
a4c9e328 | 56 | |
25e81f92 BH |
57 | /* ISA Memory physical address */ |
58 | resource_size_t isa_mem_base; | |
9445aa1a | 59 | EXPORT_SYMBOL(isa_mem_base); |
25e81f92 | 60 | |
a4c9e328 | 61 | |
68005b67 | 62 | static const struct dma_map_ops *pci_dma_ops; |
4fc665b8 | 63 | |
5299709d | 64 | void set_pci_dma_ops(const struct dma_map_ops *dma_ops) |
4fc665b8 BB |
65 | { |
66 | pci_dma_ops = dma_ops; | |
67 | } | |
68 | ||
63a72284 GP |
69 | /* |
70 | * This function should run under locking protection, specifically | |
71 | * hose_spinlock. | |
72 | */ | |
73 | static int get_phb_number(struct device_node *dn) | |
74 | { | |
75 | int ret, phb_id = -1; | |
61e8a0d5 | 76 | u32 prop_32; |
63a72284 GP |
77 | u64 prop; |
78 | ||
79 | /* | |
80 | * Try fixed PHB numbering first, by checking archs and reading | |
81 | * the respective device-tree properties. Firstly, try powernv by | |
82 | * reading "ibm,opal-phbid", only present in OPAL environment. | |
83 | */ | |
84 | ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); | |
61e8a0d5 ME |
85 | if (ret) { |
86 | ret = of_property_read_u32_index(dn, "reg", 1, &prop_32); | |
87 | prop = prop_32; | |
88 | } | |
63a72284 GP |
89 | |
90 | if (!ret) | |
91 | phb_id = (int)(prop & (MAX_PHBS - 1)); | |
92 | ||
93 | /* We need to be sure to not use the same PHB number twice. */ | |
94 | if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap)) | |
95 | return phb_id; | |
96 | ||
97 | /* | |
98 | * If not pseries nor powernv, or if fixed PHB numbering tried to add | |
99 | * the same PHB number twice, then fallback to dynamic PHB numbering. | |
100 | */ | |
101 | phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS); | |
102 | BUG_ON(phb_id >= MAX_PHBS); | |
103 | set_bit(phb_id, phb_bitmap); | |
104 | ||
105 | return phb_id; | |
106 | } | |
107 | ||
e60516e3 | 108 | struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
a4c9e328 KG |
109 | { |
110 | struct pci_controller *phb; | |
111 | ||
e60516e3 | 112 | phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
a4c9e328 KG |
113 | if (phb == NULL) |
114 | return NULL; | |
e60516e3 | 115 | spin_lock(&hose_spinlock); |
63a72284 | 116 | phb->global_number = get_phb_number(dev); |
e60516e3 SR |
117 | list_add_tail(&phb->list_node, &hose_list); |
118 | spin_unlock(&hose_spinlock); | |
44ef3390 | 119 | phb->dn = dev; |
f691fa10 | 120 | phb->is_dynamic = slab_is_available(); |
a4c9e328 KG |
121 | #ifdef CONFIG_PPC64 |
122 | if (dev) { | |
123 | int nid = of_node_to_nid(dev); | |
124 | ||
125 | if (nid < 0 || !node_online(nid)) | |
98fa15f3 | 126 | nid = NUMA_NO_NODE; |
a4c9e328 KG |
127 | |
128 | PHB_SET_NODE(phb, nid); | |
129 | } | |
130 | #endif | |
131 | return phb; | |
132 | } | |
5b64d2cc | 133 | EXPORT_SYMBOL_GPL(pcibios_alloc_controller); |
a4c9e328 KG |
134 | |
135 | void pcibios_free_controller(struct pci_controller *phb) | |
136 | { | |
137 | spin_lock(&hose_spinlock); | |
63a72284 GP |
138 | |
139 | /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ | |
140 | if (phb->global_number < MAX_PHBS) | |
141 | clear_bit(phb->global_number, phb_bitmap); | |
142 | ||
a4c9e328 KG |
143 | list_del(&phb->list_node); |
144 | spin_unlock(&hose_spinlock); | |
145 | ||
146 | if (phb->is_dynamic) | |
147 | kfree(phb); | |
148 | } | |
6b8b252f | 149 | EXPORT_SYMBOL_GPL(pcibios_free_controller); |
a4c9e328 | 150 | |
2dd9c11b MFO |
151 | /* |
152 | * This function is used to call pcibios_free_controller() | |
153 | * in a deferred manner: a callback from the PCI subsystem. | |
154 | * | |
155 | * _*DO NOT*_ call pcibios_free_controller() explicitly if | |
156 | * this is used (or it may access an invalid *phb pointer). | |
157 | * | |
158 | * The callback occurs when all references to the root bus | |
159 | * are dropped (e.g., child buses/devices and their users). | |
160 | * | |
161 | * It's called as .release_fn() of 'struct pci_host_bridge' | |
162 | * which is associated with the 'struct pci_controller.bus' | |
163 | * (root bus) - it expects .release_data to hold a pointer | |
164 | * to 'struct pci_controller'. | |
165 | * | |
166 | * In order to use it, register .release_fn()/release_data | |
167 | * like this: | |
168 | * | |
169 | * pci_set_host_bridge_release(bridge, | |
170 | * pcibios_free_controller_deferred | |
171 | * (void *) phb); | |
172 | * | |
173 | * e.g. in the pcibios_root_bridge_prepare() callback from | |
174 | * pci_create_root_bus(). | |
175 | */ | |
176 | void pcibios_free_controller_deferred(struct pci_host_bridge *bridge) | |
177 | { | |
178 | struct pci_controller *phb = (struct pci_controller *) | |
179 | bridge->release_data; | |
180 | ||
181 | pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); | |
182 | ||
183 | pcibios_free_controller(phb); | |
184 | } | |
185 | EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred); | |
186 | ||
4c2245bb GS |
187 | /* |
188 | * The function is used to return the minimal alignment | |
189 | * for memory or I/O windows of the associated P2P bridge. | |
190 | * By default, 4KiB alignment for I/O windows and 1MiB for | |
191 | * memory windows. | |
192 | */ | |
193 | resource_size_t pcibios_window_alignment(struct pci_bus *bus, | |
194 | unsigned long type) | |
195 | { | |
467efc2e DA |
196 | struct pci_controller *phb = pci_bus_to_host(bus); |
197 | ||
198 | if (phb->controller_ops.window_alignment) | |
199 | return phb->controller_ops.window_alignment(bus, type); | |
200 | ||
201 | /* | |
202 | * PCI core will figure out the default | |
203 | * alignment: 4KiB for I/O and 1MiB for | |
204 | * memory window. | |
205 | */ | |
206 | return 1; | |
4c2245bb GS |
207 | } |
208 | ||
c5fcb29a GS |
209 | void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) |
210 | { | |
211 | struct pci_controller *hose = pci_bus_to_host(bus); | |
212 | ||
213 | if (hose->controller_ops.setup_bridge) | |
214 | hose->controller_ops.setup_bridge(bus, type); | |
215 | } | |
216 | ||
d92a208d GS |
217 | void pcibios_reset_secondary_bus(struct pci_dev *dev) |
218 | { | |
467efc2e DA |
219 | struct pci_controller *phb = pci_bus_to_host(dev->bus); |
220 | ||
221 | if (phb->controller_ops.reset_secondary_bus) { | |
222 | phb->controller_ops.reset_secondary_bus(dev); | |
223 | return; | |
224 | } | |
225 | ||
226 | pci_reset_secondary_bus(dev); | |
d92a208d GS |
227 | } |
228 | ||
38274637 YX |
229 | resource_size_t pcibios_default_alignment(void) |
230 | { | |
231 | if (ppc_md.pcibios_default_alignment) | |
232 | return ppc_md.pcibios_default_alignment(); | |
233 | ||
234 | return 0; | |
235 | } | |
236 | ||
5350ab3f WY |
237 | #ifdef CONFIG_PCI_IOV |
238 | resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) | |
239 | { | |
240 | if (ppc_md.pcibios_iov_resource_alignment) | |
241 | return ppc_md.pcibios_iov_resource_alignment(pdev, resno); | |
242 | ||
243 | return pci_iov_resource_size(pdev, resno); | |
244 | } | |
988fc3ba BL |
245 | |
246 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) | |
247 | { | |
248 | if (ppc_md.pcibios_sriov_enable) | |
249 | return ppc_md.pcibios_sriov_enable(pdev, num_vfs); | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | int pcibios_sriov_disable(struct pci_dev *pdev) | |
255 | { | |
256 | if (ppc_md.pcibios_sriov_disable) | |
257 | return ppc_md.pcibios_sriov_disable(pdev); | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
5350ab3f WY |
262 | #endif /* CONFIG_PCI_IOV */ |
263 | ||
988fc3ba BL |
264 | void pcibios_bus_add_device(struct pci_dev *pdev) |
265 | { | |
266 | if (ppc_md.pcibios_bus_add_device) | |
267 | ppc_md.pcibios_bus_add_device(pdev); | |
268 | } | |
269 | ||
c3bd517d MM |
270 | static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
271 | { | |
272 | #ifdef CONFIG_PPC64 | |
273 | return hose->pci_io_size; | |
274 | #else | |
28f65c11 | 275 | return resource_size(&hose->io_resource); |
c3bd517d MM |
276 | #endif |
277 | } | |
278 | ||
6dfbde20 BH |
279 | int pcibios_vaddr_is_ioport(void __iomem *address) |
280 | { | |
281 | int ret = 0; | |
282 | struct pci_controller *hose; | |
c3bd517d | 283 | resource_size_t size; |
6dfbde20 BH |
284 | |
285 | spin_lock(&hose_spinlock); | |
286 | list_for_each_entry(hose, &hose_list, list_node) { | |
c3bd517d | 287 | size = pcibios_io_size(hose); |
6dfbde20 BH |
288 | if (address >= hose->io_base_virt && |
289 | address < (hose->io_base_virt + size)) { | |
290 | ret = 1; | |
291 | break; | |
292 | } | |
293 | } | |
294 | spin_unlock(&hose_spinlock); | |
295 | return ret; | |
296 | } | |
297 | ||
c3bd517d MM |
298 | unsigned long pci_address_to_pio(phys_addr_t address) |
299 | { | |
300 | struct pci_controller *hose; | |
301 | resource_size_t size; | |
302 | unsigned long ret = ~0; | |
303 | ||
304 | spin_lock(&hose_spinlock); | |
305 | list_for_each_entry(hose, &hose_list, list_node) { | |
306 | size = pcibios_io_size(hose); | |
307 | if (address >= hose->io_base_phys && | |
308 | address < (hose->io_base_phys + size)) { | |
309 | unsigned long base = | |
310 | (unsigned long)hose->io_base_virt - _IO_BASE; | |
311 | ret = base + (address - hose->io_base_phys); | |
312 | break; | |
313 | } | |
314 | } | |
315 | spin_unlock(&hose_spinlock); | |
316 | ||
317 | return ret; | |
318 | } | |
319 | EXPORT_SYMBOL_GPL(pci_address_to_pio); | |
320 | ||
5516b540 KG |
321 | /* |
322 | * Return the domain number for this bus. | |
323 | */ | |
324 | int pci_domain_nr(struct pci_bus *bus) | |
325 | { | |
6207e816 | 326 | struct pci_controller *hose = pci_bus_to_host(bus); |
5516b540 | 327 | |
6207e816 | 328 | return hose->global_number; |
5516b540 | 329 | } |
5516b540 | 330 | EXPORT_SYMBOL(pci_domain_nr); |
58083dad | 331 | |
a4c9e328 KG |
332 | /* This routine is meant to be used early during boot, when the |
333 | * PCI bus numbers have not yet been assigned, and you need to | |
334 | * issue PCI config cycles to an OF device. | |
335 | * It could also be used to "fix" RTAS config cycles if you want | |
336 | * to set pci_assign_all_buses to 1 and still use RTAS for PCI | |
337 | * config cycles. | |
338 | */ | |
339 | struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) | |
340 | { | |
a4c9e328 KG |
341 | while(node) { |
342 | struct pci_controller *hose, *tmp; | |
343 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) | |
44ef3390 | 344 | if (hose->dn == node) |
a4c9e328 KG |
345 | return hose; |
346 | node = node->parent; | |
347 | } | |
348 | return NULL; | |
349 | } | |
350 | ||
67060cb1 OH |
351 | struct pci_controller *pci_find_controller_for_domain(int domain_nr) |
352 | { | |
353 | struct pci_controller *hose; | |
354 | ||
355 | list_for_each_entry(hose, &hose_list, list_node) | |
356 | if (hose->global_number == domain_nr) | |
357 | return hose; | |
358 | ||
359 | return NULL; | |
360 | } | |
361 | ||
58083dad KG |
362 | /* |
363 | * Reads the interrupt pin to determine if interrupt is use by card. | |
364 | * If the interrupt is used, then gets the interrupt line from the | |
365 | * openfirmware and sets it in the pci_dev and pci_config line. | |
366 | */ | |
4666ca2a | 367 | static int pci_read_irq_line(struct pci_dev *pci_dev) |
58083dad | 368 | { |
c591c2e3 | 369 | int virq; |
58083dad | 370 | |
b0494bc8 | 371 | pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); |
58083dad | 372 | |
58083dad | 373 | /* Try to get a mapping from the device-tree */ |
c591c2e3 AK |
374 | virq = of_irq_parse_and_map_pci(pci_dev, 0, 0); |
375 | if (virq <= 0) { | |
58083dad KG |
376 | u8 line, pin; |
377 | ||
378 | /* If that fails, lets fallback to what is in the config | |
379 | * space and map that through the default controller. We | |
380 | * also set the type to level low since that's what PCI | |
381 | * interrupts are. If your platform does differently, then | |
382 | * either provide a proper interrupt tree or don't use this | |
383 | * function. | |
384 | */ | |
385 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) | |
386 | return -1; | |
387 | if (pin == 0) | |
388 | return -1; | |
389 | if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || | |
54a24cbb | 390 | line == 0xff || line == 0) { |
58083dad KG |
391 | return -1; |
392 | } | |
b0494bc8 BH |
393 | pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", |
394 | line, pin); | |
58083dad KG |
395 | |
396 | virq = irq_create_mapping(NULL, line); | |
ef24ba70 | 397 | if (virq) |
ec775d0e | 398 | irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); |
58083dad | 399 | } |
ef24ba70 ME |
400 | |
401 | if (!virq) { | |
b0494bc8 | 402 | pr_debug(" Failed to map !\n"); |
58083dad KG |
403 | return -1; |
404 | } | |
405 | ||
b0494bc8 | 406 | pr_debug(" Mapped to linux irq %d\n", virq); |
58083dad KG |
407 | |
408 | pci_dev->irq = virq; | |
409 | ||
410 | return 0; | |
411 | } | |
58083dad KG |
412 | |
413 | /* | |
28f8f183 | 414 | * Platform support for /proc/bus/pci/X/Y mmap()s. |
58083dad KG |
415 | * -- paulus. |
416 | */ | |
28f8f183 | 417 | int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) |
58083dad | 418 | { |
28f8f183 DW |
419 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
420 | resource_size_t ioaddr = pci_resource_start(pdev, bar); | |
58083dad | 421 | |
28f8f183 DW |
422 | if (!hose) |
423 | return -EINVAL; | |
58083dad | 424 | |
28f8f183 DW |
425 | /* Convert to an offset within this PCI controller */ |
426 | ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; | |
58083dad | 427 | |
28f8f183 DW |
428 | vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; |
429 | return 0; | |
58083dad KG |
430 | } |
431 | ||
58083dad KG |
432 | /* |
433 | * This one is used by /dev/mem and fbdev who have no clue about the | |
434 | * PCI device, it tries to find the PCI device first and calls the | |
435 | * above routine | |
436 | */ | |
437 | pgprot_t pci_phys_mem_access_prot(struct file *file, | |
438 | unsigned long pfn, | |
439 | unsigned long size, | |
64b3d0e8 | 440 | pgprot_t prot) |
58083dad KG |
441 | { |
442 | struct pci_dev *pdev = NULL; | |
443 | struct resource *found = NULL; | |
7c12d906 | 444 | resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
58083dad KG |
445 | int i; |
446 | ||
447 | if (page_is_ram(pfn)) | |
64b3d0e8 | 448 | return prot; |
58083dad | 449 | |
64b3d0e8 | 450 | prot = pgprot_noncached(prot); |
58083dad KG |
451 | for_each_pci_dev(pdev) { |
452 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
453 | struct resource *rp = &pdev->resource[i]; | |
454 | int flags = rp->flags; | |
455 | ||
456 | /* Active and same type? */ | |
457 | if ((flags & IORESOURCE_MEM) == 0) | |
458 | continue; | |
459 | /* In the range of this resource? */ | |
460 | if (offset < (rp->start & PAGE_MASK) || | |
461 | offset > rp->end) | |
462 | continue; | |
463 | found = rp; | |
464 | break; | |
465 | } | |
466 | if (found) | |
467 | break; | |
468 | } | |
469 | if (found) { | |
470 | if (found->flags & IORESOURCE_PREFETCH) | |
64b3d0e8 | 471 | prot = pgprot_noncached_wc(prot); |
58083dad KG |
472 | pci_dev_put(pdev); |
473 | } | |
474 | ||
b0494bc8 | 475 | pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
64b3d0e8 | 476 | (unsigned long long)offset, pgprot_val(prot)); |
58083dad | 477 | |
64b3d0e8 | 478 | return prot; |
58083dad KG |
479 | } |
480 | ||
e9f82cb7 BH |
481 | /* This provides legacy IO read access on a bus */ |
482 | int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) | |
483 | { | |
484 | unsigned long offset; | |
485 | struct pci_controller *hose = pci_bus_to_host(bus); | |
486 | struct resource *rp = &hose->io_resource; | |
487 | void __iomem *addr; | |
488 | ||
489 | /* Check if port can be supported by that bus. We only check | |
490 | * the ranges of the PHB though, not the bus itself as the rules | |
491 | * for forwarding legacy cycles down bridges are not our problem | |
492 | * here. So if the host bridge supports it, we do it. | |
493 | */ | |
494 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
495 | offset += port; | |
496 | ||
497 | if (!(rp->flags & IORESOURCE_IO)) | |
498 | return -ENXIO; | |
499 | if (offset < rp->start || (offset + size) > rp->end) | |
500 | return -ENXIO; | |
501 | addr = hose->io_base_virt + port; | |
502 | ||
503 | switch(size) { | |
504 | case 1: | |
505 | *((u8 *)val) = in_8(addr); | |
506 | return 1; | |
507 | case 2: | |
508 | if (port & 1) | |
509 | return -EINVAL; | |
510 | *((u16 *)val) = in_le16(addr); | |
511 | return 2; | |
512 | case 4: | |
513 | if (port & 3) | |
514 | return -EINVAL; | |
515 | *((u32 *)val) = in_le32(addr); | |
516 | return 4; | |
517 | } | |
518 | return -EINVAL; | |
519 | } | |
520 | ||
521 | /* This provides legacy IO write access on a bus */ | |
522 | int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) | |
523 | { | |
524 | unsigned long offset; | |
525 | struct pci_controller *hose = pci_bus_to_host(bus); | |
526 | struct resource *rp = &hose->io_resource; | |
527 | void __iomem *addr; | |
528 | ||
529 | /* Check if port can be supported by that bus. We only check | |
530 | * the ranges of the PHB though, not the bus itself as the rules | |
531 | * for forwarding legacy cycles down bridges are not our problem | |
532 | * here. So if the host bridge supports it, we do it. | |
533 | */ | |
534 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
535 | offset += port; | |
536 | ||
537 | if (!(rp->flags & IORESOURCE_IO)) | |
538 | return -ENXIO; | |
539 | if (offset < rp->start || (offset + size) > rp->end) | |
540 | return -ENXIO; | |
541 | addr = hose->io_base_virt + port; | |
542 | ||
543 | /* WARNING: The generic code is idiotic. It gets passed a pointer | |
544 | * to what can be a 1, 2 or 4 byte quantity and always reads that | |
545 | * as a u32, which means that we have to correct the location of | |
546 | * the data read within those 32 bits for size 1 and 2 | |
547 | */ | |
548 | switch(size) { | |
549 | case 1: | |
550 | out_8(addr, val >> 24); | |
551 | return 1; | |
552 | case 2: | |
553 | if (port & 1) | |
554 | return -EINVAL; | |
555 | out_le16(addr, val >> 16); | |
556 | return 2; | |
557 | case 4: | |
558 | if (port & 3) | |
559 | return -EINVAL; | |
560 | out_le32(addr, val); | |
561 | return 4; | |
562 | } | |
563 | return -EINVAL; | |
564 | } | |
565 | ||
566 | /* This provides legacy IO or memory mmap access on a bus */ | |
567 | int pci_mmap_legacy_page_range(struct pci_bus *bus, | |
568 | struct vm_area_struct *vma, | |
569 | enum pci_mmap_state mmap_state) | |
570 | { | |
571 | struct pci_controller *hose = pci_bus_to_host(bus); | |
572 | resource_size_t offset = | |
573 | ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; | |
574 | resource_size_t size = vma->vm_end - vma->vm_start; | |
575 | struct resource *rp; | |
576 | ||
577 | pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", | |
578 | pci_domain_nr(bus), bus->number, | |
579 | mmap_state == pci_mmap_mem ? "MEM" : "IO", | |
580 | (unsigned long long)offset, | |
581 | (unsigned long long)(offset + size - 1)); | |
582 | ||
583 | if (mmap_state == pci_mmap_mem) { | |
5b11abfd BH |
584 | /* Hack alert ! |
585 | * | |
586 | * Because X is lame and can fail starting if it gets an error trying | |
587 | * to mmap legacy_mem (instead of just moving on without legacy memory | |
588 | * access) we fake it here by giving it anonymous memory, effectively | |
589 | * behaving just like /dev/zero | |
590 | */ | |
591 | if ((offset + size) > hose->isa_mem_size) { | |
592 | printk(KERN_DEBUG | |
593 | "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", | |
594 | current->comm, current->pid, pci_domain_nr(bus), bus->number); | |
595 | if (vma->vm_flags & VM_SHARED) | |
596 | return shmem_zero_setup(vma); | |
597 | return 0; | |
598 | } | |
e9f82cb7 BH |
599 | offset += hose->isa_mem_phys; |
600 | } else { | |
601 | unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
602 | unsigned long roffset = offset + io_offset; | |
603 | rp = &hose->io_resource; | |
604 | if (!(rp->flags & IORESOURCE_IO)) | |
605 | return -ENXIO; | |
606 | if (roffset < rp->start || (roffset + size) > rp->end) | |
607 | return -ENXIO; | |
608 | offset += hose->io_base_phys; | |
609 | } | |
610 | pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); | |
611 | ||
612 | vma->vm_pgoff = offset >> PAGE_SHIFT; | |
64b3d0e8 | 613 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
e9f82cb7 BH |
614 | return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
615 | vma->vm_end - vma->vm_start, | |
616 | vma->vm_page_prot); | |
617 | } | |
618 | ||
58083dad KG |
619 | void pci_resource_to_user(const struct pci_dev *dev, int bar, |
620 | const struct resource *rsrc, | |
621 | resource_size_t *start, resource_size_t *end) | |
622 | { | |
38301358 | 623 | struct pci_bus_region region; |
58083dad | 624 | |
38301358 BH |
625 | if (rsrc->flags & IORESOURCE_IO) { |
626 | pcibios_resource_to_bus(dev->bus, ®ion, | |
627 | (struct resource *) rsrc); | |
628 | *start = region.start; | |
629 | *end = region.end; | |
58083dad | 630 | return; |
38301358 | 631 | } |
58083dad | 632 | |
38301358 BH |
633 | /* We pass a CPU physical address to userland for MMIO instead of a |
634 | * BAR value because X is lame and expects to be able to use that | |
635 | * to pass to /dev/mem! | |
58083dad | 636 | * |
38301358 BH |
637 | * That means we may have 64-bit values where some apps only expect |
638 | * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). | |
58083dad | 639 | */ |
38301358 BH |
640 | *start = rsrc->start; |
641 | *end = rsrc->end; | |
58083dad | 642 | } |
13dccb9e BH |
643 | |
644 | /** | |
645 | * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree | |
646 | * @hose: newly allocated pci_controller to be setup | |
647 | * @dev: device node of the host bridge | |
648 | * @primary: set if primary bus (32 bits only, soon to be deprecated) | |
649 | * | |
650 | * This function will parse the "ranges" property of a PCI host bridge device | |
651 | * node and setup the resource mapping of a pci controller based on its | |
652 | * content. | |
653 | * | |
654 | * Life would be boring if it wasn't for a few issues that we have to deal | |
655 | * with here: | |
656 | * | |
657 | * - We can only cope with one IO space range and up to 3 Memory space | |
658 | * ranges. However, some machines (thanks Apple !) tend to split their | |
659 | * space into lots of small contiguous ranges. So we have to coalesce. | |
660 | * | |
13dccb9e BH |
661 | * - Some busses have IO space not starting at 0, which causes trouble with |
662 | * the way we do our IO resource renumbering. The code somewhat deals with | |
663 | * it for 64 bits but I would expect problems on 32 bits. | |
664 | * | |
665 | * - Some 32 bits platforms such as 4xx can have physical space larger than | |
666 | * 32 bits so we need to use 64 bits values for the parsing | |
667 | */ | |
cad5cef6 GKH |
668 | void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
669 | struct device_node *dev, int primary) | |
13dccb9e | 670 | { |
858957ab | 671 | int memno = 0; |
13dccb9e | 672 | struct resource *res; |
654837e8 AM |
673 | struct of_pci_range range; |
674 | struct of_pci_range_parser parser; | |
13dccb9e | 675 | |
b7c670d6 RH |
676 | printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n", |
677 | dev, primary ? "(primary)" : ""); | |
13dccb9e | 678 | |
654837e8 AM |
679 | /* Check for ranges property */ |
680 | if (of_pci_range_parser_init(&parser, dev)) | |
13dccb9e BH |
681 | return; |
682 | ||
683 | /* Parse it */ | |
654837e8 | 684 | for_each_of_pci_range(&parser, &range) { |
e9f82cb7 BH |
685 | /* If we failed translation or got a zero-sized region |
686 | * (some FW try to feed us with non sensical zero sized regions | |
687 | * such as power3 which look like some kind of attempt at exposing | |
688 | * the VGA memory hole) | |
689 | */ | |
654837e8 | 690 | if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) |
13dccb9e BH |
691 | continue; |
692 | ||
13dccb9e BH |
693 | /* Act based on address space type */ |
694 | res = NULL; | |
654837e8 AM |
695 | switch (range.flags & IORESOURCE_TYPE_BITS) { |
696 | case IORESOURCE_IO: | |
13dccb9e BH |
697 | printk(KERN_INFO |
698 | " IO 0x%016llx..0x%016llx -> 0x%016llx\n", | |
654837e8 AM |
699 | range.cpu_addr, range.cpu_addr + range.size - 1, |
700 | range.pci_addr); | |
13dccb9e BH |
701 | |
702 | /* We support only one IO range */ | |
703 | if (hose->pci_io_size) { | |
704 | printk(KERN_INFO | |
705 | " \\--> Skipped (too many) !\n"); | |
706 | continue; | |
707 | } | |
708 | #ifdef CONFIG_PPC32 | |
709 | /* On 32 bits, limit I/O space to 16MB */ | |
654837e8 AM |
710 | if (range.size > 0x01000000) |
711 | range.size = 0x01000000; | |
13dccb9e BH |
712 | |
713 | /* 32 bits needs to map IOs here */ | |
654837e8 AM |
714 | hose->io_base_virt = ioremap(range.cpu_addr, |
715 | range.size); | |
13dccb9e BH |
716 | |
717 | /* Expect trouble if pci_addr is not 0 */ | |
718 | if (primary) | |
719 | isa_io_base = | |
720 | (unsigned long)hose->io_base_virt; | |
721 | #endif /* CONFIG_PPC32 */ | |
722 | /* pci_io_size and io_base_phys always represent IO | |
723 | * space starting at 0 so we factor in pci_addr | |
724 | */ | |
654837e8 AM |
725 | hose->pci_io_size = range.pci_addr + range.size; |
726 | hose->io_base_phys = range.cpu_addr - range.pci_addr; | |
13dccb9e BH |
727 | |
728 | /* Build resource */ | |
729 | res = &hose->io_resource; | |
654837e8 | 730 | range.cpu_addr = range.pci_addr; |
13dccb9e | 731 | break; |
654837e8 | 732 | case IORESOURCE_MEM: |
13dccb9e BH |
733 | printk(KERN_INFO |
734 | " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", | |
654837e8 AM |
735 | range.cpu_addr, range.cpu_addr + range.size - 1, |
736 | range.pci_addr, | |
737 | (range.pci_space & 0x40000000) ? | |
738 | "Prefetch" : ""); | |
13dccb9e BH |
739 | |
740 | /* We support only 3 memory ranges */ | |
741 | if (memno >= 3) { | |
742 | printk(KERN_INFO | |
743 | " \\--> Skipped (too many) !\n"); | |
744 | continue; | |
745 | } | |
746 | /* Handles ISA memory hole space here */ | |
654837e8 | 747 | if (range.pci_addr == 0) { |
13dccb9e | 748 | if (primary || isa_mem_base == 0) |
654837e8 AM |
749 | isa_mem_base = range.cpu_addr; |
750 | hose->isa_mem_phys = range.cpu_addr; | |
751 | hose->isa_mem_size = range.size; | |
13dccb9e BH |
752 | } |
753 | ||
13dccb9e | 754 | /* Build resource */ |
654837e8 AM |
755 | hose->mem_offset[memno] = range.cpu_addr - |
756 | range.pci_addr; | |
13dccb9e | 757 | res = &hose->mem_resources[memno++]; |
13dccb9e BH |
758 | break; |
759 | } | |
760 | if (res != NULL) { | |
aeba3731 ME |
761 | res->name = dev->full_name; |
762 | res->flags = range.flags; | |
763 | res->start = range.cpu_addr; | |
764 | res->end = range.cpu_addr + range.size - 1; | |
765 | res->parent = res->child = res->sibling = NULL; | |
13dccb9e BH |
766 | } |
767 | } | |
13dccb9e | 768 | } |
fa462f2d BH |
769 | |
770 | /* Decide whether to display the domain number in /proc */ | |
771 | int pci_proc_domain(struct pci_bus *bus) | |
772 | { | |
773 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1fd0f525 | 774 | |
0e47ff1c | 775 | if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) |
fa462f2d | 776 | return 0; |
0e47ff1c | 777 | if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) |
fa462f2d BH |
778 | return hose->global_number != 0; |
779 | return 1; | |
fa462f2d BH |
780 | } |
781 | ||
d82fb31a KSS |
782 | int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) |
783 | { | |
784 | if (ppc_md.pcibios_root_bridge_prepare) | |
785 | return ppc_md.pcibios_root_bridge_prepare(bridge); | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
bf5e2ba2 BH |
790 | /* This header fixup will do the resource fixup for all devices as they are |
791 | * probed, but not for bridge ranges | |
792 | */ | |
cad5cef6 | 793 | static void pcibios_fixup_resources(struct pci_dev *dev) |
bf5e2ba2 BH |
794 | { |
795 | struct pci_controller *hose = pci_bus_to_host(dev->bus); | |
796 | int i; | |
797 | ||
798 | if (!hose) { | |
799 | printk(KERN_ERR "No host bridge for PCI dev %s !\n", | |
800 | pci_name(dev)); | |
801 | return; | |
802 | } | |
c3b80fb0 WY |
803 | |
804 | if (dev->is_virtfn) | |
805 | return; | |
806 | ||
bf5e2ba2 BH |
807 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
808 | struct resource *res = dev->resource + i; | |
c5df457f | 809 | struct pci_bus_region reg; |
bf5e2ba2 BH |
810 | if (!res->flags) |
811 | continue; | |
48c2ce97 BH |
812 | |
813 | /* If we're going to re-assign everything, we mark all resources | |
814 | * as unset (and 0-base them). In addition, we mark BARs starting | |
815 | * at 0 as unset as well, except if PCI_PROBE_ONLY is also set | |
816 | * since in that case, we don't want to re-assign anything | |
7f172890 | 817 | */ |
fc279850 | 818 | pcibios_resource_to_bus(dev->bus, ®, res); |
48c2ce97 | 819 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || |
c5df457f | 820 | (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { |
48c2ce97 BH |
821 | /* Only print message if not re-assigning */ |
822 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) | |
ae2a84b4 KH |
823 | pr_debug("PCI:%s Resource %d %pR is unassigned\n", |
824 | pci_name(dev), i, res); | |
bf5e2ba2 BH |
825 | res->end -= res->start; |
826 | res->start = 0; | |
827 | res->flags |= IORESOURCE_UNSET; | |
828 | continue; | |
829 | } | |
830 | ||
ae2a84b4 | 831 | pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); |
bf5e2ba2 BH |
832 | } |
833 | ||
834 | /* Call machine specific resource fixup */ | |
835 | if (ppc_md.pcibios_fixup_resources) | |
836 | ppc_md.pcibios_fixup_resources(dev); | |
837 | } | |
838 | DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); | |
839 | ||
b5561511 BH |
840 | /* This function tries to figure out if a bridge resource has been initialized |
841 | * by the firmware or not. It doesn't have to be absolutely bullet proof, but | |
842 | * things go more smoothly when it gets it right. It should covers cases such | |
843 | * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges | |
844 | */ | |
cad5cef6 GKH |
845 | static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, |
846 | struct resource *res) | |
bf5e2ba2 | 847 | { |
be8cbcd8 | 848 | struct pci_controller *hose = pci_bus_to_host(bus); |
bf5e2ba2 | 849 | struct pci_dev *dev = bus->self; |
b5561511 | 850 | resource_size_t offset; |
3fd47f06 | 851 | struct pci_bus_region region; |
b5561511 BH |
852 | u16 command; |
853 | int i; | |
bf5e2ba2 | 854 | |
b5561511 | 855 | /* We don't do anything if PCI_PROBE_ONLY is set */ |
0e47ff1c | 856 | if (pci_has_flag(PCI_PROBE_ONLY)) |
b5561511 | 857 | return 0; |
bf5e2ba2 | 858 | |
b5561511 BH |
859 | /* Job is a bit different between memory and IO */ |
860 | if (res->flags & IORESOURCE_MEM) { | |
fc279850 | 861 | pcibios_resource_to_bus(dev->bus, ®ion, res); |
3fd47f06 BH |
862 | |
863 | /* If the BAR is non-0 then it's probably been initialized */ | |
864 | if (region.start != 0) | |
b5561511 | 865 | return 0; |
bf5e2ba2 | 866 | |
b5561511 BH |
867 | /* The BAR is 0, let's check if memory decoding is enabled on |
868 | * the bridge. If not, we consider it unassigned | |
869 | */ | |
870 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
871 | if ((command & PCI_COMMAND_MEMORY) == 0) | |
872 | return 1; | |
be8cbcd8 | 873 | |
b5561511 BH |
874 | /* Memory decoding is enabled and the BAR is 0. If any of the bridge |
875 | * resources covers that starting address (0 then it's good enough for | |
3fd47f06 | 876 | * us for memory space) |
b5561511 BH |
877 | */ |
878 | for (i = 0; i < 3; i++) { | |
879 | if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && | |
3fd47f06 | 880 | hose->mem_resources[i].start == hose->mem_offset[i]) |
b5561511 BH |
881 | return 0; |
882 | } | |
883 | ||
884 | /* Well, it starts at 0 and we know it will collide so we may as | |
885 | * well consider it as unassigned. That covers the Apple case. | |
886 | */ | |
887 | return 1; | |
888 | } else { | |
889 | /* If the BAR is non-0, then we consider it assigned */ | |
890 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
891 | if (((res->start - offset) & 0xfffffffful) != 0) | |
892 | return 0; | |
893 | ||
894 | /* Here, we are a bit different than memory as typically IO space | |
895 | * starting at low addresses -is- valid. What we do instead if that | |
896 | * we consider as unassigned anything that doesn't have IO enabled | |
897 | * in the PCI command register, and that's it. | |
898 | */ | |
899 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
900 | if (command & PCI_COMMAND_IO) | |
901 | return 0; | |
902 | ||
903 | /* It's starting at 0 and IO is disabled in the bridge, consider | |
904 | * it unassigned | |
905 | */ | |
906 | return 1; | |
907 | } | |
908 | } | |
909 | ||
910 | /* Fixup resources of a PCI<->PCI bridge */ | |
cad5cef6 | 911 | static void pcibios_fixup_bridge(struct pci_bus *bus) |
b5561511 BH |
912 | { |
913 | struct resource *res; | |
914 | int i; | |
915 | ||
916 | struct pci_dev *dev = bus->self; | |
917 | ||
89a74ecc BH |
918 | pci_bus_for_each_resource(bus, res, i) { |
919 | if (!res || !res->flags) | |
b5561511 BH |
920 | continue; |
921 | if (i >= 3 && bus->self->transparent) | |
922 | continue; | |
923 | ||
cf1a4cf8 GS |
924 | /* If we're going to reassign everything, we can |
925 | * shrink the P2P resource to have size as being | |
926 | * of 0 in order to save space. | |
48c2ce97 BH |
927 | */ |
928 | if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { | |
929 | res->flags |= IORESOURCE_UNSET; | |
48c2ce97 | 930 | res->start = 0; |
cf1a4cf8 | 931 | res->end = -1; |
48c2ce97 BH |
932 | continue; |
933 | } | |
934 | ||
ae2a84b4 | 935 | pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); |
bf5e2ba2 | 936 | |
b5561511 BH |
937 | /* Try to detect uninitialized P2P bridge resources, |
938 | * and clear them out so they get re-assigned later | |
939 | */ | |
940 | if (pcibios_uninitialized_bridge_resource(bus, res)) { | |
941 | res->flags = 0; | |
942 | pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); | |
bf5e2ba2 BH |
943 | } |
944 | } | |
b5561511 BH |
945 | } |
946 | ||
cad5cef6 | 947 | void pcibios_setup_bus_self(struct pci_bus *bus) |
8b8da358 | 948 | { |
467efc2e DA |
949 | struct pci_controller *phb; |
950 | ||
7eef440a | 951 | /* Fix up the bus resources for P2P bridges */ |
8b8da358 BH |
952 | if (bus->self != NULL) |
953 | pcibios_fixup_bridge(bus); | |
954 | ||
955 | /* Platform specific bus fixups. This is currently only used | |
7eef440a | 956 | * by fsl_pci and I'm hoping to get rid of it at some point |
8b8da358 BH |
957 | */ |
958 | if (ppc_md.pcibios_fixup_bus) | |
959 | ppc_md.pcibios_fixup_bus(bus); | |
960 | ||
961 | /* Setup bus DMA mappings */ | |
467efc2e DA |
962 | phb = pci_bus_to_host(bus); |
963 | if (phb->controller_ops.dma_bus_setup) | |
964 | phb->controller_ops.dma_bus_setup(bus); | |
8b8da358 BH |
965 | } |
966 | ||
7846de40 | 967 | static void pcibios_setup_device(struct pci_dev *dev) |
37f02195 | 968 | { |
467efc2e | 969 | struct pci_controller *phb; |
37f02195 YC |
970 | /* Fixup NUMA node as it may not be setup yet by the generic |
971 | * code and is needed by the DMA init | |
972 | */ | |
973 | set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); | |
974 | ||
975 | /* Hook up default DMA ops */ | |
976 | set_dma_ops(&dev->dev, pci_dma_ops); | |
0617fc0c | 977 | dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; |
37f02195 YC |
978 | |
979 | /* Additional platform DMA/iommu setup */ | |
467efc2e DA |
980 | phb = pci_bus_to_host(dev->bus); |
981 | if (phb->controller_ops.dma_dev_setup) | |
982 | phb->controller_ops.dma_dev_setup(dev); | |
37f02195 YC |
983 | |
984 | /* Read default IRQs and fixup if necessary */ | |
985 | pci_read_irq_line(dev); | |
986 | if (ppc_md.pci_irq_fixup) | |
987 | ppc_md.pci_irq_fixup(dev); | |
988 | } | |
989 | ||
7846de40 GR |
990 | int pcibios_add_device(struct pci_dev *dev) |
991 | { | |
992 | /* | |
993 | * We can only call pcibios_setup_device() after bus setup is complete, | |
994 | * since some of the platform specific DMA setup code depends on it. | |
995 | */ | |
996 | if (dev->bus->is_added) | |
997 | pcibios_setup_device(dev); | |
6e628c7d WY |
998 | |
999 | #ifdef CONFIG_PCI_IOV | |
1000 | if (ppc_md.pcibios_fixup_sriov) | |
1001 | ppc_md.pcibios_fixup_sriov(dev); | |
1002 | #endif /* CONFIG_PCI_IOV */ | |
1003 | ||
7846de40 GR |
1004 | return 0; |
1005 | } | |
1006 | ||
cad5cef6 | 1007 | void pcibios_setup_bus_devices(struct pci_bus *bus) |
7eef440a BH |
1008 | { |
1009 | struct pci_dev *dev; | |
1010 | ||
1011 | pr_debug("PCI: Fixup bus devices %d (%s)\n", | |
1012 | bus->number, bus->self ? pci_name(bus->self) : "PHB"); | |
1013 | ||
1014 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
2d1c8618 BH |
1015 | /* Cardbus can call us to add new devices to a bus, so ignore |
1016 | * those who are already fully discovered | |
1017 | */ | |
44bda4b7 | 1018 | if (pci_dev_is_added(dev)) |
2d1c8618 BH |
1019 | continue; |
1020 | ||
37f02195 | 1021 | pcibios_setup_device(dev); |
7eef440a BH |
1022 | } |
1023 | } | |
1024 | ||
79c8be83 MS |
1025 | void pcibios_set_master(struct pci_dev *dev) |
1026 | { | |
1027 | /* No special bus mastering setup handling */ | |
1028 | } | |
1029 | ||
cad5cef6 | 1030 | void pcibios_fixup_bus(struct pci_bus *bus) |
bf5e2ba2 | 1031 | { |
237865f1 BH |
1032 | /* When called from the generic PCI probe, read PCI<->PCI bridge |
1033 | * bases. This is -not- called when generating the PCI tree from | |
1034 | * the OF device-tree. | |
1035 | */ | |
1036 | pci_read_bridge_bases(bus); | |
1037 | ||
1038 | /* Now fixup the bus bus */ | |
8b8da358 BH |
1039 | pcibios_setup_bus_self(bus); |
1040 | ||
1041 | /* Now fixup devices on that bus */ | |
1042 | pcibios_setup_bus_devices(bus); | |
bf5e2ba2 | 1043 | } |
8b8da358 | 1044 | EXPORT_SYMBOL(pcibios_fixup_bus); |
3fd94c6b | 1045 | |
cad5cef6 | 1046 | void pci_fixup_cardbus(struct pci_bus *bus) |
2d1c8618 BH |
1047 | { |
1048 | /* Now fixup devices on that bus */ | |
1049 | pcibios_setup_bus_devices(bus); | |
1050 | } | |
1051 | ||
1052 | ||
3fd94c6b BH |
1053 | static int skip_isa_ioresource_align(struct pci_dev *dev) |
1054 | { | |
0e47ff1c | 1055 | if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && |
3fd94c6b BH |
1056 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
1057 | return 1; | |
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * We need to avoid collisions with `mirrored' VGA ports | |
1063 | * and other strange ISA hardware, so we always want the | |
1064 | * addresses to be allocated in the 0x000-0x0ff region | |
1065 | * modulo 0x400. | |
1066 | * | |
1067 | * Why? Because some silly external IO cards only decode | |
1068 | * the low 10 bits of the IO address. The 0x00-0xff region | |
1069 | * is reserved for motherboard devices that decode all 16 | |
1070 | * bits, so it's ok to allocate at, say, 0x2800-0x28ff, | |
1071 | * but we want to try to avoid allocating at 0x2900-0x2bff | |
1072 | * which might have be mirrored at 0x0100-0x03ff.. | |
1073 | */ | |
3b7a17fc | 1074 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, |
3fd94c6b BH |
1075 | resource_size_t size, resource_size_t align) |
1076 | { | |
1077 | struct pci_dev *dev = data; | |
b26b2d49 | 1078 | resource_size_t start = res->start; |
3fd94c6b BH |
1079 | |
1080 | if (res->flags & IORESOURCE_IO) { | |
3fd94c6b | 1081 | if (skip_isa_ioresource_align(dev)) |
b26b2d49 DB |
1082 | return start; |
1083 | if (start & 0x300) | |
3fd94c6b | 1084 | start = (start + 0x3ff) & ~0x3ff; |
3fd94c6b | 1085 | } |
b26b2d49 DB |
1086 | |
1087 | return start; | |
3fd94c6b BH |
1088 | } |
1089 | EXPORT_SYMBOL(pcibios_align_resource); | |
1090 | ||
1091 | /* | |
1092 | * Reparent resource children of pr that conflict with res | |
1093 | * under res, and make res replace those children. | |
1094 | */ | |
0f6023d5 | 1095 | static int reparent_resources(struct resource *parent, |
3fd94c6b BH |
1096 | struct resource *res) |
1097 | { | |
1098 | struct resource *p, **pp; | |
1099 | struct resource **firstpp = NULL; | |
1100 | ||
1101 | for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { | |
1102 | if (p->end < res->start) | |
1103 | continue; | |
1104 | if (res->end < p->start) | |
1105 | break; | |
1106 | if (p->start < res->start || p->end > res->end) | |
1107 | return -1; /* not completely contained */ | |
1108 | if (firstpp == NULL) | |
1109 | firstpp = pp; | |
1110 | } | |
1111 | if (firstpp == NULL) | |
1112 | return -1; /* didn't find any conflicting entries? */ | |
1113 | res->parent = parent; | |
1114 | res->child = *firstpp; | |
1115 | res->sibling = *pp; | |
1116 | *firstpp = res; | |
1117 | *pp = NULL; | |
1118 | for (p = res->child; p != NULL; p = p->sibling) { | |
1119 | p->parent = res; | |
ae2a84b4 KH |
1120 | pr_debug("PCI: Reparented %s %pR under %s\n", |
1121 | p->name, p, res->name); | |
3fd94c6b BH |
1122 | } |
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | /* | |
1127 | * Handle resources of PCI devices. If the world were perfect, we could | |
1128 | * just allocate all the resource regions and do nothing more. It isn't. | |
1129 | * On the other hand, we cannot just re-allocate all devices, as it would | |
1130 | * require us to know lots of host bridge internals. So we attempt to | |
1131 | * keep as much of the original configuration as possible, but tweak it | |
1132 | * when it's found to be wrong. | |
1133 | * | |
1134 | * Known BIOS problems we have to work around: | |
1135 | * - I/O or memory regions not configured | |
1136 | * - regions configured, but not enabled in the command register | |
1137 | * - bogus I/O addresses above 64K used | |
1138 | * - expansion ROMs left enabled (this may sound harmless, but given | |
1139 | * the fact the PCI specs explicitly allow address decoders to be | |
1140 | * shared between expansion ROMs and other resource regions, it's | |
1141 | * at least dangerous) | |
1142 | * | |
1143 | * Our solution: | |
1144 | * (1) Allocate resources for all buses behind PCI-to-PCI bridges. | |
1145 | * This gives us fixed barriers on where we can allocate. | |
1146 | * (2) Allocate resources for all enabled devices. If there is | |
1147 | * a collision, just mark the resource as unallocated. Also | |
1148 | * disable expansion ROMs during this step. | |
1149 | * (3) Try to allocate resources for disabled devices. If the | |
1150 | * resources were assigned correctly, everything goes well, | |
1151 | * if they weren't, they won't disturb allocation of other | |
1152 | * resources. | |
1153 | * (4) Assign new addresses to resources which were either | |
1154 | * not configured at all or misconfigured. If explicitly | |
1155 | * requested by the user, configure expansion ROM address | |
1156 | * as well. | |
1157 | */ | |
1158 | ||
e51df2c1 | 1159 | static void pcibios_allocate_bus_resources(struct pci_bus *bus) |
3fd94c6b | 1160 | { |
e90a1318 | 1161 | struct pci_bus *b; |
3fd94c6b BH |
1162 | int i; |
1163 | struct resource *res, *pr; | |
1164 | ||
b5ae5f91 BH |
1165 | pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
1166 | pci_domain_nr(bus), bus->number); | |
1167 | ||
89a74ecc BH |
1168 | pci_bus_for_each_resource(bus, res, i) { |
1169 | if (!res || !res->flags || res->start > res->end || res->parent) | |
e90a1318 | 1170 | continue; |
48c2ce97 BH |
1171 | |
1172 | /* If the resource was left unset at this point, we clear it */ | |
1173 | if (res->flags & IORESOURCE_UNSET) | |
1174 | goto clear_resource; | |
1175 | ||
e90a1318 NF |
1176 | if (bus->parent == NULL) |
1177 | pr = (res->flags & IORESOURCE_IO) ? | |
1178 | &ioport_resource : &iomem_resource; | |
1179 | else { | |
e90a1318 NF |
1180 | pr = pci_find_parent_resource(bus->self, res); |
1181 | if (pr == res) { | |
1182 | /* this happens when the generic PCI | |
1183 | * code (wrongly) decides that this | |
1184 | * bridge is transparent -- paulus | |
3fd94c6b | 1185 | */ |
e90a1318 | 1186 | continue; |
3fd94c6b | 1187 | } |
e90a1318 | 1188 | } |
3fd94c6b | 1189 | |
ae2a84b4 KH |
1190 | pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", |
1191 | bus->self ? pci_name(bus->self) : "PHB", bus->number, | |
1192 | i, res, pr, (pr && pr->name) ? pr->name : "nil"); | |
e90a1318 NF |
1193 | |
1194 | if (pr && !(pr->flags & IORESOURCE_UNSET)) { | |
3ebfe46a YL |
1195 | struct pci_dev *dev = bus->self; |
1196 | ||
e90a1318 NF |
1197 | if (request_resource(pr, res) == 0) |
1198 | continue; | |
1199 | /* | |
1200 | * Must be a conflict with an existing entry. | |
1201 | * Move that entry (or entries) under the | |
1202 | * bridge resource and try again. | |
1203 | */ | |
1204 | if (reparent_resources(pr, res) == 0) | |
1205 | continue; | |
3ebfe46a YL |
1206 | |
1207 | if (dev && i < PCI_BRIDGE_RESOURCE_NUM && | |
1208 | pci_claim_bridge_resource(dev, | |
1209 | i + PCI_BRIDGE_RESOURCES) == 0) | |
1210 | continue; | |
3fd94c6b | 1211 | } |
f2c2cbcc JP |
1212 | pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n", |
1213 | i, bus->number); | |
48c2ce97 | 1214 | clear_resource: |
cf1a4cf8 GS |
1215 | /* The resource might be figured out when doing |
1216 | * reassignment based on the resources required | |
1217 | * by the downstream PCI devices. Here we set | |
1218 | * the size of the resource to be 0 in order to | |
1219 | * save more space. | |
1220 | */ | |
1221 | res->start = 0; | |
1222 | res->end = -1; | |
e90a1318 | 1223 | res->flags = 0; |
3fd94c6b | 1224 | } |
e90a1318 NF |
1225 | |
1226 | list_for_each_entry(b, &bus->children, node) | |
1227 | pcibios_allocate_bus_resources(b); | |
3fd94c6b BH |
1228 | } |
1229 | ||
cad5cef6 | 1230 | static inline void alloc_resource(struct pci_dev *dev, int idx) |
3fd94c6b BH |
1231 | { |
1232 | struct resource *pr, *r = &dev->resource[idx]; | |
1233 | ||
ae2a84b4 KH |
1234 | pr_debug("PCI: Allocating %s: Resource %d: %pR\n", |
1235 | pci_name(dev), idx, r); | |
3fd94c6b BH |
1236 | |
1237 | pr = pci_find_parent_resource(dev, r); | |
1238 | if (!pr || (pr->flags & IORESOURCE_UNSET) || | |
1239 | request_resource(pr, r) < 0) { | |
1240 | printk(KERN_WARNING "PCI: Cannot allocate resource region %d" | |
1241 | " of device %s, will remap\n", idx, pci_name(dev)); | |
1242 | if (pr) | |
ae2a84b4 | 1243 | pr_debug("PCI: parent is %p: %pR\n", pr, pr); |
3fd94c6b BH |
1244 | /* We'll assign a new address later */ |
1245 | r->flags |= IORESOURCE_UNSET; | |
1246 | r->end -= r->start; | |
1247 | r->start = 0; | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | static void __init pcibios_allocate_resources(int pass) | |
1252 | { | |
1253 | struct pci_dev *dev = NULL; | |
1254 | int idx, disabled; | |
1255 | u16 command; | |
1256 | struct resource *r; | |
1257 | ||
1258 | for_each_pci_dev(dev) { | |
1259 | pci_read_config_word(dev, PCI_COMMAND, &command); | |
ad892a63 | 1260 | for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
3fd94c6b BH |
1261 | r = &dev->resource[idx]; |
1262 | if (r->parent) /* Already allocated */ | |
1263 | continue; | |
1264 | if (!r->flags || (r->flags & IORESOURCE_UNSET)) | |
1265 | continue; /* Not assigned at all */ | |
ad892a63 BH |
1266 | /* We only allocate ROMs on pass 1 just in case they |
1267 | * have been screwed up by firmware | |
1268 | */ | |
1269 | if (idx == PCI_ROM_RESOURCE ) | |
1270 | disabled = 1; | |
3fd94c6b BH |
1271 | if (r->flags & IORESOURCE_IO) |
1272 | disabled = !(command & PCI_COMMAND_IO); | |
1273 | else | |
1274 | disabled = !(command & PCI_COMMAND_MEMORY); | |
533b1928 PM |
1275 | if (pass == disabled) |
1276 | alloc_resource(dev, idx); | |
3fd94c6b BH |
1277 | } |
1278 | if (pass) | |
1279 | continue; | |
1280 | r = &dev->resource[PCI_ROM_RESOURCE]; | |
ad892a63 | 1281 | if (r->flags) { |
3fd94c6b BH |
1282 | /* Turn the ROM off, leave the resource region, |
1283 | * but keep it unregistered. | |
1284 | */ | |
1285 | u32 reg; | |
3fd94c6b | 1286 | pci_read_config_dword(dev, dev->rom_base_reg, ®); |
ad892a63 BH |
1287 | if (reg & PCI_ROM_ADDRESS_ENABLE) { |
1288 | pr_debug("PCI: Switching off ROM of %s\n", | |
1289 | pci_name(dev)); | |
1290 | r->flags &= ~IORESOURCE_ROM_ENABLE; | |
1291 | pci_write_config_dword(dev, dev->rom_base_reg, | |
1292 | reg & ~PCI_ROM_ADDRESS_ENABLE); | |
1293 | } | |
3fd94c6b BH |
1294 | } |
1295 | } | |
1296 | } | |
1297 | ||
c1f34302 BH |
1298 | static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
1299 | { | |
1300 | struct pci_controller *hose = pci_bus_to_host(bus); | |
1301 | resource_size_t offset; | |
1302 | struct resource *res, *pres; | |
1303 | int i; | |
1304 | ||
1305 | pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); | |
1306 | ||
1307 | /* Check for IO */ | |
1308 | if (!(hose->io_resource.flags & IORESOURCE_IO)) | |
1309 | goto no_io; | |
1310 | offset = (unsigned long)hose->io_base_virt - _IO_BASE; | |
1311 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1312 | BUG_ON(res == NULL); | |
1313 | res->name = "Legacy IO"; | |
1314 | res->flags = IORESOURCE_IO; | |
1315 | res->start = offset; | |
1316 | res->end = (offset + 0xfff) & 0xfffffffful; | |
1317 | pr_debug("Candidate legacy IO: %pR\n", res); | |
1318 | if (request_resource(&hose->io_resource, res)) { | |
1319 | printk(KERN_DEBUG | |
1320 | "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", | |
1321 | pci_domain_nr(bus), bus->number, res); | |
1322 | kfree(res); | |
1323 | } | |
1324 | ||
1325 | no_io: | |
1326 | /* Check for memory */ | |
c1f34302 BH |
1327 | for (i = 0; i < 3; i++) { |
1328 | pres = &hose->mem_resources[i]; | |
3fd47f06 | 1329 | offset = hose->mem_offset[i]; |
c1f34302 BH |
1330 | if (!(pres->flags & IORESOURCE_MEM)) |
1331 | continue; | |
1332 | pr_debug("hose mem res: %pR\n", pres); | |
1333 | if ((pres->start - offset) <= 0xa0000 && | |
1334 | (pres->end - offset) >= 0xbffff) | |
1335 | break; | |
1336 | } | |
1337 | if (i >= 3) | |
1338 | return; | |
1339 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
1340 | BUG_ON(res == NULL); | |
1341 | res->name = "Legacy VGA memory"; | |
1342 | res->flags = IORESOURCE_MEM; | |
1343 | res->start = 0xa0000 + offset; | |
1344 | res->end = 0xbffff + offset; | |
1345 | pr_debug("Candidate VGA memory: %pR\n", res); | |
1346 | if (request_resource(pres, res)) { | |
1347 | printk(KERN_DEBUG | |
1348 | "PCI %04x:%02x Cannot reserve VGA memory %pR\n", | |
1349 | pci_domain_nr(bus), bus->number, res); | |
1350 | kfree(res); | |
1351 | } | |
1352 | } | |
1353 | ||
3fd94c6b BH |
1354 | void __init pcibios_resource_survey(void) |
1355 | { | |
e90a1318 NF |
1356 | struct pci_bus *b; |
1357 | ||
48c2ce97 | 1358 | /* Allocate and assign resources */ |
e90a1318 NF |
1359 | list_for_each_entry(b, &pci_root_buses, node) |
1360 | pcibios_allocate_bus_resources(b); | |
9a1a70ae BH |
1361 | if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { |
1362 | pcibios_allocate_resources(0); | |
1363 | pcibios_allocate_resources(1); | |
1364 | } | |
3fd94c6b | 1365 | |
c1f34302 BH |
1366 | /* Before we start assigning unassigned resource, we try to reserve |
1367 | * the low IO area and the VGA memory area if they intersect the | |
1368 | * bus available resources to avoid allocating things on top of them | |
1369 | */ | |
0e47ff1c | 1370 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
c1f34302 BH |
1371 | list_for_each_entry(b, &pci_root_buses, node) |
1372 | pcibios_reserve_legacy_regions(b); | |
1373 | } | |
1374 | ||
1375 | /* Now, if the platform didn't decide to blindly trust the firmware, | |
1376 | * we proceed to assigning things that were left unassigned | |
1377 | */ | |
0e47ff1c | 1378 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
a77acda0 | 1379 | pr_debug("PCI: Assigning unassigned resources...\n"); |
3fd94c6b BH |
1380 | pci_assign_unassigned_resources(); |
1381 | } | |
1382 | ||
1383 | /* Call machine dependent fixup */ | |
1384 | if (ppc_md.pcibios_fixup) | |
1385 | ppc_md.pcibios_fixup(); | |
1386 | } | |
1387 | ||
fd6852c8 | 1388 | /* This is used by the PCI hotplug driver to allocate resource |
3fd94c6b | 1389 | * of newly plugged busses. We can try to consolidate with the |
fd6852c8 BH |
1390 | * rest of the code later, for now, keep it as-is as our main |
1391 | * resource allocation function doesn't deal with sub-trees yet. | |
3fd94c6b | 1392 | */ |
baf75b0a | 1393 | void pcibios_claim_one_bus(struct pci_bus *bus) |
3fd94c6b BH |
1394 | { |
1395 | struct pci_dev *dev; | |
1396 | struct pci_bus *child_bus; | |
1397 | ||
1398 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1399 | int i; | |
1400 | ||
1401 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
1402 | struct resource *r = &dev->resource[i]; | |
1403 | ||
1404 | if (r->parent || !r->start || !r->flags) | |
1405 | continue; | |
fd6852c8 | 1406 | |
ae2a84b4 KH |
1407 | pr_debug("PCI: Claiming %s: Resource %d: %pR\n", |
1408 | pci_name(dev), i, r); | |
fd6852c8 | 1409 | |
3ebfe46a YL |
1410 | if (pci_claim_resource(dev, i) == 0) |
1411 | continue; | |
1412 | ||
1413 | pci_claim_bridge_resource(dev, i); | |
3fd94c6b BH |
1414 | } |
1415 | } | |
1416 | ||
1417 | list_for_each_entry(child_bus, &bus->children, node) | |
1418 | pcibios_claim_one_bus(child_bus); | |
1419 | } | |
5b64d2cc | 1420 | EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); |
fd6852c8 BH |
1421 | |
1422 | ||
1423 | /* pcibios_finish_adding_to_bus | |
1424 | * | |
1425 | * This is to be called by the hotplug code after devices have been | |
1426 | * added to a bus, this include calling it for a PHB that is just | |
1427 | * being added | |
1428 | */ | |
1429 | void pcibios_finish_adding_to_bus(struct pci_bus *bus) | |
1430 | { | |
1431 | pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", | |
1432 | pci_domain_nr(bus), bus->number); | |
1433 | ||
1434 | /* Allocate bus and devices resources */ | |
1435 | pcibios_allocate_bus_resources(bus); | |
1436 | pcibios_claim_one_bus(bus); | |
7415c14c GS |
1437 | if (!pci_has_flag(PCI_PROBE_ONLY)) { |
1438 | if (bus->self) | |
1439 | pci_assign_unassigned_bridge_resources(bus->self); | |
1440 | else | |
1441 | pci_assign_unassigned_bus_resources(bus); | |
1442 | } | |
fd6852c8 | 1443 | |
6a040ce7 TLSC |
1444 | /* Fixup EEH */ |
1445 | eeh_add_device_tree_late(bus); | |
1446 | ||
fd6852c8 BH |
1447 | /* Add new devices to global lists. Register in proc, sysfs. */ |
1448 | pci_bus_add_devices(bus); | |
1449 | ||
6a040ce7 TLSC |
1450 | /* sysfs files should only be added after devices are added */ |
1451 | eeh_add_sysfs_files(bus); | |
fd6852c8 BH |
1452 | } |
1453 | EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); | |
1454 | ||
549beb9b BH |
1455 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1456 | { | |
467efc2e DA |
1457 | struct pci_controller *phb = pci_bus_to_host(dev->bus); |
1458 | ||
1459 | if (phb->controller_ops.enable_device_hook) | |
1460 | if (!phb->controller_ops.enable_device_hook(dev)) | |
1461 | return -EINVAL; | |
549beb9b | 1462 | |
7cfb5f9a | 1463 | return pci_enable_resources(dev, mask); |
549beb9b | 1464 | } |
53280323 | 1465 | |
abeeed6d MN |
1466 | void pcibios_disable_device(struct pci_dev *dev) |
1467 | { | |
1468 | struct pci_controller *phb = pci_bus_to_host(dev->bus); | |
1469 | ||
1470 | if (phb->controller_ops.disable_device) | |
1471 | phb->controller_ops.disable_device(dev); | |
1472 | } | |
1473 | ||
38973ba7 BH |
1474 | resource_size_t pcibios_io_space_offset(struct pci_controller *hose) |
1475 | { | |
1476 | return (unsigned long) hose->io_base_virt - _IO_BASE; | |
1477 | } | |
1478 | ||
cad5cef6 GKH |
1479 | static void pcibios_setup_phb_resources(struct pci_controller *hose, |
1480 | struct list_head *resources) | |
53280323 | 1481 | { |
53280323 | 1482 | struct resource *res; |
3fd47f06 | 1483 | resource_size_t offset; |
53280323 BH |
1484 | int i; |
1485 | ||
1486 | /* Hookup PHB IO resource */ | |
45a709f8 | 1487 | res = &hose->io_resource; |
53280323 BH |
1488 | |
1489 | if (!res->flags) { | |
cdb1b342 | 1490 | pr_debug("PCI: I/O resource not set for host" |
b7c670d6 RH |
1491 | " bridge %pOF (domain %d)\n", |
1492 | hose->dn, hose->global_number); | |
3fd47f06 BH |
1493 | } else { |
1494 | offset = pcibios_io_space_offset(hose); | |
1495 | ||
ae2a84b4 KH |
1496 | pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", |
1497 | res, (unsigned long long)offset); | |
3fd47f06 | 1498 | pci_add_resource_offset(resources, res, offset); |
a0b8e76f | 1499 | } |
53280323 BH |
1500 | |
1501 | /* Hookup PHB Memory resources */ | |
1502 | for (i = 0; i < 3; ++i) { | |
1503 | res = &hose->mem_resources[i]; | |
727597d1 | 1504 | if (!res->flags) |
3fd47f06 | 1505 | continue; |
3fd47f06 | 1506 | |
727597d1 | 1507 | offset = hose->mem_offset[i]; |
ae2a84b4 KH |
1508 | pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, |
1509 | res, (unsigned long long)offset); | |
3fd47f06 BH |
1510 | |
1511 | pci_add_resource_offset(resources, res, offset); | |
1512 | } | |
53280323 | 1513 | } |
89c2dd62 KG |
1514 | |
1515 | /* | |
1516 | * Null PCI config access functions, for the case when we can't | |
1517 | * find a hose. | |
1518 | */ | |
1519 | #define NULL_PCI_OP(rw, size, type) \ | |
1520 | static int \ | |
1521 | null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ | |
1522 | { \ | |
1523 | return PCIBIOS_DEVICE_NOT_FOUND; \ | |
1524 | } | |
1525 | ||
1526 | static int | |
1527 | null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1528 | int len, u32 *val) | |
1529 | { | |
1530 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1531 | } | |
1532 | ||
1533 | static int | |
1534 | null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, | |
1535 | int len, u32 val) | |
1536 | { | |
1537 | return PCIBIOS_DEVICE_NOT_FOUND; | |
1538 | } | |
1539 | ||
1540 | static struct pci_ops null_pci_ops = | |
1541 | { | |
1542 | .read = null_read_config, | |
1543 | .write = null_write_config, | |
1544 | }; | |
1545 | ||
1546 | /* | |
1547 | * These functions are used early on before PCI scanning is done | |
1548 | * and all of the pci_dev and pci_bus structures have been created. | |
1549 | */ | |
1550 | static struct pci_bus * | |
1551 | fake_pci_bus(struct pci_controller *hose, int busnr) | |
1552 | { | |
1553 | static struct pci_bus bus; | |
1554 | ||
b0d436c7 | 1555 | if (hose == NULL) { |
89c2dd62 KG |
1556 | printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); |
1557 | } | |
1558 | bus.number = busnr; | |
1559 | bus.sysdata = hose; | |
1560 | bus.ops = hose? hose->ops: &null_pci_ops; | |
1561 | return &bus; | |
1562 | } | |
1563 | ||
1564 | #define EARLY_PCI_OP(rw, size, type) \ | |
1565 | int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ | |
1566 | int devfn, int offset, type value) \ | |
1567 | { \ | |
1568 | return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ | |
1569 | devfn, offset, value); \ | |
1570 | } | |
1571 | ||
1572 | EARLY_PCI_OP(read, byte, u8 *) | |
1573 | EARLY_PCI_OP(read, word, u16 *) | |
1574 | EARLY_PCI_OP(read, dword, u32 *) | |
1575 | EARLY_PCI_OP(write, byte, u8) | |
1576 | EARLY_PCI_OP(write, word, u16) | |
1577 | EARLY_PCI_OP(write, dword, u32) | |
1578 | ||
89c2dd62 KG |
1579 | int early_find_capability(struct pci_controller *hose, int bus, int devfn, |
1580 | int cap) | |
1581 | { | |
1582 | return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); | |
1583 | } | |
0ed2c722 | 1584 | |
98d9f30c BH |
1585 | struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) |
1586 | { | |
1587 | struct pci_controller *hose = bus->sysdata; | |
1588 | ||
1589 | return of_node_get(hose->dn); | |
1590 | } | |
1591 | ||
0ed2c722 GL |
1592 | /** |
1593 | * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus | |
1594 | * @hose: Pointer to the PCI host controller instance structure | |
0ed2c722 | 1595 | */ |
cad5cef6 | 1596 | void pcibios_scan_phb(struct pci_controller *hose) |
0ed2c722 | 1597 | { |
45a709f8 | 1598 | LIST_HEAD(resources); |
0ed2c722 GL |
1599 | struct pci_bus *bus; |
1600 | struct device_node *node = hose->dn; | |
1601 | int mode; | |
1602 | ||
b7c670d6 | 1603 | pr_debug("PCI: Scanning PHB %pOF\n", node); |
0ed2c722 | 1604 | |
45a709f8 BH |
1605 | /* Get some IO space for the new PHB */ |
1606 | pcibios_setup_phb_io_space(hose); | |
1607 | ||
1608 | /* Wire up PHB bus resources */ | |
1609 | pcibios_setup_phb_resources(hose, &resources); | |
1610 | ||
be8e60d8 YL |
1611 | hose->busn.start = hose->first_busno; |
1612 | hose->busn.end = hose->last_busno; | |
1613 | hose->busn.flags = IORESOURCE_BUS; | |
1614 | pci_add_resource(&resources, &hose->busn); | |
1615 | ||
0ed2c722 | 1616 | /* Create an empty bus for the toplevel */ |
45a709f8 BH |
1617 | bus = pci_create_root_bus(hose->parent, hose->first_busno, |
1618 | hose->ops, hose, &resources); | |
0ed2c722 GL |
1619 | if (bus == NULL) { |
1620 | pr_err("Failed to create bus for PCI domain %04x\n", | |
1621 | hose->global_number); | |
45a709f8 | 1622 | pci_free_resource_list(&resources); |
0ed2c722 GL |
1623 | return; |
1624 | } | |
0ed2c722 GL |
1625 | hose->bus = bus; |
1626 | ||
0ed2c722 GL |
1627 | /* Get probe mode and perform scan */ |
1628 | mode = PCI_PROBE_NORMAL; | |
467efc2e DA |
1629 | if (node && hose->controller_ops.probe_mode) |
1630 | mode = hose->controller_ops.probe_mode(bus); | |
0ed2c722 | 1631 | pr_debug(" probe mode: %d\n", mode); |
be8e60d8 | 1632 | if (mode == PCI_PROBE_DEVTREE) |
0ed2c722 | 1633 | of_scan_bus(node, bus); |
0ed2c722 | 1634 | |
be8e60d8 YL |
1635 | if (mode == PCI_PROBE_NORMAL) { |
1636 | pci_bus_update_busn_res_end(bus, 255); | |
1637 | hose->last_busno = pci_scan_child_bus(bus); | |
1638 | pci_bus_update_busn_res_end(bus, hose->last_busno); | |
1639 | } | |
781fb7a3 | 1640 | |
491b98c3 BH |
1641 | /* Platform gets a chance to do some global fixups before |
1642 | * we proceed to resource allocation | |
1643 | */ | |
1644 | if (ppc_md.pcibios_fixup_phb) | |
1645 | ppc_md.pcibios_fixup_phb(hose); | |
1646 | ||
781fb7a3 | 1647 | /* Configure PCI Express settings */ |
bb36c445 | 1648 | if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { |
781fb7a3 | 1649 | struct pci_bus *child; |
a58674ff BH |
1650 | list_for_each_entry(child, &bus->children, node) |
1651 | pcie_bus_configure_settings(child); | |
781fb7a3 | 1652 | } |
0ed2c722 | 1653 | } |
5b64d2cc | 1654 | EXPORT_SYMBOL_GPL(pcibios_scan_phb); |
c065488f KG |
1655 | |
1656 | static void fixup_hide_host_resource_fsl(struct pci_dev *dev) | |
1657 | { | |
1658 | int i, class = dev->class >> 8; | |
05737c7c JJ |
1659 | /* When configured as agent, programing interface = 1 */ |
1660 | int prog_if = dev->class & 0xf; | |
c065488f KG |
1661 | |
1662 | if ((class == PCI_CLASS_PROCESSOR_POWERPC || | |
1663 | class == PCI_CLASS_BRIDGE_OTHER) && | |
1664 | (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && | |
05737c7c | 1665 | (prog_if == 0) && |
c065488f KG |
1666 | (dev->bus->parent == NULL)) { |
1667 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
1668 | dev->resource[i].start = 0; | |
1669 | dev->resource[i].end = 0; | |
1670 | dev->resource[i].flags = 0; | |
1671 | } | |
1672 | } | |
1673 | } | |
1674 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); | |
1675 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); |