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1da177e4 LT |
1 | /* |
2 | * Port for PPC64 David Engebretsen, IBM Corp. | |
3 | * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. | |
4 | * | |
5 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
6 | * Rework, based on alpha PCI code. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #undef DEBUG | |
15 | ||
1da177e4 LT |
16 | #include <linux/kernel.h> |
17 | #include <linux/pci.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/bootmem.h> | |
66b15db6 | 21 | #include <linux/export.h> |
1da177e4 LT |
22 | #include <linux/mm.h> |
23 | #include <linux/list.h> | |
b2ad7b5e | 24 | #include <linux/syscalls.h> |
6e99e458 | 25 | #include <linux/irq.h> |
3d5134ee | 26 | #include <linux/vmalloc.h> |
1da177e4 LT |
27 | |
28 | #include <asm/processor.h> | |
29 | #include <asm/io.h> | |
30 | #include <asm/prom.h> | |
31 | #include <asm/pci-bridge.h> | |
32 | #include <asm/byteorder.h> | |
1da177e4 | 33 | #include <asm/machdep.h> |
d387899f | 34 | #include <asm/ppc-pci.h> |
1da177e4 | 35 | |
1da177e4 LT |
36 | /* pci_io_base -- the base address from which io bars are offsets. |
37 | * This is the lowest I/O base address (so bar values are always positive), | |
38 | * and it *must* be the start of ISA space if an ISA bus exists because | |
3d5134ee BH |
39 | * ISA drivers use hard coded offsets. If no ISA bus exists nothing |
40 | * is mapped on the first 64K of IO space | |
1da177e4 | 41 | */ |
3d5134ee | 42 | unsigned long pci_io_base = ISA_IO_BASE; |
1da177e4 LT |
43 | EXPORT_SYMBOL(pci_io_base); |
44 | ||
1da177e4 LT |
45 | static int __init pcibios_init(void) |
46 | { | |
47 | struct pci_controller *hose, *tmp; | |
1da177e4 | 48 | |
3fd94c6b BH |
49 | printk(KERN_INFO "PCI: Probing PCI hardware\n"); |
50 | ||
53280323 | 51 | /* For now, override phys_mem_access_prot. If we need it,g |
1da177e4 LT |
52 | * later, we may move that initialization to each ppc_md |
53 | */ | |
54 | ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot; | |
55 | ||
1fd0f525 BH |
56 | /* On ppc64, we always enable PCI domains and we keep domain 0 |
57 | * backward compatible in /proc for video cards | |
58 | */ | |
0e47ff1c | 59 | pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0); |
1fd0f525 | 60 | |
1da177e4 | 61 | /* Scan all of the recorded PCI controllers. */ |
92eb4602 | 62 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
b5d937de | 63 | pcibios_scan_phb(hose); |
92eb4602 JR |
64 | pci_bus_add_devices(hose->bus); |
65 | } | |
1da177e4 | 66 | |
3fd94c6b BH |
67 | /* Call common code to handle resource allocation */ |
68 | pcibios_resource_survey(); | |
1da177e4 | 69 | |
e884e9c5 | 70 | printk(KERN_DEBUG "PCI: Probing PCI hardware done\n"); |
1da177e4 LT |
71 | |
72 | return 0; | |
73 | } | |
74 | ||
75 | subsys_initcall(pcibios_init); | |
76 | ||
3d5134ee | 77 | int pcibios_unmap_io_space(struct pci_bus *bus) |
1da177e4 | 78 | { |
3d5134ee | 79 | struct pci_controller *hose; |
1da177e4 | 80 | |
3d5134ee | 81 | WARN_ON(bus == NULL); |
de821204 | 82 | |
3d5134ee BH |
83 | /* If this is not a PHB, we only flush the hash table over |
84 | * the area mapped by this bridge. We don't play with the PTE | |
85 | * mappings since we might have to deal with sub-page alignemnts | |
86 | * so flushing the hash table is the only sane way to make sure | |
87 | * that no hash entries are covering that removed bridge area | |
88 | * while still allowing other busses overlapping those pages | |
94491685 BH |
89 | * |
90 | * Note: If we ever support P2P hotplug on Book3E, we'll have | |
91 | * to do an appropriate TLB flush here too | |
3d5134ee BH |
92 | */ |
93 | if (bus->self) { | |
ce7a35c7 | 94 | #ifdef CONFIG_PPC_STD_MMU_64 |
3d5134ee | 95 | struct resource *res = bus->resource[0]; |
ce7a35c7 | 96 | #endif |
1da177e4 | 97 | |
b0494bc8 BH |
98 | pr_debug("IO unmapping for PCI-PCI bridge %s\n", |
99 | pci_name(bus->self)); | |
de821204 | 100 | |
94491685 | 101 | #ifdef CONFIG_PPC_STD_MMU_64 |
3d5134ee | 102 | __flush_hash_table_range(&init_mm, res->start + _IO_BASE, |
b30115ea | 103 | res->end + _IO_BASE + 1); |
94491685 | 104 | #endif |
3d5134ee BH |
105 | return 0; |
106 | } | |
1da177e4 | 107 | |
3d5134ee BH |
108 | /* Get the host bridge */ |
109 | hose = pci_bus_to_host(bus); | |
1da177e4 | 110 | |
3d5134ee | 111 | /* Check if we have IOs allocated */ |
b0d436c7 | 112 | if (hose->io_base_alloc == NULL) |
3d5134ee | 113 | return 0; |
de821204 | 114 | |
b0494bc8 BH |
115 | pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name); |
116 | pr_debug(" alloc=0x%p\n", hose->io_base_alloc); | |
1da177e4 | 117 | |
3d5134ee BH |
118 | /* This is a PHB, we fully unmap the IO area */ |
119 | vunmap(hose->io_base_alloc); | |
1da177e4 | 120 | |
3d5134ee | 121 | return 0; |
1da177e4 | 122 | } |
3d5134ee | 123 | EXPORT_SYMBOL_GPL(pcibios_unmap_io_space); |
1da177e4 | 124 | |
cad5cef6 | 125 | static int pcibios_map_phb_io_space(struct pci_controller *hose) |
1da177e4 | 126 | { |
3d5134ee BH |
127 | struct vm_struct *area; |
128 | unsigned long phys_page; | |
129 | unsigned long size_page; | |
130 | unsigned long io_virt_offset; | |
1da177e4 | 131 | |
3d5134ee BH |
132 | phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE); |
133 | size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE); | |
1da177e4 | 134 | |
3d5134ee BH |
135 | /* Make sure IO area address is clear */ |
136 | hose->io_base_alloc = NULL; | |
1da177e4 | 137 | |
3d5134ee BH |
138 | /* If there's no IO to map on that bus, get away too */ |
139 | if (hose->pci_io_size == 0 || hose->io_base_phys == 0) | |
140 | return 0; | |
1da177e4 | 141 | |
3d5134ee BH |
142 | /* Let's allocate some IO space for that guy. We don't pass |
143 | * VM_IOREMAP because we don't care about alignment tricks that | |
144 | * the core does in that case. Maybe we should due to stupid card | |
145 | * with incomplete address decoding but I'd rather not deal with | |
146 | * those outside of the reserved 64K legacy region. | |
147 | */ | |
148 | area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END); | |
149 | if (area == NULL) | |
150 | return -ENOMEM; | |
151 | hose->io_base_alloc = area->addr; | |
152 | hose->io_base_virt = (void __iomem *)(area->addr + | |
153 | hose->io_base_phys - phys_page); | |
154 | ||
b0494bc8 | 155 | pr_debug("IO mapping for PHB %s\n", hose->dn->full_name); |
9477e455 | 156 | pr_debug(" phys=0x%016llx, virt=0x%p (alloc=0x%p)\n", |
b0494bc8 | 157 | hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc); |
bcba0778 | 158 | pr_debug(" size=0x%016llx (alloc=0x%016lx)\n", |
b0494bc8 | 159 | hose->pci_io_size, size_page); |
3d5134ee BH |
160 | |
161 | /* Establish the mapping */ | |
162 | if (__ioremap_at(phys_page, area->addr, size_page, | |
163 | _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL) | |
164 | return -ENOMEM; | |
165 | ||
166 | /* Fixup hose IO resource */ | |
38973ba7 | 167 | io_virt_offset = pcibios_io_space_offset(hose); |
3d5134ee BH |
168 | hose->io_resource.start += io_virt_offset; |
169 | hose->io_resource.end += io_virt_offset; | |
170 | ||
518fdae2 | 171 | pr_debug(" hose->io_resource=%pR\n", &hose->io_resource); |
1da177e4 LT |
172 | |
173 | return 0; | |
174 | } | |
49a6cba4 | 175 | |
cad5cef6 | 176 | int pcibios_map_io_space(struct pci_bus *bus) |
49a6cba4 BH |
177 | { |
178 | WARN_ON(bus == NULL); | |
179 | ||
180 | /* If this not a PHB, nothing to do, page tables still exist and | |
181 | * thus HPTEs will be faulted in when needed | |
182 | */ | |
183 | if (bus->self) { | |
184 | pr_debug("IO mapping for PCI-PCI bridge %s\n", | |
185 | pci_name(bus->self)); | |
186 | pr_debug(" virt=0x%016llx...0x%016llx\n", | |
187 | bus->resource[0]->start + _IO_BASE, | |
188 | bus->resource[0]->end + _IO_BASE); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | return pcibios_map_phb_io_space(pci_bus_to_host(bus)); | |
193 | } | |
3d5134ee | 194 | EXPORT_SYMBOL_GPL(pcibios_map_io_space); |
1da177e4 | 195 | |
cad5cef6 | 196 | void pcibios_setup_phb_io_space(struct pci_controller *hose) |
0ed2c722 | 197 | { |
49a6cba4 | 198 | pcibios_map_phb_io_space(hose); |
0ed2c722 GL |
199 | } |
200 | ||
b2ad7b5e PM |
201 | #define IOBASE_BRIDGE_NUMBER 0 |
202 | #define IOBASE_MEMORY 1 | |
203 | #define IOBASE_IO 2 | |
204 | #define IOBASE_ISA_IO 3 | |
205 | #define IOBASE_ISA_MEM 4 | |
206 | ||
207 | long sys_pciconfig_iobase(long which, unsigned long in_bus, | |
208 | unsigned long in_devfn) | |
209 | { | |
210 | struct pci_controller* hose; | |
b2ad7b5e PM |
211 | struct pci_bus *bus = NULL; |
212 | struct device_node *hose_node; | |
213 | ||
214 | /* Argh ! Please forgive me for that hack, but that's the | |
215 | * simplest way to get existing XFree to not lockup on some | |
216 | * G5 machines... So when something asks for bus 0 io base | |
217 | * (bus 0 is HT root), we return the AGP one instead. | |
218 | */ | |
71a157e8 | 219 | if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) { |
16124f10 PM |
220 | struct device_node *agp; |
221 | ||
222 | agp = of_find_compatible_node(NULL, NULL, "u3-agp"); | |
223 | if (agp) | |
b2ad7b5e | 224 | in_bus = 0xf0; |
16124f10 PM |
225 | of_node_put(agp); |
226 | } | |
b2ad7b5e PM |
227 | |
228 | /* That syscall isn't quite compatible with PCI domains, but it's | |
229 | * used on pre-domains setup. We return the first match | |
230 | */ | |
231 | ||
3bc95598 | 232 | list_for_each_entry(bus, &pci_root_buses, node) { |
b918c62e | 233 | if (in_bus >= bus->number && in_bus <= bus->busn_res.end) |
b2ad7b5e PM |
234 | break; |
235 | bus = NULL; | |
236 | } | |
b5d937de | 237 | if (bus == NULL || bus->dev.of_node == NULL) |
b2ad7b5e PM |
238 | return -ENODEV; |
239 | ||
b5d937de | 240 | hose_node = bus->dev.of_node; |
b2ad7b5e PM |
241 | hose = PCI_DN(hose_node)->phb; |
242 | ||
243 | switch (which) { | |
244 | case IOBASE_BRIDGE_NUMBER: | |
245 | return (long)hose->first_busno; | |
246 | case IOBASE_MEMORY: | |
3fd47f06 | 247 | return (long)hose->mem_offset[0]; |
b2ad7b5e PM |
248 | case IOBASE_IO: |
249 | return (long)hose->io_base_phys; | |
250 | case IOBASE_ISA_IO: | |
251 | return (long)isa_io_base; | |
252 | case IOBASE_ISA_MEM: | |
253 | return -EINVAL; | |
254 | } | |
255 | ||
256 | return -EOPNOTSUPP; | |
257 | } | |
357518fa AB |
258 | |
259 | #ifdef CONFIG_NUMA | |
260 | int pcibus_to_node(struct pci_bus *bus) | |
261 | { | |
262 | struct pci_controller *phb = pci_bus_to_host(bus); | |
263 | return phb->node; | |
264 | } | |
265 | EXPORT_SYMBOL(pcibus_to_node); | |
266 | #endif | |
b72c1f65 BH |
267 | |
268 | static void quirk_radeon_32bit_msi(struct pci_dev *dev) | |
269 | { | |
270 | struct pci_dn *pdn = pci_get_pdn(dev); | |
271 | ||
272 | if (pdn) | |
0c69f9c5 | 273 | pdn->force_32bit_msi = true; |
b72c1f65 BH |
274 | } |
275 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x68f2, quirk_radeon_32bit_msi); | |
276 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0xaa68, quirk_radeon_32bit_msi); |