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fbe65447 GL |
1 | /* |
2 | * Helper routines to scan the device tree for PCI devices and busses | |
3 | * | |
4 | * Migrated out of PowerPC architecture pci_64.c file by Grant Likely | |
5 | * <grant.likely@secretlab.ca> so that these routines are available for | |
6 | * 32 bit also. | |
7 | * | |
8 | * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM | |
9 | * Rework, based on alpha PCI code. | |
10 | * Copyright (c) 2009 Secret Lab Technologies Ltd. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License | |
14 | * version 2 as published by the Free Software Foundation. | |
15 | */ | |
16 | ||
17 | #include <linux/pci.h> | |
66b15db6 | 18 | #include <linux/export.h> |
fbe65447 GL |
19 | #include <asm/pci-bridge.h> |
20 | #include <asm/prom.h> | |
21 | ||
22 | /** | |
23 | * get_int_prop - Decode a u32 from a device tree property | |
24 | */ | |
25 | static u32 get_int_prop(struct device_node *np, const char *name, u32 def) | |
26 | { | |
a795dc54 | 27 | const __be32 *prop; |
fbe65447 GL |
28 | int len; |
29 | ||
30 | prop = of_get_property(np, name, &len); | |
31 | if (prop && len >= 4) | |
a795dc54 | 32 | return of_read_number(prop, 1); |
fbe65447 GL |
33 | return def; |
34 | } | |
35 | ||
36 | /** | |
37 | * pci_parse_of_flags - Parse the flags cell of a device tree PCI address | |
38 | * @addr0: value of 1st cell of a device tree PCI address. | |
39 | * @bridge: Set this flag if the address is from a bridge 'ranges' property | |
40 | */ | |
e51df2c1 | 41 | static unsigned int pci_parse_of_flags(u32 addr0, int bridge) |
fbe65447 GL |
42 | { |
43 | unsigned int flags = 0; | |
44 | ||
45 | if (addr0 & 0x02000000) { | |
46 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
47 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
48 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
49 | if (addr0 & 0x40000000) | |
50 | flags |= IORESOURCE_PREFETCH | |
51 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
52 | /* Note: We don't know whether the ROM has been left enabled | |
53 | * by the firmware or not. We mark it as disabled (ie, we do | |
54 | * not set the IORESOURCE_ROM_ENABLE flag) for now rather than | |
55 | * do a config space read, it will be force-enabled if needed | |
56 | */ | |
57 | if (!bridge && (addr0 & 0xff) == 0x30) | |
58 | flags |= IORESOURCE_READONLY; | |
59 | } else if (addr0 & 0x01000000) | |
60 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
61 | if (flags) | |
62 | flags |= IORESOURCE_SIZEALIGN; | |
63 | return flags; | |
64 | } | |
65 | ||
66 | /** | |
67 | * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node | |
68 | * @node: device tree node for the PCI device | |
69 | * @dev: pci_dev structure for the device | |
70 | * | |
71 | * This function parses the 'assigned-addresses' property of a PCI devices' | |
72 | * device tree node and writes them into the associated pci_dev structure. | |
73 | */ | |
74 | static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev) | |
75 | { | |
76 | u64 base, size; | |
77 | unsigned int flags; | |
39aa146a | 78 | struct pci_bus_region region; |
fbe65447 | 79 | struct resource *res; |
a795dc54 | 80 | const __be32 *addrs; |
fbe65447 GL |
81 | u32 i; |
82 | int proplen; | |
83 | ||
84 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
85 | if (!addrs) | |
86 | return; | |
87 | pr_debug(" parse addresses (%d bytes) @ %p\n", proplen, addrs); | |
88 | for (; proplen >= 20; proplen -= 20, addrs += 5) { | |
a795dc54 | 89 | flags = pci_parse_of_flags(of_read_number(addrs, 1), 0); |
fbe65447 GL |
90 | if (!flags) |
91 | continue; | |
92 | base = of_read_number(&addrs[1], 2); | |
93 | size = of_read_number(&addrs[3], 2); | |
94 | if (!size) | |
95 | continue; | |
a795dc54 | 96 | i = of_read_number(addrs, 1) & 0xff; |
fbe65447 GL |
97 | pr_debug(" base: %llx, size: %llx, i: %x\n", |
98 | (unsigned long long)base, | |
99 | (unsigned long long)size, i); | |
100 | ||
101 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
102 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
103 | } else if (i == dev->rom_base_reg) { | |
104 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
92b19ff5 | 105 | flags |= IORESOURCE_READONLY; |
fbe65447 GL |
106 | } else { |
107 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
108 | continue; | |
109 | } | |
fbe65447 GL |
110 | res->flags = flags; |
111 | res->name = pci_name(dev); | |
39aa146a BH |
112 | region.start = base; |
113 | region.end = base + size - 1; | |
fc279850 | 114 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
fbe65447 GL |
115 | } |
116 | } | |
117 | ||
118 | /** | |
119 | * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev | |
120 | * @node: device tree node pointer | |
121 | * @bus: bus the device is sitting on | |
122 | * @devfn: PCI function number, extracted from device tree by caller. | |
123 | */ | |
124 | struct pci_dev *of_create_pci_dev(struct device_node *node, | |
125 | struct pci_bus *bus, int devfn) | |
126 | { | |
127 | struct pci_dev *dev; | |
128 | const char *type; | |
129 | ||
8b1fce04 | 130 | dev = pci_alloc_dev(bus); |
fbe65447 GL |
131 | if (!dev) |
132 | return NULL; | |
133 | type = of_get_property(node, "device_type", NULL); | |
134 | if (type == NULL) | |
135 | type = ""; | |
136 | ||
137 | pr_debug(" create device, devfn: %x, type: %s\n", devfn, type); | |
138 | ||
b5d937de | 139 | dev->dev.of_node = of_node_get(node); |
fbe65447 GL |
140 | dev->dev.parent = bus->bridge; |
141 | dev->dev.bus = &pci_bus_type; | |
142 | dev->devfn = devfn; | |
143 | dev->multifunction = 0; /* maybe a lie? */ | |
4406c56d | 144 | dev->needs_freset = 0; /* pcie fundamental reset required */ |
bb209c82 | 145 | set_pcie_port_type(dev); |
fbe65447 | 146 | |
017ffe64 | 147 | pci_dev_assign_slot(dev); |
fbe65447 GL |
148 | dev->vendor = get_int_prop(node, "vendor-id", 0xffff); |
149 | dev->device = get_int_prop(node, "device-id", 0xffff); | |
150 | dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0); | |
151 | dev->subsystem_device = get_int_prop(node, "subsystem-id", 0); | |
152 | ||
153 | dev->cfg_size = pci_cfg_space_size(dev); | |
154 | ||
155 | dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
156 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
157 | dev->class = get_int_prop(node, "class-code", 0); | |
158 | dev->revision = get_int_prop(node, "revision-id", 0); | |
159 | ||
160 | pr_debug(" class: 0x%x\n", dev->class); | |
161 | pr_debug(" revision: 0x%x\n", dev->revision); | |
162 | ||
c2defb5f | 163 | dev->current_state = PCI_UNKNOWN; /* unknown power state */ |
fbe65447 GL |
164 | dev->error_state = pci_channel_io_normal; |
165 | dev->dma_mask = 0xffffffff; | |
166 | ||
94afc008 BH |
167 | /* Early fixups, before probing the BARs */ |
168 | pci_fixup_device(pci_fixup_early, dev); | |
169 | ||
fbe65447 GL |
170 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
171 | /* a PCI-PCI bridge */ | |
172 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
173 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
bb209c82 | 174 | set_pcie_hotplug_bridge(dev); |
fbe65447 GL |
175 | } else if (!strcmp(type, "cardbus")) { |
176 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
177 | } else { | |
178 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
179 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
180 | /* Maybe do a default OF mapping here */ | |
ef24ba70 | 181 | dev->irq = 0; |
fbe65447 GL |
182 | } |
183 | ||
184 | of_pci_parse_addrs(node, dev); | |
185 | ||
186 | pr_debug(" adding to system ...\n"); | |
187 | ||
188 | pci_device_add(dev, bus); | |
189 | ||
190 | return dev; | |
191 | } | |
192 | EXPORT_SYMBOL(of_create_pci_dev); | |
193 | ||
194 | /** | |
195 | * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes | |
fbe65447 GL |
196 | * @dev: pci_dev structure for the bridge |
197 | * | |
198 | * of_scan_bus() calls this routine for each PCI bridge that it finds, and | |
199 | * this routine in turn call of_scan_bus() recusively to scan for more child | |
200 | * devices. | |
201 | */ | |
cad5cef6 | 202 | void of_scan_pci_bridge(struct pci_dev *dev) |
fbe65447 | 203 | { |
98d9f30c | 204 | struct device_node *node = dev->dev.of_node; |
fbe65447 | 205 | struct pci_bus *bus; |
467efc2e | 206 | struct pci_controller *phb; |
a795dc54 | 207 | const __be32 *busrange, *ranges; |
fbe65447 | 208 | int len, i, mode; |
39aa146a | 209 | struct pci_bus_region region; |
fbe65447 GL |
210 | struct resource *res; |
211 | unsigned int flags; | |
212 | u64 size; | |
213 | ||
214 | pr_debug("of_scan_pci_bridge(%s)\n", node->full_name); | |
215 | ||
216 | /* parse bus-range property */ | |
217 | busrange = of_get_property(node, "bus-range", &len); | |
218 | if (busrange == NULL || len != 8) { | |
219 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
220 | node->full_name); | |
221 | return; | |
222 | } | |
223 | ranges = of_get_property(node, "ranges", &len); | |
224 | if (ranges == NULL) { | |
225 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", | |
226 | node->full_name); | |
227 | return; | |
228 | } | |
229 | ||
a795dc54 AB |
230 | bus = pci_find_bus(pci_domain_nr(dev->bus), |
231 | of_read_number(busrange, 1)); | |
fbe65447 | 232 | if (!bus) { |
a795dc54 AB |
233 | bus = pci_add_new_bus(dev->bus, dev, |
234 | of_read_number(busrange, 1)); | |
ab444ec9 GS |
235 | if (!bus) { |
236 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
237 | node->full_name); | |
238 | return; | |
239 | } | |
fbe65447 GL |
240 | } |
241 | ||
242 | bus->primary = dev->bus->number; | |
a795dc54 AB |
243 | pci_bus_insert_busn_res(bus, of_read_number(busrange, 1), |
244 | of_read_number(busrange+1, 1)); | |
fbe65447 | 245 | bus->bridge_ctl = 0; |
fbe65447 GL |
246 | |
247 | /* parse ranges property */ | |
248 | /* PCI #address-cells == 3 and #size-cells == 2 always */ | |
249 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
250 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
251 | res->flags = 0; | |
252 | bus->resource[i] = res; | |
253 | ++res; | |
254 | } | |
255 | i = 1; | |
256 | for (; len >= 32; len -= 32, ranges += 8) { | |
a795dc54 | 257 | flags = pci_parse_of_flags(of_read_number(ranges, 1), 1); |
fbe65447 GL |
258 | size = of_read_number(&ranges[6], 2); |
259 | if (flags == 0 || size == 0) | |
260 | continue; | |
261 | if (flags & IORESOURCE_IO) { | |
262 | res = bus->resource[0]; | |
263 | if (res->flags) { | |
264 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
265 | " for bridge %s\n", node->full_name); | |
266 | continue; | |
267 | } | |
268 | } else { | |
269 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
270 | printk(KERN_ERR "PCI: too many memory ranges" | |
271 | " for bridge %s\n", node->full_name); | |
272 | continue; | |
273 | } | |
274 | res = bus->resource[i]; | |
275 | ++i; | |
276 | } | |
fbe65447 | 277 | res->flags = flags; |
39aa146a BH |
278 | region.start = of_read_number(&ranges[1], 2); |
279 | region.end = region.start + size - 1; | |
fc279850 | 280 | pcibios_bus_to_resource(dev->bus, res, ®ion); |
fbe65447 GL |
281 | } |
282 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), | |
283 | bus->number); | |
284 | pr_debug(" bus name: %s\n", bus->name); | |
285 | ||
467efc2e DA |
286 | phb = pci_bus_to_host(bus); |
287 | ||
fbe65447 | 288 | mode = PCI_PROBE_NORMAL; |
467efc2e DA |
289 | if (phb->controller_ops.probe_mode) |
290 | mode = phb->controller_ops.probe_mode(bus); | |
fbe65447 GL |
291 | pr_debug(" probe mode: %d\n", mode); |
292 | ||
293 | if (mode == PCI_PROBE_DEVTREE) | |
294 | of_scan_bus(node, bus); | |
295 | else if (mode == PCI_PROBE_NORMAL) | |
296 | pci_scan_child_bus(bus); | |
297 | } | |
298 | EXPORT_SYMBOL(of_scan_pci_bridge); | |
299 | ||
ab444ec9 GS |
300 | static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus, |
301 | struct device_node *dn) | |
302 | { | |
303 | struct pci_dev *dev = NULL; | |
3e7cec6b | 304 | const __be32 *reg; |
ab444ec9 | 305 | int reglen, devfn; |
d2b0f6f7 | 306 | #ifdef CONFIG_EEH |
c6406d8f | 307 | struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn)); |
d2b0f6f7 | 308 | #endif |
ab444ec9 GS |
309 | |
310 | pr_debug(" * %s\n", dn->full_name); | |
311 | if (!of_device_is_available(dn)) | |
312 | return NULL; | |
313 | ||
314 | reg = of_get_property(dn, "reg", ®len); | |
315 | if (reg == NULL || reglen < 20) | |
316 | return NULL; | |
3e7cec6b | 317 | devfn = (of_read_number(reg, 1) >> 8) & 0xff; |
ab444ec9 GS |
318 | |
319 | /* Check if the PCI device is already there */ | |
320 | dev = pci_get_slot(bus, devfn); | |
321 | if (dev) { | |
322 | pci_dev_put(dev); | |
323 | return dev; | |
324 | } | |
325 | ||
d2b0f6f7 GS |
326 | /* Device removed permanently ? */ |
327 | #ifdef CONFIG_EEH | |
328 | if (edev && (edev->mode & EEH_DEV_REMOVED)) | |
329 | return NULL; | |
330 | #endif | |
331 | ||
ab444ec9 GS |
332 | /* create a new pci_dev for this device */ |
333 | dev = of_create_pci_dev(dn, bus, devfn); | |
334 | if (!dev) | |
335 | return NULL; | |
336 | ||
337 | pr_debug(" dev header type: %x\n", dev->hdr_type); | |
338 | return dev; | |
339 | } | |
340 | ||
fbe65447 GL |
341 | /** |
342 | * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices | |
343 | * @node: device tree node for the PCI bus | |
344 | * @bus: pci_bus structure for the PCI bus | |
345 | * @rescan_existing: Flag indicating bus has already been set up | |
346 | */ | |
cad5cef6 GKH |
347 | static void __of_scan_bus(struct device_node *node, struct pci_bus *bus, |
348 | int rescan_existing) | |
fbe65447 GL |
349 | { |
350 | struct device_node *child; | |
fbe65447 GL |
351 | struct pci_dev *dev; |
352 | ||
8354be9c | 353 | pr_debug("of_scan_bus(%s) bus no %d...\n", |
fbe65447 GL |
354 | node->full_name, bus->number); |
355 | ||
356 | /* Scan direct children */ | |
357 | for_each_child_of_node(node, child) { | |
ab444ec9 | 358 | dev = of_scan_pci_dev(bus, child); |
fbe65447 GL |
359 | if (!dev) |
360 | continue; | |
361 | pr_debug(" dev header type: %x\n", dev->hdr_type); | |
362 | } | |
363 | ||
364 | /* Apply all fixups necessary. We don't fixup the bus "self" | |
365 | * for an existing bridge that is being rescanned | |
366 | */ | |
367 | if (!rescan_existing) | |
368 | pcibios_setup_bus_self(bus); | |
369 | pcibios_setup_bus_devices(bus); | |
370 | ||
371 | /* Now scan child busses */ | |
372 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
c888770e | 373 | if (pci_is_bridge(dev)) { |
98d9f30c | 374 | of_scan_pci_bridge(dev); |
fbe65447 GL |
375 | } |
376 | } | |
377 | } | |
378 | ||
379 | /** | |
380 | * of_scan_bus - given a PCI bus node, setup bus and scan for child devices | |
381 | * @node: device tree node for the PCI bus | |
382 | * @bus: pci_bus structure for the PCI bus | |
383 | */ | |
cad5cef6 | 384 | void of_scan_bus(struct device_node *node, struct pci_bus *bus) |
fbe65447 GL |
385 | { |
386 | __of_scan_bus(node, bus, 0); | |
387 | } | |
388 | EXPORT_SYMBOL_GPL(of_scan_bus); | |
389 | ||
390 | /** | |
391 | * of_rescan_bus - given a PCI bus node, scan for child devices | |
392 | * @node: device tree node for the PCI bus | |
393 | * @bus: pci_bus structure for the PCI bus | |
394 | * | |
395 | * Same as of_scan_bus, but for a pci_bus structure that has already been | |
396 | * setup. | |
397 | */ | |
cad5cef6 | 398 | void of_rescan_bus(struct device_node *node, struct pci_bus *bus) |
fbe65447 GL |
399 | { |
400 | __of_scan_bus(node, bus, 1); | |
401 | } | |
402 | EXPORT_SYMBOL_GPL(of_rescan_bus); | |
403 |