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16b06799 PM |
1 | /* |
2 | * Performance counter support for PPC970-family processors. | |
3 | * | |
4 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | */ | |
11 | #include <linux/string.h> | |
12 | #include <linux/perf_counter.h> | |
13 | #include <asm/reg.h> | |
14 | ||
15 | /* | |
16 | * Bits in event code for PPC970 | |
17 | */ | |
18 | #define PM_PMC_SH 12 /* PMC number (1-based) for direct events */ | |
19 | #define PM_PMC_MSK 0xf | |
20 | #define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */ | |
21 | #define PM_UNIT_MSK 0xf | |
22 | #define PM_BYTE_SH 4 /* Byte number of event bus to use */ | |
23 | #define PM_BYTE_MSK 3 | |
24 | #define PM_PMCSEL_MSK 0xf | |
25 | ||
26 | /* Values in PM_UNIT field */ | |
27 | #define PM_NONE 0 | |
28 | #define PM_FPU 1 | |
29 | #define PM_VPU 2 | |
30 | #define PM_ISU 3 | |
31 | #define PM_IFU 4 | |
32 | #define PM_IDU 5 | |
33 | #define PM_STS 6 | |
34 | #define PM_LSU0 7 | |
35 | #define PM_LSU1U 8 | |
36 | #define PM_LSU1L 9 | |
37 | #define PM_LASTUNIT 9 | |
38 | ||
39 | /* | |
40 | * Bits in MMCR0 for PPC970 | |
41 | */ | |
42 | #define MMCR0_PMC1SEL_SH 8 | |
43 | #define MMCR0_PMC2SEL_SH 1 | |
44 | #define MMCR_PMCSEL_MSK 0x1f | |
45 | ||
46 | /* | |
47 | * Bits in MMCR1 for PPC970 | |
48 | */ | |
49 | #define MMCR1_TTM0SEL_SH 62 | |
50 | #define MMCR1_TTM1SEL_SH 59 | |
51 | #define MMCR1_TTM3SEL_SH 53 | |
52 | #define MMCR1_TTMSEL_MSK 3 | |
53 | #define MMCR1_TD_CP_DBG0SEL_SH 50 | |
54 | #define MMCR1_TD_CP_DBG1SEL_SH 48 | |
55 | #define MMCR1_TD_CP_DBG2SEL_SH 46 | |
56 | #define MMCR1_TD_CP_DBG3SEL_SH 44 | |
57 | #define MMCR1_PMC1_ADDER_SEL_SH 39 | |
58 | #define MMCR1_PMC2_ADDER_SEL_SH 38 | |
59 | #define MMCR1_PMC6_ADDER_SEL_SH 37 | |
60 | #define MMCR1_PMC5_ADDER_SEL_SH 36 | |
61 | #define MMCR1_PMC8_ADDER_SEL_SH 35 | |
62 | #define MMCR1_PMC7_ADDER_SEL_SH 34 | |
63 | #define MMCR1_PMC3_ADDER_SEL_SH 33 | |
64 | #define MMCR1_PMC4_ADDER_SEL_SH 32 | |
65 | #define MMCR1_PMC3SEL_SH 27 | |
66 | #define MMCR1_PMC4SEL_SH 22 | |
67 | #define MMCR1_PMC5SEL_SH 17 | |
68 | #define MMCR1_PMC6SEL_SH 12 | |
69 | #define MMCR1_PMC7SEL_SH 7 | |
70 | #define MMCR1_PMC8SEL_SH 2 | |
71 | ||
72 | static short mmcr1_adder_bits[8] = { | |
73 | MMCR1_PMC1_ADDER_SEL_SH, | |
74 | MMCR1_PMC2_ADDER_SEL_SH, | |
75 | MMCR1_PMC3_ADDER_SEL_SH, | |
76 | MMCR1_PMC4_ADDER_SEL_SH, | |
77 | MMCR1_PMC5_ADDER_SEL_SH, | |
78 | MMCR1_PMC6_ADDER_SEL_SH, | |
79 | MMCR1_PMC7_ADDER_SEL_SH, | |
80 | MMCR1_PMC8_ADDER_SEL_SH | |
81 | }; | |
82 | ||
83 | /* | |
84 | * Bits in MMCRA | |
85 | */ | |
86 | ||
87 | /* | |
88 | * Layout of constraint bits: | |
89 | * 6666555555555544444444443333333333222222222211111111110000000000 | |
90 | * 3210987654321098765432109876543210987654321098765432109876543210 | |
91 | * <><>[ >[ >[ >< >< >< >< ><><><><><><><><> | |
92 | * T0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8 | |
93 | * | |
94 | * T0 - TTM0 constraint | |
95 | * 46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000 | |
96 | * | |
97 | * T1 - TTM1 constraint | |
98 | * 44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000 | |
99 | * | |
100 | * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS | |
101 | * 43: UC3 error 0x0800_0000_0000 | |
102 | * 42: FPU|IFU|VPU events needed 0x0400_0000_0000 | |
103 | * 41: ISU events needed 0x0200_0000_0000 | |
104 | * 40: IDU|STS events needed 0x0100_0000_0000 | |
105 | * | |
106 | * PS1 | |
107 | * 39: PS1 error 0x0080_0000_0000 | |
108 | * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000 | |
109 | * | |
110 | * PS2 | |
111 | * 35: PS2 error 0x0008_0000_0000 | |
112 | * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000 | |
113 | * | |
114 | * B0 | |
115 | * 28-31: Byte 0 event source 0xf000_0000 | |
116 | * Encoding as for the event code | |
117 | * | |
118 | * B1, B2, B3 | |
119 | * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources | |
120 | * | |
121 | * P1 | |
122 | * 15: P1 error 0x8000 | |
123 | * 14-15: Count of events needing PMC1 | |
124 | * | |
125 | * P2..P8 | |
126 | * 0-13: Count of events needing PMC2..PMC8 | |
127 | */ | |
128 | ||
129 | /* Masks and values for using events from the various units */ | |
130 | static u64 unit_cons[PM_LASTUNIT+1][2] = { | |
131 | [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull }, | |
132 | [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull }, | |
133 | [PM_ISU] = { 0x080000000000ull, 0x020000000000ull }, | |
134 | [PM_IFU] = { 0xc80000000000ull, 0x840000000000ull }, | |
135 | [PM_IDU] = { 0x380000000000ull, 0x010000000000ull }, | |
136 | [PM_STS] = { 0x380000000000ull, 0x310000000000ull }, | |
137 | }; | |
138 | ||
139 | static int p970_get_constraint(unsigned int event, u64 *maskp, u64 *valp) | |
140 | { | |
141 | int pmc, byte, unit, sh; | |
142 | u64 mask = 0, value = 0; | |
143 | int grp = -1; | |
144 | ||
145 | pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; | |
146 | if (pmc) { | |
147 | if (pmc > 8) | |
148 | return -1; | |
149 | sh = (pmc - 1) * 2; | |
150 | mask |= 2 << sh; | |
151 | value |= 1 << sh; | |
152 | grp = ((pmc - 1) >> 1) & 1; | |
153 | } | |
154 | unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; | |
155 | if (unit) { | |
156 | if (unit > PM_LASTUNIT) | |
157 | return -1; | |
158 | mask |= unit_cons[unit][0]; | |
159 | value |= unit_cons[unit][1]; | |
160 | byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; | |
161 | /* | |
162 | * Bus events on bytes 0 and 2 can be counted | |
163 | * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8. | |
164 | */ | |
165 | if (!pmc) | |
166 | grp = byte & 1; | |
167 | /* Set byte lane select field */ | |
168 | mask |= 0xfULL << (28 - 4 * byte); | |
169 | value |= (u64)unit << (28 - 4 * byte); | |
170 | } | |
171 | if (grp == 0) { | |
172 | /* increment PMC1/2/5/6 field */ | |
173 | mask |= 0x8000000000ull; | |
174 | value |= 0x1000000000ull; | |
175 | } else if (grp == 1) { | |
176 | /* increment PMC3/4/7/8 field */ | |
177 | mask |= 0x800000000ull; | |
178 | value |= 0x100000000ull; | |
179 | } | |
180 | *maskp = mask; | |
181 | *valp = value; | |
182 | return 0; | |
183 | } | |
184 | ||
185 | static int p970_get_alternatives(unsigned int event, unsigned int alt[]) | |
186 | { | |
187 | alt[0] = event; | |
188 | ||
189 | /* 2 alternatives for LSU empty */ | |
190 | if (event == 0x2002 || event == 0x3002) { | |
191 | alt[1] = event ^ 0x1000; | |
192 | return 2; | |
193 | } | |
194 | ||
195 | return 1; | |
196 | } | |
197 | ||
198 | static int p970_compute_mmcr(unsigned int event[], int n_ev, | |
199 | unsigned int hwc[], u64 mmcr[]) | |
200 | { | |
201 | u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; | |
202 | unsigned int pmc, unit, byte, psel; | |
203 | unsigned int ttm, grp; | |
204 | unsigned int pmc_inuse = 0; | |
205 | unsigned int pmc_grp_use[2]; | |
206 | unsigned char busbyte[4]; | |
207 | unsigned char unituse[16]; | |
208 | unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 }; | |
209 | unsigned char ttmuse[2]; | |
210 | unsigned char pmcsel[8]; | |
211 | int i; | |
212 | ||
213 | if (n_ev > 8) | |
214 | return -1; | |
215 | ||
216 | /* First pass to count resource use */ | |
217 | pmc_grp_use[0] = pmc_grp_use[1] = 0; | |
218 | memset(busbyte, 0, sizeof(busbyte)); | |
219 | memset(unituse, 0, sizeof(unituse)); | |
220 | for (i = 0; i < n_ev; ++i) { | |
221 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | |
222 | if (pmc) { | |
223 | if (pmc_inuse & (1 << (pmc - 1))) | |
224 | return -1; | |
225 | pmc_inuse |= 1 << (pmc - 1); | |
226 | /* count 1/2/5/6 vs 3/4/7/8 use */ | |
227 | ++pmc_grp_use[((pmc - 1) >> 1) & 1]; | |
228 | } | |
229 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | |
230 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | |
231 | if (unit) { | |
232 | if (unit > PM_LASTUNIT) | |
233 | return -1; | |
234 | if (!pmc) | |
235 | ++pmc_grp_use[byte & 1]; | |
236 | if (busbyte[byte] && busbyte[byte] != unit) | |
237 | return -1; | |
238 | busbyte[byte] = unit; | |
239 | unituse[unit] = 1; | |
240 | } | |
241 | } | |
242 | if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4) | |
243 | return -1; | |
244 | ||
245 | /* | |
246 | * Assign resources and set multiplexer selects. | |
247 | * | |
248 | * PM_ISU can go either on TTM0 or TTM1, but that's the only | |
249 | * choice we have to deal with. | |
250 | */ | |
251 | if (unituse[PM_ISU] & | |
252 | (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU])) | |
253 | unitmap[PM_ISU] = 2 | 4; /* move ISU to TTM1 */ | |
254 | /* Set TTM[01]SEL fields. */ | |
255 | ttmuse[0] = ttmuse[1] = 0; | |
256 | for (i = PM_FPU; i <= PM_STS; ++i) { | |
257 | if (!unituse[i]) | |
258 | continue; | |
259 | ttm = unitmap[i]; | |
260 | ++ttmuse[(ttm >> 2) & 1]; | |
261 | mmcr1 |= (u64)(ttm & ~4) << MMCR1_TTM1SEL_SH; | |
262 | } | |
263 | /* Check only one unit per TTMx */ | |
264 | if (ttmuse[0] > 1 || ttmuse[1] > 1) | |
265 | return -1; | |
266 | ||
267 | /* Set byte lane select fields and TTM3SEL. */ | |
268 | for (byte = 0; byte < 4; ++byte) { | |
269 | unit = busbyte[byte]; | |
270 | if (!unit) | |
271 | continue; | |
272 | if (unit <= PM_STS) | |
273 | ttm = (unitmap[unit] >> 2) & 1; | |
274 | else if (unit == PM_LSU0) | |
275 | ttm = 2; | |
276 | else { | |
277 | ttm = 3; | |
278 | if (unit == PM_LSU1L && byte >= 2) | |
279 | mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); | |
280 | } | |
281 | mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); | |
282 | } | |
283 | ||
284 | /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ | |
285 | memset(pmcsel, 0x8, sizeof(pmcsel)); /* 8 means don't count */ | |
286 | for (i = 0; i < n_ev; ++i) { | |
287 | pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; | |
288 | unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; | |
289 | byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK; | |
290 | psel = event[i] & PM_PMCSEL_MSK; | |
291 | if (!pmc) { | |
292 | /* Bus event or any-PMC direct event */ | |
293 | if (unit) | |
294 | psel |= 0x10 | ((byte & 2) << 2); | |
295 | else | |
296 | psel |= 8; | |
297 | for (pmc = 0; pmc < 8; ++pmc) { | |
298 | if (pmc_inuse & (1 << pmc)) | |
299 | continue; | |
300 | grp = (pmc >> 1) & 1; | |
301 | if (unit) { | |
302 | if (grp == (byte & 1)) | |
303 | break; | |
304 | } else if (pmc_grp_use[grp] < 4) { | |
305 | ++pmc_grp_use[grp]; | |
306 | break; | |
307 | } | |
308 | } | |
309 | pmc_inuse |= 1 << pmc; | |
310 | } else { | |
311 | /* Direct event */ | |
312 | --pmc; | |
313 | if (psel == 0 && (byte & 2)) | |
314 | /* add events on higher-numbered bus */ | |
315 | mmcr1 |= 1ull << mmcr1_adder_bits[pmc]; | |
316 | } | |
317 | pmcsel[pmc] = psel; | |
318 | hwc[i] = pmc; | |
319 | } | |
320 | for (pmc = 0; pmc < 2; ++pmc) | |
321 | mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc); | |
322 | for (; pmc < 8; ++pmc) | |
323 | mmcr1 |= (u64)pmcsel[pmc] << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); | |
324 | if (pmc_inuse & 1) | |
325 | mmcr0 |= MMCR0_PMC1CE; | |
326 | if (pmc_inuse & 0xfe) | |
327 | mmcr0 |= MMCR0_PMCjCE; | |
328 | ||
329 | mmcra |= 0x2000; /* mark only one IOP per PPC instruction */ | |
330 | ||
331 | /* Return MMCRx values */ | |
332 | mmcr[0] = mmcr0; | |
333 | mmcr[1] = mmcr1; | |
334 | mmcr[2] = mmcra; | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static void p970_disable_pmc(unsigned int pmc, u64 mmcr[]) | |
339 | { | |
340 | int shift, i; | |
341 | ||
342 | if (pmc <= 1) { | |
343 | shift = MMCR0_PMC1SEL_SH - 7 * pmc; | |
344 | i = 0; | |
345 | } else { | |
346 | shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2); | |
347 | i = 1; | |
348 | } | |
349 | /* | |
350 | * Setting the PMCxSEL field to 0x08 disables PMC x. | |
351 | */ | |
352 | mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift); | |
353 | } | |
354 | ||
355 | static int ppc970_generic_events[] = { | |
356 | [PERF_COUNT_CPU_CYCLES] = 7, | |
357 | [PERF_COUNT_INSTRUCTIONS] = 1, | |
358 | [PERF_COUNT_CACHE_REFERENCES] = 0x8810, /* PM_LD_REF_L1 */ | |
359 | [PERF_COUNT_CACHE_MISSES] = 0x3810, /* PM_LD_MISS_L1 */ | |
360 | [PERF_COUNT_BRANCH_INSTRUCTIONS] = 0x431, /* PM_BR_ISSUED */ | |
361 | [PERF_COUNT_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */ | |
362 | }; | |
363 | ||
364 | struct power_pmu ppc970_pmu = { | |
365 | .n_counter = 8, | |
366 | .max_alternatives = 2, | |
367 | .add_fields = 0x001100005555ull, | |
368 | .test_adder = 0x013300000000ull, | |
369 | .compute_mmcr = p970_compute_mmcr, | |
370 | .get_constraint = p970_get_constraint, | |
371 | .get_alternatives = p970_get_alternatives, | |
372 | .disable_pmc = p970_disable_pmc, | |
373 | .n_generic = ARRAY_SIZE(ppc970_generic_events), | |
374 | .generic_events = ppc970_generic_events, | |
375 | }; |