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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
14cf11af | 2 | /* |
14cf11af PM |
3 | * Derived from "arch/i386/kernel/process.c" |
4 | * Copyright (C) 1995 Linus Torvalds | |
5 | * | |
6 | * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and | |
7 | * Paul Mackerras (paulus@cs.anu.edu.au) | |
8 | * | |
9 | * PowerPC version | |
10 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
14cf11af PM |
11 | */ |
12 | ||
14cf11af PM |
13 | #include <linux/errno.h> |
14 | #include <linux/sched.h> | |
b17b0153 | 15 | #include <linux/sched/debug.h> |
29930025 | 16 | #include <linux/sched/task.h> |
68db0cf1 | 17 | #include <linux/sched/task_stack.h> |
14cf11af PM |
18 | #include <linux/kernel.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/smp.h> | |
14cf11af PM |
21 | #include <linux/stddef.h> |
22 | #include <linux/unistd.h> | |
23 | #include <linux/ptrace.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/user.h> | |
26 | #include <linux/elf.h> | |
14cf11af PM |
27 | #include <linux/prctl.h> |
28 | #include <linux/init_task.h> | |
4b16f8e2 | 29 | #include <linux/export.h> |
14cf11af PM |
30 | #include <linux/kallsyms.h> |
31 | #include <linux/mqueue.h> | |
32 | #include <linux/hardirq.h> | |
06d67d54 | 33 | #include <linux/utsname.h> |
6794c782 | 34 | #include <linux/ftrace.h> |
79741dd3 | 35 | #include <linux/kernel_stat.h> |
d839088c AB |
36 | #include <linux/personality.h> |
37 | #include <linux/random.h> | |
5aae8a53 | 38 | #include <linux/hw_breakpoint.h> |
7b051f66 | 39 | #include <linux/uaccess.h> |
7f92bc56 | 40 | #include <linux/elf-randomize.h> |
06bb53b3 | 41 | #include <linux/pkeys.h> |
fb2d9505 | 42 | #include <linux/seq_buf.h> |
14cf11af | 43 | |
14cf11af PM |
44 | #include <asm/io.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/mmu.h> | |
47 | #include <asm/prom.h> | |
76032de8 | 48 | #include <asm/machdep.h> |
c6622f63 | 49 | #include <asm/time.h> |
ae3a197e | 50 | #include <asm/runlatch.h> |
a7f31841 | 51 | #include <asm/syscalls.h> |
ae3a197e | 52 | #include <asm/switch_to.h> |
fb09692e | 53 | #include <asm/tm.h> |
ae3a197e | 54 | #include <asm/debug.h> |
06d67d54 PM |
55 | #ifdef CONFIG_PPC64 |
56 | #include <asm/firmware.h> | |
c2e480ba | 57 | #include <asm/hw_irq.h> |
06d67d54 | 58 | #endif |
7cedd601 | 59 | #include <asm/code-patching.h> |
7f92bc56 | 60 | #include <asm/exec.h> |
5d31a96e | 61 | #include <asm/livepatch.h> |
b92a226e | 62 | #include <asm/cpu_has_feature.h> |
0545d543 | 63 | #include <asm/asm-prototypes.h> |
c9386bfd | 64 | #include <asm/stacktrace.h> |
c1fe190c | 65 | #include <asm/hw_breakpoint.h> |
5d31a96e | 66 | |
d6a61bfc LM |
67 | #include <linux/kprobes.h> |
68 | #include <linux/kdebug.h> | |
14cf11af | 69 | |
8b3c34cf MN |
70 | /* Transactional Memory debug */ |
71 | #ifdef TM_DEBUG_SW | |
72 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
73 | #else | |
74 | #define TM_DEBUG(x...) do { } while(0) | |
75 | #endif | |
76 | ||
14cf11af PM |
77 | extern unsigned long _get_SP(void); |
78 | ||
d31626f7 | 79 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
54820530 ME |
80 | /* |
81 | * Are we running in "Suspend disabled" mode? If so we have to block any | |
82 | * sigreturn that would get us into suspended state, and we also warn in some | |
83 | * other paths that we should never reach with suspend disabled. | |
84 | */ | |
85 | bool tm_suspend_disabled __ro_after_init = false; | |
86 | ||
b86fd2bd | 87 | static void check_if_tm_restore_required(struct task_struct *tsk) |
d31626f7 PM |
88 | { |
89 | /* | |
90 | * If we are saving the current thread's registers, and the | |
91 | * thread is in a transactional state, set the TIF_RESTORE_TM | |
92 | * bit so that we know to restore the registers before | |
93 | * returning to userspace. | |
94 | */ | |
95 | if (tsk == current && tsk->thread.regs && | |
96 | MSR_TM_ACTIVE(tsk->thread.regs->msr) && | |
97 | !test_thread_flag(TIF_RESTORE_TM)) { | |
829023df | 98 | tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; |
d31626f7 PM |
99 | set_thread_flag(TIF_RESTORE_TM); |
100 | } | |
d31626f7 | 101 | } |
dc16b553 | 102 | |
d31626f7 | 103 | #else |
b86fd2bd | 104 | static inline void check_if_tm_restore_required(struct task_struct *tsk) { } |
d31626f7 PM |
105 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
106 | ||
3eb5d588 AB |
107 | bool strict_msr_control; |
108 | EXPORT_SYMBOL(strict_msr_control); | |
109 | ||
110 | static int __init enable_strict_msr_control(char *str) | |
111 | { | |
112 | strict_msr_control = true; | |
113 | pr_info("Enabling strict facility control\n"); | |
114 | ||
115 | return 0; | |
116 | } | |
117 | early_param("ppc_strict_facility_enable", enable_strict_msr_control); | |
118 | ||
e2b36d59 NP |
119 | /* notrace because it's called by restore_math */ |
120 | unsigned long notrace msr_check_and_set(unsigned long bits) | |
98da581e | 121 | { |
a0e72cf1 AB |
122 | unsigned long oldmsr = mfmsr(); |
123 | unsigned long newmsr; | |
98da581e | 124 | |
a0e72cf1 | 125 | newmsr = oldmsr | bits; |
98da581e | 126 | |
a0e72cf1 | 127 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
98da581e | 128 | newmsr |= MSR_VSX; |
a0e72cf1 | 129 | |
98da581e AB |
130 | if (oldmsr != newmsr) |
131 | mtmsr_isync(newmsr); | |
3cee070a CB |
132 | |
133 | return newmsr; | |
a0e72cf1 | 134 | } |
d1c72112 | 135 | EXPORT_SYMBOL_GPL(msr_check_and_set); |
98da581e | 136 | |
e2b36d59 NP |
137 | /* notrace because it's called by restore_math */ |
138 | void notrace __msr_check_and_clear(unsigned long bits) | |
a0e72cf1 AB |
139 | { |
140 | unsigned long oldmsr = mfmsr(); | |
141 | unsigned long newmsr; | |
142 | ||
143 | newmsr = oldmsr & ~bits; | |
144 | ||
a0e72cf1 AB |
145 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
146 | newmsr &= ~MSR_VSX; | |
a0e72cf1 AB |
147 | |
148 | if (oldmsr != newmsr) | |
149 | mtmsr_isync(newmsr); | |
150 | } | |
3eb5d588 | 151 | EXPORT_SYMBOL(__msr_check_and_clear); |
a0e72cf1 AB |
152 | |
153 | #ifdef CONFIG_PPC_FPU | |
1cdf039b | 154 | static void __giveup_fpu(struct task_struct *tsk) |
8792468d | 155 | { |
8eb98037 AB |
156 | unsigned long msr; |
157 | ||
8792468d | 158 | save_fpu(tsk); |
8eb98037 | 159 | msr = tsk->thread.regs->msr; |
fe1ef6bc | 160 | msr &= ~(MSR_FP|MSR_FE0|MSR_FE1); |
8792468d | 161 | if (cpu_has_feature(CPU_FTR_VSX)) |
8eb98037 | 162 | msr &= ~MSR_VSX; |
8eb98037 | 163 | tsk->thread.regs->msr = msr; |
8792468d CB |
164 | } |
165 | ||
a0e72cf1 AB |
166 | void giveup_fpu(struct task_struct *tsk) |
167 | { | |
168 | check_if_tm_restore_required(tsk); | |
169 | ||
170 | msr_check_and_set(MSR_FP); | |
98da581e | 171 | __giveup_fpu(tsk); |
a0e72cf1 | 172 | msr_check_and_clear(MSR_FP); |
98da581e AB |
173 | } |
174 | EXPORT_SYMBOL(giveup_fpu); | |
175 | ||
14cf11af PM |
176 | /* |
177 | * Make sure the floating-point register state in the | |
178 | * the thread_struct is up to date for task tsk. | |
179 | */ | |
180 | void flush_fp_to_thread(struct task_struct *tsk) | |
181 | { | |
182 | if (tsk->thread.regs) { | |
183 | /* | |
184 | * We need to disable preemption here because if we didn't, | |
185 | * another process could get scheduled after the regs->msr | |
186 | * test but before we have finished saving the FP registers | |
187 | * to the thread_struct. That process could take over the | |
188 | * FPU, and then when we get scheduled again we would store | |
189 | * bogus values for the remaining FP registers. | |
190 | */ | |
191 | preempt_disable(); | |
192 | if (tsk->thread.regs->msr & MSR_FP) { | |
14cf11af PM |
193 | /* |
194 | * This should only ever be called for current or | |
195 | * for a stopped child process. Since we save away | |
af1bbc3d | 196 | * the FP register state on context switch, |
14cf11af PM |
197 | * there is something wrong if a stopped child appears |
198 | * to still have its FP state in the CPU registers. | |
199 | */ | |
200 | BUG_ON(tsk != current); | |
b86fd2bd | 201 | giveup_fpu(tsk); |
14cf11af PM |
202 | } |
203 | preempt_enable(); | |
204 | } | |
205 | } | |
de56a948 | 206 | EXPORT_SYMBOL_GPL(flush_fp_to_thread); |
14cf11af PM |
207 | |
208 | void enable_kernel_fp(void) | |
209 | { | |
e909fb83 CB |
210 | unsigned long cpumsr; |
211 | ||
14cf11af PM |
212 | WARN_ON(preemptible()); |
213 | ||
e909fb83 | 214 | cpumsr = msr_check_and_set(MSR_FP); |
611b0e5c | 215 | |
d64d02ce AB |
216 | if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { |
217 | check_if_tm_restore_required(current); | |
e909fb83 CB |
218 | /* |
219 | * If a thread has already been reclaimed then the | |
220 | * checkpointed registers are on the CPU but have definitely | |
221 | * been saved by the reclaim code. Don't need to and *cannot* | |
222 | * giveup as this would save to the 'live' structure not the | |
223 | * checkpointed structure. | |
224 | */ | |
5c784c84 BL |
225 | if (!MSR_TM_ACTIVE(cpumsr) && |
226 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 227 | return; |
a0e72cf1 | 228 | __giveup_fpu(current); |
d64d02ce | 229 | } |
14cf11af PM |
230 | } |
231 | EXPORT_SYMBOL(enable_kernel_fp); | |
c83c192a CL |
232 | #else |
233 | static inline void __giveup_fpu(struct task_struct *tsk) { } | |
d1e1cf2e | 234 | #endif /* CONFIG_PPC_FPU */ |
14cf11af | 235 | |
14cf11af | 236 | #ifdef CONFIG_ALTIVEC |
6f515d84 CB |
237 | static void __giveup_altivec(struct task_struct *tsk) |
238 | { | |
8eb98037 AB |
239 | unsigned long msr; |
240 | ||
6f515d84 | 241 | save_altivec(tsk); |
8eb98037 AB |
242 | msr = tsk->thread.regs->msr; |
243 | msr &= ~MSR_VEC; | |
6f515d84 | 244 | if (cpu_has_feature(CPU_FTR_VSX)) |
8eb98037 | 245 | msr &= ~MSR_VSX; |
8eb98037 | 246 | tsk->thread.regs->msr = msr; |
6f515d84 CB |
247 | } |
248 | ||
98da581e AB |
249 | void giveup_altivec(struct task_struct *tsk) |
250 | { | |
98da581e AB |
251 | check_if_tm_restore_required(tsk); |
252 | ||
a0e72cf1 | 253 | msr_check_and_set(MSR_VEC); |
98da581e | 254 | __giveup_altivec(tsk); |
a0e72cf1 | 255 | msr_check_and_clear(MSR_VEC); |
98da581e AB |
256 | } |
257 | EXPORT_SYMBOL(giveup_altivec); | |
258 | ||
14cf11af PM |
259 | void enable_kernel_altivec(void) |
260 | { | |
e909fb83 CB |
261 | unsigned long cpumsr; |
262 | ||
14cf11af PM |
263 | WARN_ON(preemptible()); |
264 | ||
e909fb83 | 265 | cpumsr = msr_check_and_set(MSR_VEC); |
611b0e5c | 266 | |
d64d02ce AB |
267 | if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { |
268 | check_if_tm_restore_required(current); | |
e909fb83 CB |
269 | /* |
270 | * If a thread has already been reclaimed then the | |
271 | * checkpointed registers are on the CPU but have definitely | |
272 | * been saved by the reclaim code. Don't need to and *cannot* | |
273 | * giveup as this would save to the 'live' structure not the | |
274 | * checkpointed structure. | |
275 | */ | |
5c784c84 BL |
276 | if (!MSR_TM_ACTIVE(cpumsr) && |
277 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 278 | return; |
a0e72cf1 | 279 | __giveup_altivec(current); |
d64d02ce | 280 | } |
14cf11af PM |
281 | } |
282 | EXPORT_SYMBOL(enable_kernel_altivec); | |
283 | ||
284 | /* | |
285 | * Make sure the VMX/Altivec register state in the | |
286 | * the thread_struct is up to date for task tsk. | |
287 | */ | |
288 | void flush_altivec_to_thread(struct task_struct *tsk) | |
289 | { | |
290 | if (tsk->thread.regs) { | |
291 | preempt_disable(); | |
292 | if (tsk->thread.regs->msr & MSR_VEC) { | |
14cf11af | 293 | BUG_ON(tsk != current); |
b86fd2bd | 294 | giveup_altivec(tsk); |
14cf11af PM |
295 | } |
296 | preempt_enable(); | |
297 | } | |
298 | } | |
de56a948 | 299 | EXPORT_SYMBOL_GPL(flush_altivec_to_thread); |
14cf11af PM |
300 | #endif /* CONFIG_ALTIVEC */ |
301 | ||
ce48b210 | 302 | #ifdef CONFIG_VSX |
bf6a4d5b | 303 | static void __giveup_vsx(struct task_struct *tsk) |
a7d623d4 | 304 | { |
dc801081 BH |
305 | unsigned long msr = tsk->thread.regs->msr; |
306 | ||
307 | /* | |
308 | * We should never be ssetting MSR_VSX without also setting | |
309 | * MSR_FP and MSR_VEC | |
310 | */ | |
311 | WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); | |
312 | ||
313 | /* __giveup_fpu will clear MSR_VSX */ | |
314 | if (msr & MSR_FP) | |
a7d623d4 | 315 | __giveup_fpu(tsk); |
dc801081 | 316 | if (msr & MSR_VEC) |
a7d623d4 | 317 | __giveup_altivec(tsk); |
bf6a4d5b CB |
318 | } |
319 | ||
320 | static void giveup_vsx(struct task_struct *tsk) | |
321 | { | |
322 | check_if_tm_restore_required(tsk); | |
323 | ||
324 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); | |
a7d623d4 | 325 | __giveup_vsx(tsk); |
a0e72cf1 | 326 | msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); |
a7d623d4 | 327 | } |
bf6a4d5b | 328 | |
ce48b210 MN |
329 | void enable_kernel_vsx(void) |
330 | { | |
e909fb83 CB |
331 | unsigned long cpumsr; |
332 | ||
ce48b210 MN |
333 | WARN_ON(preemptible()); |
334 | ||
e909fb83 | 335 | cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); |
611b0e5c | 336 | |
5a69aec9 BH |
337 | if (current->thread.regs && |
338 | (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { | |
d64d02ce | 339 | check_if_tm_restore_required(current); |
e909fb83 CB |
340 | /* |
341 | * If a thread has already been reclaimed then the | |
342 | * checkpointed registers are on the CPU but have definitely | |
343 | * been saved by the reclaim code. Don't need to and *cannot* | |
344 | * giveup as this would save to the 'live' structure not the | |
345 | * checkpointed structure. | |
346 | */ | |
5c784c84 BL |
347 | if (!MSR_TM_ACTIVE(cpumsr) && |
348 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 349 | return; |
a0e72cf1 | 350 | __giveup_vsx(current); |
611b0e5c | 351 | } |
ce48b210 MN |
352 | } |
353 | EXPORT_SYMBOL(enable_kernel_vsx); | |
ce48b210 MN |
354 | |
355 | void flush_vsx_to_thread(struct task_struct *tsk) | |
356 | { | |
357 | if (tsk->thread.regs) { | |
358 | preempt_disable(); | |
5a69aec9 | 359 | if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { |
ce48b210 | 360 | BUG_ON(tsk != current); |
ce48b210 MN |
361 | giveup_vsx(tsk); |
362 | } | |
363 | preempt_enable(); | |
364 | } | |
365 | } | |
de56a948 | 366 | EXPORT_SYMBOL_GPL(flush_vsx_to_thread); |
ce48b210 MN |
367 | #endif /* CONFIG_VSX */ |
368 | ||
14cf11af | 369 | #ifdef CONFIG_SPE |
98da581e AB |
370 | void giveup_spe(struct task_struct *tsk) |
371 | { | |
98da581e AB |
372 | check_if_tm_restore_required(tsk); |
373 | ||
a0e72cf1 | 374 | msr_check_and_set(MSR_SPE); |
98da581e | 375 | __giveup_spe(tsk); |
a0e72cf1 | 376 | msr_check_and_clear(MSR_SPE); |
98da581e AB |
377 | } |
378 | EXPORT_SYMBOL(giveup_spe); | |
14cf11af PM |
379 | |
380 | void enable_kernel_spe(void) | |
381 | { | |
382 | WARN_ON(preemptible()); | |
383 | ||
a0e72cf1 | 384 | msr_check_and_set(MSR_SPE); |
611b0e5c | 385 | |
d64d02ce AB |
386 | if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { |
387 | check_if_tm_restore_required(current); | |
a0e72cf1 | 388 | __giveup_spe(current); |
d64d02ce | 389 | } |
14cf11af PM |
390 | } |
391 | EXPORT_SYMBOL(enable_kernel_spe); | |
392 | ||
393 | void flush_spe_to_thread(struct task_struct *tsk) | |
394 | { | |
395 | if (tsk->thread.regs) { | |
396 | preempt_disable(); | |
397 | if (tsk->thread.regs->msr & MSR_SPE) { | |
14cf11af | 398 | BUG_ON(tsk != current); |
685659ee | 399 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); |
0ee6c15e | 400 | giveup_spe(tsk); |
14cf11af PM |
401 | } |
402 | preempt_enable(); | |
403 | } | |
404 | } | |
14cf11af PM |
405 | #endif /* CONFIG_SPE */ |
406 | ||
c2085059 AB |
407 | static unsigned long msr_all_available; |
408 | ||
409 | static int __init init_msr_all_available(void) | |
410 | { | |
c83c192a CL |
411 | if (IS_ENABLED(CONFIG_PPC_FPU)) |
412 | msr_all_available |= MSR_FP; | |
c2085059 AB |
413 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
414 | msr_all_available |= MSR_VEC; | |
c2085059 AB |
415 | if (cpu_has_feature(CPU_FTR_VSX)) |
416 | msr_all_available |= MSR_VSX; | |
c2085059 AB |
417 | if (cpu_has_feature(CPU_FTR_SPE)) |
418 | msr_all_available |= MSR_SPE; | |
c2085059 AB |
419 | |
420 | return 0; | |
421 | } | |
422 | early_initcall(init_msr_all_available); | |
423 | ||
424 | void giveup_all(struct task_struct *tsk) | |
425 | { | |
426 | unsigned long usermsr; | |
427 | ||
428 | if (!tsk->thread.regs) | |
429 | return; | |
430 | ||
8205d5d9 GR |
431 | check_if_tm_restore_required(tsk); |
432 | ||
c2085059 AB |
433 | usermsr = tsk->thread.regs->msr; |
434 | ||
435 | if ((usermsr & msr_all_available) == 0) | |
436 | return; | |
437 | ||
438 | msr_check_and_set(msr_all_available); | |
439 | ||
96c79b6b BH |
440 | WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); |
441 | ||
c2085059 AB |
442 | if (usermsr & MSR_FP) |
443 | __giveup_fpu(tsk); | |
c2085059 AB |
444 | if (usermsr & MSR_VEC) |
445 | __giveup_altivec(tsk); | |
c2085059 AB |
446 | if (usermsr & MSR_SPE) |
447 | __giveup_spe(tsk); | |
c2085059 AB |
448 | |
449 | msr_check_and_clear(msr_all_available); | |
450 | } | |
451 | EXPORT_SYMBOL(giveup_all); | |
452 | ||
6cc0c16d NP |
453 | #ifdef CONFIG_PPC_BOOK3S_64 |
454 | #ifdef CONFIG_PPC_FPU | |
01eb0187 | 455 | static bool should_restore_fp(void) |
6cc0c16d | 456 | { |
01eb0187 | 457 | if (current->thread.load_fp) { |
6cc0c16d | 458 | current->thread.load_fp++; |
01eb0187 | 459 | return true; |
6cc0c16d | 460 | } |
01eb0187 NP |
461 | return false; |
462 | } | |
463 | ||
464 | static void do_restore_fp(void) | |
465 | { | |
466 | load_fp_state(¤t->thread.fp_state); | |
6cc0c16d NP |
467 | } |
468 | #else | |
01eb0187 NP |
469 | static bool should_restore_fp(void) { return false; } |
470 | static void do_restore_fp(void) { } | |
6cc0c16d NP |
471 | #endif /* CONFIG_PPC_FPU */ |
472 | ||
473 | #ifdef CONFIG_ALTIVEC | |
01eb0187 | 474 | static bool should_restore_altivec(void) |
6cc0c16d | 475 | { |
01eb0187 NP |
476 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && (current->thread.load_vec)) { |
477 | current->thread.load_vec++; | |
478 | return true; | |
6cc0c16d | 479 | } |
01eb0187 NP |
480 | return false; |
481 | } | |
482 | ||
483 | static void do_restore_altivec(void) | |
484 | { | |
485 | load_vr_state(¤t->thread.vr_state); | |
486 | current->thread.used_vr = 1; | |
6cc0c16d NP |
487 | } |
488 | #else | |
01eb0187 NP |
489 | static bool should_restore_altivec(void) { return false; } |
490 | static void do_restore_altivec(void) { } | |
6cc0c16d NP |
491 | #endif /* CONFIG_ALTIVEC */ |
492 | ||
01eb0187 | 493 | static bool should_restore_vsx(void) |
6cc0c16d | 494 | { |
01eb0187 NP |
495 | if (cpu_has_feature(CPU_FTR_VSX)) |
496 | return true; | |
497 | return false; | |
498 | } | |
80739c2b | 499 | #ifdef CONFIG_VSX |
01eb0187 NP |
500 | static void do_restore_vsx(void) |
501 | { | |
502 | current->thread.used_vsr = 1; | |
6cc0c16d NP |
503 | } |
504 | #else | |
01eb0187 | 505 | static void do_restore_vsx(void) { } |
6cc0c16d NP |
506 | #endif /* CONFIG_VSX */ |
507 | ||
e2b36d59 NP |
508 | /* |
509 | * The exception exit path calls restore_math() with interrupts hard disabled | |
510 | * but the soft irq state not "reconciled". ftrace code that calls | |
511 | * local_irq_save/restore causes warnings. | |
512 | * | |
513 | * Rather than complicate the exit path, just don't trace restore_math. This | |
514 | * could be done by having ftrace entry code check for this un-reconciled | |
515 | * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and | |
516 | * temporarily fix it up for the duration of the ftrace call. | |
517 | */ | |
518 | void notrace restore_math(struct pt_regs *regs) | |
70fe3d98 CB |
519 | { |
520 | unsigned long msr; | |
01eb0187 | 521 | unsigned long new_msr = 0; |
70fe3d98 CB |
522 | |
523 | msr = regs->msr; | |
70fe3d98 CB |
524 | |
525 | /* | |
01eb0187 NP |
526 | * new_msr tracks the facilities that are to be restored. Only reload |
527 | * if the bit is not set in the user MSR (if it is set, the registers | |
528 | * are live for the user thread). | |
70fe3d98 | 529 | */ |
01eb0187 | 530 | if ((!(msr & MSR_FP)) && should_restore_fp()) |
b91eb518 | 531 | new_msr |= MSR_FP; |
70fe3d98 | 532 | |
01eb0187 NP |
533 | if ((!(msr & MSR_VEC)) && should_restore_altivec()) |
534 | new_msr |= MSR_VEC; | |
70fe3d98 | 535 | |
01eb0187 NP |
536 | if ((!(msr & MSR_VSX)) && should_restore_vsx()) { |
537 | if (((msr | new_msr) & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) | |
538 | new_msr |= MSR_VSX; | |
70fe3d98 CB |
539 | } |
540 | ||
01eb0187 | 541 | if (new_msr) { |
b91eb518 ME |
542 | unsigned long fpexc_mode = 0; |
543 | ||
01eb0187 NP |
544 | msr_check_and_set(new_msr); |
545 | ||
b91eb518 | 546 | if (new_msr & MSR_FP) { |
01eb0187 NP |
547 | do_restore_fp(); |
548 | ||
b91eb518 ME |
549 | // This also covers VSX, because VSX implies FP |
550 | fpexc_mode = current->thread.fpexc_mode; | |
551 | } | |
552 | ||
01eb0187 NP |
553 | if (new_msr & MSR_VEC) |
554 | do_restore_altivec(); | |
70fe3d98 | 555 | |
01eb0187 NP |
556 | if (new_msr & MSR_VSX) |
557 | do_restore_vsx(); | |
558 | ||
559 | msr_check_and_clear(new_msr); | |
560 | ||
b91eb518 | 561 | regs->msr |= new_msr | fpexc_mode; |
01eb0187 | 562 | } |
70fe3d98 | 563 | } |
60d62bfd | 564 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
70fe3d98 | 565 | |
1cdf039b | 566 | static void save_all(struct task_struct *tsk) |
de2a20aa CB |
567 | { |
568 | unsigned long usermsr; | |
569 | ||
570 | if (!tsk->thread.regs) | |
571 | return; | |
572 | ||
573 | usermsr = tsk->thread.regs->msr; | |
574 | ||
575 | if ((usermsr & msr_all_available) == 0) | |
576 | return; | |
577 | ||
578 | msr_check_and_set(msr_all_available); | |
579 | ||
96c79b6b BH |
580 | WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); |
581 | ||
582 | if (usermsr & MSR_FP) | |
583 | save_fpu(tsk); | |
584 | ||
585 | if (usermsr & MSR_VEC) | |
586 | save_altivec(tsk); | |
de2a20aa CB |
587 | |
588 | if (usermsr & MSR_SPE) | |
589 | __giveup_spe(tsk); | |
590 | ||
591 | msr_check_and_clear(msr_all_available); | |
592 | } | |
593 | ||
579e633e AB |
594 | void flush_all_to_thread(struct task_struct *tsk) |
595 | { | |
596 | if (tsk->thread.regs) { | |
597 | preempt_disable(); | |
598 | BUG_ON(tsk != current); | |
579e633e AB |
599 | #ifdef CONFIG_SPE |
600 | if (tsk->thread.regs->msr & MSR_SPE) | |
601 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); | |
602 | #endif | |
e9013785 | 603 | save_all(tsk); |
579e633e AB |
604 | |
605 | preempt_enable(); | |
606 | } | |
607 | } | |
608 | EXPORT_SYMBOL(flush_all_to_thread); | |
609 | ||
3bffb652 DK |
610 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
611 | void do_send_trap(struct pt_regs *regs, unsigned long address, | |
47355040 | 612 | unsigned long error_code, int breakpt) |
3bffb652 | 613 | { |
47355040 | 614 | current->thread.trap_nr = TRAP_HWBKPT; |
3bffb652 DK |
615 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
616 | 11, SIGSEGV) == NOTIFY_STOP) | |
617 | return; | |
618 | ||
619 | /* Deliver the signal to userspace */ | |
f71dd7dc EB |
620 | force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ |
621 | (void __user *)address); | |
3bffb652 DK |
622 | } |
623 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
5b905d77 RB |
624 | |
625 | static void do_break_handler(struct pt_regs *regs) | |
626 | { | |
627 | struct arch_hw_breakpoint null_brk = {0}; | |
628 | struct arch_hw_breakpoint *info; | |
629 | struct ppc_inst instr = ppc_inst(0); | |
630 | int type = 0; | |
631 | int size = 0; | |
632 | unsigned long ea; | |
633 | int i; | |
634 | ||
635 | /* | |
636 | * If underneath hw supports only one watchpoint, we know it | |
637 | * caused exception. 8xx also falls into this category. | |
638 | */ | |
639 | if (nr_wp_slots() == 1) { | |
640 | __set_breakpoint(0, &null_brk); | |
641 | current->thread.hw_brk[0] = null_brk; | |
642 | current->thread.hw_brk[0].flags |= HW_BRK_FLAG_DISABLED; | |
643 | return; | |
644 | } | |
645 | ||
646 | /* Otherwise findout which DAWR caused exception and disable it. */ | |
647 | wp_get_instr_detail(regs, &instr, &type, &size, &ea); | |
648 | ||
649 | for (i = 0; i < nr_wp_slots(); i++) { | |
650 | info = ¤t->thread.hw_brk[i]; | |
651 | if (!info->address) | |
652 | continue; | |
653 | ||
654 | if (wp_check_constraints(regs, instr, ea, type, size, info)) { | |
655 | __set_breakpoint(i, &null_brk); | |
656 | current->thread.hw_brk[i] = null_brk; | |
657 | current->thread.hw_brk[i].flags |= HW_BRK_FLAG_DISABLED; | |
658 | } | |
659 | } | |
660 | } | |
661 | ||
9422de3e | 662 | void do_break (struct pt_regs *regs, unsigned long address, |
d6a61bfc LM |
663 | unsigned long error_code) |
664 | { | |
41ab5266 | 665 | current->thread.trap_nr = TRAP_HWBKPT; |
d6a61bfc LM |
666 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
667 | 11, SIGSEGV) == NOTIFY_STOP) | |
668 | return; | |
669 | ||
9422de3e | 670 | if (debugger_break_match(regs)) |
d6a61bfc LM |
671 | return; |
672 | ||
5b905d77 RB |
673 | /* |
674 | * We reach here only when watchpoint exception is generated by ptrace | |
675 | * event (or hw is buggy!). Now if CONFIG_HAVE_HW_BREAKPOINT is set, | |
676 | * watchpoint is already handled by hw_breakpoint_handler() so we don't | |
677 | * have to do anything. But when CONFIG_HAVE_HW_BREAKPOINT is not set, | |
678 | * we need to manually handle the watchpoint here. | |
679 | */ | |
680 | if (!IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT)) | |
681 | do_break_handler(regs); | |
682 | ||
d6a61bfc | 683 | /* Deliver the signal to userspace */ |
2e1661d2 | 684 | force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address); |
d6a61bfc | 685 | } |
3bffb652 | 686 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc | 687 | |
4a8a9379 | 688 | static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]); |
a2ceff5e | 689 | |
3bffb652 DK |
690 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
691 | /* | |
692 | * Set the debug registers back to their default "safe" values. | |
693 | */ | |
694 | static void set_debug_reg_defaults(struct thread_struct *thread) | |
695 | { | |
51ae8d4a | 696 | thread->debug.iac1 = thread->debug.iac2 = 0; |
3bffb652 | 697 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
51ae8d4a | 698 | thread->debug.iac3 = thread->debug.iac4 = 0; |
3bffb652 | 699 | #endif |
51ae8d4a | 700 | thread->debug.dac1 = thread->debug.dac2 = 0; |
3bffb652 | 701 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
51ae8d4a | 702 | thread->debug.dvc1 = thread->debug.dvc2 = 0; |
3bffb652 | 703 | #endif |
51ae8d4a | 704 | thread->debug.dbcr0 = 0; |
3bffb652 DK |
705 | #ifdef CONFIG_BOOKE |
706 | /* | |
707 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | |
708 | */ | |
51ae8d4a | 709 | thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | |
3bffb652 DK |
710 | DBCR1_IAC3US | DBCR1_IAC4US; |
711 | /* | |
712 | * Force Data Address Compare User/Supervisor bits to be User-only | |
713 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | |
714 | */ | |
51ae8d4a | 715 | thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; |
3bffb652 | 716 | #else |
51ae8d4a | 717 | thread->debug.dbcr1 = 0; |
3bffb652 DK |
718 | #endif |
719 | } | |
720 | ||
f5f97210 | 721 | static void prime_debug_regs(struct debug_reg *debug) |
3bffb652 | 722 | { |
6cecf76b SW |
723 | /* |
724 | * We could have inherited MSR_DE from userspace, since | |
725 | * it doesn't get cleared on exception entry. Make sure | |
726 | * MSR_DE is clear before we enable any debug events. | |
727 | */ | |
728 | mtmsr(mfmsr() & ~MSR_DE); | |
729 | ||
f5f97210 SW |
730 | mtspr(SPRN_IAC1, debug->iac1); |
731 | mtspr(SPRN_IAC2, debug->iac2); | |
3bffb652 | 732 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
f5f97210 SW |
733 | mtspr(SPRN_IAC3, debug->iac3); |
734 | mtspr(SPRN_IAC4, debug->iac4); | |
3bffb652 | 735 | #endif |
f5f97210 SW |
736 | mtspr(SPRN_DAC1, debug->dac1); |
737 | mtspr(SPRN_DAC2, debug->dac2); | |
3bffb652 | 738 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
f5f97210 SW |
739 | mtspr(SPRN_DVC1, debug->dvc1); |
740 | mtspr(SPRN_DVC2, debug->dvc2); | |
3bffb652 | 741 | #endif |
f5f97210 SW |
742 | mtspr(SPRN_DBCR0, debug->dbcr0); |
743 | mtspr(SPRN_DBCR1, debug->dbcr1); | |
3bffb652 | 744 | #ifdef CONFIG_BOOKE |
f5f97210 | 745 | mtspr(SPRN_DBCR2, debug->dbcr2); |
3bffb652 DK |
746 | #endif |
747 | } | |
748 | /* | |
749 | * Unless neither the old or new thread are making use of the | |
750 | * debug registers, set the debug registers from the values | |
751 | * stored in the new thread. | |
752 | */ | |
f5f97210 | 753 | void switch_booke_debug_regs(struct debug_reg *new_debug) |
3bffb652 | 754 | { |
51ae8d4a | 755 | if ((current->thread.debug.dbcr0 & DBCR0_IDM) |
f5f97210 SW |
756 | || (new_debug->dbcr0 & DBCR0_IDM)) |
757 | prime_debug_regs(new_debug); | |
3bffb652 | 758 | } |
3743c9b8 | 759 | EXPORT_SYMBOL_GPL(switch_booke_debug_regs); |
3bffb652 | 760 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ |
e0780b72 | 761 | #ifndef CONFIG_HAVE_HW_BREAKPOINT |
303e6a9d | 762 | static void set_breakpoint(int i, struct arch_hw_breakpoint *brk) |
b5ac51d7 CL |
763 | { |
764 | preempt_disable(); | |
303e6a9d | 765 | __set_breakpoint(i, brk); |
b5ac51d7 CL |
766 | preempt_enable(); |
767 | } | |
768 | ||
3bffb652 DK |
769 | static void set_debug_reg_defaults(struct thread_struct *thread) |
770 | { | |
303e6a9d RB |
771 | int i; |
772 | struct arch_hw_breakpoint null_brk = {0}; | |
773 | ||
774 | for (i = 0; i < nr_wp_slots(); i++) { | |
775 | thread->hw_brk[i] = null_brk; | |
776 | if (ppc_breakpoint_available()) | |
777 | set_breakpoint(i, &thread->hw_brk[i]); | |
778 | } | |
779 | } | |
780 | ||
781 | static inline bool hw_brk_match(struct arch_hw_breakpoint *a, | |
782 | struct arch_hw_breakpoint *b) | |
783 | { | |
784 | if (a->address != b->address) | |
785 | return false; | |
786 | if (a->type != b->type) | |
787 | return false; | |
788 | if (a->len != b->len) | |
789 | return false; | |
790 | /* no need to check hw_len. it's calculated from address and len */ | |
791 | return true; | |
792 | } | |
793 | ||
794 | static void switch_hw_breakpoint(struct task_struct *new) | |
795 | { | |
796 | int i; | |
797 | ||
798 | for (i = 0; i < nr_wp_slots(); i++) { | |
799 | if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]), | |
800 | &new->thread.hw_brk[i]))) | |
801 | continue; | |
802 | ||
803 | __set_breakpoint(i, &new->thread.hw_brk[i]); | |
804 | } | |
3bffb652 | 805 | } |
e0780b72 | 806 | #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 DK |
807 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
808 | ||
9422de3e MN |
809 | static inline int set_dabr(struct arch_hw_breakpoint *brk) |
810 | { | |
811 | unsigned long dabr, dabrx; | |
812 | ||
813 | dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); | |
814 | dabrx = ((brk->type >> 3) & 0x7); | |
815 | ||
816 | if (ppc_md.set_dabr) | |
817 | return ppc_md.set_dabr(dabr, dabrx); | |
818 | ||
ad3ed15c CL |
819 | if (IS_ENABLED(CONFIG_PPC_ADV_DEBUG_REGS)) { |
820 | mtspr(SPRN_DAC1, dabr); | |
821 | if (IS_ENABLED(CONFIG_PPC_47x)) | |
822 | isync(); | |
823 | return 0; | |
824 | } else if (IS_ENABLED(CONFIG_PPC_BOOK3S)) { | |
825 | mtspr(SPRN_DABR, dabr); | |
826 | if (cpu_has_feature(CPU_FTR_DABRX)) | |
827 | mtspr(SPRN_DABRX, dabrx); | |
828 | return 0; | |
829 | } else { | |
830 | return -EINVAL; | |
831 | } | |
9422de3e MN |
832 | } |
833 | ||
39413ae0 CL |
834 | static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk) |
835 | { | |
836 | unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW | | |
837 | LCTRL1_CRWF_RW; | |
838 | unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN; | |
e68ef121 RB |
839 | unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE); |
840 | unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE); | |
39413ae0 CL |
841 | |
842 | if (start_addr == 0) | |
843 | lctrl2 |= LCTRL2_LW0LA_F; | |
e68ef121 | 844 | else if (end_addr == 0) |
39413ae0 CL |
845 | lctrl2 |= LCTRL2_LW0LA_E; |
846 | else | |
847 | lctrl2 |= LCTRL2_LW0LA_EandF; | |
848 | ||
849 | mtspr(SPRN_LCTRL2, 0); | |
850 | ||
851 | if ((brk->type & HW_BRK_TYPE_RDWR) == 0) | |
852 | return 0; | |
853 | ||
854 | if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) | |
855 | lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO; | |
856 | if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) | |
857 | lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO; | |
858 | ||
859 | mtspr(SPRN_CMPE, start_addr - 1); | |
e68ef121 | 860 | mtspr(SPRN_CMPF, end_addr); |
39413ae0 CL |
861 | mtspr(SPRN_LCTRL1, lctrl1); |
862 | mtspr(SPRN_LCTRL2, lctrl2); | |
863 | ||
864 | return 0; | |
865 | } | |
866 | ||
4a8a9379 | 867 | void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk) |
9422de3e | 868 | { |
4a8a9379 | 869 | memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk)); |
9422de3e | 870 | |
c1fe190c | 871 | if (dawr_enabled()) |
252988cb | 872 | // Power8 or later |
4a8a9379 | 873 | set_dawr(nr, brk); |
39413ae0 CL |
874 | else if (IS_ENABLED(CONFIG_PPC_8xx)) |
875 | set_breakpoint_8xx(brk); | |
252988cb NP |
876 | else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) |
877 | // Power7 or earlier | |
04c32a51 | 878 | set_dabr(brk); |
252988cb NP |
879 | else |
880 | // Shouldn't happen due to higher level checks | |
881 | WARN_ON_ONCE(1); | |
9422de3e | 882 | } |
14cf11af | 883 | |
404b27d6 MN |
884 | /* Check if we have DAWR or DABR hardware */ |
885 | bool ppc_breakpoint_available(void) | |
886 | { | |
c1fe190c MN |
887 | if (dawr_enabled()) |
888 | return true; /* POWER8 DAWR or POWER9 forced DAWR */ | |
404b27d6 MN |
889 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) |
890 | return false; /* POWER9 with DAWR disabled */ | |
891 | /* DABR: Everything but POWER8 and POWER9 */ | |
892 | return true; | |
893 | } | |
894 | EXPORT_SYMBOL_GPL(ppc_breakpoint_available); | |
895 | ||
fb09692e | 896 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
5d176f75 CB |
897 | |
898 | static inline bool tm_enabled(struct task_struct *tsk) | |
899 | { | |
900 | return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); | |
901 | } | |
902 | ||
edd00b83 | 903 | static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause) |
d31626f7 | 904 | { |
7f821fc9 MN |
905 | /* |
906 | * Use the current MSR TM suspended bit to track if we have | |
907 | * checkpointed state outstanding. | |
908 | * On signal delivery, we'd normally reclaim the checkpointed | |
909 | * state to obtain stack pointer (see:get_tm_stackpointer()). | |
910 | * This will then directly return to userspace without going | |
911 | * through __switch_to(). However, if the stack frame is bad, | |
912 | * we need to exit this thread which calls __switch_to() which | |
913 | * will again attempt to reclaim the already saved tm state. | |
914 | * Hence we need to check that we've not already reclaimed | |
915 | * this state. | |
916 | * We do this using the current MSR, rather tracking it in | |
917 | * some specific thread_struct bit, as it has the additional | |
027dfac6 | 918 | * benefit of checking for a potential TM bad thing exception. |
7f821fc9 MN |
919 | */ |
920 | if (!MSR_TM_SUSPENDED(mfmsr())) | |
921 | return; | |
922 | ||
91381b9c CB |
923 | giveup_all(container_of(thr, struct task_struct, thread)); |
924 | ||
eb5c3f1c CB |
925 | tm_reclaim(thr, cause); |
926 | ||
f48e91e8 MN |
927 | /* |
928 | * If we are in a transaction and FP is off then we can't have | |
929 | * used FP inside that transaction. Hence the checkpointed | |
930 | * state is the same as the live state. We need to copy the | |
931 | * live state to the checkpointed state so that when the | |
932 | * transaction is restored, the checkpointed state is correct | |
933 | * and the aborted transaction sees the correct state. We use | |
934 | * ckpt_regs.msr here as that's what tm_reclaim will use to | |
935 | * determine if it's going to write the checkpointed state or | |
936 | * not. So either this will write the checkpointed registers, | |
937 | * or reclaim will. Similarly for VMX. | |
938 | */ | |
939 | if ((thr->ckpt_regs.msr & MSR_FP) == 0) | |
940 | memcpy(&thr->ckfp_state, &thr->fp_state, | |
941 | sizeof(struct thread_fp_state)); | |
942 | if ((thr->ckpt_regs.msr & MSR_VEC) == 0) | |
943 | memcpy(&thr->ckvr_state, &thr->vr_state, | |
944 | sizeof(struct thread_vr_state)); | |
d31626f7 PM |
945 | } |
946 | ||
947 | void tm_reclaim_current(uint8_t cause) | |
948 | { | |
949 | tm_enable(); | |
edd00b83 | 950 | tm_reclaim_thread(¤t->thread, cause); |
d31626f7 PM |
951 | } |
952 | ||
fb09692e MN |
953 | static inline void tm_reclaim_task(struct task_struct *tsk) |
954 | { | |
955 | /* We have to work out if we're switching from/to a task that's in the | |
956 | * middle of a transaction. | |
957 | * | |
958 | * In switching we need to maintain a 2nd register state as | |
959 | * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the | |
000ec280 CB |
960 | * checkpointed (tbegin) state in ckpt_regs, ckfp_state and |
961 | * ckvr_state | |
fb09692e MN |
962 | * |
963 | * We also context switch (save) TFHAR/TEXASR/TFIAR in here. | |
964 | */ | |
965 | struct thread_struct *thr = &tsk->thread; | |
966 | ||
967 | if (!thr->regs) | |
968 | return; | |
969 | ||
970 | if (!MSR_TM_ACTIVE(thr->regs->msr)) | |
971 | goto out_and_saveregs; | |
972 | ||
92fb8690 MN |
973 | WARN_ON(tm_suspend_disabled); |
974 | ||
fb09692e MN |
975 | TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " |
976 | "ccr=%lx, msr=%lx, trap=%lx)\n", | |
977 | tsk->pid, thr->regs->nip, | |
978 | thr->regs->ccr, thr->regs->msr, | |
979 | thr->regs->trap); | |
980 | ||
edd00b83 | 981 | tm_reclaim_thread(thr, TM_CAUSE_RESCHED); |
fb09692e MN |
982 | |
983 | TM_DEBUG("--- tm_reclaim on pid %d complete\n", | |
984 | tsk->pid); | |
985 | ||
986 | out_and_saveregs: | |
987 | /* Always save the regs here, even if a transaction's not active. | |
988 | * This context-switches a thread's TM info SPRs. We do it here to | |
989 | * be consistent with the restore path (in recheckpoint) which | |
990 | * cannot happen later in _switch(). | |
991 | */ | |
992 | tm_save_sprs(thr); | |
993 | } | |
994 | ||
eb5c3f1c | 995 | extern void __tm_recheckpoint(struct thread_struct *thread); |
e6b8fd02 | 996 | |
eb5c3f1c | 997 | void tm_recheckpoint(struct thread_struct *thread) |
e6b8fd02 MN |
998 | { |
999 | unsigned long flags; | |
1000 | ||
5d176f75 CB |
1001 | if (!(thread->regs->msr & MSR_TM)) |
1002 | return; | |
1003 | ||
e6b8fd02 MN |
1004 | /* We really can't be interrupted here as the TEXASR registers can't |
1005 | * change and later in the trecheckpoint code, we have a userspace R1. | |
1006 | * So let's hard disable over this region. | |
1007 | */ | |
1008 | local_irq_save(flags); | |
1009 | hard_irq_disable(); | |
1010 | ||
1011 | /* The TM SPRs are restored here, so that TEXASR.FS can be set | |
1012 | * before the trecheckpoint and no explosion occurs. | |
1013 | */ | |
1014 | tm_restore_sprs(thread); | |
1015 | ||
eb5c3f1c | 1016 | __tm_recheckpoint(thread); |
e6b8fd02 MN |
1017 | |
1018 | local_irq_restore(flags); | |
1019 | } | |
1020 | ||
bc2a9408 | 1021 | static inline void tm_recheckpoint_new_task(struct task_struct *new) |
fb09692e | 1022 | { |
fb09692e MN |
1023 | if (!cpu_has_feature(CPU_FTR_TM)) |
1024 | return; | |
1025 | ||
1026 | /* Recheckpoint the registers of the thread we're about to switch to. | |
1027 | * | |
1028 | * If the task was using FP, we non-lazily reload both the original and | |
1029 | * the speculative FP register states. This is because the kernel | |
1030 | * doesn't see if/when a TM rollback occurs, so if we take an FP | |
dc310669 | 1031 | * unavailable later, we are unable to determine which set of FP regs |
fb09692e MN |
1032 | * need to be restored. |
1033 | */ | |
5d176f75 | 1034 | if (!tm_enabled(new)) |
fb09692e MN |
1035 | return; |
1036 | ||
e6b8fd02 MN |
1037 | if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ |
1038 | tm_restore_sprs(&new->thread); | |
fb09692e | 1039 | return; |
e6b8fd02 | 1040 | } |
fb09692e | 1041 | /* Recheckpoint to restore original checkpointed register state. */ |
eb5c3f1c CB |
1042 | TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", |
1043 | new->pid, new->thread.regs->msr); | |
fb09692e | 1044 | |
eb5c3f1c | 1045 | tm_recheckpoint(&new->thread); |
fb09692e | 1046 | |
dc310669 CB |
1047 | /* |
1048 | * The checkpointed state has been restored but the live state has | |
1049 | * not, ensure all the math functionality is turned off to trigger | |
1050 | * restore_math() to reload. | |
1051 | */ | |
1052 | new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); | |
fb09692e MN |
1053 | |
1054 | TM_DEBUG("*** tm_recheckpoint of pid %d complete " | |
1055 | "(kernel msr 0x%lx)\n", | |
1056 | new->pid, mfmsr()); | |
1057 | } | |
1058 | ||
dc310669 CB |
1059 | static inline void __switch_to_tm(struct task_struct *prev, |
1060 | struct task_struct *new) | |
fb09692e MN |
1061 | { |
1062 | if (cpu_has_feature(CPU_FTR_TM)) { | |
5d176f75 CB |
1063 | if (tm_enabled(prev) || tm_enabled(new)) |
1064 | tm_enable(); | |
1065 | ||
1066 | if (tm_enabled(prev)) { | |
1067 | prev->thread.load_tm++; | |
1068 | tm_reclaim_task(prev); | |
1069 | if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) | |
1070 | prev->thread.regs->msr &= ~MSR_TM; | |
1071 | } | |
1072 | ||
dc310669 | 1073 | tm_recheckpoint_new_task(new); |
fb09692e MN |
1074 | } |
1075 | } | |
d31626f7 PM |
1076 | |
1077 | /* | |
1078 | * This is called if we are on the way out to userspace and the | |
1079 | * TIF_RESTORE_TM flag is set. It checks if we need to reload | |
1080 | * FP and/or vector state and does so if necessary. | |
1081 | * If userspace is inside a transaction (whether active or | |
1082 | * suspended) and FP/VMX/VSX instructions have ever been enabled | |
1083 | * inside that transaction, then we have to keep them enabled | |
1084 | * and keep the FP/VMX/VSX state loaded while ever the transaction | |
1085 | * continues. The reason is that if we didn't, and subsequently | |
1086 | * got a FP/VMX/VSX unavailable interrupt inside a transaction, | |
1087 | * we don't know whether it's the same transaction, and thus we | |
1088 | * don't know which of the checkpointed state and the transactional | |
1089 | * state to use. | |
1090 | */ | |
1091 | void restore_tm_state(struct pt_regs *regs) | |
1092 | { | |
1093 | unsigned long msr_diff; | |
1094 | ||
dc310669 CB |
1095 | /* |
1096 | * This is the only moment we should clear TIF_RESTORE_TM as | |
1097 | * it is here that ckpt_regs.msr and pt_regs.msr become the same | |
1098 | * again, anything else could lead to an incorrect ckpt_msr being | |
1099 | * saved and therefore incorrect signal contexts. | |
1100 | */ | |
d31626f7 PM |
1101 | clear_thread_flag(TIF_RESTORE_TM); |
1102 | if (!MSR_TM_ACTIVE(regs->msr)) | |
1103 | return; | |
1104 | ||
829023df | 1105 | msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; |
d31626f7 | 1106 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; |
70fe3d98 | 1107 | |
dc16b553 CB |
1108 | /* Ensure that restore_math() will restore */ |
1109 | if (msr_diff & MSR_FP) | |
1110 | current->thread.load_fp = 1; | |
39715bf9 | 1111 | #ifdef CONFIG_ALTIVEC |
dc16b553 CB |
1112 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) |
1113 | current->thread.load_vec = 1; | |
1114 | #endif | |
70fe3d98 CB |
1115 | restore_math(regs); |
1116 | ||
d31626f7 PM |
1117 | regs->msr |= msr_diff; |
1118 | } | |
1119 | ||
fb09692e MN |
1120 | #else |
1121 | #define tm_recheckpoint_new_task(new) | |
dc310669 | 1122 | #define __switch_to_tm(prev, new) |
fb09692e | 1123 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
9422de3e | 1124 | |
152d523e AB |
1125 | static inline void save_sprs(struct thread_struct *t) |
1126 | { | |
1127 | #ifdef CONFIG_ALTIVEC | |
01d7c2a2 | 1128 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
152d523e AB |
1129 | t->vrsave = mfspr(SPRN_VRSAVE); |
1130 | #endif | |
1131 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1132 | if (cpu_has_feature(CPU_FTR_DSCR)) | |
1133 | t->dscr = mfspr(SPRN_DSCR); | |
1134 | ||
1135 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1136 | t->bescr = mfspr(SPRN_BESCR); | |
1137 | t->ebbhr = mfspr(SPRN_EBBHR); | |
1138 | t->ebbrr = mfspr(SPRN_EBBRR); | |
1139 | ||
1140 | t->fscr = mfspr(SPRN_FSCR); | |
1141 | ||
1142 | /* | |
1143 | * Note that the TAR is not available for use in the kernel. | |
1144 | * (To provide this, the TAR should be backed up/restored on | |
1145 | * exception entry/exit instead, and be in pt_regs. FIXME, | |
1146 | * this should be in pt_regs anyway (for debug).) | |
1147 | */ | |
1148 | t->tar = mfspr(SPRN_TAR); | |
1149 | } | |
1150 | #endif | |
1151 | } | |
1152 | ||
1153 | static inline void restore_sprs(struct thread_struct *old_thread, | |
1154 | struct thread_struct *new_thread) | |
1155 | { | |
1156 | #ifdef CONFIG_ALTIVEC | |
1157 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && | |
1158 | old_thread->vrsave != new_thread->vrsave) | |
1159 | mtspr(SPRN_VRSAVE, new_thread->vrsave); | |
1160 | #endif | |
1161 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1162 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1163 | u64 dscr = get_paca()->dscr_default; | |
b57bd2de | 1164 | if (new_thread->dscr_inherit) |
152d523e | 1165 | dscr = new_thread->dscr; |
152d523e AB |
1166 | |
1167 | if (old_thread->dscr != dscr) | |
1168 | mtspr(SPRN_DSCR, dscr); | |
152d523e AB |
1169 | } |
1170 | ||
1171 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1172 | if (old_thread->bescr != new_thread->bescr) | |
1173 | mtspr(SPRN_BESCR, new_thread->bescr); | |
1174 | if (old_thread->ebbhr != new_thread->ebbhr) | |
1175 | mtspr(SPRN_EBBHR, new_thread->ebbhr); | |
1176 | if (old_thread->ebbrr != new_thread->ebbrr) | |
1177 | mtspr(SPRN_EBBRR, new_thread->ebbrr); | |
1178 | ||
b57bd2de MN |
1179 | if (old_thread->fscr != new_thread->fscr) |
1180 | mtspr(SPRN_FSCR, new_thread->fscr); | |
1181 | ||
152d523e AB |
1182 | if (old_thread->tar != new_thread->tar) |
1183 | mtspr(SPRN_TAR, new_thread->tar); | |
1184 | } | |
ec233ede | 1185 | |
3449f191 | 1186 | if (cpu_has_feature(CPU_FTR_P9_TIDR) && |
ec233ede SB |
1187 | old_thread->tidr != new_thread->tidr) |
1188 | mtspr(SPRN_TIDR, new_thread->tidr); | |
152d523e | 1189 | #endif |
06bb53b3 | 1190 | |
152d523e AB |
1191 | } |
1192 | ||
14cf11af PM |
1193 | struct task_struct *__switch_to(struct task_struct *prev, |
1194 | struct task_struct *new) | |
1195 | { | |
1196 | struct thread_struct *new_thread, *old_thread; | |
14cf11af | 1197 | struct task_struct *last; |
d6bf29b4 PZ |
1198 | #ifdef CONFIG_PPC_BOOK3S_64 |
1199 | struct ppc64_tlb_batch *batch; | |
1200 | #endif | |
14cf11af | 1201 | |
152d523e AB |
1202 | new_thread = &new->thread; |
1203 | old_thread = ¤t->thread; | |
1204 | ||
7ba5fef7 MN |
1205 | WARN_ON(!irqs_disabled()); |
1206 | ||
4e003747 | 1207 | #ifdef CONFIG_PPC_BOOK3S_64 |
69111bac | 1208 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1209 | if (batch->active) { |
1210 | current_thread_info()->local_flags |= _TLF_LAZY_MMU; | |
1211 | if (batch->index) | |
1212 | __flush_tlb_pending(batch); | |
1213 | batch->active = 0; | |
1214 | } | |
4e003747 | 1215 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
06d67d54 | 1216 | |
f3d885cc AB |
1217 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1218 | switch_booke_debug_regs(&new->thread.debug); | |
1219 | #else | |
1220 | /* | |
1221 | * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would | |
1222 | * schedule DABR | |
1223 | */ | |
1224 | #ifndef CONFIG_HAVE_HW_BREAKPOINT | |
303e6a9d | 1225 | switch_hw_breakpoint(new); |
f3d885cc AB |
1226 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
1227 | #endif | |
1228 | ||
1229 | /* | |
1230 | * We need to save SPRs before treclaim/trecheckpoint as these will | |
1231 | * change a number of them. | |
1232 | */ | |
1233 | save_sprs(&prev->thread); | |
1234 | ||
f3d885cc AB |
1235 | /* Save FPU, Altivec, VSX and SPE state */ |
1236 | giveup_all(prev); | |
1237 | ||
dc310669 CB |
1238 | __switch_to_tm(prev, new); |
1239 | ||
e4c0fc5f NP |
1240 | if (!radix_enabled()) { |
1241 | /* | |
1242 | * We can't take a PMU exception inside _switch() since there | |
1243 | * is a window where the kernel stack SLB and the kernel stack | |
1244 | * are out of sync. Hard disable here. | |
1245 | */ | |
1246 | hard_irq_disable(); | |
1247 | } | |
bc2a9408 | 1248 | |
20dbe670 AB |
1249 | /* |
1250 | * Call restore_sprs() before calling _switch(). If we move it after | |
1251 | * _switch() then we miss out on calling it for new tasks. The reason | |
1252 | * for this is we manually create a stack frame for new tasks that | |
1253 | * directly returns through ret_from_fork() or | |
1254 | * ret_from_kernel_thread(). See copy_thread() for details. | |
1255 | */ | |
f3d885cc AB |
1256 | restore_sprs(old_thread, new_thread); |
1257 | ||
20dbe670 AB |
1258 | last = _switch(old_thread, new_thread); |
1259 | ||
4e003747 | 1260 | #ifdef CONFIG_PPC_BOOK3S_64 |
d6bf29b4 PZ |
1261 | if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { |
1262 | current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; | |
69111bac | 1263 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1264 | batch->active = 1; |
1265 | } | |
70fe3d98 | 1266 | |
05b98791 CL |
1267 | if (current->thread.regs) { |
1268 | restore_math(current->thread.regs); | |
07d2a628 NP |
1269 | |
1270 | /* | |
dc462267 NP |
1271 | * On POWER9 the copy-paste buffer can only paste into |
1272 | * foreign real addresses, so unprivileged processes can not | |
1273 | * see the data or use it in any way unless they have | |
1274 | * foreign real mappings. If the new process has the foreign | |
1275 | * real address mappings, we must issue a cp_abort to clear | |
1276 | * any state and prevent snooping, corruption or a covert | |
1277 | * channel. ISA v3.1 supports paste into local memory. | |
07d2a628 | 1278 | */ |
c420644c | 1279 | if (current->mm && |
dc462267 NP |
1280 | (cpu_has_feature(CPU_FTR_ARCH_31) || |
1281 | atomic_read(¤t->mm->context.vas_windows))) | |
9d2a4d71 | 1282 | asm volatile(PPC_CP_ABORT); |
07d2a628 | 1283 | } |
4e003747 | 1284 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
d6bf29b4 | 1285 | |
14cf11af PM |
1286 | return last; |
1287 | } | |
1288 | ||
df13102f | 1289 | #define NR_INSN_TO_PRINT 16 |
06d67d54 | 1290 | |
06d67d54 PM |
1291 | static void show_instructions(struct pt_regs *regs) |
1292 | { | |
1293 | int i; | |
a6e2c226 | 1294 | unsigned long nip = regs->nip; |
df13102f | 1295 | unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); |
06d67d54 PM |
1296 | |
1297 | printk("Instruction dump:"); | |
1298 | ||
a6e2c226 AK |
1299 | /* |
1300 | * If we were executing with the MMU off for instructions, adjust pc | |
1301 | * rather than printing XXXXXXXX. | |
1302 | */ | |
1303 | if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) { | |
1304 | pc = (unsigned long)phys_to_virt(pc); | |
1305 | nip = (unsigned long)phys_to_virt(regs->nip); | |
1306 | } | |
1307 | ||
df13102f | 1308 | for (i = 0; i < NR_INSN_TO_PRINT; i++) { |
06d67d54 PM |
1309 | int instr; |
1310 | ||
1311 | if (!(i % 8)) | |
2ffd04de | 1312 | pr_cont("\n"); |
06d67d54 | 1313 | |
00ae36de | 1314 | if (!__kernel_text_address(pc) || |
25f12ae4 | 1315 | get_kernel_nofault(instr, (const void *)pc)) { |
2ffd04de | 1316 | pr_cont("XXXXXXXX "); |
06d67d54 | 1317 | } else { |
a6e2c226 | 1318 | if (nip == pc) |
2ffd04de | 1319 | pr_cont("<%08x> ", instr); |
06d67d54 | 1320 | else |
2ffd04de | 1321 | pr_cont("%08x ", instr); |
06d67d54 PM |
1322 | } |
1323 | ||
1324 | pc += sizeof(int); | |
1325 | } | |
1326 | ||
2ffd04de | 1327 | pr_cont("\n"); |
06d67d54 PM |
1328 | } |
1329 | ||
88b0fe17 MOA |
1330 | void show_user_instructions(struct pt_regs *regs) |
1331 | { | |
1332 | unsigned long pc; | |
df13102f | 1333 | int n = NR_INSN_TO_PRINT; |
fb2d9505 CL |
1334 | struct seq_buf s; |
1335 | char buf[96]; /* enough for 8 times 9 + 2 chars */ | |
88b0fe17 | 1336 | |
df13102f | 1337 | pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int)); |
88b0fe17 | 1338 | |
fb2d9505 | 1339 | seq_buf_init(&s, buf, sizeof(buf)); |
88b0fe17 | 1340 | |
fb2d9505 CL |
1341 | while (n) { |
1342 | int i; | |
88b0fe17 | 1343 | |
fb2d9505 | 1344 | seq_buf_clear(&s); |
88b0fe17 | 1345 | |
fb2d9505 CL |
1346 | for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) { |
1347 | int instr; | |
1348 | ||
c0ee37e8 CH |
1349 | if (copy_from_user_nofault(&instr, (void __user *)pc, |
1350 | sizeof(instr))) { | |
fb2d9505 CL |
1351 | seq_buf_printf(&s, "XXXXXXXX "); |
1352 | continue; | |
1353 | } | |
1354 | seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr); | |
88b0fe17 MOA |
1355 | } |
1356 | ||
fb2d9505 CL |
1357 | if (!seq_buf_has_overflowed(&s)) |
1358 | pr_info("%s[%d]: code: %s\n", current->comm, | |
1359 | current->pid, s.buffer); | |
88b0fe17 | 1360 | } |
88b0fe17 MOA |
1361 | } |
1362 | ||
801c0b2c | 1363 | struct regbit { |
06d67d54 PM |
1364 | unsigned long bit; |
1365 | const char *name; | |
801c0b2c MN |
1366 | }; |
1367 | ||
1368 | static struct regbit msr_bits[] = { | |
3bfd0c9c AB |
1369 | #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) |
1370 | {MSR_SF, "SF"}, | |
1371 | {MSR_HV, "HV"}, | |
1372 | #endif | |
1373 | {MSR_VEC, "VEC"}, | |
1374 | {MSR_VSX, "VSX"}, | |
1375 | #ifdef CONFIG_BOOKE | |
1376 | {MSR_CE, "CE"}, | |
1377 | #endif | |
06d67d54 PM |
1378 | {MSR_EE, "EE"}, |
1379 | {MSR_PR, "PR"}, | |
1380 | {MSR_FP, "FP"}, | |
1381 | {MSR_ME, "ME"}, | |
3bfd0c9c | 1382 | #ifdef CONFIG_BOOKE |
1b98326b | 1383 | {MSR_DE, "DE"}, |
3bfd0c9c AB |
1384 | #else |
1385 | {MSR_SE, "SE"}, | |
1386 | {MSR_BE, "BE"}, | |
1387 | #endif | |
06d67d54 PM |
1388 | {MSR_IR, "IR"}, |
1389 | {MSR_DR, "DR"}, | |
3bfd0c9c AB |
1390 | {MSR_PMM, "PMM"}, |
1391 | #ifndef CONFIG_BOOKE | |
1392 | {MSR_RI, "RI"}, | |
1393 | {MSR_LE, "LE"}, | |
1394 | #endif | |
06d67d54 PM |
1395 | {0, NULL} |
1396 | }; | |
1397 | ||
801c0b2c | 1398 | static void print_bits(unsigned long val, struct regbit *bits, const char *sep) |
06d67d54 | 1399 | { |
801c0b2c | 1400 | const char *s = ""; |
06d67d54 | 1401 | |
06d67d54 PM |
1402 | for (; bits->bit; ++bits) |
1403 | if (val & bits->bit) { | |
db5ba5ae | 1404 | pr_cont("%s%s", s, bits->name); |
801c0b2c | 1405 | s = sep; |
06d67d54 | 1406 | } |
801c0b2c MN |
1407 | } |
1408 | ||
1409 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1410 | static struct regbit msr_tm_bits[] = { | |
1411 | {MSR_TS_T, "T"}, | |
1412 | {MSR_TS_S, "S"}, | |
1413 | {MSR_TM, "E"}, | |
1414 | {0, NULL} | |
1415 | }; | |
1416 | ||
1417 | static void print_tm_bits(unsigned long val) | |
1418 | { | |
1419 | /* | |
1420 | * This only prints something if at least one of the TM bit is set. | |
1421 | * Inside the TM[], the output means: | |
1422 | * E: Enabled (bit 32) | |
1423 | * S: Suspended (bit 33) | |
1424 | * T: Transactional (bit 34) | |
1425 | */ | |
1426 | if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { | |
db5ba5ae | 1427 | pr_cont(",TM["); |
801c0b2c | 1428 | print_bits(val, msr_tm_bits, ""); |
db5ba5ae | 1429 | pr_cont("]"); |
801c0b2c MN |
1430 | } |
1431 | } | |
1432 | #else | |
1433 | static void print_tm_bits(unsigned long val) {} | |
1434 | #endif | |
1435 | ||
1436 | static void print_msr_bits(unsigned long val) | |
1437 | { | |
db5ba5ae | 1438 | pr_cont("<"); |
801c0b2c MN |
1439 | print_bits(val, msr_bits, ","); |
1440 | print_tm_bits(val); | |
db5ba5ae | 1441 | pr_cont(">"); |
06d67d54 PM |
1442 | } |
1443 | ||
1444 | #ifdef CONFIG_PPC64 | |
f6f7dde3 | 1445 | #define REG "%016lx" |
06d67d54 PM |
1446 | #define REGS_PER_LINE 4 |
1447 | #define LAST_VOLATILE 13 | |
1448 | #else | |
f6f7dde3 | 1449 | #define REG "%08lx" |
06d67d54 PM |
1450 | #define REGS_PER_LINE 8 |
1451 | #define LAST_VOLATILE 12 | |
1452 | #endif | |
1453 | ||
bf13718b | 1454 | static void __show_regs(struct pt_regs *regs) |
14cf11af PM |
1455 | { |
1456 | int i, trap; | |
1457 | ||
a6036100 | 1458 | printk("NIP: "REG" LR: "REG" CTR: "REG"\n", |
06d67d54 | 1459 | regs->nip, regs->link, regs->ctr); |
182dc9c7 | 1460 | printk("REGS: %px TRAP: %04lx %s (%s)\n", |
96b644bd | 1461 | regs, regs->trap, print_tainted(), init_utsname()->release); |
a6036100 | 1462 | printk("MSR: "REG" ", regs->msr); |
801c0b2c | 1463 | print_msr_bits(regs->msr); |
f6fc73fb | 1464 | pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); |
14cf11af | 1465 | trap = TRAP(regs); |
912237ea | 1466 | if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR)) |
7dae865f | 1467 | pr_cont("CFAR: "REG" ", regs->orig_gpr3); |
2ec42996 CL |
1468 | if (trap == 0x200 || trap == 0x300 || trap == 0x600) { |
1469 | if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE)) | |
1470 | pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); | |
1471 | else | |
1472 | pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); | |
1473 | } | |
1474 | ||
9db8bcfd | 1475 | #ifdef CONFIG_PPC64 |
3130a7bb | 1476 | pr_cont("IRQMASK: %lx ", regs->softe); |
9db8bcfd AB |
1477 | #endif |
1478 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
6d888d1a | 1479 | if (MSR_TM_ACTIVE(regs->msr)) |
7dae865f | 1480 | pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); |
14170789 | 1481 | #endif |
14cf11af PM |
1482 | |
1483 | for (i = 0; i < 32; i++) { | |
06d67d54 | 1484 | if ((i % REGS_PER_LINE) == 0) |
7dae865f ME |
1485 | pr_cont("\nGPR%02d: ", i); |
1486 | pr_cont(REG " ", regs->gpr[i]); | |
06d67d54 | 1487 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) |
14cf11af PM |
1488 | break; |
1489 | } | |
7dae865f | 1490 | pr_cont("\n"); |
14cf11af PM |
1491 | /* |
1492 | * Lookup NIP late so we have the best change of getting the | |
1493 | * above info out without failing | |
1494 | */ | |
8f020c7c CL |
1495 | if (IS_ENABLED(CONFIG_KALLSYMS)) { |
1496 | printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); | |
1497 | printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); | |
1498 | } | |
bf13718b NP |
1499 | } |
1500 | ||
1501 | void show_regs(struct pt_regs *regs) | |
1502 | { | |
1503 | show_regs_print_info(KERN_DEFAULT); | |
1504 | __show_regs(regs); | |
9cb8f069 | 1505 | show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT); |
06d67d54 PM |
1506 | if (!user_mode(regs)) |
1507 | show_instructions(regs); | |
14cf11af PM |
1508 | } |
1509 | ||
14cf11af PM |
1510 | void flush_thread(void) |
1511 | { | |
e0780b72 | 1512 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
5aae8a53 | 1513 | flush_ptrace_hw_breakpoint(current); |
e0780b72 | 1514 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1515 | set_debug_reg_defaults(¤t->thread); |
e0780b72 | 1516 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
14cf11af PM |
1517 | } |
1518 | ||
425d3314 NP |
1519 | void arch_setup_new_exec(void) |
1520 | { | |
d7df77e8 AK |
1521 | |
1522 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1523 | if (!radix_enabled()) | |
1524 | hash__setup_new_exec(); | |
425d3314 | 1525 | #endif |
d7df77e8 AK |
1526 | /* |
1527 | * If we exec out of a kernel thread then thread.regs will not be | |
1528 | * set. Do it now. | |
1529 | */ | |
1530 | if (!current->thread.regs) { | |
1531 | struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; | |
1532 | current->thread.regs = regs - 1; | |
1533 | } | |
d5fa30e6 AK |
1534 | |
1535 | #ifdef CONFIG_PPC_MEM_KEYS | |
1536 | current->thread.regs->amr = default_amr; | |
1537 | current->thread.regs->iamr = default_iamr; | |
1538 | #endif | |
d7df77e8 | 1539 | } |
425d3314 | 1540 | |
ec233ede | 1541 | #ifdef CONFIG_PPC64 |
71cc64a8 AS |
1542 | /** |
1543 | * Assign a TIDR (thread ID) for task @t and set it in the thread | |
1544 | * structure. For now, we only support setting TIDR for 'current' task. | |
ec233ede | 1545 | * |
71cc64a8 AS |
1546 | * Since the TID value is a truncated form of it PID, it is possible |
1547 | * (but unlikely) for 2 threads to have the same TID. In the unlikely event | |
1548 | * that 2 threads share the same TID and are waiting, one of the following | |
1549 | * cases will happen: | |
ec233ede | 1550 | * |
71cc64a8 AS |
1551 | * 1. The correct thread is running, the wrong thread is not |
1552 | * In this situation, the correct thread is woken and proceeds to pass it's | |
1553 | * condition check. | |
ec233ede | 1554 | * |
71cc64a8 AS |
1555 | * 2. Neither threads are running |
1556 | * In this situation, neither thread will be woken. When scheduled, the waiting | |
1557 | * threads will execute either a wait, which will return immediately, followed | |
1558 | * by a condition check, which will pass for the correct thread and fail | |
1559 | * for the wrong thread, or they will execute the condition check immediately. | |
ec233ede | 1560 | * |
71cc64a8 AS |
1561 | * 3. The wrong thread is running, the correct thread is not |
1562 | * The wrong thread will be woken, but will fail it's condition check and | |
1563 | * re-execute wait. The correct thread, when scheduled, will execute either | |
1564 | * it's condition check (which will pass), or wait, which returns immediately | |
1565 | * when called the first time after the thread is scheduled, followed by it's | |
1566 | * condition check (which will pass). | |
ec233ede | 1567 | * |
71cc64a8 AS |
1568 | * 4. Both threads are running |
1569 | * Both threads will be woken. The wrong thread will fail it's condition check | |
1570 | * and execute another wait, while the correct thread will pass it's condition | |
1571 | * check. | |
1572 | * | |
1573 | * @t: the task to set the thread ID for | |
ec233ede SB |
1574 | */ |
1575 | int set_thread_tidr(struct task_struct *t) | |
1576 | { | |
3449f191 | 1577 | if (!cpu_has_feature(CPU_FTR_P9_TIDR)) |
ec233ede SB |
1578 | return -EINVAL; |
1579 | ||
1580 | if (t != current) | |
1581 | return -EINVAL; | |
1582 | ||
7e4d4233 VJ |
1583 | if (t->thread.tidr) |
1584 | return 0; | |
1585 | ||
71cc64a8 | 1586 | t->thread.tidr = (u16)task_pid_nr(t); |
ec233ede SB |
1587 | mtspr(SPRN_TIDR, t->thread.tidr); |
1588 | ||
1589 | return 0; | |
1590 | } | |
b1db5513 | 1591 | EXPORT_SYMBOL_GPL(set_thread_tidr); |
ec233ede SB |
1592 | |
1593 | #endif /* CONFIG_PPC64 */ | |
1594 | ||
14cf11af PM |
1595 | void |
1596 | release_thread(struct task_struct *t) | |
1597 | { | |
1598 | } | |
1599 | ||
1600 | /* | |
55ccf3fe SS |
1601 | * this gets called so that we can store coprocessor state into memory and |
1602 | * copy the current task into the new thread. | |
14cf11af | 1603 | */ |
55ccf3fe | 1604 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
14cf11af | 1605 | { |
579e633e | 1606 | flush_all_to_thread(src); |
621b5060 MN |
1607 | /* |
1608 | * Flush TM state out so we can copy it. __switch_to_tm() does this | |
1609 | * flush but it removes the checkpointed state from the current CPU and | |
1610 | * transitions the CPU out of TM mode. Hence we need to call | |
1611 | * tm_recheckpoint_new_task() (on the same task) to restore the | |
1612 | * checkpointed state back and the TM mode. | |
5d176f75 CB |
1613 | * |
1614 | * Can't pass dst because it isn't ready. Doesn't matter, passing | |
1615 | * dst is only important for __switch_to() | |
621b5060 | 1616 | */ |
dc310669 | 1617 | __switch_to_tm(src, src); |
330a1eb7 | 1618 | |
55ccf3fe | 1619 | *dst = *src; |
330a1eb7 ME |
1620 | |
1621 | clear_task_ebb(dst); | |
1622 | ||
55ccf3fe | 1623 | return 0; |
14cf11af PM |
1624 | } |
1625 | ||
cec15488 ME |
1626 | static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) |
1627 | { | |
4e003747 | 1628 | #ifdef CONFIG_PPC_BOOK3S_64 |
cec15488 ME |
1629 | unsigned long sp_vsid; |
1630 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
1631 | ||
caca285e AK |
1632 | if (radix_enabled()) |
1633 | return; | |
1634 | ||
cec15488 ME |
1635 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
1636 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) | |
1637 | << SLB_VSID_SHIFT_1T; | |
1638 | else | |
1639 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) | |
1640 | << SLB_VSID_SHIFT; | |
1641 | sp_vsid |= SLB_VSID_KERNEL | llp; | |
1642 | p->thread.ksp_vsid = sp_vsid; | |
1643 | #endif | |
1644 | } | |
1645 | ||
14cf11af PM |
1646 | /* |
1647 | * Copy a thread.. | |
1648 | */ | |
efcac658 | 1649 | |
6eca8933 AD |
1650 | /* |
1651 | * Copy architecture-specific thread state | |
1652 | */ | |
714acdbd | 1653 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
facd04a9 NP |
1654 | unsigned long kthread_arg, struct task_struct *p, |
1655 | unsigned long tls) | |
14cf11af PM |
1656 | { |
1657 | struct pt_regs *childregs, *kregs; | |
1658 | extern void ret_from_fork(void); | |
7fa95f9a | 1659 | extern void ret_from_fork_scv(void); |
58254e10 AV |
1660 | extern void ret_from_kernel_thread(void); |
1661 | void (*f)(void); | |
0cec6fd1 | 1662 | unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
5d31a96e | 1663 | struct thread_info *ti = task_thread_info(p); |
6b424efa RB |
1664 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1665 | int i; | |
1666 | #endif | |
5d31a96e | 1667 | |
ed1cd6de | 1668 | klp_init_thread_info(p); |
14cf11af | 1669 | |
14cf11af PM |
1670 | /* Copy registers */ |
1671 | sp -= sizeof(struct pt_regs); | |
1672 | childregs = (struct pt_regs *) sp; | |
ab75819d | 1673 | if (unlikely(p->flags & PF_KTHREAD)) { |
6eca8933 | 1674 | /* kernel thread */ |
58254e10 | 1675 | memset(childregs, 0, sizeof(struct pt_regs)); |
14cf11af | 1676 | childregs->gpr[1] = sp + sizeof(struct pt_regs); |
7cedd601 AB |
1677 | /* function */ |
1678 | if (usp) | |
1679 | childregs->gpr[14] = ppc_function_entry((void *)usp); | |
58254e10 | 1680 | #ifdef CONFIG_PPC64 |
b5e2fc1c | 1681 | clear_tsk_thread_flag(p, TIF_32BIT); |
c2e480ba | 1682 | childregs->softe = IRQS_ENABLED; |
06d67d54 | 1683 | #endif |
6eca8933 | 1684 | childregs->gpr[15] = kthread_arg; |
14cf11af | 1685 | p->thread.regs = NULL; /* no user register state */ |
138d1ce8 | 1686 | ti->flags |= _TIF_RESTOREALL; |
58254e10 | 1687 | f = ret_from_kernel_thread; |
14cf11af | 1688 | } else { |
6eca8933 | 1689 | /* user thread */ |
afa86fc4 | 1690 | struct pt_regs *regs = current_pt_regs(); |
58254e10 AV |
1691 | CHECK_FULL_REGS(regs); |
1692 | *childregs = *regs; | |
ea516b11 AV |
1693 | if (usp) |
1694 | childregs->gpr[1] = usp; | |
14cf11af | 1695 | p->thread.regs = childregs; |
7fa95f9a NP |
1696 | /* 64s sets this in ret_from_fork */ |
1697 | if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64)) | |
1698 | childregs->gpr[3] = 0; /* Result from fork() */ | |
06d67d54 | 1699 | if (clone_flags & CLONE_SETTLS) { |
9904b005 | 1700 | if (!is_32bit_task()) |
facd04a9 | 1701 | childregs->gpr[13] = tls; |
06d67d54 | 1702 | else |
facd04a9 | 1703 | childregs->gpr[2] = tls; |
06d67d54 | 1704 | } |
58254e10 | 1705 | |
7fa95f9a NP |
1706 | if (trap_is_scv(regs)) |
1707 | f = ret_from_fork_scv; | |
1708 | else | |
1709 | f = ret_from_fork; | |
14cf11af | 1710 | } |
d272f667 | 1711 | childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); |
14cf11af | 1712 | sp -= STACK_FRAME_OVERHEAD; |
14cf11af PM |
1713 | |
1714 | /* | |
1715 | * The way this works is that at some point in the future | |
1716 | * some task will call _switch to switch to the new task. | |
1717 | * That will pop off the stack frame created below and start | |
1718 | * the new task running at ret_from_fork. The new task will | |
1719 | * do some house keeping and then return from the fork or clone | |
1720 | * system call, using the stack frame created above. | |
1721 | */ | |
af945cf4 | 1722 | ((unsigned long *)sp)[0] = 0; |
14cf11af PM |
1723 | sp -= sizeof(struct pt_regs); |
1724 | kregs = (struct pt_regs *) sp; | |
1725 | sp -= STACK_FRAME_OVERHEAD; | |
1726 | p->thread.ksp = sp; | |
cbc9565e | 1727 | #ifdef CONFIG_PPC32 |
a7916a1d | 1728 | p->thread.ksp_limit = (unsigned long)end_of_stack(p); |
cbc9565e | 1729 | #endif |
28d170ab | 1730 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6b424efa RB |
1731 | for (i = 0; i < nr_wp_slots(); i++) |
1732 | p->thread.ptrace_bps[i] = NULL; | |
28d170ab ON |
1733 | #endif |
1734 | ||
b6254ced | 1735 | #ifdef CONFIG_PPC_FPU_REGS |
18461960 | 1736 | p->thread.fp_save_area = NULL; |
b6254ced | 1737 | #endif |
18461960 PM |
1738 | #ifdef CONFIG_ALTIVEC |
1739 | p->thread.vr_save_area = NULL; | |
1740 | #endif | |
1741 | ||
cec15488 ME |
1742 | setup_ksp_vsid(p, sp); |
1743 | ||
efcac658 AK |
1744 | #ifdef CONFIG_PPC64 |
1745 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1021cb26 | 1746 | p->thread.dscr_inherit = current->thread.dscr_inherit; |
db1231dc | 1747 | p->thread.dscr = mfspr(SPRN_DSCR); |
efcac658 | 1748 | } |
92779245 | 1749 | if (cpu_has_feature(CPU_FTR_HAS_PPR)) |
4c2de74c | 1750 | childregs->ppr = DEFAULT_PPR; |
ec233ede SB |
1751 | |
1752 | p->thread.tidr = 0; | |
f643fcab AK |
1753 | #endif |
1754 | /* | |
1755 | * Run with the current AMR value of the kernel | |
1756 | */ | |
1757 | #ifdef CONFIG_PPC_PKEY | |
1758 | if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP)) | |
1759 | kregs->amr = AMR_KUAP_BLOCKED; | |
1760 | ||
1761 | if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) | |
1762 | kregs->iamr = AMR_KUEP_BLOCKED; | |
efcac658 | 1763 | #endif |
7cedd601 | 1764 | kregs->nip = ppc_function_entry(f); |
14cf11af PM |
1765 | return 0; |
1766 | } | |
1767 | ||
5434ae74 NP |
1768 | void preload_new_slb_context(unsigned long start, unsigned long sp); |
1769 | ||
14cf11af PM |
1770 | /* |
1771 | * Set up a thread for executing a new program | |
1772 | */ | |
06d67d54 | 1773 | void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) |
14cf11af | 1774 | { |
90eac727 ME |
1775 | #ifdef CONFIG_PPC64 |
1776 | unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ | |
5434ae74 | 1777 | |
bfac2799 | 1778 | if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled()) |
f89bd8ba | 1779 | preload_new_slb_context(start, sp); |
90eac727 ME |
1780 | #endif |
1781 | ||
8e96a87c CB |
1782 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1783 | /* | |
1784 | * Clear any transactional state, we're exec()ing. The cause is | |
1785 | * not important as there will never be a recheckpoint so it's not | |
1786 | * user visible. | |
1787 | */ | |
1788 | if (MSR_TM_SUSPENDED(mfmsr())) | |
1789 | tm_reclaim_current(0); | |
1790 | #endif | |
1791 | ||
14cf11af PM |
1792 | memset(regs->gpr, 0, sizeof(regs->gpr)); |
1793 | regs->ctr = 0; | |
1794 | regs->link = 0; | |
1795 | regs->xer = 0; | |
1796 | regs->ccr = 0; | |
14cf11af | 1797 | regs->gpr[1] = sp; |
06d67d54 | 1798 | |
474f8196 RM |
1799 | /* |
1800 | * We have just cleared all the nonvolatile GPRs, so make | |
1801 | * FULL_REGS(regs) return true. This is necessary to allow | |
1802 | * ptrace to examine the thread immediately after exec. | |
1803 | */ | |
feb9df34 | 1804 | SET_FULL_REGS(regs); |
474f8196 | 1805 | |
06d67d54 PM |
1806 | #ifdef CONFIG_PPC32 |
1807 | regs->mq = 0; | |
1808 | regs->nip = start; | |
14cf11af | 1809 | regs->msr = MSR_USER; |
06d67d54 | 1810 | #else |
9904b005 | 1811 | if (!is_32bit_task()) { |
94af3abf | 1812 | unsigned long entry; |
06d67d54 | 1813 | |
94af3abf RR |
1814 | if (is_elf2_task()) { |
1815 | /* Look ma, no function descriptors! */ | |
1816 | entry = start; | |
06d67d54 | 1817 | |
94af3abf RR |
1818 | /* |
1819 | * Ulrich says: | |
1820 | * The latest iteration of the ABI requires that when | |
1821 | * calling a function (at its global entry point), | |
1822 | * the caller must ensure r12 holds the entry point | |
1823 | * address (so that the function can quickly | |
1824 | * establish addressability). | |
1825 | */ | |
1826 | regs->gpr[12] = start; | |
1827 | /* Make sure that's restored on entry to userspace. */ | |
1828 | set_thread_flag(TIF_RESTOREALL); | |
1829 | } else { | |
1830 | unsigned long toc; | |
1831 | ||
1832 | /* start is a relocated pointer to the function | |
1833 | * descriptor for the elf _start routine. The first | |
1834 | * entry in the function descriptor is the entry | |
1835 | * address of _start and the second entry is the TOC | |
1836 | * value we need to use. | |
1837 | */ | |
1838 | __get_user(entry, (unsigned long __user *)start); | |
1839 | __get_user(toc, (unsigned long __user *)start+1); | |
1840 | ||
1841 | /* Check whether the e_entry function descriptor entries | |
1842 | * need to be relocated before we can use them. | |
1843 | */ | |
1844 | if (load_addr != 0) { | |
1845 | entry += load_addr; | |
1846 | toc += load_addr; | |
1847 | } | |
1848 | regs->gpr[2] = toc; | |
06d67d54 PM |
1849 | } |
1850 | regs->nip = entry; | |
06d67d54 | 1851 | regs->msr = MSR_USER64; |
d4bf9a78 SR |
1852 | } else { |
1853 | regs->nip = start; | |
1854 | regs->gpr[2] = 0; | |
1855 | regs->msr = MSR_USER32; | |
06d67d54 PM |
1856 | } |
1857 | #endif | |
ce48b210 MN |
1858 | #ifdef CONFIG_VSX |
1859 | current->thread.used_vsr = 0; | |
1860 | #endif | |
5434ae74 | 1861 | current->thread.load_slb = 0; |
1195892c | 1862 | current->thread.load_fp = 0; |
b6254ced | 1863 | #ifdef CONFIG_PPC_FPU_REGS |
de79f7b9 | 1864 | memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); |
18461960 | 1865 | current->thread.fp_save_area = NULL; |
b6254ced | 1866 | #endif |
14cf11af | 1867 | #ifdef CONFIG_ALTIVEC |
de79f7b9 PM |
1868 | memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); |
1869 | current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ | |
18461960 | 1870 | current->thread.vr_save_area = NULL; |
14cf11af PM |
1871 | current->thread.vrsave = 0; |
1872 | current->thread.used_vr = 0; | |
1195892c | 1873 | current->thread.load_vec = 0; |
14cf11af PM |
1874 | #endif /* CONFIG_ALTIVEC */ |
1875 | #ifdef CONFIG_SPE | |
1876 | memset(current->thread.evr, 0, sizeof(current->thread.evr)); | |
1877 | current->thread.acc = 0; | |
1878 | current->thread.spefscr = 0; | |
1879 | current->thread.used_spe = 0; | |
1880 | #endif /* CONFIG_SPE */ | |
bc2a9408 | 1881 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
bc2a9408 MN |
1882 | current->thread.tm_tfhar = 0; |
1883 | current->thread.tm_texasr = 0; | |
1884 | current->thread.tm_tfiar = 0; | |
7f22ced4 | 1885 | current->thread.load_tm = 0; |
bc2a9408 | 1886 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
06bb53b3 | 1887 | |
14cf11af | 1888 | } |
e1802b06 | 1889 | EXPORT_SYMBOL(start_thread); |
14cf11af PM |
1890 | |
1891 | #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ | |
1892 | | PR_FP_EXC_RES | PR_FP_EXC_INV) | |
1893 | ||
1894 | int set_fpexc_mode(struct task_struct *tsk, unsigned int val) | |
1895 | { | |
1896 | struct pt_regs *regs = tsk->thread.regs; | |
1897 | ||
1898 | /* This is a bit hairy. If we are an SPE enabled processor | |
1899 | * (have embedded fp) we store the IEEE exception enable flags in | |
1900 | * fpexc_mode. fpexc_mode is also used for setting FP exception | |
1901 | * mode (asyn, precise, disabled) for 'Classic' FP. */ | |
1902 | if (val & PR_FP_EXC_SW_ENABLE) { | |
5e14d21e | 1903 | if (cpu_has_feature(CPU_FTR_SPE)) { |
640e9225 JM |
1904 | /* |
1905 | * When the sticky exception bits are set | |
1906 | * directly by userspace, it must call prctl | |
1907 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1908 | * in the existing prctl settings) or | |
1909 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1910 | * the bits being set). <fenv.h> functions | |
1911 | * saving and restoring the whole | |
1912 | * floating-point environment need to do so | |
1913 | * anyway to restore the prctl settings from | |
1914 | * the saved environment. | |
1915 | */ | |
532ed190 | 1916 | #ifdef CONFIG_SPE |
640e9225 | 1917 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); |
5e14d21e KG |
1918 | tsk->thread.fpexc_mode = val & |
1919 | (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); | |
532ed190 | 1920 | #endif |
5e14d21e KG |
1921 | return 0; |
1922 | } else { | |
1923 | return -EINVAL; | |
1924 | } | |
14cf11af | 1925 | } |
06d67d54 PM |
1926 | |
1927 | /* on a CONFIG_SPE this does not hurt us. The bits that | |
1928 | * __pack_fe01 use do not overlap with bits used for | |
1929 | * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits | |
1930 | * on CONFIG_SPE implementations are reserved so writing to | |
1931 | * them does not change anything */ | |
1932 | if (val > PR_FP_EXC_PRECISE) | |
1933 | return -EINVAL; | |
1934 | tsk->thread.fpexc_mode = __pack_fe01(val); | |
1935 | if (regs != NULL && (regs->msr & MSR_FP) != 0) | |
1936 | regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) | |
1937 | | tsk->thread.fpexc_mode; | |
14cf11af PM |
1938 | return 0; |
1939 | } | |
1940 | ||
1941 | int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) | |
1942 | { | |
d208e13c | 1943 | unsigned int val = 0; |
14cf11af | 1944 | |
532ed190 | 1945 | if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) { |
640e9225 JM |
1946 | if (cpu_has_feature(CPU_FTR_SPE)) { |
1947 | /* | |
1948 | * When the sticky exception bits are set | |
1949 | * directly by userspace, it must call prctl | |
1950 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1951 | * in the existing prctl settings) or | |
1952 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1953 | * the bits being set). <fenv.h> functions | |
1954 | * saving and restoring the whole | |
1955 | * floating-point environment need to do so | |
1956 | * anyway to restore the prctl settings from | |
1957 | * the saved environment. | |
1958 | */ | |
532ed190 | 1959 | #ifdef CONFIG_SPE |
640e9225 | 1960 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); |
5e14d21e | 1961 | val = tsk->thread.fpexc_mode; |
532ed190 | 1962 | #endif |
640e9225 | 1963 | } else |
5e14d21e | 1964 | return -EINVAL; |
532ed190 | 1965 | } else { |
14cf11af | 1966 | val = __unpack_fe01(tsk->thread.fpexc_mode); |
532ed190 | 1967 | } |
14cf11af PM |
1968 | return put_user(val, (unsigned int __user *) adr); |
1969 | } | |
1970 | ||
fab5db97 PM |
1971 | int set_endian(struct task_struct *tsk, unsigned int val) |
1972 | { | |
1973 | struct pt_regs *regs = tsk->thread.regs; | |
1974 | ||
1975 | if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || | |
1976 | (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) | |
1977 | return -EINVAL; | |
1978 | ||
1979 | if (regs == NULL) | |
1980 | return -EINVAL; | |
1981 | ||
1982 | if (val == PR_ENDIAN_BIG) | |
1983 | regs->msr &= ~MSR_LE; | |
1984 | else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) | |
1985 | regs->msr |= MSR_LE; | |
1986 | else | |
1987 | return -EINVAL; | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | ||
1992 | int get_endian(struct task_struct *tsk, unsigned long adr) | |
1993 | { | |
1994 | struct pt_regs *regs = tsk->thread.regs; | |
1995 | unsigned int val; | |
1996 | ||
1997 | if (!cpu_has_feature(CPU_FTR_PPC_LE) && | |
1998 | !cpu_has_feature(CPU_FTR_REAL_LE)) | |
1999 | return -EINVAL; | |
2000 | ||
2001 | if (regs == NULL) | |
2002 | return -EINVAL; | |
2003 | ||
2004 | if (regs->msr & MSR_LE) { | |
2005 | if (cpu_has_feature(CPU_FTR_REAL_LE)) | |
2006 | val = PR_ENDIAN_LITTLE; | |
2007 | else | |
2008 | val = PR_ENDIAN_PPC_LITTLE; | |
2009 | } else | |
2010 | val = PR_ENDIAN_BIG; | |
2011 | ||
2012 | return put_user(val, (unsigned int __user *)adr); | |
2013 | } | |
2014 | ||
e9370ae1 PM |
2015 | int set_unalign_ctl(struct task_struct *tsk, unsigned int val) |
2016 | { | |
2017 | tsk->thread.align_ctl = val; | |
2018 | return 0; | |
2019 | } | |
2020 | ||
2021 | int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) | |
2022 | { | |
2023 | return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); | |
2024 | } | |
2025 | ||
bb72c481 PM |
2026 | static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, |
2027 | unsigned long nbytes) | |
2028 | { | |
2029 | unsigned long stack_page; | |
2030 | unsigned long cpu = task_cpu(p); | |
2031 | ||
a7916a1d CL |
2032 | stack_page = (unsigned long)hardirq_ctx[cpu]; |
2033 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2034 | return 1; | |
2035 | ||
2036 | stack_page = (unsigned long)softirq_ctx[cpu]; | |
2037 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2038 | return 1; | |
2039 | ||
bb72c481 PM |
2040 | return 0; |
2041 | } | |
2042 | ||
a2e36683 NP |
2043 | static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p, |
2044 | unsigned long nbytes) | |
2045 | { | |
2046 | #ifdef CONFIG_PPC64 | |
2047 | unsigned long stack_page; | |
2048 | unsigned long cpu = task_cpu(p); | |
2049 | ||
2050 | stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE; | |
2051 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2052 | return 1; | |
2053 | ||
2054 | # ifdef CONFIG_PPC_BOOK3S_64 | |
2055 | stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE; | |
2056 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2057 | return 1; | |
2058 | ||
2059 | stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE; | |
2060 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
2061 | return 1; | |
2062 | # endif | |
2063 | #endif | |
2064 | ||
2065 | return 0; | |
2066 | } | |
2067 | ||
2068 | ||
2f25194d | 2069 | int validate_sp(unsigned long sp, struct task_struct *p, |
14cf11af PM |
2070 | unsigned long nbytes) |
2071 | { | |
0cec6fd1 | 2072 | unsigned long stack_page = (unsigned long)task_stack_page(p); |
14cf11af | 2073 | |
a7916a1d CL |
2074 | if (sp < THREAD_SIZE) |
2075 | return 0; | |
2076 | ||
2077 | if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes) | |
14cf11af PM |
2078 | return 1; |
2079 | ||
a2e36683 NP |
2080 | if (valid_irq_stack(sp, p, nbytes)) |
2081 | return 1; | |
2082 | ||
2083 | return valid_emergency_stack(sp, p, nbytes); | |
14cf11af PM |
2084 | } |
2085 | ||
2f25194d AB |
2086 | EXPORT_SYMBOL(validate_sp); |
2087 | ||
018cce33 | 2088 | static unsigned long __get_wchan(struct task_struct *p) |
14cf11af PM |
2089 | { |
2090 | unsigned long ip, sp; | |
2091 | int count = 0; | |
2092 | ||
2093 | if (!p || p == current || p->state == TASK_RUNNING) | |
2094 | return 0; | |
2095 | ||
2096 | sp = p->thread.ksp; | |
ec2b36b9 | 2097 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
2098 | return 0; |
2099 | ||
2100 | do { | |
2101 | sp = *(unsigned long *)sp; | |
4ca360f3 KC |
2102 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || |
2103 | p->state == TASK_RUNNING) | |
14cf11af PM |
2104 | return 0; |
2105 | if (count > 0) { | |
ec2b36b9 | 2106 | ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; |
14cf11af PM |
2107 | if (!in_sched_functions(ip)) |
2108 | return ip; | |
2109 | } | |
2110 | } while (count++ < 16); | |
2111 | return 0; | |
2112 | } | |
06d67d54 | 2113 | |
018cce33 CL |
2114 | unsigned long get_wchan(struct task_struct *p) |
2115 | { | |
2116 | unsigned long ret; | |
2117 | ||
2118 | if (!try_get_task_stack(p)) | |
2119 | return 0; | |
2120 | ||
2121 | ret = __get_wchan(p); | |
2122 | ||
2123 | put_task_stack(p); | |
2124 | ||
2125 | return ret; | |
2126 | } | |
2127 | ||
c4d04be1 | 2128 | static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; |
06d67d54 | 2129 | |
9cb8f069 DS |
2130 | void show_stack(struct task_struct *tsk, unsigned long *stack, |
2131 | const char *loglvl) | |
06d67d54 PM |
2132 | { |
2133 | unsigned long sp, ip, lr, newsp; | |
2134 | int count = 0; | |
2135 | int firstframe = 1; | |
7c1bb6bb NR |
2136 | unsigned long ret_addr; |
2137 | int ftrace_idx = 0; | |
06d67d54 | 2138 | |
06d67d54 PM |
2139 | if (tsk == NULL) |
2140 | tsk = current; | |
018cce33 CL |
2141 | |
2142 | if (!try_get_task_stack(tsk)) | |
2143 | return; | |
2144 | ||
2145 | sp = (unsigned long) stack; | |
06d67d54 PM |
2146 | if (sp == 0) { |
2147 | if (tsk == current) | |
3d13e839 | 2148 | sp = current_stack_frame(); |
06d67d54 PM |
2149 | else |
2150 | sp = tsk->thread.ksp; | |
2151 | } | |
2152 | ||
2153 | lr = 0; | |
b9677a8c | 2154 | printk("%sCall Trace:\n", loglvl); |
06d67d54 | 2155 | do { |
ec2b36b9 | 2156 | if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) |
018cce33 | 2157 | break; |
06d67d54 PM |
2158 | |
2159 | stack = (unsigned long *) sp; | |
2160 | newsp = stack[0]; | |
ec2b36b9 | 2161 | ip = stack[STACK_FRAME_LR_SAVE]; |
06d67d54 | 2162 | if (!firstframe || ip != lr) { |
b9677a8c DS |
2163 | printk("%s["REG"] ["REG"] %pS", |
2164 | loglvl, sp, ip, (void *)ip); | |
7c1bb6bb NR |
2165 | ret_addr = ftrace_graph_ret_addr(current, |
2166 | &ftrace_idx, ip, stack); | |
2167 | if (ret_addr != ip) | |
2168 | pr_cont(" (%pS)", (void *)ret_addr); | |
06d67d54 | 2169 | if (firstframe) |
9a1f490f ME |
2170 | pr_cont(" (unreliable)"); |
2171 | pr_cont("\n"); | |
06d67d54 PM |
2172 | } |
2173 | firstframe = 0; | |
2174 | ||
2175 | /* | |
2176 | * See if this is an exception frame. | |
2177 | * We look for the "regshere" marker in the current frame. | |
2178 | */ | |
ec2b36b9 BH |
2179 | if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) |
2180 | && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { | |
06d67d54 PM |
2181 | struct pt_regs *regs = (struct pt_regs *) |
2182 | (sp + STACK_FRAME_OVERHEAD); | |
bf13718b | 2183 | |
06d67d54 | 2184 | lr = regs->link; |
bf13718b NP |
2185 | printk("%s--- interrupt: %lx at %pS\n", |
2186 | loglvl, regs->trap, (void *)regs->nip); | |
2187 | __show_regs(regs); | |
2188 | printk("%s--- interrupt: %lx\n", | |
2189 | loglvl, regs->trap); | |
2190 | ||
06d67d54 PM |
2191 | firstframe = 1; |
2192 | } | |
2193 | ||
2194 | sp = newsp; | |
2195 | } while (count++ < kstack_depth_to_print); | |
018cce33 CL |
2196 | |
2197 | put_task_stack(tsk); | |
06d67d54 PM |
2198 | } |
2199 | ||
cb2c9b27 | 2200 | #ifdef CONFIG_PPC64 |
fe1952fc | 2201 | /* Called with hard IRQs off */ |
0e37739b | 2202 | void notrace __ppc64_runlatch_on(void) |
cb2c9b27 | 2203 | { |
fe1952fc | 2204 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 | 2205 | |
d1d0d5ff NP |
2206 | if (cpu_has_feature(CPU_FTR_ARCH_206)) { |
2207 | /* | |
2208 | * Least significant bit (RUN) is the only writable bit of | |
2209 | * the CTRL register, so we can avoid mfspr. 2.06 is not the | |
2210 | * earliest ISA where this is the case, but it's convenient. | |
2211 | */ | |
2212 | mtspr(SPRN_CTRLT, CTRL_RUNLATCH); | |
2213 | } else { | |
2214 | unsigned long ctrl; | |
2215 | ||
2216 | /* | |
2217 | * Some architectures (e.g., Cell) have writable fields other | |
2218 | * than RUN, so do the read-modify-write. | |
2219 | */ | |
2220 | ctrl = mfspr(SPRN_CTRLF); | |
2221 | ctrl |= CTRL_RUNLATCH; | |
2222 | mtspr(SPRN_CTRLT, ctrl); | |
2223 | } | |
cb2c9b27 | 2224 | |
fae2e0fb | 2225 | ti->local_flags |= _TLF_RUNLATCH; |
cb2c9b27 AB |
2226 | } |
2227 | ||
fe1952fc | 2228 | /* Called with hard IRQs off */ |
0e37739b | 2229 | void notrace __ppc64_runlatch_off(void) |
cb2c9b27 | 2230 | { |
fe1952fc | 2231 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 | 2232 | |
fae2e0fb | 2233 | ti->local_flags &= ~_TLF_RUNLATCH; |
cb2c9b27 | 2234 | |
d1d0d5ff NP |
2235 | if (cpu_has_feature(CPU_FTR_ARCH_206)) { |
2236 | mtspr(SPRN_CTRLT, 0); | |
2237 | } else { | |
2238 | unsigned long ctrl; | |
2239 | ||
2240 | ctrl = mfspr(SPRN_CTRLF); | |
2241 | ctrl &= ~CTRL_RUNLATCH; | |
2242 | mtspr(SPRN_CTRLT, ctrl); | |
2243 | } | |
cb2c9b27 | 2244 | } |
fe1952fc | 2245 | #endif /* CONFIG_PPC64 */ |
f6a61680 | 2246 | |
d839088c AB |
2247 | unsigned long arch_align_stack(unsigned long sp) |
2248 | { | |
2249 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
2250 | sp -= get_random_int() & ~PAGE_MASK; | |
2251 | return sp & ~0xf; | |
2252 | } | |
912f9ee2 AB |
2253 | |
2254 | static inline unsigned long brk_rnd(void) | |
2255 | { | |
2256 | unsigned long rnd = 0; | |
2257 | ||
2258 | /* 8MB for 32bit, 1GB for 64bit */ | |
2259 | if (is_32bit_task()) | |
5ef11c35 | 2260 | rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); |
912f9ee2 | 2261 | else |
5ef11c35 | 2262 | rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); |
912f9ee2 AB |
2263 | |
2264 | return rnd << PAGE_SHIFT; | |
2265 | } | |
2266 | ||
2267 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
2268 | { | |
8bbde7a7 AB |
2269 | unsigned long base = mm->brk; |
2270 | unsigned long ret; | |
2271 | ||
4e003747 | 2272 | #ifdef CONFIG_PPC_BOOK3S_64 |
8bbde7a7 AB |
2273 | /* |
2274 | * If we are using 1TB segments and we are allowed to randomise | |
2275 | * the heap, we can put it above 1TB so it is backed by a 1TB | |
2276 | * segment. Otherwise the heap will be in the bottom 1TB | |
2277 | * which always uses 256MB segments and this may result in a | |
caca285e AK |
2278 | * performance penalty. We don't need to worry about radix. For |
2279 | * radix, mmu_highuser_ssize remains unchanged from 256MB. | |
8bbde7a7 AB |
2280 | */ |
2281 | if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) | |
2282 | base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); | |
2283 | #endif | |
2284 | ||
2285 | ret = PAGE_ALIGN(base + brk_rnd()); | |
912f9ee2 AB |
2286 | |
2287 | if (ret < mm->brk) | |
2288 | return mm->brk; | |
2289 | ||
2290 | return ret; | |
2291 | } | |
501cb16d | 2292 |