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Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Derived from "arch/i386/kernel/process.c" |
3 | * Copyright (C) 1995 Linus Torvalds | |
4 | * | |
5 | * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and | |
6 | * Paul Mackerras (paulus@cs.anu.edu.au) | |
7 | * | |
8 | * PowerPC version | |
9 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
14cf11af PM |
22 | #include <linux/stddef.h> |
23 | #include <linux/unistd.h> | |
24 | #include <linux/ptrace.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/user.h> | |
27 | #include <linux/elf.h> | |
14cf11af PM |
28 | #include <linux/prctl.h> |
29 | #include <linux/init_task.h> | |
4b16f8e2 | 30 | #include <linux/export.h> |
14cf11af PM |
31 | #include <linux/kallsyms.h> |
32 | #include <linux/mqueue.h> | |
33 | #include <linux/hardirq.h> | |
06d67d54 | 34 | #include <linux/utsname.h> |
6794c782 | 35 | #include <linux/ftrace.h> |
79741dd3 | 36 | #include <linux/kernel_stat.h> |
d839088c AB |
37 | #include <linux/personality.h> |
38 | #include <linux/random.h> | |
5aae8a53 | 39 | #include <linux/hw_breakpoint.h> |
7b051f66 | 40 | #include <linux/uaccess.h> |
14cf11af PM |
41 | |
42 | #include <asm/pgtable.h> | |
14cf11af PM |
43 | #include <asm/io.h> |
44 | #include <asm/processor.h> | |
45 | #include <asm/mmu.h> | |
46 | #include <asm/prom.h> | |
76032de8 | 47 | #include <asm/machdep.h> |
c6622f63 | 48 | #include <asm/time.h> |
ae3a197e | 49 | #include <asm/runlatch.h> |
a7f31841 | 50 | #include <asm/syscalls.h> |
ae3a197e | 51 | #include <asm/switch_to.h> |
fb09692e | 52 | #include <asm/tm.h> |
ae3a197e | 53 | #include <asm/debug.h> |
06d67d54 PM |
54 | #ifdef CONFIG_PPC64 |
55 | #include <asm/firmware.h> | |
06d67d54 | 56 | #endif |
7cedd601 | 57 | #include <asm/code-patching.h> |
d6a61bfc LM |
58 | #include <linux/kprobes.h> |
59 | #include <linux/kdebug.h> | |
14cf11af | 60 | |
8b3c34cf MN |
61 | /* Transactional Memory debug */ |
62 | #ifdef TM_DEBUG_SW | |
63 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
64 | #else | |
65 | #define TM_DEBUG(x...) do { } while(0) | |
66 | #endif | |
67 | ||
14cf11af PM |
68 | extern unsigned long _get_SP(void); |
69 | ||
d31626f7 | 70 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
b86fd2bd | 71 | static void check_if_tm_restore_required(struct task_struct *tsk) |
d31626f7 PM |
72 | { |
73 | /* | |
74 | * If we are saving the current thread's registers, and the | |
75 | * thread is in a transactional state, set the TIF_RESTORE_TM | |
76 | * bit so that we know to restore the registers before | |
77 | * returning to userspace. | |
78 | */ | |
79 | if (tsk == current && tsk->thread.regs && | |
80 | MSR_TM_ACTIVE(tsk->thread.regs->msr) && | |
81 | !test_thread_flag(TIF_RESTORE_TM)) { | |
829023df | 82 | tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; |
d31626f7 PM |
83 | set_thread_flag(TIF_RESTORE_TM); |
84 | } | |
d31626f7 | 85 | } |
d31626f7 | 86 | #else |
b86fd2bd | 87 | static inline void check_if_tm_restore_required(struct task_struct *tsk) { } |
d31626f7 PM |
88 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
89 | ||
3eb5d588 AB |
90 | bool strict_msr_control; |
91 | EXPORT_SYMBOL(strict_msr_control); | |
92 | ||
93 | static int __init enable_strict_msr_control(char *str) | |
94 | { | |
95 | strict_msr_control = true; | |
96 | pr_info("Enabling strict facility control\n"); | |
97 | ||
98 | return 0; | |
99 | } | |
100 | early_param("ppc_strict_facility_enable", enable_strict_msr_control); | |
101 | ||
102 | void msr_check_and_set(unsigned long bits) | |
98da581e | 103 | { |
a0e72cf1 AB |
104 | unsigned long oldmsr = mfmsr(); |
105 | unsigned long newmsr; | |
98da581e | 106 | |
a0e72cf1 | 107 | newmsr = oldmsr | bits; |
98da581e | 108 | |
98da581e | 109 | #ifdef CONFIG_VSX |
a0e72cf1 | 110 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
98da581e AB |
111 | newmsr |= MSR_VSX; |
112 | #endif | |
a0e72cf1 | 113 | |
98da581e AB |
114 | if (oldmsr != newmsr) |
115 | mtmsr_isync(newmsr); | |
a0e72cf1 | 116 | } |
98da581e | 117 | |
3eb5d588 | 118 | void __msr_check_and_clear(unsigned long bits) |
a0e72cf1 AB |
119 | { |
120 | unsigned long oldmsr = mfmsr(); | |
121 | unsigned long newmsr; | |
122 | ||
123 | newmsr = oldmsr & ~bits; | |
124 | ||
125 | #ifdef CONFIG_VSX | |
126 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) | |
127 | newmsr &= ~MSR_VSX; | |
128 | #endif | |
129 | ||
130 | if (oldmsr != newmsr) | |
131 | mtmsr_isync(newmsr); | |
132 | } | |
3eb5d588 | 133 | EXPORT_SYMBOL(__msr_check_and_clear); |
a0e72cf1 AB |
134 | |
135 | #ifdef CONFIG_PPC_FPU | |
136 | void giveup_fpu(struct task_struct *tsk) | |
137 | { | |
138 | check_if_tm_restore_required(tsk); | |
139 | ||
140 | msr_check_and_set(MSR_FP); | |
98da581e | 141 | __giveup_fpu(tsk); |
a0e72cf1 | 142 | msr_check_and_clear(MSR_FP); |
98da581e AB |
143 | } |
144 | EXPORT_SYMBOL(giveup_fpu); | |
145 | ||
14cf11af PM |
146 | /* |
147 | * Make sure the floating-point register state in the | |
148 | * the thread_struct is up to date for task tsk. | |
149 | */ | |
150 | void flush_fp_to_thread(struct task_struct *tsk) | |
151 | { | |
152 | if (tsk->thread.regs) { | |
153 | /* | |
154 | * We need to disable preemption here because if we didn't, | |
155 | * another process could get scheduled after the regs->msr | |
156 | * test but before we have finished saving the FP registers | |
157 | * to the thread_struct. That process could take over the | |
158 | * FPU, and then when we get scheduled again we would store | |
159 | * bogus values for the remaining FP registers. | |
160 | */ | |
161 | preempt_disable(); | |
162 | if (tsk->thread.regs->msr & MSR_FP) { | |
14cf11af PM |
163 | /* |
164 | * This should only ever be called for current or | |
165 | * for a stopped child process. Since we save away | |
af1bbc3d | 166 | * the FP register state on context switch, |
14cf11af PM |
167 | * there is something wrong if a stopped child appears |
168 | * to still have its FP state in the CPU registers. | |
169 | */ | |
170 | BUG_ON(tsk != current); | |
b86fd2bd | 171 | giveup_fpu(tsk); |
14cf11af PM |
172 | } |
173 | preempt_enable(); | |
174 | } | |
175 | } | |
de56a948 | 176 | EXPORT_SYMBOL_GPL(flush_fp_to_thread); |
14cf11af PM |
177 | |
178 | void enable_kernel_fp(void) | |
179 | { | |
180 | WARN_ON(preemptible()); | |
181 | ||
a0e72cf1 | 182 | msr_check_and_set(MSR_FP); |
611b0e5c | 183 | |
d64d02ce AB |
184 | if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { |
185 | check_if_tm_restore_required(current); | |
a0e72cf1 | 186 | __giveup_fpu(current); |
d64d02ce | 187 | } |
14cf11af PM |
188 | } |
189 | EXPORT_SYMBOL(enable_kernel_fp); | |
70fe3d98 CB |
190 | |
191 | static int restore_fp(struct task_struct *tsk) { | |
192 | if (tsk->thread.load_fp) { | |
193 | load_fp_state(¤t->thread.fp_state); | |
194 | current->thread.load_fp++; | |
195 | return 1; | |
196 | } | |
197 | return 0; | |
198 | } | |
199 | #else | |
200 | static int restore_fp(struct task_struct *tsk) { return 0; } | |
d1e1cf2e | 201 | #endif /* CONFIG_PPC_FPU */ |
14cf11af | 202 | |
14cf11af | 203 | #ifdef CONFIG_ALTIVEC |
70fe3d98 CB |
204 | #define loadvec(thr) ((thr).load_vec) |
205 | ||
98da581e AB |
206 | void giveup_altivec(struct task_struct *tsk) |
207 | { | |
98da581e AB |
208 | check_if_tm_restore_required(tsk); |
209 | ||
a0e72cf1 | 210 | msr_check_and_set(MSR_VEC); |
98da581e | 211 | __giveup_altivec(tsk); |
a0e72cf1 | 212 | msr_check_and_clear(MSR_VEC); |
98da581e AB |
213 | } |
214 | EXPORT_SYMBOL(giveup_altivec); | |
215 | ||
14cf11af PM |
216 | void enable_kernel_altivec(void) |
217 | { | |
218 | WARN_ON(preemptible()); | |
219 | ||
a0e72cf1 | 220 | msr_check_and_set(MSR_VEC); |
611b0e5c | 221 | |
d64d02ce AB |
222 | if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { |
223 | check_if_tm_restore_required(current); | |
a0e72cf1 | 224 | __giveup_altivec(current); |
d64d02ce | 225 | } |
14cf11af PM |
226 | } |
227 | EXPORT_SYMBOL(enable_kernel_altivec); | |
228 | ||
229 | /* | |
230 | * Make sure the VMX/Altivec register state in the | |
231 | * the thread_struct is up to date for task tsk. | |
232 | */ | |
233 | void flush_altivec_to_thread(struct task_struct *tsk) | |
234 | { | |
235 | if (tsk->thread.regs) { | |
236 | preempt_disable(); | |
237 | if (tsk->thread.regs->msr & MSR_VEC) { | |
14cf11af | 238 | BUG_ON(tsk != current); |
b86fd2bd | 239 | giveup_altivec(tsk); |
14cf11af PM |
240 | } |
241 | preempt_enable(); | |
242 | } | |
243 | } | |
de56a948 | 244 | EXPORT_SYMBOL_GPL(flush_altivec_to_thread); |
70fe3d98 CB |
245 | |
246 | static int restore_altivec(struct task_struct *tsk) | |
247 | { | |
248 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && tsk->thread.load_vec) { | |
249 | load_vr_state(&tsk->thread.vr_state); | |
250 | tsk->thread.used_vr = 1; | |
251 | tsk->thread.load_vec++; | |
252 | ||
253 | return 1; | |
254 | } | |
255 | return 0; | |
256 | } | |
257 | #else | |
258 | #define loadvec(thr) 0 | |
259 | static inline int restore_altivec(struct task_struct *tsk) { return 0; } | |
14cf11af PM |
260 | #endif /* CONFIG_ALTIVEC */ |
261 | ||
ce48b210 | 262 | #ifdef CONFIG_VSX |
a7d623d4 AB |
263 | void giveup_vsx(struct task_struct *tsk) |
264 | { | |
a7d623d4 AB |
265 | check_if_tm_restore_required(tsk); |
266 | ||
a0e72cf1 | 267 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); |
a7d623d4 AB |
268 | if (tsk->thread.regs->msr & MSR_FP) |
269 | __giveup_fpu(tsk); | |
270 | if (tsk->thread.regs->msr & MSR_VEC) | |
271 | __giveup_altivec(tsk); | |
272 | __giveup_vsx(tsk); | |
a0e72cf1 | 273 | msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); |
a7d623d4 AB |
274 | } |
275 | EXPORT_SYMBOL(giveup_vsx); | |
276 | ||
ce48b210 MN |
277 | void enable_kernel_vsx(void) |
278 | { | |
279 | WARN_ON(preemptible()); | |
280 | ||
a0e72cf1 | 281 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); |
611b0e5c | 282 | |
a0e72cf1 | 283 | if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { |
d64d02ce | 284 | check_if_tm_restore_required(current); |
a0e72cf1 AB |
285 | if (current->thread.regs->msr & MSR_FP) |
286 | __giveup_fpu(current); | |
287 | if (current->thread.regs->msr & MSR_VEC) | |
288 | __giveup_altivec(current); | |
289 | __giveup_vsx(current); | |
611b0e5c | 290 | } |
ce48b210 MN |
291 | } |
292 | EXPORT_SYMBOL(enable_kernel_vsx); | |
ce48b210 MN |
293 | |
294 | void flush_vsx_to_thread(struct task_struct *tsk) | |
295 | { | |
296 | if (tsk->thread.regs) { | |
297 | preempt_disable(); | |
298 | if (tsk->thread.regs->msr & MSR_VSX) { | |
ce48b210 | 299 | BUG_ON(tsk != current); |
ce48b210 MN |
300 | giveup_vsx(tsk); |
301 | } | |
302 | preempt_enable(); | |
303 | } | |
304 | } | |
de56a948 | 305 | EXPORT_SYMBOL_GPL(flush_vsx_to_thread); |
70fe3d98 CB |
306 | |
307 | static int restore_vsx(struct task_struct *tsk) | |
308 | { | |
309 | if (cpu_has_feature(CPU_FTR_VSX)) { | |
310 | tsk->thread.used_vsr = 1; | |
311 | return 1; | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
316 | #else | |
317 | static inline int restore_vsx(struct task_struct *tsk) { return 0; } | |
ce48b210 MN |
318 | #endif /* CONFIG_VSX */ |
319 | ||
14cf11af | 320 | #ifdef CONFIG_SPE |
98da581e AB |
321 | void giveup_spe(struct task_struct *tsk) |
322 | { | |
98da581e AB |
323 | check_if_tm_restore_required(tsk); |
324 | ||
a0e72cf1 | 325 | msr_check_and_set(MSR_SPE); |
98da581e | 326 | __giveup_spe(tsk); |
a0e72cf1 | 327 | msr_check_and_clear(MSR_SPE); |
98da581e AB |
328 | } |
329 | EXPORT_SYMBOL(giveup_spe); | |
14cf11af PM |
330 | |
331 | void enable_kernel_spe(void) | |
332 | { | |
333 | WARN_ON(preemptible()); | |
334 | ||
a0e72cf1 | 335 | msr_check_and_set(MSR_SPE); |
611b0e5c | 336 | |
d64d02ce AB |
337 | if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { |
338 | check_if_tm_restore_required(current); | |
a0e72cf1 | 339 | __giveup_spe(current); |
d64d02ce | 340 | } |
14cf11af PM |
341 | } |
342 | EXPORT_SYMBOL(enable_kernel_spe); | |
343 | ||
344 | void flush_spe_to_thread(struct task_struct *tsk) | |
345 | { | |
346 | if (tsk->thread.regs) { | |
347 | preempt_disable(); | |
348 | if (tsk->thread.regs->msr & MSR_SPE) { | |
14cf11af | 349 | BUG_ON(tsk != current); |
685659ee | 350 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); |
0ee6c15e | 351 | giveup_spe(tsk); |
14cf11af PM |
352 | } |
353 | preempt_enable(); | |
354 | } | |
355 | } | |
14cf11af PM |
356 | #endif /* CONFIG_SPE */ |
357 | ||
c2085059 AB |
358 | static unsigned long msr_all_available; |
359 | ||
360 | static int __init init_msr_all_available(void) | |
361 | { | |
362 | #ifdef CONFIG_PPC_FPU | |
363 | msr_all_available |= MSR_FP; | |
364 | #endif | |
365 | #ifdef CONFIG_ALTIVEC | |
366 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | |
367 | msr_all_available |= MSR_VEC; | |
368 | #endif | |
369 | #ifdef CONFIG_VSX | |
370 | if (cpu_has_feature(CPU_FTR_VSX)) | |
371 | msr_all_available |= MSR_VSX; | |
372 | #endif | |
373 | #ifdef CONFIG_SPE | |
374 | if (cpu_has_feature(CPU_FTR_SPE)) | |
375 | msr_all_available |= MSR_SPE; | |
376 | #endif | |
377 | ||
378 | return 0; | |
379 | } | |
380 | early_initcall(init_msr_all_available); | |
381 | ||
382 | void giveup_all(struct task_struct *tsk) | |
383 | { | |
384 | unsigned long usermsr; | |
385 | ||
386 | if (!tsk->thread.regs) | |
387 | return; | |
388 | ||
389 | usermsr = tsk->thread.regs->msr; | |
390 | ||
391 | if ((usermsr & msr_all_available) == 0) | |
392 | return; | |
393 | ||
394 | msr_check_and_set(msr_all_available); | |
395 | ||
396 | #ifdef CONFIG_PPC_FPU | |
397 | if (usermsr & MSR_FP) | |
398 | __giveup_fpu(tsk); | |
399 | #endif | |
400 | #ifdef CONFIG_ALTIVEC | |
401 | if (usermsr & MSR_VEC) | |
402 | __giveup_altivec(tsk); | |
403 | #endif | |
404 | #ifdef CONFIG_VSX | |
405 | if (usermsr & MSR_VSX) | |
406 | __giveup_vsx(tsk); | |
407 | #endif | |
408 | #ifdef CONFIG_SPE | |
409 | if (usermsr & MSR_SPE) | |
410 | __giveup_spe(tsk); | |
411 | #endif | |
412 | ||
413 | msr_check_and_clear(msr_all_available); | |
414 | } | |
415 | EXPORT_SYMBOL(giveup_all); | |
416 | ||
70fe3d98 CB |
417 | void restore_math(struct pt_regs *regs) |
418 | { | |
419 | unsigned long msr; | |
420 | ||
421 | if (!current->thread.load_fp && !loadvec(current->thread)) | |
422 | return; | |
423 | ||
424 | msr = regs->msr; | |
425 | msr_check_and_set(msr_all_available); | |
426 | ||
427 | /* | |
428 | * Only reload if the bit is not set in the user MSR, the bit BEING set | |
429 | * indicates that the registers are hot | |
430 | */ | |
431 | if ((!(msr & MSR_FP)) && restore_fp(current)) | |
432 | msr |= MSR_FP | current->thread.fpexc_mode; | |
433 | ||
434 | if ((!(msr & MSR_VEC)) && restore_altivec(current)) | |
435 | msr |= MSR_VEC; | |
436 | ||
437 | if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && | |
438 | restore_vsx(current)) { | |
439 | msr |= MSR_VSX; | |
440 | } | |
441 | ||
442 | msr_check_and_clear(msr_all_available); | |
443 | ||
444 | regs->msr = msr; | |
445 | } | |
446 | ||
579e633e AB |
447 | void flush_all_to_thread(struct task_struct *tsk) |
448 | { | |
449 | if (tsk->thread.regs) { | |
450 | preempt_disable(); | |
451 | BUG_ON(tsk != current); | |
452 | giveup_all(tsk); | |
453 | ||
454 | #ifdef CONFIG_SPE | |
455 | if (tsk->thread.regs->msr & MSR_SPE) | |
456 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); | |
457 | #endif | |
458 | ||
459 | preempt_enable(); | |
460 | } | |
461 | } | |
462 | EXPORT_SYMBOL(flush_all_to_thread); | |
463 | ||
3bffb652 DK |
464 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
465 | void do_send_trap(struct pt_regs *regs, unsigned long address, | |
466 | unsigned long error_code, int signal_code, int breakpt) | |
467 | { | |
468 | siginfo_t info; | |
469 | ||
41ab5266 | 470 | current->thread.trap_nr = signal_code; |
3bffb652 DK |
471 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
472 | 11, SIGSEGV) == NOTIFY_STOP) | |
473 | return; | |
474 | ||
475 | /* Deliver the signal to userspace */ | |
476 | info.si_signo = SIGTRAP; | |
477 | info.si_errno = breakpt; /* breakpoint or watchpoint id */ | |
478 | info.si_code = signal_code; | |
479 | info.si_addr = (void __user *)address; | |
480 | force_sig_info(SIGTRAP, &info, current); | |
481 | } | |
482 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
9422de3e | 483 | void do_break (struct pt_regs *regs, unsigned long address, |
d6a61bfc LM |
484 | unsigned long error_code) |
485 | { | |
486 | siginfo_t info; | |
487 | ||
41ab5266 | 488 | current->thread.trap_nr = TRAP_HWBKPT; |
d6a61bfc LM |
489 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
490 | 11, SIGSEGV) == NOTIFY_STOP) | |
491 | return; | |
492 | ||
9422de3e | 493 | if (debugger_break_match(regs)) |
d6a61bfc LM |
494 | return; |
495 | ||
9422de3e MN |
496 | /* Clear the breakpoint */ |
497 | hw_breakpoint_disable(); | |
d6a61bfc LM |
498 | |
499 | /* Deliver the signal to userspace */ | |
500 | info.si_signo = SIGTRAP; | |
501 | info.si_errno = 0; | |
502 | info.si_code = TRAP_HWBKPT; | |
503 | info.si_addr = (void __user *)address; | |
504 | force_sig_info(SIGTRAP, &info, current); | |
505 | } | |
3bffb652 | 506 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc | 507 | |
9422de3e | 508 | static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); |
a2ceff5e | 509 | |
3bffb652 DK |
510 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
511 | /* | |
512 | * Set the debug registers back to their default "safe" values. | |
513 | */ | |
514 | static void set_debug_reg_defaults(struct thread_struct *thread) | |
515 | { | |
51ae8d4a | 516 | thread->debug.iac1 = thread->debug.iac2 = 0; |
3bffb652 | 517 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
51ae8d4a | 518 | thread->debug.iac3 = thread->debug.iac4 = 0; |
3bffb652 | 519 | #endif |
51ae8d4a | 520 | thread->debug.dac1 = thread->debug.dac2 = 0; |
3bffb652 | 521 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
51ae8d4a | 522 | thread->debug.dvc1 = thread->debug.dvc2 = 0; |
3bffb652 | 523 | #endif |
51ae8d4a | 524 | thread->debug.dbcr0 = 0; |
3bffb652 DK |
525 | #ifdef CONFIG_BOOKE |
526 | /* | |
527 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | |
528 | */ | |
51ae8d4a | 529 | thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | |
3bffb652 DK |
530 | DBCR1_IAC3US | DBCR1_IAC4US; |
531 | /* | |
532 | * Force Data Address Compare User/Supervisor bits to be User-only | |
533 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | |
534 | */ | |
51ae8d4a | 535 | thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; |
3bffb652 | 536 | #else |
51ae8d4a | 537 | thread->debug.dbcr1 = 0; |
3bffb652 DK |
538 | #endif |
539 | } | |
540 | ||
f5f97210 | 541 | static void prime_debug_regs(struct debug_reg *debug) |
3bffb652 | 542 | { |
6cecf76b SW |
543 | /* |
544 | * We could have inherited MSR_DE from userspace, since | |
545 | * it doesn't get cleared on exception entry. Make sure | |
546 | * MSR_DE is clear before we enable any debug events. | |
547 | */ | |
548 | mtmsr(mfmsr() & ~MSR_DE); | |
549 | ||
f5f97210 SW |
550 | mtspr(SPRN_IAC1, debug->iac1); |
551 | mtspr(SPRN_IAC2, debug->iac2); | |
3bffb652 | 552 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
f5f97210 SW |
553 | mtspr(SPRN_IAC3, debug->iac3); |
554 | mtspr(SPRN_IAC4, debug->iac4); | |
3bffb652 | 555 | #endif |
f5f97210 SW |
556 | mtspr(SPRN_DAC1, debug->dac1); |
557 | mtspr(SPRN_DAC2, debug->dac2); | |
3bffb652 | 558 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
f5f97210 SW |
559 | mtspr(SPRN_DVC1, debug->dvc1); |
560 | mtspr(SPRN_DVC2, debug->dvc2); | |
3bffb652 | 561 | #endif |
f5f97210 SW |
562 | mtspr(SPRN_DBCR0, debug->dbcr0); |
563 | mtspr(SPRN_DBCR1, debug->dbcr1); | |
3bffb652 | 564 | #ifdef CONFIG_BOOKE |
f5f97210 | 565 | mtspr(SPRN_DBCR2, debug->dbcr2); |
3bffb652 DK |
566 | #endif |
567 | } | |
568 | /* | |
569 | * Unless neither the old or new thread are making use of the | |
570 | * debug registers, set the debug registers from the values | |
571 | * stored in the new thread. | |
572 | */ | |
f5f97210 | 573 | void switch_booke_debug_regs(struct debug_reg *new_debug) |
3bffb652 | 574 | { |
51ae8d4a | 575 | if ((current->thread.debug.dbcr0 & DBCR0_IDM) |
f5f97210 SW |
576 | || (new_debug->dbcr0 & DBCR0_IDM)) |
577 | prime_debug_regs(new_debug); | |
3bffb652 | 578 | } |
3743c9b8 | 579 | EXPORT_SYMBOL_GPL(switch_booke_debug_regs); |
3bffb652 | 580 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ |
e0780b72 | 581 | #ifndef CONFIG_HAVE_HW_BREAKPOINT |
3bffb652 DK |
582 | static void set_debug_reg_defaults(struct thread_struct *thread) |
583 | { | |
9422de3e MN |
584 | thread->hw_brk.address = 0; |
585 | thread->hw_brk.type = 0; | |
b9818c33 | 586 | set_breakpoint(&thread->hw_brk); |
3bffb652 | 587 | } |
e0780b72 | 588 | #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 DK |
589 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
590 | ||
172ae2e7 | 591 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e MN |
592 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
593 | { | |
d6a61bfc | 594 | mtspr(SPRN_DAC1, dabr); |
221c185d DK |
595 | #ifdef CONFIG_PPC_47x |
596 | isync(); | |
597 | #endif | |
9422de3e MN |
598 | return 0; |
599 | } | |
c6c9eace | 600 | #elif defined(CONFIG_PPC_BOOK3S) |
9422de3e MN |
601 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
602 | { | |
c6c9eace | 603 | mtspr(SPRN_DABR, dabr); |
82a9f16a MN |
604 | if (cpu_has_feature(CPU_FTR_DABRX)) |
605 | mtspr(SPRN_DABRX, dabrx); | |
cab0af98 | 606 | return 0; |
14cf11af | 607 | } |
9422de3e MN |
608 | #else |
609 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | |
610 | { | |
611 | return -EINVAL; | |
612 | } | |
613 | #endif | |
614 | ||
615 | static inline int set_dabr(struct arch_hw_breakpoint *brk) | |
616 | { | |
617 | unsigned long dabr, dabrx; | |
618 | ||
619 | dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); | |
620 | dabrx = ((brk->type >> 3) & 0x7); | |
621 | ||
622 | if (ppc_md.set_dabr) | |
623 | return ppc_md.set_dabr(dabr, dabrx); | |
624 | ||
625 | return __set_dabr(dabr, dabrx); | |
626 | } | |
627 | ||
bf99de36 MN |
628 | static inline int set_dawr(struct arch_hw_breakpoint *brk) |
629 | { | |
05d694ea | 630 | unsigned long dawr, dawrx, mrd; |
bf99de36 MN |
631 | |
632 | dawr = brk->address; | |
633 | ||
634 | dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ | |
635 | << (63 - 58); //* read/write bits */ | |
636 | dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ | |
637 | << (63 - 59); //* translate */ | |
638 | dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ | |
639 | >> 3; //* PRIM bits */ | |
05d694ea MN |
640 | /* dawr length is stored in field MDR bits 48:53. Matches range in |
641 | doublewords (64 bits) baised by -1 eg. 0b000000=1DW and | |
642 | 0b111111=64DW. | |
643 | brk->len is in bytes. | |
644 | This aligns up to double word size, shifts and does the bias. | |
645 | */ | |
646 | mrd = ((brk->len + 7) >> 3) - 1; | |
647 | dawrx |= (mrd & 0x3f) << (63 - 53); | |
bf99de36 MN |
648 | |
649 | if (ppc_md.set_dawr) | |
650 | return ppc_md.set_dawr(dawr, dawrx); | |
651 | mtspr(SPRN_DAWR, dawr); | |
652 | mtspr(SPRN_DAWRX, dawrx); | |
653 | return 0; | |
654 | } | |
655 | ||
21f58507 | 656 | void __set_breakpoint(struct arch_hw_breakpoint *brk) |
9422de3e | 657 | { |
69111bac | 658 | memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); |
9422de3e | 659 | |
bf99de36 | 660 | if (cpu_has_feature(CPU_FTR_DAWR)) |
04c32a51 PG |
661 | set_dawr(brk); |
662 | else | |
663 | set_dabr(brk); | |
9422de3e | 664 | } |
14cf11af | 665 | |
21f58507 PG |
666 | void set_breakpoint(struct arch_hw_breakpoint *brk) |
667 | { | |
668 | preempt_disable(); | |
669 | __set_breakpoint(brk); | |
670 | preempt_enable(); | |
671 | } | |
672 | ||
06d67d54 PM |
673 | #ifdef CONFIG_PPC64 |
674 | DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); | |
06d67d54 | 675 | #endif |
14cf11af | 676 | |
9422de3e MN |
677 | static inline bool hw_brk_match(struct arch_hw_breakpoint *a, |
678 | struct arch_hw_breakpoint *b) | |
679 | { | |
680 | if (a->address != b->address) | |
681 | return false; | |
682 | if (a->type != b->type) | |
683 | return false; | |
684 | if (a->len != b->len) | |
685 | return false; | |
686 | return true; | |
687 | } | |
d31626f7 | 688 | |
fb09692e | 689 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
d31626f7 PM |
690 | static void tm_reclaim_thread(struct thread_struct *thr, |
691 | struct thread_info *ti, uint8_t cause) | |
692 | { | |
693 | unsigned long msr_diff = 0; | |
694 | ||
695 | /* | |
696 | * If FP/VSX registers have been already saved to the | |
697 | * thread_struct, move them to the transact_fp array. | |
698 | * We clear the TIF_RESTORE_TM bit since after the reclaim | |
699 | * the thread will no longer be transactional. | |
700 | */ | |
701 | if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { | |
829023df | 702 | msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr; |
d31626f7 PM |
703 | if (msr_diff & MSR_FP) |
704 | memcpy(&thr->transact_fp, &thr->fp_state, | |
705 | sizeof(struct thread_fp_state)); | |
706 | if (msr_diff & MSR_VEC) | |
707 | memcpy(&thr->transact_vr, &thr->vr_state, | |
708 | sizeof(struct thread_vr_state)); | |
709 | clear_ti_thread_flag(ti, TIF_RESTORE_TM); | |
710 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; | |
711 | } | |
712 | ||
7f821fc9 MN |
713 | /* |
714 | * Use the current MSR TM suspended bit to track if we have | |
715 | * checkpointed state outstanding. | |
716 | * On signal delivery, we'd normally reclaim the checkpointed | |
717 | * state to obtain stack pointer (see:get_tm_stackpointer()). | |
718 | * This will then directly return to userspace without going | |
719 | * through __switch_to(). However, if the stack frame is bad, | |
720 | * we need to exit this thread which calls __switch_to() which | |
721 | * will again attempt to reclaim the already saved tm state. | |
722 | * Hence we need to check that we've not already reclaimed | |
723 | * this state. | |
724 | * We do this using the current MSR, rather tracking it in | |
725 | * some specific thread_struct bit, as it has the additional | |
726 | * benifit of checking for a potential TM bad thing exception. | |
727 | */ | |
728 | if (!MSR_TM_SUSPENDED(mfmsr())) | |
729 | return; | |
730 | ||
d31626f7 PM |
731 | tm_reclaim(thr, thr->regs->msr, cause); |
732 | ||
733 | /* Having done the reclaim, we now have the checkpointed | |
734 | * FP/VSX values in the registers. These might be valid | |
735 | * even if we have previously called enable_kernel_fp() or | |
736 | * flush_fp_to_thread(), so update thr->regs->msr to | |
737 | * indicate their current validity. | |
738 | */ | |
739 | thr->regs->msr |= msr_diff; | |
740 | } | |
741 | ||
742 | void tm_reclaim_current(uint8_t cause) | |
743 | { | |
744 | tm_enable(); | |
745 | tm_reclaim_thread(¤t->thread, current_thread_info(), cause); | |
746 | } | |
747 | ||
fb09692e MN |
748 | static inline void tm_reclaim_task(struct task_struct *tsk) |
749 | { | |
750 | /* We have to work out if we're switching from/to a task that's in the | |
751 | * middle of a transaction. | |
752 | * | |
753 | * In switching we need to maintain a 2nd register state as | |
754 | * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the | |
755 | * checkpointed (tbegin) state in ckpt_regs and saves the transactional | |
756 | * (current) FPRs into oldtask->thread.transact_fpr[]. | |
757 | * | |
758 | * We also context switch (save) TFHAR/TEXASR/TFIAR in here. | |
759 | */ | |
760 | struct thread_struct *thr = &tsk->thread; | |
761 | ||
762 | if (!thr->regs) | |
763 | return; | |
764 | ||
765 | if (!MSR_TM_ACTIVE(thr->regs->msr)) | |
766 | goto out_and_saveregs; | |
767 | ||
768 | /* Stash the original thread MSR, as giveup_fpu et al will | |
769 | * modify it. We hold onto it to see whether the task used | |
d31626f7 | 770 | * FP & vector regs. If the TIF_RESTORE_TM flag is set, |
829023df | 771 | * ckpt_regs.msr is already set. |
fb09692e | 772 | */ |
d31626f7 | 773 | if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) |
829023df | 774 | thr->ckpt_regs.msr = thr->regs->msr; |
fb09692e MN |
775 | |
776 | TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " | |
777 | "ccr=%lx, msr=%lx, trap=%lx)\n", | |
778 | tsk->pid, thr->regs->nip, | |
779 | thr->regs->ccr, thr->regs->msr, | |
780 | thr->regs->trap); | |
781 | ||
d31626f7 | 782 | tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); |
fb09692e MN |
783 | |
784 | TM_DEBUG("--- tm_reclaim on pid %d complete\n", | |
785 | tsk->pid); | |
786 | ||
787 | out_and_saveregs: | |
788 | /* Always save the regs here, even if a transaction's not active. | |
789 | * This context-switches a thread's TM info SPRs. We do it here to | |
790 | * be consistent with the restore path (in recheckpoint) which | |
791 | * cannot happen later in _switch(). | |
792 | */ | |
793 | tm_save_sprs(thr); | |
794 | } | |
795 | ||
e6b8fd02 MN |
796 | extern void __tm_recheckpoint(struct thread_struct *thread, |
797 | unsigned long orig_msr); | |
798 | ||
799 | void tm_recheckpoint(struct thread_struct *thread, | |
800 | unsigned long orig_msr) | |
801 | { | |
802 | unsigned long flags; | |
803 | ||
804 | /* We really can't be interrupted here as the TEXASR registers can't | |
805 | * change and later in the trecheckpoint code, we have a userspace R1. | |
806 | * So let's hard disable over this region. | |
807 | */ | |
808 | local_irq_save(flags); | |
809 | hard_irq_disable(); | |
810 | ||
811 | /* The TM SPRs are restored here, so that TEXASR.FS can be set | |
812 | * before the trecheckpoint and no explosion occurs. | |
813 | */ | |
814 | tm_restore_sprs(thread); | |
815 | ||
816 | __tm_recheckpoint(thread, orig_msr); | |
817 | ||
818 | local_irq_restore(flags); | |
819 | } | |
820 | ||
bc2a9408 | 821 | static inline void tm_recheckpoint_new_task(struct task_struct *new) |
fb09692e MN |
822 | { |
823 | unsigned long msr; | |
824 | ||
825 | if (!cpu_has_feature(CPU_FTR_TM)) | |
826 | return; | |
827 | ||
828 | /* Recheckpoint the registers of the thread we're about to switch to. | |
829 | * | |
830 | * If the task was using FP, we non-lazily reload both the original and | |
831 | * the speculative FP register states. This is because the kernel | |
832 | * doesn't see if/when a TM rollback occurs, so if we take an FP | |
833 | * unavoidable later, we are unable to determine which set of FP regs | |
834 | * need to be restored. | |
835 | */ | |
836 | if (!new->thread.regs) | |
837 | return; | |
838 | ||
e6b8fd02 MN |
839 | if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ |
840 | tm_restore_sprs(&new->thread); | |
fb09692e | 841 | return; |
e6b8fd02 | 842 | } |
829023df | 843 | msr = new->thread.ckpt_regs.msr; |
fb09692e MN |
844 | /* Recheckpoint to restore original checkpointed register state. */ |
845 | TM_DEBUG("*** tm_recheckpoint of pid %d " | |
846 | "(new->msr 0x%lx, new->origmsr 0x%lx)\n", | |
847 | new->pid, new->thread.regs->msr, msr); | |
848 | ||
849 | /* This loads the checkpointed FP/VEC state, if used */ | |
850 | tm_recheckpoint(&new->thread, msr); | |
851 | ||
852 | /* This loads the speculative FP/VEC state, if used */ | |
853 | if (msr & MSR_FP) { | |
854 | do_load_up_transact_fpu(&new->thread); | |
855 | new->thread.regs->msr |= | |
856 | (MSR_FP | new->thread.fpexc_mode); | |
857 | } | |
f110c0c1 | 858 | #ifdef CONFIG_ALTIVEC |
fb09692e MN |
859 | if (msr & MSR_VEC) { |
860 | do_load_up_transact_altivec(&new->thread); | |
861 | new->thread.regs->msr |= MSR_VEC; | |
862 | } | |
f110c0c1 | 863 | #endif |
fb09692e MN |
864 | /* We may as well turn on VSX too since all the state is restored now */ |
865 | if (msr & MSR_VSX) | |
866 | new->thread.regs->msr |= MSR_VSX; | |
867 | ||
868 | TM_DEBUG("*** tm_recheckpoint of pid %d complete " | |
869 | "(kernel msr 0x%lx)\n", | |
870 | new->pid, mfmsr()); | |
871 | } | |
872 | ||
873 | static inline void __switch_to_tm(struct task_struct *prev) | |
874 | { | |
875 | if (cpu_has_feature(CPU_FTR_TM)) { | |
876 | tm_enable(); | |
877 | tm_reclaim_task(prev); | |
878 | } | |
879 | } | |
d31626f7 PM |
880 | |
881 | /* | |
882 | * This is called if we are on the way out to userspace and the | |
883 | * TIF_RESTORE_TM flag is set. It checks if we need to reload | |
884 | * FP and/or vector state and does so if necessary. | |
885 | * If userspace is inside a transaction (whether active or | |
886 | * suspended) and FP/VMX/VSX instructions have ever been enabled | |
887 | * inside that transaction, then we have to keep them enabled | |
888 | * and keep the FP/VMX/VSX state loaded while ever the transaction | |
889 | * continues. The reason is that if we didn't, and subsequently | |
890 | * got a FP/VMX/VSX unavailable interrupt inside a transaction, | |
891 | * we don't know whether it's the same transaction, and thus we | |
892 | * don't know which of the checkpointed state and the transactional | |
893 | * state to use. | |
894 | */ | |
895 | void restore_tm_state(struct pt_regs *regs) | |
896 | { | |
897 | unsigned long msr_diff; | |
898 | ||
899 | clear_thread_flag(TIF_RESTORE_TM); | |
900 | if (!MSR_TM_ACTIVE(regs->msr)) | |
901 | return; | |
902 | ||
829023df | 903 | msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; |
d31626f7 | 904 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; |
70fe3d98 CB |
905 | |
906 | restore_math(regs); | |
907 | ||
d31626f7 PM |
908 | regs->msr |= msr_diff; |
909 | } | |
910 | ||
fb09692e MN |
911 | #else |
912 | #define tm_recheckpoint_new_task(new) | |
913 | #define __switch_to_tm(prev) | |
914 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
9422de3e | 915 | |
152d523e AB |
916 | static inline void save_sprs(struct thread_struct *t) |
917 | { | |
918 | #ifdef CONFIG_ALTIVEC | |
919 | if (cpu_has_feature(cpu_has_feature(CPU_FTR_ALTIVEC))) | |
920 | t->vrsave = mfspr(SPRN_VRSAVE); | |
921 | #endif | |
922 | #ifdef CONFIG_PPC_BOOK3S_64 | |
923 | if (cpu_has_feature(CPU_FTR_DSCR)) | |
924 | t->dscr = mfspr(SPRN_DSCR); | |
925 | ||
926 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
927 | t->bescr = mfspr(SPRN_BESCR); | |
928 | t->ebbhr = mfspr(SPRN_EBBHR); | |
929 | t->ebbrr = mfspr(SPRN_EBBRR); | |
930 | ||
931 | t->fscr = mfspr(SPRN_FSCR); | |
932 | ||
933 | /* | |
934 | * Note that the TAR is not available for use in the kernel. | |
935 | * (To provide this, the TAR should be backed up/restored on | |
936 | * exception entry/exit instead, and be in pt_regs. FIXME, | |
937 | * this should be in pt_regs anyway (for debug).) | |
938 | */ | |
939 | t->tar = mfspr(SPRN_TAR); | |
940 | } | |
941 | #endif | |
942 | } | |
943 | ||
944 | static inline void restore_sprs(struct thread_struct *old_thread, | |
945 | struct thread_struct *new_thread) | |
946 | { | |
947 | #ifdef CONFIG_ALTIVEC | |
948 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && | |
949 | old_thread->vrsave != new_thread->vrsave) | |
950 | mtspr(SPRN_VRSAVE, new_thread->vrsave); | |
951 | #endif | |
952 | #ifdef CONFIG_PPC_BOOK3S_64 | |
953 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
954 | u64 dscr = get_paca()->dscr_default; | |
955 | u64 fscr = old_thread->fscr & ~FSCR_DSCR; | |
956 | ||
957 | if (new_thread->dscr_inherit) { | |
958 | dscr = new_thread->dscr; | |
959 | fscr |= FSCR_DSCR; | |
960 | } | |
961 | ||
962 | if (old_thread->dscr != dscr) | |
963 | mtspr(SPRN_DSCR, dscr); | |
964 | ||
965 | if (old_thread->fscr != fscr) | |
966 | mtspr(SPRN_FSCR, fscr); | |
967 | } | |
968 | ||
969 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
970 | if (old_thread->bescr != new_thread->bescr) | |
971 | mtspr(SPRN_BESCR, new_thread->bescr); | |
972 | if (old_thread->ebbhr != new_thread->ebbhr) | |
973 | mtspr(SPRN_EBBHR, new_thread->ebbhr); | |
974 | if (old_thread->ebbrr != new_thread->ebbrr) | |
975 | mtspr(SPRN_EBBRR, new_thread->ebbrr); | |
976 | ||
977 | if (old_thread->tar != new_thread->tar) | |
978 | mtspr(SPRN_TAR, new_thread->tar); | |
979 | } | |
980 | #endif | |
981 | } | |
982 | ||
14cf11af PM |
983 | struct task_struct *__switch_to(struct task_struct *prev, |
984 | struct task_struct *new) | |
985 | { | |
986 | struct thread_struct *new_thread, *old_thread; | |
14cf11af | 987 | struct task_struct *last; |
d6bf29b4 PZ |
988 | #ifdef CONFIG_PPC_BOOK3S_64 |
989 | struct ppc64_tlb_batch *batch; | |
990 | #endif | |
14cf11af | 991 | |
152d523e AB |
992 | new_thread = &new->thread; |
993 | old_thread = ¤t->thread; | |
994 | ||
7ba5fef7 MN |
995 | WARN_ON(!irqs_disabled()); |
996 | ||
06d67d54 PM |
997 | #ifdef CONFIG_PPC64 |
998 | /* | |
999 | * Collect processor utilization data per process | |
1000 | */ | |
1001 | if (firmware_has_feature(FW_FEATURE_SPLPAR)) { | |
69111bac | 1002 | struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); |
06d67d54 PM |
1003 | long unsigned start_tb, current_tb; |
1004 | start_tb = old_thread->start_tb; | |
1005 | cu->current_tb = current_tb = mfspr(SPRN_PURR); | |
1006 | old_thread->accum_tb += (current_tb - start_tb); | |
1007 | new_thread->start_tb = current_tb; | |
1008 | } | |
d6bf29b4 PZ |
1009 | #endif /* CONFIG_PPC64 */ |
1010 | ||
1011 | #ifdef CONFIG_PPC_BOOK3S_64 | |
69111bac | 1012 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1013 | if (batch->active) { |
1014 | current_thread_info()->local_flags |= _TLF_LAZY_MMU; | |
1015 | if (batch->index) | |
1016 | __flush_tlb_pending(batch); | |
1017 | batch->active = 0; | |
1018 | } | |
1019 | #endif /* CONFIG_PPC_BOOK3S_64 */ | |
06d67d54 | 1020 | |
f3d885cc AB |
1021 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1022 | switch_booke_debug_regs(&new->thread.debug); | |
1023 | #else | |
1024 | /* | |
1025 | * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would | |
1026 | * schedule DABR | |
1027 | */ | |
1028 | #ifndef CONFIG_HAVE_HW_BREAKPOINT | |
1029 | if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) | |
1030 | __set_breakpoint(&new->thread.hw_brk); | |
1031 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1032 | #endif | |
1033 | ||
1034 | /* | |
1035 | * We need to save SPRs before treclaim/trecheckpoint as these will | |
1036 | * change a number of them. | |
1037 | */ | |
1038 | save_sprs(&prev->thread); | |
1039 | ||
1040 | __switch_to_tm(prev); | |
1041 | ||
1042 | /* Save FPU, Altivec, VSX and SPE state */ | |
1043 | giveup_all(prev); | |
1044 | ||
44387e9f AB |
1045 | /* |
1046 | * We can't take a PMU exception inside _switch() since there is a | |
1047 | * window where the kernel stack SLB and the kernel stack are out | |
1048 | * of sync. Hard disable here. | |
1049 | */ | |
1050 | hard_irq_disable(); | |
bc2a9408 MN |
1051 | |
1052 | tm_recheckpoint_new_task(new); | |
1053 | ||
20dbe670 AB |
1054 | /* |
1055 | * Call restore_sprs() before calling _switch(). If we move it after | |
1056 | * _switch() then we miss out on calling it for new tasks. The reason | |
1057 | * for this is we manually create a stack frame for new tasks that | |
1058 | * directly returns through ret_from_fork() or | |
1059 | * ret_from_kernel_thread(). See copy_thread() for details. | |
1060 | */ | |
f3d885cc AB |
1061 | restore_sprs(old_thread, new_thread); |
1062 | ||
20dbe670 AB |
1063 | last = _switch(old_thread, new_thread); |
1064 | ||
d6bf29b4 PZ |
1065 | #ifdef CONFIG_PPC_BOOK3S_64 |
1066 | if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { | |
1067 | current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; | |
69111bac | 1068 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1069 | batch->active = 1; |
1070 | } | |
70fe3d98 CB |
1071 | |
1072 | if (current_thread_info()->task->thread.regs) | |
1073 | restore_math(current_thread_info()->task->thread.regs); | |
1074 | ||
d6bf29b4 PZ |
1075 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
1076 | ||
14cf11af PM |
1077 | return last; |
1078 | } | |
1079 | ||
06d67d54 PM |
1080 | static int instructions_to_print = 16; |
1081 | ||
06d67d54 PM |
1082 | static void show_instructions(struct pt_regs *regs) |
1083 | { | |
1084 | int i; | |
1085 | unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * | |
1086 | sizeof(int)); | |
1087 | ||
1088 | printk("Instruction dump:"); | |
1089 | ||
1090 | for (i = 0; i < instructions_to_print; i++) { | |
1091 | int instr; | |
1092 | ||
1093 | if (!(i % 8)) | |
1094 | printk("\n"); | |
1095 | ||
0de2d820 SW |
1096 | #if !defined(CONFIG_BOOKE) |
1097 | /* If executing with the IMMU off, adjust pc rather | |
1098 | * than print XXXXXXXX. | |
1099 | */ | |
1100 | if (!(regs->msr & MSR_IR)) | |
1101 | pc = (unsigned long)phys_to_virt(pc); | |
1102 | #endif | |
1103 | ||
00ae36de | 1104 | if (!__kernel_text_address(pc) || |
7b051f66 | 1105 | probe_kernel_address((unsigned int __user *)pc, instr)) { |
40c8cefa | 1106 | printk(KERN_CONT "XXXXXXXX "); |
06d67d54 PM |
1107 | } else { |
1108 | if (regs->nip == pc) | |
40c8cefa | 1109 | printk(KERN_CONT "<%08x> ", instr); |
06d67d54 | 1110 | else |
40c8cefa | 1111 | printk(KERN_CONT "%08x ", instr); |
06d67d54 PM |
1112 | } |
1113 | ||
1114 | pc += sizeof(int); | |
1115 | } | |
1116 | ||
1117 | printk("\n"); | |
1118 | } | |
1119 | ||
801c0b2c | 1120 | struct regbit { |
06d67d54 PM |
1121 | unsigned long bit; |
1122 | const char *name; | |
801c0b2c MN |
1123 | }; |
1124 | ||
1125 | static struct regbit msr_bits[] = { | |
3bfd0c9c AB |
1126 | #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) |
1127 | {MSR_SF, "SF"}, | |
1128 | {MSR_HV, "HV"}, | |
1129 | #endif | |
1130 | {MSR_VEC, "VEC"}, | |
1131 | {MSR_VSX, "VSX"}, | |
1132 | #ifdef CONFIG_BOOKE | |
1133 | {MSR_CE, "CE"}, | |
1134 | #endif | |
06d67d54 PM |
1135 | {MSR_EE, "EE"}, |
1136 | {MSR_PR, "PR"}, | |
1137 | {MSR_FP, "FP"}, | |
1138 | {MSR_ME, "ME"}, | |
3bfd0c9c | 1139 | #ifdef CONFIG_BOOKE |
1b98326b | 1140 | {MSR_DE, "DE"}, |
3bfd0c9c AB |
1141 | #else |
1142 | {MSR_SE, "SE"}, | |
1143 | {MSR_BE, "BE"}, | |
1144 | #endif | |
06d67d54 PM |
1145 | {MSR_IR, "IR"}, |
1146 | {MSR_DR, "DR"}, | |
3bfd0c9c AB |
1147 | {MSR_PMM, "PMM"}, |
1148 | #ifndef CONFIG_BOOKE | |
1149 | {MSR_RI, "RI"}, | |
1150 | {MSR_LE, "LE"}, | |
1151 | #endif | |
06d67d54 PM |
1152 | {0, NULL} |
1153 | }; | |
1154 | ||
801c0b2c | 1155 | static void print_bits(unsigned long val, struct regbit *bits, const char *sep) |
06d67d54 | 1156 | { |
801c0b2c | 1157 | const char *s = ""; |
06d67d54 | 1158 | |
06d67d54 PM |
1159 | for (; bits->bit; ++bits) |
1160 | if (val & bits->bit) { | |
801c0b2c MN |
1161 | printk("%s%s", s, bits->name); |
1162 | s = sep; | |
06d67d54 | 1163 | } |
801c0b2c MN |
1164 | } |
1165 | ||
1166 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1167 | static struct regbit msr_tm_bits[] = { | |
1168 | {MSR_TS_T, "T"}, | |
1169 | {MSR_TS_S, "S"}, | |
1170 | {MSR_TM, "E"}, | |
1171 | {0, NULL} | |
1172 | }; | |
1173 | ||
1174 | static void print_tm_bits(unsigned long val) | |
1175 | { | |
1176 | /* | |
1177 | * This only prints something if at least one of the TM bit is set. | |
1178 | * Inside the TM[], the output means: | |
1179 | * E: Enabled (bit 32) | |
1180 | * S: Suspended (bit 33) | |
1181 | * T: Transactional (bit 34) | |
1182 | */ | |
1183 | if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { | |
1184 | printk(",TM["); | |
1185 | print_bits(val, msr_tm_bits, ""); | |
1186 | printk("]"); | |
1187 | } | |
1188 | } | |
1189 | #else | |
1190 | static void print_tm_bits(unsigned long val) {} | |
1191 | #endif | |
1192 | ||
1193 | static void print_msr_bits(unsigned long val) | |
1194 | { | |
1195 | printk("<"); | |
1196 | print_bits(val, msr_bits, ","); | |
1197 | print_tm_bits(val); | |
06d67d54 PM |
1198 | printk(">"); |
1199 | } | |
1200 | ||
1201 | #ifdef CONFIG_PPC64 | |
f6f7dde3 | 1202 | #define REG "%016lx" |
06d67d54 PM |
1203 | #define REGS_PER_LINE 4 |
1204 | #define LAST_VOLATILE 13 | |
1205 | #else | |
f6f7dde3 | 1206 | #define REG "%08lx" |
06d67d54 PM |
1207 | #define REGS_PER_LINE 8 |
1208 | #define LAST_VOLATILE 12 | |
1209 | #endif | |
1210 | ||
14cf11af PM |
1211 | void show_regs(struct pt_regs * regs) |
1212 | { | |
1213 | int i, trap; | |
1214 | ||
a43cb95d TH |
1215 | show_regs_print_info(KERN_DEFAULT); |
1216 | ||
06d67d54 PM |
1217 | printk("NIP: "REG" LR: "REG" CTR: "REG"\n", |
1218 | regs->nip, regs->link, regs->ctr); | |
1219 | printk("REGS: %p TRAP: %04lx %s (%s)\n", | |
96b644bd | 1220 | regs, regs->trap, print_tainted(), init_utsname()->release); |
06d67d54 | 1221 | printk("MSR: "REG" ", regs->msr); |
801c0b2c | 1222 | print_msr_bits(regs->msr); |
f6f7dde3 | 1223 | printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); |
14cf11af | 1224 | trap = TRAP(regs); |
5115a026 | 1225 | if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) |
9db8bcfd | 1226 | printk("CFAR: "REG" ", regs->orig_gpr3); |
c5400649 | 1227 | if (trap == 0x200 || trap == 0x300 || trap == 0x600) |
ba28c9aa | 1228 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
9db8bcfd | 1229 | printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); |
14170789 | 1230 | #else |
9db8bcfd AB |
1231 | printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); |
1232 | #endif | |
1233 | #ifdef CONFIG_PPC64 | |
1234 | printk("SOFTE: %ld ", regs->softe); | |
1235 | #endif | |
1236 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
6d888d1a AB |
1237 | if (MSR_TM_ACTIVE(regs->msr)) |
1238 | printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); | |
14170789 | 1239 | #endif |
14cf11af PM |
1240 | |
1241 | for (i = 0; i < 32; i++) { | |
06d67d54 | 1242 | if ((i % REGS_PER_LINE) == 0) |
a2367194 | 1243 | printk("\nGPR%02d: ", i); |
06d67d54 PM |
1244 | printk(REG " ", regs->gpr[i]); |
1245 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) | |
14cf11af PM |
1246 | break; |
1247 | } | |
1248 | printk("\n"); | |
1249 | #ifdef CONFIG_KALLSYMS | |
1250 | /* | |
1251 | * Lookup NIP late so we have the best change of getting the | |
1252 | * above info out without failing | |
1253 | */ | |
058c78f4 BH |
1254 | printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); |
1255 | printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); | |
afc07701 | 1256 | #endif |
14cf11af | 1257 | show_stack(current, (unsigned long *) regs->gpr[1]); |
06d67d54 PM |
1258 | if (!user_mode(regs)) |
1259 | show_instructions(regs); | |
14cf11af PM |
1260 | } |
1261 | ||
1262 | void exit_thread(void) | |
1263 | { | |
14cf11af PM |
1264 | } |
1265 | ||
1266 | void flush_thread(void) | |
1267 | { | |
e0780b72 | 1268 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
5aae8a53 | 1269 | flush_ptrace_hw_breakpoint(current); |
e0780b72 | 1270 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1271 | set_debug_reg_defaults(¤t->thread); |
e0780b72 | 1272 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
14cf11af PM |
1273 | } |
1274 | ||
1275 | void | |
1276 | release_thread(struct task_struct *t) | |
1277 | { | |
1278 | } | |
1279 | ||
1280 | /* | |
55ccf3fe SS |
1281 | * this gets called so that we can store coprocessor state into memory and |
1282 | * copy the current task into the new thread. | |
14cf11af | 1283 | */ |
55ccf3fe | 1284 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
14cf11af | 1285 | { |
579e633e | 1286 | flush_all_to_thread(src); |
621b5060 MN |
1287 | /* |
1288 | * Flush TM state out so we can copy it. __switch_to_tm() does this | |
1289 | * flush but it removes the checkpointed state from the current CPU and | |
1290 | * transitions the CPU out of TM mode. Hence we need to call | |
1291 | * tm_recheckpoint_new_task() (on the same task) to restore the | |
1292 | * checkpointed state back and the TM mode. | |
1293 | */ | |
1294 | __switch_to_tm(src); | |
1295 | tm_recheckpoint_new_task(src); | |
330a1eb7 | 1296 | |
55ccf3fe | 1297 | *dst = *src; |
330a1eb7 ME |
1298 | |
1299 | clear_task_ebb(dst); | |
1300 | ||
55ccf3fe | 1301 | return 0; |
14cf11af PM |
1302 | } |
1303 | ||
cec15488 ME |
1304 | static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) |
1305 | { | |
1306 | #ifdef CONFIG_PPC_STD_MMU_64 | |
1307 | unsigned long sp_vsid; | |
1308 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
1309 | ||
1310 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
1311 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) | |
1312 | << SLB_VSID_SHIFT_1T; | |
1313 | else | |
1314 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) | |
1315 | << SLB_VSID_SHIFT; | |
1316 | sp_vsid |= SLB_VSID_KERNEL | llp; | |
1317 | p->thread.ksp_vsid = sp_vsid; | |
1318 | #endif | |
1319 | } | |
1320 | ||
14cf11af PM |
1321 | /* |
1322 | * Copy a thread.. | |
1323 | */ | |
efcac658 | 1324 | |
6eca8933 AD |
1325 | /* |
1326 | * Copy architecture-specific thread state | |
1327 | */ | |
6f2c55b8 | 1328 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
6eca8933 | 1329 | unsigned long kthread_arg, struct task_struct *p) |
14cf11af PM |
1330 | { |
1331 | struct pt_regs *childregs, *kregs; | |
1332 | extern void ret_from_fork(void); | |
58254e10 AV |
1333 | extern void ret_from_kernel_thread(void); |
1334 | void (*f)(void); | |
0cec6fd1 | 1335 | unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
14cf11af | 1336 | |
14cf11af PM |
1337 | /* Copy registers */ |
1338 | sp -= sizeof(struct pt_regs); | |
1339 | childregs = (struct pt_regs *) sp; | |
ab75819d | 1340 | if (unlikely(p->flags & PF_KTHREAD)) { |
6eca8933 | 1341 | /* kernel thread */ |
138d1ce8 | 1342 | struct thread_info *ti = (void *)task_stack_page(p); |
58254e10 | 1343 | memset(childregs, 0, sizeof(struct pt_regs)); |
14cf11af | 1344 | childregs->gpr[1] = sp + sizeof(struct pt_regs); |
7cedd601 AB |
1345 | /* function */ |
1346 | if (usp) | |
1347 | childregs->gpr[14] = ppc_function_entry((void *)usp); | |
58254e10 | 1348 | #ifdef CONFIG_PPC64 |
b5e2fc1c | 1349 | clear_tsk_thread_flag(p, TIF_32BIT); |
138d1ce8 | 1350 | childregs->softe = 1; |
06d67d54 | 1351 | #endif |
6eca8933 | 1352 | childregs->gpr[15] = kthread_arg; |
14cf11af | 1353 | p->thread.regs = NULL; /* no user register state */ |
138d1ce8 | 1354 | ti->flags |= _TIF_RESTOREALL; |
58254e10 | 1355 | f = ret_from_kernel_thread; |
14cf11af | 1356 | } else { |
6eca8933 | 1357 | /* user thread */ |
afa86fc4 | 1358 | struct pt_regs *regs = current_pt_regs(); |
58254e10 AV |
1359 | CHECK_FULL_REGS(regs); |
1360 | *childregs = *regs; | |
ea516b11 AV |
1361 | if (usp) |
1362 | childregs->gpr[1] = usp; | |
14cf11af | 1363 | p->thread.regs = childregs; |
58254e10 | 1364 | childregs->gpr[3] = 0; /* Result from fork() */ |
06d67d54 PM |
1365 | if (clone_flags & CLONE_SETTLS) { |
1366 | #ifdef CONFIG_PPC64 | |
9904b005 | 1367 | if (!is_32bit_task()) |
06d67d54 PM |
1368 | childregs->gpr[13] = childregs->gpr[6]; |
1369 | else | |
1370 | #endif | |
1371 | childregs->gpr[2] = childregs->gpr[6]; | |
1372 | } | |
58254e10 AV |
1373 | |
1374 | f = ret_from_fork; | |
14cf11af | 1375 | } |
d272f667 | 1376 | childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); |
14cf11af | 1377 | sp -= STACK_FRAME_OVERHEAD; |
14cf11af PM |
1378 | |
1379 | /* | |
1380 | * The way this works is that at some point in the future | |
1381 | * some task will call _switch to switch to the new task. | |
1382 | * That will pop off the stack frame created below and start | |
1383 | * the new task running at ret_from_fork. The new task will | |
1384 | * do some house keeping and then return from the fork or clone | |
1385 | * system call, using the stack frame created above. | |
1386 | */ | |
af945cf4 | 1387 | ((unsigned long *)sp)[0] = 0; |
14cf11af PM |
1388 | sp -= sizeof(struct pt_regs); |
1389 | kregs = (struct pt_regs *) sp; | |
1390 | sp -= STACK_FRAME_OVERHEAD; | |
1391 | p->thread.ksp = sp; | |
cbc9565e | 1392 | #ifdef CONFIG_PPC32 |
85218827 KG |
1393 | p->thread.ksp_limit = (unsigned long)task_stack_page(p) + |
1394 | _ALIGN_UP(sizeof(struct thread_info), 16); | |
cbc9565e | 1395 | #endif |
28d170ab ON |
1396 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1397 | p->thread.ptrace_bps[0] = NULL; | |
1398 | #endif | |
1399 | ||
18461960 PM |
1400 | p->thread.fp_save_area = NULL; |
1401 | #ifdef CONFIG_ALTIVEC | |
1402 | p->thread.vr_save_area = NULL; | |
1403 | #endif | |
1404 | ||
cec15488 ME |
1405 | setup_ksp_vsid(p, sp); |
1406 | ||
efcac658 AK |
1407 | #ifdef CONFIG_PPC64 |
1408 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1021cb26 | 1409 | p->thread.dscr_inherit = current->thread.dscr_inherit; |
db1231dc | 1410 | p->thread.dscr = mfspr(SPRN_DSCR); |
efcac658 | 1411 | } |
92779245 HM |
1412 | if (cpu_has_feature(CPU_FTR_HAS_PPR)) |
1413 | p->thread.ppr = INIT_PPR; | |
efcac658 | 1414 | #endif |
7cedd601 | 1415 | kregs->nip = ppc_function_entry(f); |
14cf11af PM |
1416 | return 0; |
1417 | } | |
1418 | ||
1419 | /* | |
1420 | * Set up a thread for executing a new program | |
1421 | */ | |
06d67d54 | 1422 | void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) |
14cf11af | 1423 | { |
90eac727 ME |
1424 | #ifdef CONFIG_PPC64 |
1425 | unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ | |
1426 | #endif | |
1427 | ||
06d67d54 PM |
1428 | /* |
1429 | * If we exec out of a kernel thread then thread.regs will not be | |
1430 | * set. Do it now. | |
1431 | */ | |
1432 | if (!current->thread.regs) { | |
0cec6fd1 AV |
1433 | struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; |
1434 | current->thread.regs = regs - 1; | |
06d67d54 PM |
1435 | } |
1436 | ||
14cf11af PM |
1437 | memset(regs->gpr, 0, sizeof(regs->gpr)); |
1438 | regs->ctr = 0; | |
1439 | regs->link = 0; | |
1440 | regs->xer = 0; | |
1441 | regs->ccr = 0; | |
14cf11af | 1442 | regs->gpr[1] = sp; |
06d67d54 | 1443 | |
474f8196 RM |
1444 | /* |
1445 | * We have just cleared all the nonvolatile GPRs, so make | |
1446 | * FULL_REGS(regs) return true. This is necessary to allow | |
1447 | * ptrace to examine the thread immediately after exec. | |
1448 | */ | |
1449 | regs->trap &= ~1UL; | |
1450 | ||
06d67d54 PM |
1451 | #ifdef CONFIG_PPC32 |
1452 | regs->mq = 0; | |
1453 | regs->nip = start; | |
14cf11af | 1454 | regs->msr = MSR_USER; |
06d67d54 | 1455 | #else |
9904b005 | 1456 | if (!is_32bit_task()) { |
94af3abf | 1457 | unsigned long entry; |
06d67d54 | 1458 | |
94af3abf RR |
1459 | if (is_elf2_task()) { |
1460 | /* Look ma, no function descriptors! */ | |
1461 | entry = start; | |
06d67d54 | 1462 | |
94af3abf RR |
1463 | /* |
1464 | * Ulrich says: | |
1465 | * The latest iteration of the ABI requires that when | |
1466 | * calling a function (at its global entry point), | |
1467 | * the caller must ensure r12 holds the entry point | |
1468 | * address (so that the function can quickly | |
1469 | * establish addressability). | |
1470 | */ | |
1471 | regs->gpr[12] = start; | |
1472 | /* Make sure that's restored on entry to userspace. */ | |
1473 | set_thread_flag(TIF_RESTOREALL); | |
1474 | } else { | |
1475 | unsigned long toc; | |
1476 | ||
1477 | /* start is a relocated pointer to the function | |
1478 | * descriptor for the elf _start routine. The first | |
1479 | * entry in the function descriptor is the entry | |
1480 | * address of _start and the second entry is the TOC | |
1481 | * value we need to use. | |
1482 | */ | |
1483 | __get_user(entry, (unsigned long __user *)start); | |
1484 | __get_user(toc, (unsigned long __user *)start+1); | |
1485 | ||
1486 | /* Check whether the e_entry function descriptor entries | |
1487 | * need to be relocated before we can use them. | |
1488 | */ | |
1489 | if (load_addr != 0) { | |
1490 | entry += load_addr; | |
1491 | toc += load_addr; | |
1492 | } | |
1493 | regs->gpr[2] = toc; | |
06d67d54 PM |
1494 | } |
1495 | regs->nip = entry; | |
06d67d54 | 1496 | regs->msr = MSR_USER64; |
d4bf9a78 SR |
1497 | } else { |
1498 | regs->nip = start; | |
1499 | regs->gpr[2] = 0; | |
1500 | regs->msr = MSR_USER32; | |
06d67d54 PM |
1501 | } |
1502 | #endif | |
ce48b210 MN |
1503 | #ifdef CONFIG_VSX |
1504 | current->thread.used_vsr = 0; | |
1505 | #endif | |
de79f7b9 | 1506 | memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); |
18461960 | 1507 | current->thread.fp_save_area = NULL; |
14cf11af | 1508 | #ifdef CONFIG_ALTIVEC |
de79f7b9 PM |
1509 | memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); |
1510 | current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ | |
18461960 | 1511 | current->thread.vr_save_area = NULL; |
14cf11af PM |
1512 | current->thread.vrsave = 0; |
1513 | current->thread.used_vr = 0; | |
1514 | #endif /* CONFIG_ALTIVEC */ | |
1515 | #ifdef CONFIG_SPE | |
1516 | memset(current->thread.evr, 0, sizeof(current->thread.evr)); | |
1517 | current->thread.acc = 0; | |
1518 | current->thread.spefscr = 0; | |
1519 | current->thread.used_spe = 0; | |
1520 | #endif /* CONFIG_SPE */ | |
bc2a9408 MN |
1521 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1522 | if (cpu_has_feature(CPU_FTR_TM)) | |
1523 | regs->msr |= MSR_TM; | |
1524 | current->thread.tm_tfhar = 0; | |
1525 | current->thread.tm_texasr = 0; | |
1526 | current->thread.tm_tfiar = 0; | |
1527 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
14cf11af | 1528 | } |
e1802b06 | 1529 | EXPORT_SYMBOL(start_thread); |
14cf11af PM |
1530 | |
1531 | #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ | |
1532 | | PR_FP_EXC_RES | PR_FP_EXC_INV) | |
1533 | ||
1534 | int set_fpexc_mode(struct task_struct *tsk, unsigned int val) | |
1535 | { | |
1536 | struct pt_regs *regs = tsk->thread.regs; | |
1537 | ||
1538 | /* This is a bit hairy. If we are an SPE enabled processor | |
1539 | * (have embedded fp) we store the IEEE exception enable flags in | |
1540 | * fpexc_mode. fpexc_mode is also used for setting FP exception | |
1541 | * mode (asyn, precise, disabled) for 'Classic' FP. */ | |
1542 | if (val & PR_FP_EXC_SW_ENABLE) { | |
1543 | #ifdef CONFIG_SPE | |
5e14d21e | 1544 | if (cpu_has_feature(CPU_FTR_SPE)) { |
640e9225 JM |
1545 | /* |
1546 | * When the sticky exception bits are set | |
1547 | * directly by userspace, it must call prctl | |
1548 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1549 | * in the existing prctl settings) or | |
1550 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1551 | * the bits being set). <fenv.h> functions | |
1552 | * saving and restoring the whole | |
1553 | * floating-point environment need to do so | |
1554 | * anyway to restore the prctl settings from | |
1555 | * the saved environment. | |
1556 | */ | |
1557 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e KG |
1558 | tsk->thread.fpexc_mode = val & |
1559 | (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); | |
1560 | return 0; | |
1561 | } else { | |
1562 | return -EINVAL; | |
1563 | } | |
14cf11af PM |
1564 | #else |
1565 | return -EINVAL; | |
1566 | #endif | |
14cf11af | 1567 | } |
06d67d54 PM |
1568 | |
1569 | /* on a CONFIG_SPE this does not hurt us. The bits that | |
1570 | * __pack_fe01 use do not overlap with bits used for | |
1571 | * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits | |
1572 | * on CONFIG_SPE implementations are reserved so writing to | |
1573 | * them does not change anything */ | |
1574 | if (val > PR_FP_EXC_PRECISE) | |
1575 | return -EINVAL; | |
1576 | tsk->thread.fpexc_mode = __pack_fe01(val); | |
1577 | if (regs != NULL && (regs->msr & MSR_FP) != 0) | |
1578 | regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) | |
1579 | | tsk->thread.fpexc_mode; | |
14cf11af PM |
1580 | return 0; |
1581 | } | |
1582 | ||
1583 | int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) | |
1584 | { | |
1585 | unsigned int val; | |
1586 | ||
1587 | if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) | |
1588 | #ifdef CONFIG_SPE | |
640e9225 JM |
1589 | if (cpu_has_feature(CPU_FTR_SPE)) { |
1590 | /* | |
1591 | * When the sticky exception bits are set | |
1592 | * directly by userspace, it must call prctl | |
1593 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1594 | * in the existing prctl settings) or | |
1595 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1596 | * the bits being set). <fenv.h> functions | |
1597 | * saving and restoring the whole | |
1598 | * floating-point environment need to do so | |
1599 | * anyway to restore the prctl settings from | |
1600 | * the saved environment. | |
1601 | */ | |
1602 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e | 1603 | val = tsk->thread.fpexc_mode; |
640e9225 | 1604 | } else |
5e14d21e | 1605 | return -EINVAL; |
14cf11af PM |
1606 | #else |
1607 | return -EINVAL; | |
1608 | #endif | |
1609 | else | |
1610 | val = __unpack_fe01(tsk->thread.fpexc_mode); | |
1611 | return put_user(val, (unsigned int __user *) adr); | |
1612 | } | |
1613 | ||
fab5db97 PM |
1614 | int set_endian(struct task_struct *tsk, unsigned int val) |
1615 | { | |
1616 | struct pt_regs *regs = tsk->thread.regs; | |
1617 | ||
1618 | if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || | |
1619 | (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) | |
1620 | return -EINVAL; | |
1621 | ||
1622 | if (regs == NULL) | |
1623 | return -EINVAL; | |
1624 | ||
1625 | if (val == PR_ENDIAN_BIG) | |
1626 | regs->msr &= ~MSR_LE; | |
1627 | else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) | |
1628 | regs->msr |= MSR_LE; | |
1629 | else | |
1630 | return -EINVAL; | |
1631 | ||
1632 | return 0; | |
1633 | } | |
1634 | ||
1635 | int get_endian(struct task_struct *tsk, unsigned long adr) | |
1636 | { | |
1637 | struct pt_regs *regs = tsk->thread.regs; | |
1638 | unsigned int val; | |
1639 | ||
1640 | if (!cpu_has_feature(CPU_FTR_PPC_LE) && | |
1641 | !cpu_has_feature(CPU_FTR_REAL_LE)) | |
1642 | return -EINVAL; | |
1643 | ||
1644 | if (regs == NULL) | |
1645 | return -EINVAL; | |
1646 | ||
1647 | if (regs->msr & MSR_LE) { | |
1648 | if (cpu_has_feature(CPU_FTR_REAL_LE)) | |
1649 | val = PR_ENDIAN_LITTLE; | |
1650 | else | |
1651 | val = PR_ENDIAN_PPC_LITTLE; | |
1652 | } else | |
1653 | val = PR_ENDIAN_BIG; | |
1654 | ||
1655 | return put_user(val, (unsigned int __user *)adr); | |
1656 | } | |
1657 | ||
e9370ae1 PM |
1658 | int set_unalign_ctl(struct task_struct *tsk, unsigned int val) |
1659 | { | |
1660 | tsk->thread.align_ctl = val; | |
1661 | return 0; | |
1662 | } | |
1663 | ||
1664 | int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) | |
1665 | { | |
1666 | return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); | |
1667 | } | |
1668 | ||
bb72c481 PM |
1669 | static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, |
1670 | unsigned long nbytes) | |
1671 | { | |
1672 | unsigned long stack_page; | |
1673 | unsigned long cpu = task_cpu(p); | |
1674 | ||
1675 | /* | |
1676 | * Avoid crashing if the stack has overflowed and corrupted | |
1677 | * task_cpu(p), which is in the thread_info struct. | |
1678 | */ | |
1679 | if (cpu < NR_CPUS && cpu_possible(cpu)) { | |
1680 | stack_page = (unsigned long) hardirq_ctx[cpu]; | |
1681 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1682 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1683 | return 1; | |
1684 | ||
1685 | stack_page = (unsigned long) softirq_ctx[cpu]; | |
1686 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1687 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1688 | return 1; | |
1689 | } | |
1690 | return 0; | |
1691 | } | |
1692 | ||
2f25194d | 1693 | int validate_sp(unsigned long sp, struct task_struct *p, |
14cf11af PM |
1694 | unsigned long nbytes) |
1695 | { | |
0cec6fd1 | 1696 | unsigned long stack_page = (unsigned long)task_stack_page(p); |
14cf11af PM |
1697 | |
1698 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1699 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1700 | return 1; | |
1701 | ||
bb72c481 | 1702 | return valid_irq_stack(sp, p, nbytes); |
14cf11af PM |
1703 | } |
1704 | ||
2f25194d AB |
1705 | EXPORT_SYMBOL(validate_sp); |
1706 | ||
14cf11af PM |
1707 | unsigned long get_wchan(struct task_struct *p) |
1708 | { | |
1709 | unsigned long ip, sp; | |
1710 | int count = 0; | |
1711 | ||
1712 | if (!p || p == current || p->state == TASK_RUNNING) | |
1713 | return 0; | |
1714 | ||
1715 | sp = p->thread.ksp; | |
ec2b36b9 | 1716 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1717 | return 0; |
1718 | ||
1719 | do { | |
1720 | sp = *(unsigned long *)sp; | |
ec2b36b9 | 1721 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1722 | return 0; |
1723 | if (count > 0) { | |
ec2b36b9 | 1724 | ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; |
14cf11af PM |
1725 | if (!in_sched_functions(ip)) |
1726 | return ip; | |
1727 | } | |
1728 | } while (count++ < 16); | |
1729 | return 0; | |
1730 | } | |
06d67d54 | 1731 | |
c4d04be1 | 1732 | static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; |
06d67d54 PM |
1733 | |
1734 | void show_stack(struct task_struct *tsk, unsigned long *stack) | |
1735 | { | |
1736 | unsigned long sp, ip, lr, newsp; | |
1737 | int count = 0; | |
1738 | int firstframe = 1; | |
6794c782 SR |
1739 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1740 | int curr_frame = current->curr_ret_stack; | |
1741 | extern void return_to_handler(void); | |
9135c3cc | 1742 | unsigned long rth = (unsigned long)return_to_handler; |
6794c782 | 1743 | #endif |
06d67d54 PM |
1744 | |
1745 | sp = (unsigned long) stack; | |
1746 | if (tsk == NULL) | |
1747 | tsk = current; | |
1748 | if (sp == 0) { | |
1749 | if (tsk == current) | |
acf620ec | 1750 | sp = current_stack_pointer(); |
06d67d54 PM |
1751 | else |
1752 | sp = tsk->thread.ksp; | |
1753 | } | |
1754 | ||
1755 | lr = 0; | |
1756 | printk("Call Trace:\n"); | |
1757 | do { | |
ec2b36b9 | 1758 | if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) |
06d67d54 PM |
1759 | return; |
1760 | ||
1761 | stack = (unsigned long *) sp; | |
1762 | newsp = stack[0]; | |
ec2b36b9 | 1763 | ip = stack[STACK_FRAME_LR_SAVE]; |
06d67d54 | 1764 | if (!firstframe || ip != lr) { |
058c78f4 | 1765 | printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); |
6794c782 | 1766 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
7d56c65a | 1767 | if ((ip == rth) && curr_frame >= 0) { |
6794c782 SR |
1768 | printk(" (%pS)", |
1769 | (void *)current->ret_stack[curr_frame].ret); | |
1770 | curr_frame--; | |
1771 | } | |
1772 | #endif | |
06d67d54 PM |
1773 | if (firstframe) |
1774 | printk(" (unreliable)"); | |
1775 | printk("\n"); | |
1776 | } | |
1777 | firstframe = 0; | |
1778 | ||
1779 | /* | |
1780 | * See if this is an exception frame. | |
1781 | * We look for the "regshere" marker in the current frame. | |
1782 | */ | |
ec2b36b9 BH |
1783 | if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) |
1784 | && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { | |
06d67d54 PM |
1785 | struct pt_regs *regs = (struct pt_regs *) |
1786 | (sp + STACK_FRAME_OVERHEAD); | |
06d67d54 | 1787 | lr = regs->link; |
9be9be2e | 1788 | printk("--- interrupt: %lx at %pS\n LR = %pS\n", |
058c78f4 | 1789 | regs->trap, (void *)regs->nip, (void *)lr); |
06d67d54 PM |
1790 | firstframe = 1; |
1791 | } | |
1792 | ||
1793 | sp = newsp; | |
1794 | } while (count++ < kstack_depth_to_print); | |
1795 | } | |
1796 | ||
cb2c9b27 | 1797 | #ifdef CONFIG_PPC64 |
fe1952fc | 1798 | /* Called with hard IRQs off */ |
0e37739b | 1799 | void notrace __ppc64_runlatch_on(void) |
cb2c9b27 | 1800 | { |
fe1952fc | 1801 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1802 | unsigned long ctrl; |
1803 | ||
fe1952fc BH |
1804 | ctrl = mfspr(SPRN_CTRLF); |
1805 | ctrl |= CTRL_RUNLATCH; | |
1806 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1807 | |
fae2e0fb | 1808 | ti->local_flags |= _TLF_RUNLATCH; |
cb2c9b27 AB |
1809 | } |
1810 | ||
fe1952fc | 1811 | /* Called with hard IRQs off */ |
0e37739b | 1812 | void notrace __ppc64_runlatch_off(void) |
cb2c9b27 | 1813 | { |
fe1952fc | 1814 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1815 | unsigned long ctrl; |
1816 | ||
fae2e0fb | 1817 | ti->local_flags &= ~_TLF_RUNLATCH; |
cb2c9b27 | 1818 | |
4138d653 AB |
1819 | ctrl = mfspr(SPRN_CTRLF); |
1820 | ctrl &= ~CTRL_RUNLATCH; | |
1821 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1822 | } |
fe1952fc | 1823 | #endif /* CONFIG_PPC64 */ |
f6a61680 | 1824 | |
d839088c AB |
1825 | unsigned long arch_align_stack(unsigned long sp) |
1826 | { | |
1827 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
1828 | sp -= get_random_int() & ~PAGE_MASK; | |
1829 | return sp & ~0xf; | |
1830 | } | |
912f9ee2 AB |
1831 | |
1832 | static inline unsigned long brk_rnd(void) | |
1833 | { | |
1834 | unsigned long rnd = 0; | |
1835 | ||
1836 | /* 8MB for 32bit, 1GB for 64bit */ | |
1837 | if (is_32bit_task()) | |
1838 | rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); | |
1839 | else | |
1840 | rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); | |
1841 | ||
1842 | return rnd << PAGE_SHIFT; | |
1843 | } | |
1844 | ||
1845 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
1846 | { | |
8bbde7a7 AB |
1847 | unsigned long base = mm->brk; |
1848 | unsigned long ret; | |
1849 | ||
ce7a35c7 | 1850 | #ifdef CONFIG_PPC_STD_MMU_64 |
8bbde7a7 AB |
1851 | /* |
1852 | * If we are using 1TB segments and we are allowed to randomise | |
1853 | * the heap, we can put it above 1TB so it is backed by a 1TB | |
1854 | * segment. Otherwise the heap will be in the bottom 1TB | |
1855 | * which always uses 256MB segments and this may result in a | |
1856 | * performance penalty. | |
1857 | */ | |
1858 | if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) | |
1859 | base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); | |
1860 | #endif | |
1861 | ||
1862 | ret = PAGE_ALIGN(base + brk_rnd()); | |
912f9ee2 AB |
1863 | |
1864 | if (ret < mm->brk) | |
1865 | return mm->brk; | |
1866 | ||
1867 | return ret; | |
1868 | } | |
501cb16d | 1869 |