]>
Commit | Line | Data |
---|---|---|
14cf11af | 1 | /* |
14cf11af PM |
2 | * Derived from "arch/i386/kernel/process.c" |
3 | * Copyright (C) 1995 Linus Torvalds | |
4 | * | |
5 | * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and | |
6 | * Paul Mackerras (paulus@cs.anu.edu.au) | |
7 | * | |
8 | * PowerPC version | |
9 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
b17b0153 | 19 | #include <linux/sched/debug.h> |
29930025 | 20 | #include <linux/sched/task.h> |
68db0cf1 | 21 | #include <linux/sched/task_stack.h> |
14cf11af PM |
22 | #include <linux/kernel.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/smp.h> | |
14cf11af PM |
25 | #include <linux/stddef.h> |
26 | #include <linux/unistd.h> | |
27 | #include <linux/ptrace.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/user.h> | |
30 | #include <linux/elf.h> | |
14cf11af PM |
31 | #include <linux/prctl.h> |
32 | #include <linux/init_task.h> | |
4b16f8e2 | 33 | #include <linux/export.h> |
14cf11af PM |
34 | #include <linux/kallsyms.h> |
35 | #include <linux/mqueue.h> | |
36 | #include <linux/hardirq.h> | |
06d67d54 | 37 | #include <linux/utsname.h> |
6794c782 | 38 | #include <linux/ftrace.h> |
79741dd3 | 39 | #include <linux/kernel_stat.h> |
d839088c AB |
40 | #include <linux/personality.h> |
41 | #include <linux/random.h> | |
5aae8a53 | 42 | #include <linux/hw_breakpoint.h> |
7b051f66 | 43 | #include <linux/uaccess.h> |
7f92bc56 | 44 | #include <linux/elf-randomize.h> |
06bb53b3 | 45 | #include <linux/pkeys.h> |
14cf11af PM |
46 | |
47 | #include <asm/pgtable.h> | |
14cf11af PM |
48 | #include <asm/io.h> |
49 | #include <asm/processor.h> | |
50 | #include <asm/mmu.h> | |
51 | #include <asm/prom.h> | |
76032de8 | 52 | #include <asm/machdep.h> |
c6622f63 | 53 | #include <asm/time.h> |
ae3a197e | 54 | #include <asm/runlatch.h> |
a7f31841 | 55 | #include <asm/syscalls.h> |
ae3a197e | 56 | #include <asm/switch_to.h> |
fb09692e | 57 | #include <asm/tm.h> |
ae3a197e | 58 | #include <asm/debug.h> |
06d67d54 PM |
59 | #ifdef CONFIG_PPC64 |
60 | #include <asm/firmware.h> | |
c2e480ba | 61 | #include <asm/hw_irq.h> |
06d67d54 | 62 | #endif |
7cedd601 | 63 | #include <asm/code-patching.h> |
7f92bc56 | 64 | #include <asm/exec.h> |
5d31a96e | 65 | #include <asm/livepatch.h> |
b92a226e | 66 | #include <asm/cpu_has_feature.h> |
0545d543 | 67 | #include <asm/asm-prototypes.h> |
5d31a96e | 68 | |
d6a61bfc LM |
69 | #include <linux/kprobes.h> |
70 | #include <linux/kdebug.h> | |
14cf11af | 71 | |
8b3c34cf MN |
72 | /* Transactional Memory debug */ |
73 | #ifdef TM_DEBUG_SW | |
74 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
75 | #else | |
76 | #define TM_DEBUG(x...) do { } while(0) | |
77 | #endif | |
78 | ||
14cf11af PM |
79 | extern unsigned long _get_SP(void); |
80 | ||
d31626f7 | 81 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
54820530 ME |
82 | /* |
83 | * Are we running in "Suspend disabled" mode? If so we have to block any | |
84 | * sigreturn that would get us into suspended state, and we also warn in some | |
85 | * other paths that we should never reach with suspend disabled. | |
86 | */ | |
87 | bool tm_suspend_disabled __ro_after_init = false; | |
88 | ||
b86fd2bd | 89 | static void check_if_tm_restore_required(struct task_struct *tsk) |
d31626f7 PM |
90 | { |
91 | /* | |
92 | * If we are saving the current thread's registers, and the | |
93 | * thread is in a transactional state, set the TIF_RESTORE_TM | |
94 | * bit so that we know to restore the registers before | |
95 | * returning to userspace. | |
96 | */ | |
97 | if (tsk == current && tsk->thread.regs && | |
98 | MSR_TM_ACTIVE(tsk->thread.regs->msr) && | |
99 | !test_thread_flag(TIF_RESTORE_TM)) { | |
829023df | 100 | tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; |
d31626f7 PM |
101 | set_thread_flag(TIF_RESTORE_TM); |
102 | } | |
d31626f7 | 103 | } |
dc16b553 | 104 | |
a7771176 CB |
105 | static bool tm_active_with_fp(struct task_struct *tsk) |
106 | { | |
5c784c84 | 107 | return MSR_TM_ACTIVE(tsk->thread.regs->msr) && |
a7771176 CB |
108 | (tsk->thread.ckpt_regs.msr & MSR_FP); |
109 | } | |
110 | ||
111 | static bool tm_active_with_altivec(struct task_struct *tsk) | |
112 | { | |
5c784c84 | 113 | return MSR_TM_ACTIVE(tsk->thread.regs->msr) && |
a7771176 CB |
114 | (tsk->thread.ckpt_regs.msr & MSR_VEC); |
115 | } | |
d31626f7 | 116 | #else |
b86fd2bd | 117 | static inline void check_if_tm_restore_required(struct task_struct *tsk) { } |
a7771176 CB |
118 | static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; } |
119 | static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; } | |
d31626f7 PM |
120 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
121 | ||
3eb5d588 AB |
122 | bool strict_msr_control; |
123 | EXPORT_SYMBOL(strict_msr_control); | |
124 | ||
125 | static int __init enable_strict_msr_control(char *str) | |
126 | { | |
127 | strict_msr_control = true; | |
128 | pr_info("Enabling strict facility control\n"); | |
129 | ||
130 | return 0; | |
131 | } | |
132 | early_param("ppc_strict_facility_enable", enable_strict_msr_control); | |
133 | ||
3cee070a | 134 | unsigned long msr_check_and_set(unsigned long bits) |
98da581e | 135 | { |
a0e72cf1 AB |
136 | unsigned long oldmsr = mfmsr(); |
137 | unsigned long newmsr; | |
98da581e | 138 | |
a0e72cf1 | 139 | newmsr = oldmsr | bits; |
98da581e | 140 | |
98da581e | 141 | #ifdef CONFIG_VSX |
a0e72cf1 | 142 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
98da581e AB |
143 | newmsr |= MSR_VSX; |
144 | #endif | |
a0e72cf1 | 145 | |
98da581e AB |
146 | if (oldmsr != newmsr) |
147 | mtmsr_isync(newmsr); | |
3cee070a CB |
148 | |
149 | return newmsr; | |
a0e72cf1 | 150 | } |
d1c72112 | 151 | EXPORT_SYMBOL_GPL(msr_check_and_set); |
98da581e | 152 | |
3eb5d588 | 153 | void __msr_check_and_clear(unsigned long bits) |
a0e72cf1 AB |
154 | { |
155 | unsigned long oldmsr = mfmsr(); | |
156 | unsigned long newmsr; | |
157 | ||
158 | newmsr = oldmsr & ~bits; | |
159 | ||
160 | #ifdef CONFIG_VSX | |
161 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) | |
162 | newmsr &= ~MSR_VSX; | |
163 | #endif | |
164 | ||
165 | if (oldmsr != newmsr) | |
166 | mtmsr_isync(newmsr); | |
167 | } | |
3eb5d588 | 168 | EXPORT_SYMBOL(__msr_check_and_clear); |
a0e72cf1 AB |
169 | |
170 | #ifdef CONFIG_PPC_FPU | |
1cdf039b | 171 | static void __giveup_fpu(struct task_struct *tsk) |
8792468d | 172 | { |
8eb98037 AB |
173 | unsigned long msr; |
174 | ||
8792468d | 175 | save_fpu(tsk); |
8eb98037 AB |
176 | msr = tsk->thread.regs->msr; |
177 | msr &= ~MSR_FP; | |
8792468d CB |
178 | #ifdef CONFIG_VSX |
179 | if (cpu_has_feature(CPU_FTR_VSX)) | |
8eb98037 | 180 | msr &= ~MSR_VSX; |
8792468d | 181 | #endif |
8eb98037 | 182 | tsk->thread.regs->msr = msr; |
8792468d CB |
183 | } |
184 | ||
a0e72cf1 AB |
185 | void giveup_fpu(struct task_struct *tsk) |
186 | { | |
187 | check_if_tm_restore_required(tsk); | |
188 | ||
189 | msr_check_and_set(MSR_FP); | |
98da581e | 190 | __giveup_fpu(tsk); |
a0e72cf1 | 191 | msr_check_and_clear(MSR_FP); |
98da581e AB |
192 | } |
193 | EXPORT_SYMBOL(giveup_fpu); | |
194 | ||
14cf11af PM |
195 | /* |
196 | * Make sure the floating-point register state in the | |
197 | * the thread_struct is up to date for task tsk. | |
198 | */ | |
199 | void flush_fp_to_thread(struct task_struct *tsk) | |
200 | { | |
201 | if (tsk->thread.regs) { | |
202 | /* | |
203 | * We need to disable preemption here because if we didn't, | |
204 | * another process could get scheduled after the regs->msr | |
205 | * test but before we have finished saving the FP registers | |
206 | * to the thread_struct. That process could take over the | |
207 | * FPU, and then when we get scheduled again we would store | |
208 | * bogus values for the remaining FP registers. | |
209 | */ | |
210 | preempt_disable(); | |
211 | if (tsk->thread.regs->msr & MSR_FP) { | |
14cf11af PM |
212 | /* |
213 | * This should only ever be called for current or | |
214 | * for a stopped child process. Since we save away | |
af1bbc3d | 215 | * the FP register state on context switch, |
14cf11af PM |
216 | * there is something wrong if a stopped child appears |
217 | * to still have its FP state in the CPU registers. | |
218 | */ | |
219 | BUG_ON(tsk != current); | |
b86fd2bd | 220 | giveup_fpu(tsk); |
14cf11af PM |
221 | } |
222 | preempt_enable(); | |
223 | } | |
224 | } | |
de56a948 | 225 | EXPORT_SYMBOL_GPL(flush_fp_to_thread); |
14cf11af PM |
226 | |
227 | void enable_kernel_fp(void) | |
228 | { | |
e909fb83 CB |
229 | unsigned long cpumsr; |
230 | ||
14cf11af PM |
231 | WARN_ON(preemptible()); |
232 | ||
e909fb83 | 233 | cpumsr = msr_check_and_set(MSR_FP); |
611b0e5c | 234 | |
d64d02ce AB |
235 | if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { |
236 | check_if_tm_restore_required(current); | |
e909fb83 CB |
237 | /* |
238 | * If a thread has already been reclaimed then the | |
239 | * checkpointed registers are on the CPU but have definitely | |
240 | * been saved by the reclaim code. Don't need to and *cannot* | |
241 | * giveup as this would save to the 'live' structure not the | |
242 | * checkpointed structure. | |
243 | */ | |
5c784c84 BL |
244 | if (!MSR_TM_ACTIVE(cpumsr) && |
245 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 246 | return; |
a0e72cf1 | 247 | __giveup_fpu(current); |
d64d02ce | 248 | } |
14cf11af PM |
249 | } |
250 | EXPORT_SYMBOL(enable_kernel_fp); | |
70fe3d98 | 251 | |
6a303833 BH |
252 | static int restore_fp(struct task_struct *tsk) |
253 | { | |
a7771176 | 254 | if (tsk->thread.load_fp || tm_active_with_fp(tsk)) { |
70fe3d98 CB |
255 | load_fp_state(¤t->thread.fp_state); |
256 | current->thread.load_fp++; | |
257 | return 1; | |
258 | } | |
259 | return 0; | |
260 | } | |
261 | #else | |
262 | static int restore_fp(struct task_struct *tsk) { return 0; } | |
d1e1cf2e | 263 | #endif /* CONFIG_PPC_FPU */ |
14cf11af | 264 | |
14cf11af | 265 | #ifdef CONFIG_ALTIVEC |
70fe3d98 CB |
266 | #define loadvec(thr) ((thr).load_vec) |
267 | ||
6f515d84 CB |
268 | static void __giveup_altivec(struct task_struct *tsk) |
269 | { | |
8eb98037 AB |
270 | unsigned long msr; |
271 | ||
6f515d84 | 272 | save_altivec(tsk); |
8eb98037 AB |
273 | msr = tsk->thread.regs->msr; |
274 | msr &= ~MSR_VEC; | |
6f515d84 CB |
275 | #ifdef CONFIG_VSX |
276 | if (cpu_has_feature(CPU_FTR_VSX)) | |
8eb98037 | 277 | msr &= ~MSR_VSX; |
6f515d84 | 278 | #endif |
8eb98037 | 279 | tsk->thread.regs->msr = msr; |
6f515d84 CB |
280 | } |
281 | ||
98da581e AB |
282 | void giveup_altivec(struct task_struct *tsk) |
283 | { | |
98da581e AB |
284 | check_if_tm_restore_required(tsk); |
285 | ||
a0e72cf1 | 286 | msr_check_and_set(MSR_VEC); |
98da581e | 287 | __giveup_altivec(tsk); |
a0e72cf1 | 288 | msr_check_and_clear(MSR_VEC); |
98da581e AB |
289 | } |
290 | EXPORT_SYMBOL(giveup_altivec); | |
291 | ||
14cf11af PM |
292 | void enable_kernel_altivec(void) |
293 | { | |
e909fb83 CB |
294 | unsigned long cpumsr; |
295 | ||
14cf11af PM |
296 | WARN_ON(preemptible()); |
297 | ||
e909fb83 | 298 | cpumsr = msr_check_and_set(MSR_VEC); |
611b0e5c | 299 | |
d64d02ce AB |
300 | if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { |
301 | check_if_tm_restore_required(current); | |
e909fb83 CB |
302 | /* |
303 | * If a thread has already been reclaimed then the | |
304 | * checkpointed registers are on the CPU but have definitely | |
305 | * been saved by the reclaim code. Don't need to and *cannot* | |
306 | * giveup as this would save to the 'live' structure not the | |
307 | * checkpointed structure. | |
308 | */ | |
5c784c84 BL |
309 | if (!MSR_TM_ACTIVE(cpumsr) && |
310 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 311 | return; |
a0e72cf1 | 312 | __giveup_altivec(current); |
d64d02ce | 313 | } |
14cf11af PM |
314 | } |
315 | EXPORT_SYMBOL(enable_kernel_altivec); | |
316 | ||
317 | /* | |
318 | * Make sure the VMX/Altivec register state in the | |
319 | * the thread_struct is up to date for task tsk. | |
320 | */ | |
321 | void flush_altivec_to_thread(struct task_struct *tsk) | |
322 | { | |
323 | if (tsk->thread.regs) { | |
324 | preempt_disable(); | |
325 | if (tsk->thread.regs->msr & MSR_VEC) { | |
14cf11af | 326 | BUG_ON(tsk != current); |
b86fd2bd | 327 | giveup_altivec(tsk); |
14cf11af PM |
328 | } |
329 | preempt_enable(); | |
330 | } | |
331 | } | |
de56a948 | 332 | EXPORT_SYMBOL_GPL(flush_altivec_to_thread); |
70fe3d98 CB |
333 | |
334 | static int restore_altivec(struct task_struct *tsk) | |
335 | { | |
dc16b553 | 336 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && |
a7771176 | 337 | (tsk->thread.load_vec || tm_active_with_altivec(tsk))) { |
70fe3d98 CB |
338 | load_vr_state(&tsk->thread.vr_state); |
339 | tsk->thread.used_vr = 1; | |
340 | tsk->thread.load_vec++; | |
341 | ||
342 | return 1; | |
343 | } | |
344 | return 0; | |
345 | } | |
346 | #else | |
347 | #define loadvec(thr) 0 | |
348 | static inline int restore_altivec(struct task_struct *tsk) { return 0; } | |
14cf11af PM |
349 | #endif /* CONFIG_ALTIVEC */ |
350 | ||
ce48b210 | 351 | #ifdef CONFIG_VSX |
bf6a4d5b | 352 | static void __giveup_vsx(struct task_struct *tsk) |
a7d623d4 | 353 | { |
dc801081 BH |
354 | unsigned long msr = tsk->thread.regs->msr; |
355 | ||
356 | /* | |
357 | * We should never be ssetting MSR_VSX without also setting | |
358 | * MSR_FP and MSR_VEC | |
359 | */ | |
360 | WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC))); | |
361 | ||
362 | /* __giveup_fpu will clear MSR_VSX */ | |
363 | if (msr & MSR_FP) | |
a7d623d4 | 364 | __giveup_fpu(tsk); |
dc801081 | 365 | if (msr & MSR_VEC) |
a7d623d4 | 366 | __giveup_altivec(tsk); |
bf6a4d5b CB |
367 | } |
368 | ||
369 | static void giveup_vsx(struct task_struct *tsk) | |
370 | { | |
371 | check_if_tm_restore_required(tsk); | |
372 | ||
373 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); | |
a7d623d4 | 374 | __giveup_vsx(tsk); |
a0e72cf1 | 375 | msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); |
a7d623d4 | 376 | } |
bf6a4d5b | 377 | |
ce48b210 MN |
378 | void enable_kernel_vsx(void) |
379 | { | |
e909fb83 CB |
380 | unsigned long cpumsr; |
381 | ||
ce48b210 MN |
382 | WARN_ON(preemptible()); |
383 | ||
e909fb83 | 384 | cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); |
611b0e5c | 385 | |
5a69aec9 BH |
386 | if (current->thread.regs && |
387 | (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) { | |
d64d02ce | 388 | check_if_tm_restore_required(current); |
e909fb83 CB |
389 | /* |
390 | * If a thread has already been reclaimed then the | |
391 | * checkpointed registers are on the CPU but have definitely | |
392 | * been saved by the reclaim code. Don't need to and *cannot* | |
393 | * giveup as this would save to the 'live' structure not the | |
394 | * checkpointed structure. | |
395 | */ | |
5c784c84 BL |
396 | if (!MSR_TM_ACTIVE(cpumsr) && |
397 | MSR_TM_ACTIVE(current->thread.regs->msr)) | |
e909fb83 | 398 | return; |
a0e72cf1 | 399 | __giveup_vsx(current); |
611b0e5c | 400 | } |
ce48b210 MN |
401 | } |
402 | EXPORT_SYMBOL(enable_kernel_vsx); | |
ce48b210 MN |
403 | |
404 | void flush_vsx_to_thread(struct task_struct *tsk) | |
405 | { | |
406 | if (tsk->thread.regs) { | |
407 | preempt_disable(); | |
5a69aec9 | 408 | if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) { |
ce48b210 | 409 | BUG_ON(tsk != current); |
ce48b210 MN |
410 | giveup_vsx(tsk); |
411 | } | |
412 | preempt_enable(); | |
413 | } | |
414 | } | |
de56a948 | 415 | EXPORT_SYMBOL_GPL(flush_vsx_to_thread); |
70fe3d98 CB |
416 | |
417 | static int restore_vsx(struct task_struct *tsk) | |
418 | { | |
419 | if (cpu_has_feature(CPU_FTR_VSX)) { | |
420 | tsk->thread.used_vsr = 1; | |
421 | return 1; | |
422 | } | |
423 | ||
424 | return 0; | |
425 | } | |
426 | #else | |
427 | static inline int restore_vsx(struct task_struct *tsk) { return 0; } | |
ce48b210 MN |
428 | #endif /* CONFIG_VSX */ |
429 | ||
14cf11af | 430 | #ifdef CONFIG_SPE |
98da581e AB |
431 | void giveup_spe(struct task_struct *tsk) |
432 | { | |
98da581e AB |
433 | check_if_tm_restore_required(tsk); |
434 | ||
a0e72cf1 | 435 | msr_check_and_set(MSR_SPE); |
98da581e | 436 | __giveup_spe(tsk); |
a0e72cf1 | 437 | msr_check_and_clear(MSR_SPE); |
98da581e AB |
438 | } |
439 | EXPORT_SYMBOL(giveup_spe); | |
14cf11af PM |
440 | |
441 | void enable_kernel_spe(void) | |
442 | { | |
443 | WARN_ON(preemptible()); | |
444 | ||
a0e72cf1 | 445 | msr_check_and_set(MSR_SPE); |
611b0e5c | 446 | |
d64d02ce AB |
447 | if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { |
448 | check_if_tm_restore_required(current); | |
a0e72cf1 | 449 | __giveup_spe(current); |
d64d02ce | 450 | } |
14cf11af PM |
451 | } |
452 | EXPORT_SYMBOL(enable_kernel_spe); | |
453 | ||
454 | void flush_spe_to_thread(struct task_struct *tsk) | |
455 | { | |
456 | if (tsk->thread.regs) { | |
457 | preempt_disable(); | |
458 | if (tsk->thread.regs->msr & MSR_SPE) { | |
14cf11af | 459 | BUG_ON(tsk != current); |
685659ee | 460 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); |
0ee6c15e | 461 | giveup_spe(tsk); |
14cf11af PM |
462 | } |
463 | preempt_enable(); | |
464 | } | |
465 | } | |
14cf11af PM |
466 | #endif /* CONFIG_SPE */ |
467 | ||
c2085059 AB |
468 | static unsigned long msr_all_available; |
469 | ||
470 | static int __init init_msr_all_available(void) | |
471 | { | |
472 | #ifdef CONFIG_PPC_FPU | |
473 | msr_all_available |= MSR_FP; | |
474 | #endif | |
475 | #ifdef CONFIG_ALTIVEC | |
476 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | |
477 | msr_all_available |= MSR_VEC; | |
478 | #endif | |
479 | #ifdef CONFIG_VSX | |
480 | if (cpu_has_feature(CPU_FTR_VSX)) | |
481 | msr_all_available |= MSR_VSX; | |
482 | #endif | |
483 | #ifdef CONFIG_SPE | |
484 | if (cpu_has_feature(CPU_FTR_SPE)) | |
485 | msr_all_available |= MSR_SPE; | |
486 | #endif | |
487 | ||
488 | return 0; | |
489 | } | |
490 | early_initcall(init_msr_all_available); | |
491 | ||
492 | void giveup_all(struct task_struct *tsk) | |
493 | { | |
494 | unsigned long usermsr; | |
495 | ||
496 | if (!tsk->thread.regs) | |
497 | return; | |
498 | ||
499 | usermsr = tsk->thread.regs->msr; | |
500 | ||
501 | if ((usermsr & msr_all_available) == 0) | |
502 | return; | |
503 | ||
504 | msr_check_and_set(msr_all_available); | |
b0f16b46 | 505 | check_if_tm_restore_required(tsk); |
c2085059 | 506 | |
96c79b6b BH |
507 | WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); |
508 | ||
c2085059 AB |
509 | #ifdef CONFIG_PPC_FPU |
510 | if (usermsr & MSR_FP) | |
511 | __giveup_fpu(tsk); | |
512 | #endif | |
513 | #ifdef CONFIG_ALTIVEC | |
514 | if (usermsr & MSR_VEC) | |
515 | __giveup_altivec(tsk); | |
516 | #endif | |
c2085059 AB |
517 | #ifdef CONFIG_SPE |
518 | if (usermsr & MSR_SPE) | |
519 | __giveup_spe(tsk); | |
520 | #endif | |
521 | ||
522 | msr_check_and_clear(msr_all_available); | |
523 | } | |
524 | EXPORT_SYMBOL(giveup_all); | |
525 | ||
70fe3d98 CB |
526 | void restore_math(struct pt_regs *regs) |
527 | { | |
528 | unsigned long msr; | |
529 | ||
5c784c84 | 530 | if (!MSR_TM_ACTIVE(regs->msr) && |
dc16b553 | 531 | !current->thread.load_fp && !loadvec(current->thread)) |
70fe3d98 CB |
532 | return; |
533 | ||
534 | msr = regs->msr; | |
535 | msr_check_and_set(msr_all_available); | |
536 | ||
537 | /* | |
538 | * Only reload if the bit is not set in the user MSR, the bit BEING set | |
539 | * indicates that the registers are hot | |
540 | */ | |
541 | if ((!(msr & MSR_FP)) && restore_fp(current)) | |
542 | msr |= MSR_FP | current->thread.fpexc_mode; | |
543 | ||
544 | if ((!(msr & MSR_VEC)) && restore_altivec(current)) | |
545 | msr |= MSR_VEC; | |
546 | ||
547 | if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && | |
548 | restore_vsx(current)) { | |
549 | msr |= MSR_VSX; | |
550 | } | |
551 | ||
552 | msr_check_and_clear(msr_all_available); | |
553 | ||
554 | regs->msr = msr; | |
555 | } | |
556 | ||
1cdf039b | 557 | static void save_all(struct task_struct *tsk) |
de2a20aa CB |
558 | { |
559 | unsigned long usermsr; | |
560 | ||
561 | if (!tsk->thread.regs) | |
562 | return; | |
563 | ||
564 | usermsr = tsk->thread.regs->msr; | |
565 | ||
566 | if ((usermsr & msr_all_available) == 0) | |
567 | return; | |
568 | ||
569 | msr_check_and_set(msr_all_available); | |
570 | ||
96c79b6b BH |
571 | WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC))); |
572 | ||
573 | if (usermsr & MSR_FP) | |
574 | save_fpu(tsk); | |
575 | ||
576 | if (usermsr & MSR_VEC) | |
577 | save_altivec(tsk); | |
de2a20aa CB |
578 | |
579 | if (usermsr & MSR_SPE) | |
580 | __giveup_spe(tsk); | |
581 | ||
582 | msr_check_and_clear(msr_all_available); | |
c76662e8 | 583 | thread_pkey_regs_save(&tsk->thread); |
de2a20aa CB |
584 | } |
585 | ||
579e633e AB |
586 | void flush_all_to_thread(struct task_struct *tsk) |
587 | { | |
588 | if (tsk->thread.regs) { | |
589 | preempt_disable(); | |
590 | BUG_ON(tsk != current); | |
de2a20aa | 591 | save_all(tsk); |
579e633e AB |
592 | |
593 | #ifdef CONFIG_SPE | |
594 | if (tsk->thread.regs->msr & MSR_SPE) | |
595 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); | |
596 | #endif | |
597 | ||
598 | preempt_enable(); | |
599 | } | |
600 | } | |
601 | EXPORT_SYMBOL(flush_all_to_thread); | |
602 | ||
3bffb652 DK |
603 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
604 | void do_send_trap(struct pt_regs *regs, unsigned long address, | |
47355040 | 605 | unsigned long error_code, int breakpt) |
3bffb652 | 606 | { |
47355040 | 607 | current->thread.trap_nr = TRAP_HWBKPT; |
3bffb652 DK |
608 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
609 | 11, SIGSEGV) == NOTIFY_STOP) | |
610 | return; | |
611 | ||
612 | /* Deliver the signal to userspace */ | |
f71dd7dc EB |
613 | force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */ |
614 | (void __user *)address); | |
3bffb652 DK |
615 | } |
616 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
9422de3e | 617 | void do_break (struct pt_regs *regs, unsigned long address, |
d6a61bfc LM |
618 | unsigned long error_code) |
619 | { | |
620 | siginfo_t info; | |
621 | ||
41ab5266 | 622 | current->thread.trap_nr = TRAP_HWBKPT; |
d6a61bfc LM |
623 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
624 | 11, SIGSEGV) == NOTIFY_STOP) | |
625 | return; | |
626 | ||
9422de3e | 627 | if (debugger_break_match(regs)) |
d6a61bfc LM |
628 | return; |
629 | ||
9422de3e MN |
630 | /* Clear the breakpoint */ |
631 | hw_breakpoint_disable(); | |
d6a61bfc LM |
632 | |
633 | /* Deliver the signal to userspace */ | |
3eb0f519 | 634 | clear_siginfo(&info); |
d6a61bfc LM |
635 | info.si_signo = SIGTRAP; |
636 | info.si_errno = 0; | |
637 | info.si_code = TRAP_HWBKPT; | |
638 | info.si_addr = (void __user *)address; | |
639 | force_sig_info(SIGTRAP, &info, current); | |
640 | } | |
3bffb652 | 641 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc | 642 | |
9422de3e | 643 | static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); |
a2ceff5e | 644 | |
3bffb652 DK |
645 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
646 | /* | |
647 | * Set the debug registers back to their default "safe" values. | |
648 | */ | |
649 | static void set_debug_reg_defaults(struct thread_struct *thread) | |
650 | { | |
51ae8d4a | 651 | thread->debug.iac1 = thread->debug.iac2 = 0; |
3bffb652 | 652 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
51ae8d4a | 653 | thread->debug.iac3 = thread->debug.iac4 = 0; |
3bffb652 | 654 | #endif |
51ae8d4a | 655 | thread->debug.dac1 = thread->debug.dac2 = 0; |
3bffb652 | 656 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
51ae8d4a | 657 | thread->debug.dvc1 = thread->debug.dvc2 = 0; |
3bffb652 | 658 | #endif |
51ae8d4a | 659 | thread->debug.dbcr0 = 0; |
3bffb652 DK |
660 | #ifdef CONFIG_BOOKE |
661 | /* | |
662 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | |
663 | */ | |
51ae8d4a | 664 | thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | |
3bffb652 DK |
665 | DBCR1_IAC3US | DBCR1_IAC4US; |
666 | /* | |
667 | * Force Data Address Compare User/Supervisor bits to be User-only | |
668 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | |
669 | */ | |
51ae8d4a | 670 | thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; |
3bffb652 | 671 | #else |
51ae8d4a | 672 | thread->debug.dbcr1 = 0; |
3bffb652 DK |
673 | #endif |
674 | } | |
675 | ||
f5f97210 | 676 | static void prime_debug_regs(struct debug_reg *debug) |
3bffb652 | 677 | { |
6cecf76b SW |
678 | /* |
679 | * We could have inherited MSR_DE from userspace, since | |
680 | * it doesn't get cleared on exception entry. Make sure | |
681 | * MSR_DE is clear before we enable any debug events. | |
682 | */ | |
683 | mtmsr(mfmsr() & ~MSR_DE); | |
684 | ||
f5f97210 SW |
685 | mtspr(SPRN_IAC1, debug->iac1); |
686 | mtspr(SPRN_IAC2, debug->iac2); | |
3bffb652 | 687 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
f5f97210 SW |
688 | mtspr(SPRN_IAC3, debug->iac3); |
689 | mtspr(SPRN_IAC4, debug->iac4); | |
3bffb652 | 690 | #endif |
f5f97210 SW |
691 | mtspr(SPRN_DAC1, debug->dac1); |
692 | mtspr(SPRN_DAC2, debug->dac2); | |
3bffb652 | 693 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
f5f97210 SW |
694 | mtspr(SPRN_DVC1, debug->dvc1); |
695 | mtspr(SPRN_DVC2, debug->dvc2); | |
3bffb652 | 696 | #endif |
f5f97210 SW |
697 | mtspr(SPRN_DBCR0, debug->dbcr0); |
698 | mtspr(SPRN_DBCR1, debug->dbcr1); | |
3bffb652 | 699 | #ifdef CONFIG_BOOKE |
f5f97210 | 700 | mtspr(SPRN_DBCR2, debug->dbcr2); |
3bffb652 DK |
701 | #endif |
702 | } | |
703 | /* | |
704 | * Unless neither the old or new thread are making use of the | |
705 | * debug registers, set the debug registers from the values | |
706 | * stored in the new thread. | |
707 | */ | |
f5f97210 | 708 | void switch_booke_debug_regs(struct debug_reg *new_debug) |
3bffb652 | 709 | { |
51ae8d4a | 710 | if ((current->thread.debug.dbcr0 & DBCR0_IDM) |
f5f97210 SW |
711 | || (new_debug->dbcr0 & DBCR0_IDM)) |
712 | prime_debug_regs(new_debug); | |
3bffb652 | 713 | } |
3743c9b8 | 714 | EXPORT_SYMBOL_GPL(switch_booke_debug_regs); |
3bffb652 | 715 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ |
e0780b72 | 716 | #ifndef CONFIG_HAVE_HW_BREAKPOINT |
b5ac51d7 CL |
717 | static void set_breakpoint(struct arch_hw_breakpoint *brk) |
718 | { | |
719 | preempt_disable(); | |
720 | __set_breakpoint(brk); | |
721 | preempt_enable(); | |
722 | } | |
723 | ||
3bffb652 DK |
724 | static void set_debug_reg_defaults(struct thread_struct *thread) |
725 | { | |
9422de3e MN |
726 | thread->hw_brk.address = 0; |
727 | thread->hw_brk.type = 0; | |
252988cb NP |
728 | if (ppc_breakpoint_available()) |
729 | set_breakpoint(&thread->hw_brk); | |
3bffb652 | 730 | } |
e0780b72 | 731 | #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 DK |
732 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
733 | ||
172ae2e7 | 734 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e MN |
735 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
736 | { | |
d6a61bfc | 737 | mtspr(SPRN_DAC1, dabr); |
221c185d DK |
738 | #ifdef CONFIG_PPC_47x |
739 | isync(); | |
740 | #endif | |
9422de3e MN |
741 | return 0; |
742 | } | |
c6c9eace | 743 | #elif defined(CONFIG_PPC_BOOK3S) |
9422de3e MN |
744 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
745 | { | |
c6c9eace | 746 | mtspr(SPRN_DABR, dabr); |
82a9f16a MN |
747 | if (cpu_has_feature(CPU_FTR_DABRX)) |
748 | mtspr(SPRN_DABRX, dabrx); | |
cab0af98 | 749 | return 0; |
14cf11af | 750 | } |
4ad8622d CL |
751 | #elif defined(CONFIG_PPC_8xx) |
752 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | |
753 | { | |
754 | unsigned long addr = dabr & ~HW_BRK_TYPE_DABR; | |
755 | unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */ | |
756 | unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */ | |
757 | ||
758 | if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ) | |
759 | lctrl1 |= 0xa0000; | |
760 | else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE) | |
761 | lctrl1 |= 0xf0000; | |
762 | else if ((dabr & HW_BRK_TYPE_RDWR) == 0) | |
763 | lctrl2 = 0; | |
764 | ||
765 | mtspr(SPRN_LCTRL2, 0); | |
766 | mtspr(SPRN_CMPE, addr); | |
767 | mtspr(SPRN_CMPF, addr + 4); | |
768 | mtspr(SPRN_LCTRL1, lctrl1); | |
769 | mtspr(SPRN_LCTRL2, lctrl2); | |
770 | ||
771 | return 0; | |
772 | } | |
9422de3e MN |
773 | #else |
774 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | |
775 | { | |
776 | return -EINVAL; | |
777 | } | |
778 | #endif | |
779 | ||
780 | static inline int set_dabr(struct arch_hw_breakpoint *brk) | |
781 | { | |
782 | unsigned long dabr, dabrx; | |
783 | ||
784 | dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); | |
785 | dabrx = ((brk->type >> 3) & 0x7); | |
786 | ||
787 | if (ppc_md.set_dabr) | |
788 | return ppc_md.set_dabr(dabr, dabrx); | |
789 | ||
790 | return __set_dabr(dabr, dabrx); | |
791 | } | |
792 | ||
bf99de36 MN |
793 | static inline int set_dawr(struct arch_hw_breakpoint *brk) |
794 | { | |
05d694ea | 795 | unsigned long dawr, dawrx, mrd; |
bf99de36 MN |
796 | |
797 | dawr = brk->address; | |
798 | ||
799 | dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ | |
800 | << (63 - 58); //* read/write bits */ | |
801 | dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ | |
802 | << (63 - 59); //* translate */ | |
803 | dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ | |
804 | >> 3; //* PRIM bits */ | |
05d694ea MN |
805 | /* dawr length is stored in field MDR bits 48:53. Matches range in |
806 | doublewords (64 bits) baised by -1 eg. 0b000000=1DW and | |
807 | 0b111111=64DW. | |
808 | brk->len is in bytes. | |
809 | This aligns up to double word size, shifts and does the bias. | |
810 | */ | |
811 | mrd = ((brk->len + 7) >> 3) - 1; | |
812 | dawrx |= (mrd & 0x3f) << (63 - 53); | |
bf99de36 MN |
813 | |
814 | if (ppc_md.set_dawr) | |
815 | return ppc_md.set_dawr(dawr, dawrx); | |
816 | mtspr(SPRN_DAWR, dawr); | |
817 | mtspr(SPRN_DAWRX, dawrx); | |
818 | return 0; | |
819 | } | |
820 | ||
21f58507 | 821 | void __set_breakpoint(struct arch_hw_breakpoint *brk) |
9422de3e | 822 | { |
69111bac | 823 | memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); |
9422de3e | 824 | |
bf99de36 | 825 | if (cpu_has_feature(CPU_FTR_DAWR)) |
252988cb | 826 | // Power8 or later |
04c32a51 | 827 | set_dawr(brk); |
252988cb NP |
828 | else if (!cpu_has_feature(CPU_FTR_ARCH_207S)) |
829 | // Power7 or earlier | |
04c32a51 | 830 | set_dabr(brk); |
252988cb NP |
831 | else |
832 | // Shouldn't happen due to higher level checks | |
833 | WARN_ON_ONCE(1); | |
9422de3e | 834 | } |
14cf11af | 835 | |
404b27d6 MN |
836 | /* Check if we have DAWR or DABR hardware */ |
837 | bool ppc_breakpoint_available(void) | |
838 | { | |
839 | if (cpu_has_feature(CPU_FTR_DAWR)) | |
840 | return true; /* POWER8 DAWR */ | |
841 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) | |
842 | return false; /* POWER9 with DAWR disabled */ | |
843 | /* DABR: Everything but POWER8 and POWER9 */ | |
844 | return true; | |
845 | } | |
846 | EXPORT_SYMBOL_GPL(ppc_breakpoint_available); | |
847 | ||
9422de3e MN |
848 | static inline bool hw_brk_match(struct arch_hw_breakpoint *a, |
849 | struct arch_hw_breakpoint *b) | |
850 | { | |
851 | if (a->address != b->address) | |
852 | return false; | |
853 | if (a->type != b->type) | |
854 | return false; | |
855 | if (a->len != b->len) | |
856 | return false; | |
857 | return true; | |
858 | } | |
d31626f7 | 859 | |
fb09692e | 860 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
5d176f75 CB |
861 | |
862 | static inline bool tm_enabled(struct task_struct *tsk) | |
863 | { | |
864 | return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); | |
865 | } | |
866 | ||
edd00b83 | 867 | static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause) |
d31626f7 | 868 | { |
7f821fc9 MN |
869 | /* |
870 | * Use the current MSR TM suspended bit to track if we have | |
871 | * checkpointed state outstanding. | |
872 | * On signal delivery, we'd normally reclaim the checkpointed | |
873 | * state to obtain stack pointer (see:get_tm_stackpointer()). | |
874 | * This will then directly return to userspace without going | |
875 | * through __switch_to(). However, if the stack frame is bad, | |
876 | * we need to exit this thread which calls __switch_to() which | |
877 | * will again attempt to reclaim the already saved tm state. | |
878 | * Hence we need to check that we've not already reclaimed | |
879 | * this state. | |
880 | * We do this using the current MSR, rather tracking it in | |
881 | * some specific thread_struct bit, as it has the additional | |
027dfac6 | 882 | * benefit of checking for a potential TM bad thing exception. |
7f821fc9 MN |
883 | */ |
884 | if (!MSR_TM_SUSPENDED(mfmsr())) | |
885 | return; | |
886 | ||
91381b9c CB |
887 | giveup_all(container_of(thr, struct task_struct, thread)); |
888 | ||
eb5c3f1c CB |
889 | tm_reclaim(thr, cause); |
890 | ||
f48e91e8 MN |
891 | /* |
892 | * If we are in a transaction and FP is off then we can't have | |
893 | * used FP inside that transaction. Hence the checkpointed | |
894 | * state is the same as the live state. We need to copy the | |
895 | * live state to the checkpointed state so that when the | |
896 | * transaction is restored, the checkpointed state is correct | |
897 | * and the aborted transaction sees the correct state. We use | |
898 | * ckpt_regs.msr here as that's what tm_reclaim will use to | |
899 | * determine if it's going to write the checkpointed state or | |
900 | * not. So either this will write the checkpointed registers, | |
901 | * or reclaim will. Similarly for VMX. | |
902 | */ | |
903 | if ((thr->ckpt_regs.msr & MSR_FP) == 0) | |
904 | memcpy(&thr->ckfp_state, &thr->fp_state, | |
905 | sizeof(struct thread_fp_state)); | |
906 | if ((thr->ckpt_regs.msr & MSR_VEC) == 0) | |
907 | memcpy(&thr->ckvr_state, &thr->vr_state, | |
908 | sizeof(struct thread_vr_state)); | |
d31626f7 PM |
909 | } |
910 | ||
911 | void tm_reclaim_current(uint8_t cause) | |
912 | { | |
913 | tm_enable(); | |
edd00b83 | 914 | tm_reclaim_thread(¤t->thread, cause); |
d31626f7 PM |
915 | } |
916 | ||
fb09692e MN |
917 | static inline void tm_reclaim_task(struct task_struct *tsk) |
918 | { | |
919 | /* We have to work out if we're switching from/to a task that's in the | |
920 | * middle of a transaction. | |
921 | * | |
922 | * In switching we need to maintain a 2nd register state as | |
923 | * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the | |
000ec280 CB |
924 | * checkpointed (tbegin) state in ckpt_regs, ckfp_state and |
925 | * ckvr_state | |
fb09692e MN |
926 | * |
927 | * We also context switch (save) TFHAR/TEXASR/TFIAR in here. | |
928 | */ | |
929 | struct thread_struct *thr = &tsk->thread; | |
930 | ||
931 | if (!thr->regs) | |
932 | return; | |
933 | ||
934 | if (!MSR_TM_ACTIVE(thr->regs->msr)) | |
935 | goto out_and_saveregs; | |
936 | ||
92fb8690 MN |
937 | WARN_ON(tm_suspend_disabled); |
938 | ||
fb09692e MN |
939 | TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " |
940 | "ccr=%lx, msr=%lx, trap=%lx)\n", | |
941 | tsk->pid, thr->regs->nip, | |
942 | thr->regs->ccr, thr->regs->msr, | |
943 | thr->regs->trap); | |
944 | ||
edd00b83 | 945 | tm_reclaim_thread(thr, TM_CAUSE_RESCHED); |
fb09692e MN |
946 | |
947 | TM_DEBUG("--- tm_reclaim on pid %d complete\n", | |
948 | tsk->pid); | |
949 | ||
950 | out_and_saveregs: | |
951 | /* Always save the regs here, even if a transaction's not active. | |
952 | * This context-switches a thread's TM info SPRs. We do it here to | |
953 | * be consistent with the restore path (in recheckpoint) which | |
954 | * cannot happen later in _switch(). | |
955 | */ | |
956 | tm_save_sprs(thr); | |
957 | } | |
958 | ||
eb5c3f1c | 959 | extern void __tm_recheckpoint(struct thread_struct *thread); |
e6b8fd02 | 960 | |
eb5c3f1c | 961 | void tm_recheckpoint(struct thread_struct *thread) |
e6b8fd02 MN |
962 | { |
963 | unsigned long flags; | |
964 | ||
5d176f75 CB |
965 | if (!(thread->regs->msr & MSR_TM)) |
966 | return; | |
967 | ||
e6b8fd02 MN |
968 | /* We really can't be interrupted here as the TEXASR registers can't |
969 | * change and later in the trecheckpoint code, we have a userspace R1. | |
970 | * So let's hard disable over this region. | |
971 | */ | |
972 | local_irq_save(flags); | |
973 | hard_irq_disable(); | |
974 | ||
975 | /* The TM SPRs are restored here, so that TEXASR.FS can be set | |
976 | * before the trecheckpoint and no explosion occurs. | |
977 | */ | |
978 | tm_restore_sprs(thread); | |
979 | ||
eb5c3f1c | 980 | __tm_recheckpoint(thread); |
e6b8fd02 MN |
981 | |
982 | local_irq_restore(flags); | |
983 | } | |
984 | ||
bc2a9408 | 985 | static inline void tm_recheckpoint_new_task(struct task_struct *new) |
fb09692e | 986 | { |
fb09692e MN |
987 | if (!cpu_has_feature(CPU_FTR_TM)) |
988 | return; | |
989 | ||
990 | /* Recheckpoint the registers of the thread we're about to switch to. | |
991 | * | |
992 | * If the task was using FP, we non-lazily reload both the original and | |
993 | * the speculative FP register states. This is because the kernel | |
994 | * doesn't see if/when a TM rollback occurs, so if we take an FP | |
dc310669 | 995 | * unavailable later, we are unable to determine which set of FP regs |
fb09692e MN |
996 | * need to be restored. |
997 | */ | |
5d176f75 | 998 | if (!tm_enabled(new)) |
fb09692e MN |
999 | return; |
1000 | ||
e6b8fd02 MN |
1001 | if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ |
1002 | tm_restore_sprs(&new->thread); | |
fb09692e | 1003 | return; |
e6b8fd02 | 1004 | } |
fb09692e | 1005 | /* Recheckpoint to restore original checkpointed register state. */ |
eb5c3f1c CB |
1006 | TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n", |
1007 | new->pid, new->thread.regs->msr); | |
fb09692e | 1008 | |
eb5c3f1c | 1009 | tm_recheckpoint(&new->thread); |
fb09692e | 1010 | |
dc310669 CB |
1011 | /* |
1012 | * The checkpointed state has been restored but the live state has | |
1013 | * not, ensure all the math functionality is turned off to trigger | |
1014 | * restore_math() to reload. | |
1015 | */ | |
1016 | new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX); | |
fb09692e MN |
1017 | |
1018 | TM_DEBUG("*** tm_recheckpoint of pid %d complete " | |
1019 | "(kernel msr 0x%lx)\n", | |
1020 | new->pid, mfmsr()); | |
1021 | } | |
1022 | ||
dc310669 CB |
1023 | static inline void __switch_to_tm(struct task_struct *prev, |
1024 | struct task_struct *new) | |
fb09692e MN |
1025 | { |
1026 | if (cpu_has_feature(CPU_FTR_TM)) { | |
5d176f75 CB |
1027 | if (tm_enabled(prev) || tm_enabled(new)) |
1028 | tm_enable(); | |
1029 | ||
1030 | if (tm_enabled(prev)) { | |
1031 | prev->thread.load_tm++; | |
1032 | tm_reclaim_task(prev); | |
1033 | if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0) | |
1034 | prev->thread.regs->msr &= ~MSR_TM; | |
1035 | } | |
1036 | ||
dc310669 | 1037 | tm_recheckpoint_new_task(new); |
fb09692e MN |
1038 | } |
1039 | } | |
d31626f7 PM |
1040 | |
1041 | /* | |
1042 | * This is called if we are on the way out to userspace and the | |
1043 | * TIF_RESTORE_TM flag is set. It checks if we need to reload | |
1044 | * FP and/or vector state and does so if necessary. | |
1045 | * If userspace is inside a transaction (whether active or | |
1046 | * suspended) and FP/VMX/VSX instructions have ever been enabled | |
1047 | * inside that transaction, then we have to keep them enabled | |
1048 | * and keep the FP/VMX/VSX state loaded while ever the transaction | |
1049 | * continues. The reason is that if we didn't, and subsequently | |
1050 | * got a FP/VMX/VSX unavailable interrupt inside a transaction, | |
1051 | * we don't know whether it's the same transaction, and thus we | |
1052 | * don't know which of the checkpointed state and the transactional | |
1053 | * state to use. | |
1054 | */ | |
1055 | void restore_tm_state(struct pt_regs *regs) | |
1056 | { | |
1057 | unsigned long msr_diff; | |
1058 | ||
dc310669 CB |
1059 | /* |
1060 | * This is the only moment we should clear TIF_RESTORE_TM as | |
1061 | * it is here that ckpt_regs.msr and pt_regs.msr become the same | |
1062 | * again, anything else could lead to an incorrect ckpt_msr being | |
1063 | * saved and therefore incorrect signal contexts. | |
1064 | */ | |
d31626f7 PM |
1065 | clear_thread_flag(TIF_RESTORE_TM); |
1066 | if (!MSR_TM_ACTIVE(regs->msr)) | |
1067 | return; | |
1068 | ||
829023df | 1069 | msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; |
d31626f7 | 1070 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; |
70fe3d98 | 1071 | |
dc16b553 CB |
1072 | /* Ensure that restore_math() will restore */ |
1073 | if (msr_diff & MSR_FP) | |
1074 | current->thread.load_fp = 1; | |
39715bf9 | 1075 | #ifdef CONFIG_ALTIVEC |
dc16b553 CB |
1076 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC) |
1077 | current->thread.load_vec = 1; | |
1078 | #endif | |
70fe3d98 CB |
1079 | restore_math(regs); |
1080 | ||
d31626f7 PM |
1081 | regs->msr |= msr_diff; |
1082 | } | |
1083 | ||
fb09692e MN |
1084 | #else |
1085 | #define tm_recheckpoint_new_task(new) | |
dc310669 | 1086 | #define __switch_to_tm(prev, new) |
fb09692e | 1087 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
9422de3e | 1088 | |
152d523e AB |
1089 | static inline void save_sprs(struct thread_struct *t) |
1090 | { | |
1091 | #ifdef CONFIG_ALTIVEC | |
01d7c2a2 | 1092 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
152d523e AB |
1093 | t->vrsave = mfspr(SPRN_VRSAVE); |
1094 | #endif | |
1095 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1096 | if (cpu_has_feature(CPU_FTR_DSCR)) | |
1097 | t->dscr = mfspr(SPRN_DSCR); | |
1098 | ||
1099 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1100 | t->bescr = mfspr(SPRN_BESCR); | |
1101 | t->ebbhr = mfspr(SPRN_EBBHR); | |
1102 | t->ebbrr = mfspr(SPRN_EBBRR); | |
1103 | ||
1104 | t->fscr = mfspr(SPRN_FSCR); | |
1105 | ||
1106 | /* | |
1107 | * Note that the TAR is not available for use in the kernel. | |
1108 | * (To provide this, the TAR should be backed up/restored on | |
1109 | * exception entry/exit instead, and be in pt_regs. FIXME, | |
1110 | * this should be in pt_regs anyway (for debug).) | |
1111 | */ | |
1112 | t->tar = mfspr(SPRN_TAR); | |
1113 | } | |
1114 | #endif | |
06bb53b3 RP |
1115 | |
1116 | thread_pkey_regs_save(t); | |
152d523e AB |
1117 | } |
1118 | ||
1119 | static inline void restore_sprs(struct thread_struct *old_thread, | |
1120 | struct thread_struct *new_thread) | |
1121 | { | |
1122 | #ifdef CONFIG_ALTIVEC | |
1123 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && | |
1124 | old_thread->vrsave != new_thread->vrsave) | |
1125 | mtspr(SPRN_VRSAVE, new_thread->vrsave); | |
1126 | #endif | |
1127 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1128 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1129 | u64 dscr = get_paca()->dscr_default; | |
b57bd2de | 1130 | if (new_thread->dscr_inherit) |
152d523e | 1131 | dscr = new_thread->dscr; |
152d523e AB |
1132 | |
1133 | if (old_thread->dscr != dscr) | |
1134 | mtspr(SPRN_DSCR, dscr); | |
152d523e AB |
1135 | } |
1136 | ||
1137 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1138 | if (old_thread->bescr != new_thread->bescr) | |
1139 | mtspr(SPRN_BESCR, new_thread->bescr); | |
1140 | if (old_thread->ebbhr != new_thread->ebbhr) | |
1141 | mtspr(SPRN_EBBHR, new_thread->ebbhr); | |
1142 | if (old_thread->ebbrr != new_thread->ebbrr) | |
1143 | mtspr(SPRN_EBBRR, new_thread->ebbrr); | |
1144 | ||
b57bd2de MN |
1145 | if (old_thread->fscr != new_thread->fscr) |
1146 | mtspr(SPRN_FSCR, new_thread->fscr); | |
1147 | ||
152d523e AB |
1148 | if (old_thread->tar != new_thread->tar) |
1149 | mtspr(SPRN_TAR, new_thread->tar); | |
1150 | } | |
ec233ede | 1151 | |
3449f191 | 1152 | if (cpu_has_feature(CPU_FTR_P9_TIDR) && |
ec233ede SB |
1153 | old_thread->tidr != new_thread->tidr) |
1154 | mtspr(SPRN_TIDR, new_thread->tidr); | |
152d523e | 1155 | #endif |
06bb53b3 RP |
1156 | |
1157 | thread_pkey_regs_restore(new_thread, old_thread); | |
152d523e AB |
1158 | } |
1159 | ||
07d2a628 NP |
1160 | #ifdef CONFIG_PPC_BOOK3S_64 |
1161 | #define CP_SIZE 128 | |
1162 | static const u8 dummy_copy_buffer[CP_SIZE] __attribute__((aligned(CP_SIZE))); | |
1163 | #endif | |
1164 | ||
14cf11af PM |
1165 | struct task_struct *__switch_to(struct task_struct *prev, |
1166 | struct task_struct *new) | |
1167 | { | |
1168 | struct thread_struct *new_thread, *old_thread; | |
14cf11af | 1169 | struct task_struct *last; |
d6bf29b4 PZ |
1170 | #ifdef CONFIG_PPC_BOOK3S_64 |
1171 | struct ppc64_tlb_batch *batch; | |
1172 | #endif | |
14cf11af | 1173 | |
152d523e AB |
1174 | new_thread = &new->thread; |
1175 | old_thread = ¤t->thread; | |
1176 | ||
7ba5fef7 MN |
1177 | WARN_ON(!irqs_disabled()); |
1178 | ||
4e003747 | 1179 | #ifdef CONFIG_PPC_BOOK3S_64 |
69111bac | 1180 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1181 | if (batch->active) { |
1182 | current_thread_info()->local_flags |= _TLF_LAZY_MMU; | |
1183 | if (batch->index) | |
1184 | __flush_tlb_pending(batch); | |
1185 | batch->active = 0; | |
1186 | } | |
4e003747 | 1187 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
06d67d54 | 1188 | |
f3d885cc AB |
1189 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1190 | switch_booke_debug_regs(&new->thread.debug); | |
1191 | #else | |
1192 | /* | |
1193 | * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would | |
1194 | * schedule DABR | |
1195 | */ | |
1196 | #ifndef CONFIG_HAVE_HW_BREAKPOINT | |
1197 | if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) | |
1198 | __set_breakpoint(&new->thread.hw_brk); | |
1199 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1200 | #endif | |
1201 | ||
1202 | /* | |
1203 | * We need to save SPRs before treclaim/trecheckpoint as these will | |
1204 | * change a number of them. | |
1205 | */ | |
1206 | save_sprs(&prev->thread); | |
1207 | ||
f3d885cc AB |
1208 | /* Save FPU, Altivec, VSX and SPE state */ |
1209 | giveup_all(prev); | |
1210 | ||
dc310669 CB |
1211 | __switch_to_tm(prev, new); |
1212 | ||
e4c0fc5f NP |
1213 | if (!radix_enabled()) { |
1214 | /* | |
1215 | * We can't take a PMU exception inside _switch() since there | |
1216 | * is a window where the kernel stack SLB and the kernel stack | |
1217 | * are out of sync. Hard disable here. | |
1218 | */ | |
1219 | hard_irq_disable(); | |
1220 | } | |
bc2a9408 | 1221 | |
20dbe670 AB |
1222 | /* |
1223 | * Call restore_sprs() before calling _switch(). If we move it after | |
1224 | * _switch() then we miss out on calling it for new tasks. The reason | |
1225 | * for this is we manually create a stack frame for new tasks that | |
1226 | * directly returns through ret_from_fork() or | |
1227 | * ret_from_kernel_thread(). See copy_thread() for details. | |
1228 | */ | |
f3d885cc AB |
1229 | restore_sprs(old_thread, new_thread); |
1230 | ||
20dbe670 AB |
1231 | last = _switch(old_thread, new_thread); |
1232 | ||
4e003747 | 1233 | #ifdef CONFIG_PPC_BOOK3S_64 |
d6bf29b4 PZ |
1234 | if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { |
1235 | current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; | |
69111bac | 1236 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1237 | batch->active = 1; |
1238 | } | |
70fe3d98 | 1239 | |
07d2a628 | 1240 | if (current_thread_info()->task->thread.regs) { |
70fe3d98 | 1241 | restore_math(current_thread_info()->task->thread.regs); |
07d2a628 NP |
1242 | |
1243 | /* | |
1244 | * The copy-paste buffer can only store into foreign real | |
1245 | * addresses, so unprivileged processes can not see the | |
1246 | * data or use it in any way unless they have foreign real | |
9d2a4d71 SB |
1247 | * mappings. If the new process has the foreign real address |
1248 | * mappings, we must issue a cp_abort to clear any state and | |
1249 | * prevent snooping, corruption or a covert channel. | |
07d2a628 | 1250 | */ |
2bf1071a | 1251 | if (current_thread_info()->task->thread.used_vas) |
9d2a4d71 | 1252 | asm volatile(PPC_CP_ABORT); |
07d2a628 | 1253 | } |
4e003747 | 1254 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
d6bf29b4 | 1255 | |
14cf11af PM |
1256 | return last; |
1257 | } | |
1258 | ||
06d67d54 PM |
1259 | static int instructions_to_print = 16; |
1260 | ||
06d67d54 PM |
1261 | static void show_instructions(struct pt_regs *regs) |
1262 | { | |
1263 | int i; | |
1264 | unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * | |
1265 | sizeof(int)); | |
1266 | ||
1267 | printk("Instruction dump:"); | |
1268 | ||
1269 | for (i = 0; i < instructions_to_print; i++) { | |
1270 | int instr; | |
1271 | ||
1272 | if (!(i % 8)) | |
2ffd04de | 1273 | pr_cont("\n"); |
06d67d54 | 1274 | |
0de2d820 SW |
1275 | #if !defined(CONFIG_BOOKE) |
1276 | /* If executing with the IMMU off, adjust pc rather | |
1277 | * than print XXXXXXXX. | |
1278 | */ | |
1279 | if (!(regs->msr & MSR_IR)) | |
1280 | pc = (unsigned long)phys_to_virt(pc); | |
1281 | #endif | |
1282 | ||
00ae36de | 1283 | if (!__kernel_text_address(pc) || |
7b051f66 | 1284 | probe_kernel_address((unsigned int __user *)pc, instr)) { |
2ffd04de | 1285 | pr_cont("XXXXXXXX "); |
06d67d54 PM |
1286 | } else { |
1287 | if (regs->nip == pc) | |
2ffd04de | 1288 | pr_cont("<%08x> ", instr); |
06d67d54 | 1289 | else |
2ffd04de | 1290 | pr_cont("%08x ", instr); |
06d67d54 PM |
1291 | } |
1292 | ||
1293 | pc += sizeof(int); | |
1294 | } | |
1295 | ||
2ffd04de | 1296 | pr_cont("\n"); |
06d67d54 PM |
1297 | } |
1298 | ||
88b0fe17 MOA |
1299 | void show_user_instructions(struct pt_regs *regs) |
1300 | { | |
1301 | unsigned long pc; | |
1302 | int i; | |
1303 | ||
1304 | pc = regs->nip - (instructions_to_print * 3 / 4 * sizeof(int)); | |
1305 | ||
a932ed3b ME |
1306 | /* |
1307 | * Make sure the NIP points at userspace, not kernel text/data or | |
1308 | * elsewhere. | |
1309 | */ | |
1310 | if (!__access_ok(pc, instructions_to_print * sizeof(int), USER_DS)) { | |
1311 | pr_info("%s[%d]: Bad NIP, not dumping instructions.\n", | |
1312 | current->comm, current->pid); | |
1313 | return; | |
1314 | } | |
1315 | ||
88b0fe17 MOA |
1316 | pr_info("%s[%d]: code: ", current->comm, current->pid); |
1317 | ||
1318 | for (i = 0; i < instructions_to_print; i++) { | |
1319 | int instr; | |
1320 | ||
1321 | if (!(i % 8) && (i > 0)) { | |
1322 | pr_cont("\n"); | |
1323 | pr_info("%s[%d]: code: ", current->comm, current->pid); | |
1324 | } | |
1325 | ||
1326 | if (probe_kernel_address((unsigned int __user *)pc, instr)) { | |
1327 | pr_cont("XXXXXXXX "); | |
1328 | } else { | |
1329 | if (regs->nip == pc) | |
1330 | pr_cont("<%08x> ", instr); | |
1331 | else | |
1332 | pr_cont("%08x ", instr); | |
1333 | } | |
1334 | ||
1335 | pc += sizeof(int); | |
1336 | } | |
1337 | ||
1338 | pr_cont("\n"); | |
1339 | } | |
1340 | ||
801c0b2c | 1341 | struct regbit { |
06d67d54 PM |
1342 | unsigned long bit; |
1343 | const char *name; | |
801c0b2c MN |
1344 | }; |
1345 | ||
1346 | static struct regbit msr_bits[] = { | |
3bfd0c9c AB |
1347 | #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) |
1348 | {MSR_SF, "SF"}, | |
1349 | {MSR_HV, "HV"}, | |
1350 | #endif | |
1351 | {MSR_VEC, "VEC"}, | |
1352 | {MSR_VSX, "VSX"}, | |
1353 | #ifdef CONFIG_BOOKE | |
1354 | {MSR_CE, "CE"}, | |
1355 | #endif | |
06d67d54 PM |
1356 | {MSR_EE, "EE"}, |
1357 | {MSR_PR, "PR"}, | |
1358 | {MSR_FP, "FP"}, | |
1359 | {MSR_ME, "ME"}, | |
3bfd0c9c | 1360 | #ifdef CONFIG_BOOKE |
1b98326b | 1361 | {MSR_DE, "DE"}, |
3bfd0c9c AB |
1362 | #else |
1363 | {MSR_SE, "SE"}, | |
1364 | {MSR_BE, "BE"}, | |
1365 | #endif | |
06d67d54 PM |
1366 | {MSR_IR, "IR"}, |
1367 | {MSR_DR, "DR"}, | |
3bfd0c9c AB |
1368 | {MSR_PMM, "PMM"}, |
1369 | #ifndef CONFIG_BOOKE | |
1370 | {MSR_RI, "RI"}, | |
1371 | {MSR_LE, "LE"}, | |
1372 | #endif | |
06d67d54 PM |
1373 | {0, NULL} |
1374 | }; | |
1375 | ||
801c0b2c | 1376 | static void print_bits(unsigned long val, struct regbit *bits, const char *sep) |
06d67d54 | 1377 | { |
801c0b2c | 1378 | const char *s = ""; |
06d67d54 | 1379 | |
06d67d54 PM |
1380 | for (; bits->bit; ++bits) |
1381 | if (val & bits->bit) { | |
db5ba5ae | 1382 | pr_cont("%s%s", s, bits->name); |
801c0b2c | 1383 | s = sep; |
06d67d54 | 1384 | } |
801c0b2c MN |
1385 | } |
1386 | ||
1387 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1388 | static struct regbit msr_tm_bits[] = { | |
1389 | {MSR_TS_T, "T"}, | |
1390 | {MSR_TS_S, "S"}, | |
1391 | {MSR_TM, "E"}, | |
1392 | {0, NULL} | |
1393 | }; | |
1394 | ||
1395 | static void print_tm_bits(unsigned long val) | |
1396 | { | |
1397 | /* | |
1398 | * This only prints something if at least one of the TM bit is set. | |
1399 | * Inside the TM[], the output means: | |
1400 | * E: Enabled (bit 32) | |
1401 | * S: Suspended (bit 33) | |
1402 | * T: Transactional (bit 34) | |
1403 | */ | |
1404 | if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { | |
db5ba5ae | 1405 | pr_cont(",TM["); |
801c0b2c | 1406 | print_bits(val, msr_tm_bits, ""); |
db5ba5ae | 1407 | pr_cont("]"); |
801c0b2c MN |
1408 | } |
1409 | } | |
1410 | #else | |
1411 | static void print_tm_bits(unsigned long val) {} | |
1412 | #endif | |
1413 | ||
1414 | static void print_msr_bits(unsigned long val) | |
1415 | { | |
db5ba5ae | 1416 | pr_cont("<"); |
801c0b2c MN |
1417 | print_bits(val, msr_bits, ","); |
1418 | print_tm_bits(val); | |
db5ba5ae | 1419 | pr_cont(">"); |
06d67d54 PM |
1420 | } |
1421 | ||
1422 | #ifdef CONFIG_PPC64 | |
f6f7dde3 | 1423 | #define REG "%016lx" |
06d67d54 PM |
1424 | #define REGS_PER_LINE 4 |
1425 | #define LAST_VOLATILE 13 | |
1426 | #else | |
f6f7dde3 | 1427 | #define REG "%08lx" |
06d67d54 PM |
1428 | #define REGS_PER_LINE 8 |
1429 | #define LAST_VOLATILE 12 | |
1430 | #endif | |
1431 | ||
14cf11af PM |
1432 | void show_regs(struct pt_regs * regs) |
1433 | { | |
1434 | int i, trap; | |
1435 | ||
a43cb95d TH |
1436 | show_regs_print_info(KERN_DEFAULT); |
1437 | ||
a6036100 | 1438 | printk("NIP: "REG" LR: "REG" CTR: "REG"\n", |
06d67d54 | 1439 | regs->nip, regs->link, regs->ctr); |
182dc9c7 | 1440 | printk("REGS: %px TRAP: %04lx %s (%s)\n", |
96b644bd | 1441 | regs, regs->trap, print_tainted(), init_utsname()->release); |
a6036100 | 1442 | printk("MSR: "REG" ", regs->msr); |
801c0b2c | 1443 | print_msr_bits(regs->msr); |
f6fc73fb | 1444 | pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); |
14cf11af | 1445 | trap = TRAP(regs); |
2271db20 | 1446 | if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) |
7dae865f | 1447 | pr_cont("CFAR: "REG" ", regs->orig_gpr3); |
c5400649 | 1448 | if (trap == 0x200 || trap == 0x300 || trap == 0x600) |
ba28c9aa | 1449 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
7dae865f | 1450 | pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); |
14170789 | 1451 | #else |
7dae865f | 1452 | pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); |
9db8bcfd AB |
1453 | #endif |
1454 | #ifdef CONFIG_PPC64 | |
3130a7bb | 1455 | pr_cont("IRQMASK: %lx ", regs->softe); |
9db8bcfd AB |
1456 | #endif |
1457 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
6d888d1a | 1458 | if (MSR_TM_ACTIVE(regs->msr)) |
7dae865f | 1459 | pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); |
14170789 | 1460 | #endif |
14cf11af PM |
1461 | |
1462 | for (i = 0; i < 32; i++) { | |
06d67d54 | 1463 | if ((i % REGS_PER_LINE) == 0) |
7dae865f ME |
1464 | pr_cont("\nGPR%02d: ", i); |
1465 | pr_cont(REG " ", regs->gpr[i]); | |
06d67d54 | 1466 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) |
14cf11af PM |
1467 | break; |
1468 | } | |
7dae865f | 1469 | pr_cont("\n"); |
14cf11af PM |
1470 | #ifdef CONFIG_KALLSYMS |
1471 | /* | |
1472 | * Lookup NIP late so we have the best change of getting the | |
1473 | * above info out without failing | |
1474 | */ | |
058c78f4 BH |
1475 | printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); |
1476 | printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); | |
afc07701 | 1477 | #endif |
14cf11af | 1478 | show_stack(current, (unsigned long *) regs->gpr[1]); |
06d67d54 PM |
1479 | if (!user_mode(regs)) |
1480 | show_instructions(regs); | |
14cf11af PM |
1481 | } |
1482 | ||
14cf11af PM |
1483 | void flush_thread(void) |
1484 | { | |
e0780b72 | 1485 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
5aae8a53 | 1486 | flush_ptrace_hw_breakpoint(current); |
e0780b72 | 1487 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1488 | set_debug_reg_defaults(¤t->thread); |
e0780b72 | 1489 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
14cf11af PM |
1490 | } |
1491 | ||
9d2a4d71 SB |
1492 | int set_thread_uses_vas(void) |
1493 | { | |
1494 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1495 | if (!cpu_has_feature(CPU_FTR_ARCH_300)) | |
1496 | return -EINVAL; | |
1497 | ||
1498 | current->thread.used_vas = 1; | |
1499 | ||
1500 | /* | |
1501 | * Even a process that has no foreign real address mapping can use | |
1502 | * an unpaired COPY instruction (to no real effect). Issue CP_ABORT | |
1503 | * to clear any pending COPY and prevent a covert channel. | |
1504 | * | |
1505 | * __switch_to() will issue CP_ABORT on future context switches. | |
1506 | */ | |
1507 | asm volatile(PPC_CP_ABORT); | |
1508 | ||
1509 | #endif /* CONFIG_PPC_BOOK3S_64 */ | |
1510 | return 0; | |
1511 | } | |
1512 | ||
ec233ede | 1513 | #ifdef CONFIG_PPC64 |
71cc64a8 AS |
1514 | /** |
1515 | * Assign a TIDR (thread ID) for task @t and set it in the thread | |
1516 | * structure. For now, we only support setting TIDR for 'current' task. | |
ec233ede | 1517 | * |
71cc64a8 AS |
1518 | * Since the TID value is a truncated form of it PID, it is possible |
1519 | * (but unlikely) for 2 threads to have the same TID. In the unlikely event | |
1520 | * that 2 threads share the same TID and are waiting, one of the following | |
1521 | * cases will happen: | |
ec233ede | 1522 | * |
71cc64a8 AS |
1523 | * 1. The correct thread is running, the wrong thread is not |
1524 | * In this situation, the correct thread is woken and proceeds to pass it's | |
1525 | * condition check. | |
ec233ede | 1526 | * |
71cc64a8 AS |
1527 | * 2. Neither threads are running |
1528 | * In this situation, neither thread will be woken. When scheduled, the waiting | |
1529 | * threads will execute either a wait, which will return immediately, followed | |
1530 | * by a condition check, which will pass for the correct thread and fail | |
1531 | * for the wrong thread, or they will execute the condition check immediately. | |
ec233ede | 1532 | * |
71cc64a8 AS |
1533 | * 3. The wrong thread is running, the correct thread is not |
1534 | * The wrong thread will be woken, but will fail it's condition check and | |
1535 | * re-execute wait. The correct thread, when scheduled, will execute either | |
1536 | * it's condition check (which will pass), or wait, which returns immediately | |
1537 | * when called the first time after the thread is scheduled, followed by it's | |
1538 | * condition check (which will pass). | |
ec233ede | 1539 | * |
71cc64a8 AS |
1540 | * 4. Both threads are running |
1541 | * Both threads will be woken. The wrong thread will fail it's condition check | |
1542 | * and execute another wait, while the correct thread will pass it's condition | |
1543 | * check. | |
1544 | * | |
1545 | * @t: the task to set the thread ID for | |
ec233ede SB |
1546 | */ |
1547 | int set_thread_tidr(struct task_struct *t) | |
1548 | { | |
3449f191 | 1549 | if (!cpu_has_feature(CPU_FTR_P9_TIDR)) |
ec233ede SB |
1550 | return -EINVAL; |
1551 | ||
1552 | if (t != current) | |
1553 | return -EINVAL; | |
1554 | ||
7e4d4233 VJ |
1555 | if (t->thread.tidr) |
1556 | return 0; | |
1557 | ||
71cc64a8 | 1558 | t->thread.tidr = (u16)task_pid_nr(t); |
ec233ede SB |
1559 | mtspr(SPRN_TIDR, t->thread.tidr); |
1560 | ||
1561 | return 0; | |
1562 | } | |
b1db5513 | 1563 | EXPORT_SYMBOL_GPL(set_thread_tidr); |
ec233ede SB |
1564 | |
1565 | #endif /* CONFIG_PPC64 */ | |
1566 | ||
14cf11af PM |
1567 | void |
1568 | release_thread(struct task_struct *t) | |
1569 | { | |
1570 | } | |
1571 | ||
1572 | /* | |
55ccf3fe SS |
1573 | * this gets called so that we can store coprocessor state into memory and |
1574 | * copy the current task into the new thread. | |
14cf11af | 1575 | */ |
55ccf3fe | 1576 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
14cf11af | 1577 | { |
579e633e | 1578 | flush_all_to_thread(src); |
621b5060 MN |
1579 | /* |
1580 | * Flush TM state out so we can copy it. __switch_to_tm() does this | |
1581 | * flush but it removes the checkpointed state from the current CPU and | |
1582 | * transitions the CPU out of TM mode. Hence we need to call | |
1583 | * tm_recheckpoint_new_task() (on the same task) to restore the | |
1584 | * checkpointed state back and the TM mode. | |
5d176f75 CB |
1585 | * |
1586 | * Can't pass dst because it isn't ready. Doesn't matter, passing | |
1587 | * dst is only important for __switch_to() | |
621b5060 | 1588 | */ |
dc310669 | 1589 | __switch_to_tm(src, src); |
330a1eb7 | 1590 | |
55ccf3fe | 1591 | *dst = *src; |
330a1eb7 ME |
1592 | |
1593 | clear_task_ebb(dst); | |
1594 | ||
55ccf3fe | 1595 | return 0; |
14cf11af PM |
1596 | } |
1597 | ||
cec15488 ME |
1598 | static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) |
1599 | { | |
4e003747 | 1600 | #ifdef CONFIG_PPC_BOOK3S_64 |
cec15488 ME |
1601 | unsigned long sp_vsid; |
1602 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
1603 | ||
caca285e AK |
1604 | if (radix_enabled()) |
1605 | return; | |
1606 | ||
cec15488 ME |
1607 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
1608 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) | |
1609 | << SLB_VSID_SHIFT_1T; | |
1610 | else | |
1611 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) | |
1612 | << SLB_VSID_SHIFT; | |
1613 | sp_vsid |= SLB_VSID_KERNEL | llp; | |
1614 | p->thread.ksp_vsid = sp_vsid; | |
1615 | #endif | |
1616 | } | |
1617 | ||
14cf11af PM |
1618 | /* |
1619 | * Copy a thread.. | |
1620 | */ | |
efcac658 | 1621 | |
6eca8933 AD |
1622 | /* |
1623 | * Copy architecture-specific thread state | |
1624 | */ | |
6f2c55b8 | 1625 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
6eca8933 | 1626 | unsigned long kthread_arg, struct task_struct *p) |
14cf11af PM |
1627 | { |
1628 | struct pt_regs *childregs, *kregs; | |
1629 | extern void ret_from_fork(void); | |
58254e10 AV |
1630 | extern void ret_from_kernel_thread(void); |
1631 | void (*f)(void); | |
0cec6fd1 | 1632 | unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
5d31a96e ME |
1633 | struct thread_info *ti = task_thread_info(p); |
1634 | ||
1635 | klp_init_thread_info(ti); | |
14cf11af | 1636 | |
14cf11af PM |
1637 | /* Copy registers */ |
1638 | sp -= sizeof(struct pt_regs); | |
1639 | childregs = (struct pt_regs *) sp; | |
ab75819d | 1640 | if (unlikely(p->flags & PF_KTHREAD)) { |
6eca8933 | 1641 | /* kernel thread */ |
58254e10 | 1642 | memset(childregs, 0, sizeof(struct pt_regs)); |
14cf11af | 1643 | childregs->gpr[1] = sp + sizeof(struct pt_regs); |
7cedd601 AB |
1644 | /* function */ |
1645 | if (usp) | |
1646 | childregs->gpr[14] = ppc_function_entry((void *)usp); | |
58254e10 | 1647 | #ifdef CONFIG_PPC64 |
b5e2fc1c | 1648 | clear_tsk_thread_flag(p, TIF_32BIT); |
c2e480ba | 1649 | childregs->softe = IRQS_ENABLED; |
06d67d54 | 1650 | #endif |
6eca8933 | 1651 | childregs->gpr[15] = kthread_arg; |
14cf11af | 1652 | p->thread.regs = NULL; /* no user register state */ |
138d1ce8 | 1653 | ti->flags |= _TIF_RESTOREALL; |
58254e10 | 1654 | f = ret_from_kernel_thread; |
14cf11af | 1655 | } else { |
6eca8933 | 1656 | /* user thread */ |
afa86fc4 | 1657 | struct pt_regs *regs = current_pt_regs(); |
58254e10 AV |
1658 | CHECK_FULL_REGS(regs); |
1659 | *childregs = *regs; | |
ea516b11 AV |
1660 | if (usp) |
1661 | childregs->gpr[1] = usp; | |
14cf11af | 1662 | p->thread.regs = childregs; |
58254e10 | 1663 | childregs->gpr[3] = 0; /* Result from fork() */ |
06d67d54 PM |
1664 | if (clone_flags & CLONE_SETTLS) { |
1665 | #ifdef CONFIG_PPC64 | |
9904b005 | 1666 | if (!is_32bit_task()) |
06d67d54 PM |
1667 | childregs->gpr[13] = childregs->gpr[6]; |
1668 | else | |
1669 | #endif | |
1670 | childregs->gpr[2] = childregs->gpr[6]; | |
1671 | } | |
58254e10 AV |
1672 | |
1673 | f = ret_from_fork; | |
14cf11af | 1674 | } |
d272f667 | 1675 | childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); |
14cf11af | 1676 | sp -= STACK_FRAME_OVERHEAD; |
14cf11af PM |
1677 | |
1678 | /* | |
1679 | * The way this works is that at some point in the future | |
1680 | * some task will call _switch to switch to the new task. | |
1681 | * That will pop off the stack frame created below and start | |
1682 | * the new task running at ret_from_fork. The new task will | |
1683 | * do some house keeping and then return from the fork or clone | |
1684 | * system call, using the stack frame created above. | |
1685 | */ | |
af945cf4 | 1686 | ((unsigned long *)sp)[0] = 0; |
14cf11af PM |
1687 | sp -= sizeof(struct pt_regs); |
1688 | kregs = (struct pt_regs *) sp; | |
1689 | sp -= STACK_FRAME_OVERHEAD; | |
1690 | p->thread.ksp = sp; | |
cbc9565e | 1691 | #ifdef CONFIG_PPC32 |
85218827 KG |
1692 | p->thread.ksp_limit = (unsigned long)task_stack_page(p) + |
1693 | _ALIGN_UP(sizeof(struct thread_info), 16); | |
cbc9565e | 1694 | #endif |
28d170ab ON |
1695 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1696 | p->thread.ptrace_bps[0] = NULL; | |
1697 | #endif | |
1698 | ||
18461960 PM |
1699 | p->thread.fp_save_area = NULL; |
1700 | #ifdef CONFIG_ALTIVEC | |
1701 | p->thread.vr_save_area = NULL; | |
1702 | #endif | |
1703 | ||
cec15488 ME |
1704 | setup_ksp_vsid(p, sp); |
1705 | ||
efcac658 AK |
1706 | #ifdef CONFIG_PPC64 |
1707 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1021cb26 | 1708 | p->thread.dscr_inherit = current->thread.dscr_inherit; |
db1231dc | 1709 | p->thread.dscr = mfspr(SPRN_DSCR); |
efcac658 | 1710 | } |
92779245 HM |
1711 | if (cpu_has_feature(CPU_FTR_HAS_PPR)) |
1712 | p->thread.ppr = INIT_PPR; | |
ec233ede SB |
1713 | |
1714 | p->thread.tidr = 0; | |
efcac658 | 1715 | #endif |
7cedd601 | 1716 | kregs->nip = ppc_function_entry(f); |
14cf11af PM |
1717 | return 0; |
1718 | } | |
1719 | ||
1720 | /* | |
1721 | * Set up a thread for executing a new program | |
1722 | */ | |
06d67d54 | 1723 | void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) |
14cf11af | 1724 | { |
90eac727 ME |
1725 | #ifdef CONFIG_PPC64 |
1726 | unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ | |
1727 | #endif | |
1728 | ||
06d67d54 PM |
1729 | /* |
1730 | * If we exec out of a kernel thread then thread.regs will not be | |
1731 | * set. Do it now. | |
1732 | */ | |
1733 | if (!current->thread.regs) { | |
0cec6fd1 AV |
1734 | struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; |
1735 | current->thread.regs = regs - 1; | |
06d67d54 PM |
1736 | } |
1737 | ||
8e96a87c CB |
1738 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1739 | /* | |
1740 | * Clear any transactional state, we're exec()ing. The cause is | |
1741 | * not important as there will never be a recheckpoint so it's not | |
1742 | * user visible. | |
1743 | */ | |
1744 | if (MSR_TM_SUSPENDED(mfmsr())) | |
1745 | tm_reclaim_current(0); | |
1746 | #endif | |
1747 | ||
14cf11af PM |
1748 | memset(regs->gpr, 0, sizeof(regs->gpr)); |
1749 | regs->ctr = 0; | |
1750 | regs->link = 0; | |
1751 | regs->xer = 0; | |
1752 | regs->ccr = 0; | |
14cf11af | 1753 | regs->gpr[1] = sp; |
06d67d54 | 1754 | |
474f8196 RM |
1755 | /* |
1756 | * We have just cleared all the nonvolatile GPRs, so make | |
1757 | * FULL_REGS(regs) return true. This is necessary to allow | |
1758 | * ptrace to examine the thread immediately after exec. | |
1759 | */ | |
1760 | regs->trap &= ~1UL; | |
1761 | ||
06d67d54 PM |
1762 | #ifdef CONFIG_PPC32 |
1763 | regs->mq = 0; | |
1764 | regs->nip = start; | |
14cf11af | 1765 | regs->msr = MSR_USER; |
06d67d54 | 1766 | #else |
9904b005 | 1767 | if (!is_32bit_task()) { |
94af3abf | 1768 | unsigned long entry; |
06d67d54 | 1769 | |
94af3abf RR |
1770 | if (is_elf2_task()) { |
1771 | /* Look ma, no function descriptors! */ | |
1772 | entry = start; | |
06d67d54 | 1773 | |
94af3abf RR |
1774 | /* |
1775 | * Ulrich says: | |
1776 | * The latest iteration of the ABI requires that when | |
1777 | * calling a function (at its global entry point), | |
1778 | * the caller must ensure r12 holds the entry point | |
1779 | * address (so that the function can quickly | |
1780 | * establish addressability). | |
1781 | */ | |
1782 | regs->gpr[12] = start; | |
1783 | /* Make sure that's restored on entry to userspace. */ | |
1784 | set_thread_flag(TIF_RESTOREALL); | |
1785 | } else { | |
1786 | unsigned long toc; | |
1787 | ||
1788 | /* start is a relocated pointer to the function | |
1789 | * descriptor for the elf _start routine. The first | |
1790 | * entry in the function descriptor is the entry | |
1791 | * address of _start and the second entry is the TOC | |
1792 | * value we need to use. | |
1793 | */ | |
1794 | __get_user(entry, (unsigned long __user *)start); | |
1795 | __get_user(toc, (unsigned long __user *)start+1); | |
1796 | ||
1797 | /* Check whether the e_entry function descriptor entries | |
1798 | * need to be relocated before we can use them. | |
1799 | */ | |
1800 | if (load_addr != 0) { | |
1801 | entry += load_addr; | |
1802 | toc += load_addr; | |
1803 | } | |
1804 | regs->gpr[2] = toc; | |
06d67d54 PM |
1805 | } |
1806 | regs->nip = entry; | |
06d67d54 | 1807 | regs->msr = MSR_USER64; |
d4bf9a78 SR |
1808 | } else { |
1809 | regs->nip = start; | |
1810 | regs->gpr[2] = 0; | |
1811 | regs->msr = MSR_USER32; | |
06d67d54 PM |
1812 | } |
1813 | #endif | |
ce48b210 MN |
1814 | #ifdef CONFIG_VSX |
1815 | current->thread.used_vsr = 0; | |
1816 | #endif | |
1195892c | 1817 | current->thread.load_fp = 0; |
de79f7b9 | 1818 | memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); |
18461960 | 1819 | current->thread.fp_save_area = NULL; |
14cf11af | 1820 | #ifdef CONFIG_ALTIVEC |
de79f7b9 PM |
1821 | memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); |
1822 | current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ | |
18461960 | 1823 | current->thread.vr_save_area = NULL; |
14cf11af PM |
1824 | current->thread.vrsave = 0; |
1825 | current->thread.used_vr = 0; | |
1195892c | 1826 | current->thread.load_vec = 0; |
14cf11af PM |
1827 | #endif /* CONFIG_ALTIVEC */ |
1828 | #ifdef CONFIG_SPE | |
1829 | memset(current->thread.evr, 0, sizeof(current->thread.evr)); | |
1830 | current->thread.acc = 0; | |
1831 | current->thread.spefscr = 0; | |
1832 | current->thread.used_spe = 0; | |
1833 | #endif /* CONFIG_SPE */ | |
bc2a9408 | 1834 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
bc2a9408 MN |
1835 | current->thread.tm_tfhar = 0; |
1836 | current->thread.tm_texasr = 0; | |
1837 | current->thread.tm_tfiar = 0; | |
7f22ced4 | 1838 | current->thread.load_tm = 0; |
bc2a9408 | 1839 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
06bb53b3 RP |
1840 | |
1841 | thread_pkey_regs_init(¤t->thread); | |
14cf11af | 1842 | } |
e1802b06 | 1843 | EXPORT_SYMBOL(start_thread); |
14cf11af PM |
1844 | |
1845 | #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ | |
1846 | | PR_FP_EXC_RES | PR_FP_EXC_INV) | |
1847 | ||
1848 | int set_fpexc_mode(struct task_struct *tsk, unsigned int val) | |
1849 | { | |
1850 | struct pt_regs *regs = tsk->thread.regs; | |
1851 | ||
1852 | /* This is a bit hairy. If we are an SPE enabled processor | |
1853 | * (have embedded fp) we store the IEEE exception enable flags in | |
1854 | * fpexc_mode. fpexc_mode is also used for setting FP exception | |
1855 | * mode (asyn, precise, disabled) for 'Classic' FP. */ | |
1856 | if (val & PR_FP_EXC_SW_ENABLE) { | |
1857 | #ifdef CONFIG_SPE | |
5e14d21e | 1858 | if (cpu_has_feature(CPU_FTR_SPE)) { |
640e9225 JM |
1859 | /* |
1860 | * When the sticky exception bits are set | |
1861 | * directly by userspace, it must call prctl | |
1862 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1863 | * in the existing prctl settings) or | |
1864 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1865 | * the bits being set). <fenv.h> functions | |
1866 | * saving and restoring the whole | |
1867 | * floating-point environment need to do so | |
1868 | * anyway to restore the prctl settings from | |
1869 | * the saved environment. | |
1870 | */ | |
1871 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e KG |
1872 | tsk->thread.fpexc_mode = val & |
1873 | (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); | |
1874 | return 0; | |
1875 | } else { | |
1876 | return -EINVAL; | |
1877 | } | |
14cf11af PM |
1878 | #else |
1879 | return -EINVAL; | |
1880 | #endif | |
14cf11af | 1881 | } |
06d67d54 PM |
1882 | |
1883 | /* on a CONFIG_SPE this does not hurt us. The bits that | |
1884 | * __pack_fe01 use do not overlap with bits used for | |
1885 | * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits | |
1886 | * on CONFIG_SPE implementations are reserved so writing to | |
1887 | * them does not change anything */ | |
1888 | if (val > PR_FP_EXC_PRECISE) | |
1889 | return -EINVAL; | |
1890 | tsk->thread.fpexc_mode = __pack_fe01(val); | |
1891 | if (regs != NULL && (regs->msr & MSR_FP) != 0) | |
1892 | regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) | |
1893 | | tsk->thread.fpexc_mode; | |
14cf11af PM |
1894 | return 0; |
1895 | } | |
1896 | ||
1897 | int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) | |
1898 | { | |
1899 | unsigned int val; | |
1900 | ||
1901 | if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) | |
1902 | #ifdef CONFIG_SPE | |
640e9225 JM |
1903 | if (cpu_has_feature(CPU_FTR_SPE)) { |
1904 | /* | |
1905 | * When the sticky exception bits are set | |
1906 | * directly by userspace, it must call prctl | |
1907 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1908 | * in the existing prctl settings) or | |
1909 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1910 | * the bits being set). <fenv.h> functions | |
1911 | * saving and restoring the whole | |
1912 | * floating-point environment need to do so | |
1913 | * anyway to restore the prctl settings from | |
1914 | * the saved environment. | |
1915 | */ | |
1916 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e | 1917 | val = tsk->thread.fpexc_mode; |
640e9225 | 1918 | } else |
5e14d21e | 1919 | return -EINVAL; |
14cf11af PM |
1920 | #else |
1921 | return -EINVAL; | |
1922 | #endif | |
1923 | else | |
1924 | val = __unpack_fe01(tsk->thread.fpexc_mode); | |
1925 | return put_user(val, (unsigned int __user *) adr); | |
1926 | } | |
1927 | ||
fab5db97 PM |
1928 | int set_endian(struct task_struct *tsk, unsigned int val) |
1929 | { | |
1930 | struct pt_regs *regs = tsk->thread.regs; | |
1931 | ||
1932 | if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || | |
1933 | (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) | |
1934 | return -EINVAL; | |
1935 | ||
1936 | if (regs == NULL) | |
1937 | return -EINVAL; | |
1938 | ||
1939 | if (val == PR_ENDIAN_BIG) | |
1940 | regs->msr &= ~MSR_LE; | |
1941 | else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) | |
1942 | regs->msr |= MSR_LE; | |
1943 | else | |
1944 | return -EINVAL; | |
1945 | ||
1946 | return 0; | |
1947 | } | |
1948 | ||
1949 | int get_endian(struct task_struct *tsk, unsigned long adr) | |
1950 | { | |
1951 | struct pt_regs *regs = tsk->thread.regs; | |
1952 | unsigned int val; | |
1953 | ||
1954 | if (!cpu_has_feature(CPU_FTR_PPC_LE) && | |
1955 | !cpu_has_feature(CPU_FTR_REAL_LE)) | |
1956 | return -EINVAL; | |
1957 | ||
1958 | if (regs == NULL) | |
1959 | return -EINVAL; | |
1960 | ||
1961 | if (regs->msr & MSR_LE) { | |
1962 | if (cpu_has_feature(CPU_FTR_REAL_LE)) | |
1963 | val = PR_ENDIAN_LITTLE; | |
1964 | else | |
1965 | val = PR_ENDIAN_PPC_LITTLE; | |
1966 | } else | |
1967 | val = PR_ENDIAN_BIG; | |
1968 | ||
1969 | return put_user(val, (unsigned int __user *)adr); | |
1970 | } | |
1971 | ||
e9370ae1 PM |
1972 | int set_unalign_ctl(struct task_struct *tsk, unsigned int val) |
1973 | { | |
1974 | tsk->thread.align_ctl = val; | |
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) | |
1979 | { | |
1980 | return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); | |
1981 | } | |
1982 | ||
bb72c481 PM |
1983 | static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, |
1984 | unsigned long nbytes) | |
1985 | { | |
1986 | unsigned long stack_page; | |
1987 | unsigned long cpu = task_cpu(p); | |
1988 | ||
1989 | /* | |
1990 | * Avoid crashing if the stack has overflowed and corrupted | |
1991 | * task_cpu(p), which is in the thread_info struct. | |
1992 | */ | |
1993 | if (cpu < NR_CPUS && cpu_possible(cpu)) { | |
1994 | stack_page = (unsigned long) hardirq_ctx[cpu]; | |
1995 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1996 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1997 | return 1; | |
1998 | ||
1999 | stack_page = (unsigned long) softirq_ctx[cpu]; | |
2000 | if (sp >= stack_page + sizeof(struct thread_struct) | |
2001 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
2002 | return 1; | |
2003 | } | |
2004 | return 0; | |
2005 | } | |
2006 | ||
2f25194d | 2007 | int validate_sp(unsigned long sp, struct task_struct *p, |
14cf11af PM |
2008 | unsigned long nbytes) |
2009 | { | |
0cec6fd1 | 2010 | unsigned long stack_page = (unsigned long)task_stack_page(p); |
14cf11af PM |
2011 | |
2012 | if (sp >= stack_page + sizeof(struct thread_struct) | |
2013 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
2014 | return 1; | |
2015 | ||
bb72c481 | 2016 | return valid_irq_stack(sp, p, nbytes); |
14cf11af PM |
2017 | } |
2018 | ||
2f25194d AB |
2019 | EXPORT_SYMBOL(validate_sp); |
2020 | ||
14cf11af PM |
2021 | unsigned long get_wchan(struct task_struct *p) |
2022 | { | |
2023 | unsigned long ip, sp; | |
2024 | int count = 0; | |
2025 | ||
2026 | if (!p || p == current || p->state == TASK_RUNNING) | |
2027 | return 0; | |
2028 | ||
2029 | sp = p->thread.ksp; | |
ec2b36b9 | 2030 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
2031 | return 0; |
2032 | ||
2033 | do { | |
2034 | sp = *(unsigned long *)sp; | |
4ca360f3 KC |
2035 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) || |
2036 | p->state == TASK_RUNNING) | |
14cf11af PM |
2037 | return 0; |
2038 | if (count > 0) { | |
ec2b36b9 | 2039 | ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; |
14cf11af PM |
2040 | if (!in_sched_functions(ip)) |
2041 | return ip; | |
2042 | } | |
2043 | } while (count++ < 16); | |
2044 | return 0; | |
2045 | } | |
06d67d54 | 2046 | |
c4d04be1 | 2047 | static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; |
06d67d54 PM |
2048 | |
2049 | void show_stack(struct task_struct *tsk, unsigned long *stack) | |
2050 | { | |
2051 | unsigned long sp, ip, lr, newsp; | |
2052 | int count = 0; | |
2053 | int firstframe = 1; | |
6794c782 SR |
2054 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
2055 | int curr_frame = current->curr_ret_stack; | |
2056 | extern void return_to_handler(void); | |
9135c3cc | 2057 | unsigned long rth = (unsigned long)return_to_handler; |
6794c782 | 2058 | #endif |
06d67d54 PM |
2059 | |
2060 | sp = (unsigned long) stack; | |
2061 | if (tsk == NULL) | |
2062 | tsk = current; | |
2063 | if (sp == 0) { | |
2064 | if (tsk == current) | |
acf620ec | 2065 | sp = current_stack_pointer(); |
06d67d54 PM |
2066 | else |
2067 | sp = tsk->thread.ksp; | |
2068 | } | |
2069 | ||
2070 | lr = 0; | |
2071 | printk("Call Trace:\n"); | |
2072 | do { | |
ec2b36b9 | 2073 | if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) |
06d67d54 PM |
2074 | return; |
2075 | ||
2076 | stack = (unsigned long *) sp; | |
2077 | newsp = stack[0]; | |
ec2b36b9 | 2078 | ip = stack[STACK_FRAME_LR_SAVE]; |
06d67d54 | 2079 | if (!firstframe || ip != lr) { |
058c78f4 | 2080 | printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); |
6794c782 | 2081 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
7d56c65a | 2082 | if ((ip == rth) && curr_frame >= 0) { |
9a1f490f | 2083 | pr_cont(" (%pS)", |
6794c782 SR |
2084 | (void *)current->ret_stack[curr_frame].ret); |
2085 | curr_frame--; | |
2086 | } | |
2087 | #endif | |
06d67d54 | 2088 | if (firstframe) |
9a1f490f ME |
2089 | pr_cont(" (unreliable)"); |
2090 | pr_cont("\n"); | |
06d67d54 PM |
2091 | } |
2092 | firstframe = 0; | |
2093 | ||
2094 | /* | |
2095 | * See if this is an exception frame. | |
2096 | * We look for the "regshere" marker in the current frame. | |
2097 | */ | |
ec2b36b9 BH |
2098 | if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) |
2099 | && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { | |
06d67d54 PM |
2100 | struct pt_regs *regs = (struct pt_regs *) |
2101 | (sp + STACK_FRAME_OVERHEAD); | |
06d67d54 | 2102 | lr = regs->link; |
9be9be2e | 2103 | printk("--- interrupt: %lx at %pS\n LR = %pS\n", |
058c78f4 | 2104 | regs->trap, (void *)regs->nip, (void *)lr); |
06d67d54 PM |
2105 | firstframe = 1; |
2106 | } | |
2107 | ||
2108 | sp = newsp; | |
2109 | } while (count++ < kstack_depth_to_print); | |
2110 | } | |
2111 | ||
cb2c9b27 | 2112 | #ifdef CONFIG_PPC64 |
fe1952fc | 2113 | /* Called with hard IRQs off */ |
0e37739b | 2114 | void notrace __ppc64_runlatch_on(void) |
cb2c9b27 | 2115 | { |
fe1952fc | 2116 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 | 2117 | |
d1d0d5ff NP |
2118 | if (cpu_has_feature(CPU_FTR_ARCH_206)) { |
2119 | /* | |
2120 | * Least significant bit (RUN) is the only writable bit of | |
2121 | * the CTRL register, so we can avoid mfspr. 2.06 is not the | |
2122 | * earliest ISA where this is the case, but it's convenient. | |
2123 | */ | |
2124 | mtspr(SPRN_CTRLT, CTRL_RUNLATCH); | |
2125 | } else { | |
2126 | unsigned long ctrl; | |
2127 | ||
2128 | /* | |
2129 | * Some architectures (e.g., Cell) have writable fields other | |
2130 | * than RUN, so do the read-modify-write. | |
2131 | */ | |
2132 | ctrl = mfspr(SPRN_CTRLF); | |
2133 | ctrl |= CTRL_RUNLATCH; | |
2134 | mtspr(SPRN_CTRLT, ctrl); | |
2135 | } | |
cb2c9b27 | 2136 | |
fae2e0fb | 2137 | ti->local_flags |= _TLF_RUNLATCH; |
cb2c9b27 AB |
2138 | } |
2139 | ||
fe1952fc | 2140 | /* Called with hard IRQs off */ |
0e37739b | 2141 | void notrace __ppc64_runlatch_off(void) |
cb2c9b27 | 2142 | { |
fe1952fc | 2143 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 | 2144 | |
fae2e0fb | 2145 | ti->local_flags &= ~_TLF_RUNLATCH; |
cb2c9b27 | 2146 | |
d1d0d5ff NP |
2147 | if (cpu_has_feature(CPU_FTR_ARCH_206)) { |
2148 | mtspr(SPRN_CTRLT, 0); | |
2149 | } else { | |
2150 | unsigned long ctrl; | |
2151 | ||
2152 | ctrl = mfspr(SPRN_CTRLF); | |
2153 | ctrl &= ~CTRL_RUNLATCH; | |
2154 | mtspr(SPRN_CTRLT, ctrl); | |
2155 | } | |
cb2c9b27 | 2156 | } |
fe1952fc | 2157 | #endif /* CONFIG_PPC64 */ |
f6a61680 | 2158 | |
d839088c AB |
2159 | unsigned long arch_align_stack(unsigned long sp) |
2160 | { | |
2161 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
2162 | sp -= get_random_int() & ~PAGE_MASK; | |
2163 | return sp & ~0xf; | |
2164 | } | |
912f9ee2 AB |
2165 | |
2166 | static inline unsigned long brk_rnd(void) | |
2167 | { | |
2168 | unsigned long rnd = 0; | |
2169 | ||
2170 | /* 8MB for 32bit, 1GB for 64bit */ | |
2171 | if (is_32bit_task()) | |
5ef11c35 | 2172 | rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); |
912f9ee2 | 2173 | else |
5ef11c35 | 2174 | rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); |
912f9ee2 AB |
2175 | |
2176 | return rnd << PAGE_SHIFT; | |
2177 | } | |
2178 | ||
2179 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
2180 | { | |
8bbde7a7 AB |
2181 | unsigned long base = mm->brk; |
2182 | unsigned long ret; | |
2183 | ||
4e003747 | 2184 | #ifdef CONFIG_PPC_BOOK3S_64 |
8bbde7a7 AB |
2185 | /* |
2186 | * If we are using 1TB segments and we are allowed to randomise | |
2187 | * the heap, we can put it above 1TB so it is backed by a 1TB | |
2188 | * segment. Otherwise the heap will be in the bottom 1TB | |
2189 | * which always uses 256MB segments and this may result in a | |
caca285e AK |
2190 | * performance penalty. We don't need to worry about radix. For |
2191 | * radix, mmu_highuser_ssize remains unchanged from 256MB. | |
8bbde7a7 AB |
2192 | */ |
2193 | if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) | |
2194 | base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); | |
2195 | #endif | |
2196 | ||
2197 | ret = PAGE_ALIGN(base + brk_rnd()); | |
912f9ee2 AB |
2198 | |
2199 | if (ret < mm->brk) | |
2200 | return mm->brk; | |
2201 | ||
2202 | return ret; | |
2203 | } | |
501cb16d | 2204 |