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Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Derived from "arch/i386/kernel/process.c" |
3 | * Copyright (C) 1995 Linus Torvalds | |
4 | * | |
5 | * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and | |
6 | * Paul Mackerras (paulus@cs.anu.edu.au) | |
7 | * | |
8 | * PowerPC version | |
9 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
14cf11af PM |
22 | #include <linux/stddef.h> |
23 | #include <linux/unistd.h> | |
24 | #include <linux/ptrace.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/user.h> | |
27 | #include <linux/elf.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/prctl.h> | |
30 | #include <linux/init_task.h> | |
4b16f8e2 | 31 | #include <linux/export.h> |
14cf11af PM |
32 | #include <linux/kallsyms.h> |
33 | #include <linux/mqueue.h> | |
34 | #include <linux/hardirq.h> | |
06d67d54 | 35 | #include <linux/utsname.h> |
6794c782 | 36 | #include <linux/ftrace.h> |
79741dd3 | 37 | #include <linux/kernel_stat.h> |
d839088c AB |
38 | #include <linux/personality.h> |
39 | #include <linux/random.h> | |
5aae8a53 | 40 | #include <linux/hw_breakpoint.h> |
14cf11af PM |
41 | |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/uaccess.h> | |
14cf11af PM |
44 | #include <asm/io.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/mmu.h> | |
47 | #include <asm/prom.h> | |
76032de8 | 48 | #include <asm/machdep.h> |
c6622f63 | 49 | #include <asm/time.h> |
ae3a197e | 50 | #include <asm/runlatch.h> |
a7f31841 | 51 | #include <asm/syscalls.h> |
ae3a197e DH |
52 | #include <asm/switch_to.h> |
53 | #include <asm/debug.h> | |
06d67d54 PM |
54 | #ifdef CONFIG_PPC64 |
55 | #include <asm/firmware.h> | |
06d67d54 | 56 | #endif |
d6a61bfc LM |
57 | #include <linux/kprobes.h> |
58 | #include <linux/kdebug.h> | |
14cf11af PM |
59 | |
60 | extern unsigned long _get_SP(void); | |
61 | ||
62 | #ifndef CONFIG_SMP | |
63 | struct task_struct *last_task_used_math = NULL; | |
64 | struct task_struct *last_task_used_altivec = NULL; | |
ce48b210 | 65 | struct task_struct *last_task_used_vsx = NULL; |
14cf11af PM |
66 | struct task_struct *last_task_used_spe = NULL; |
67 | #endif | |
68 | ||
14cf11af PM |
69 | /* |
70 | * Make sure the floating-point register state in the | |
71 | * the thread_struct is up to date for task tsk. | |
72 | */ | |
73 | void flush_fp_to_thread(struct task_struct *tsk) | |
74 | { | |
75 | if (tsk->thread.regs) { | |
76 | /* | |
77 | * We need to disable preemption here because if we didn't, | |
78 | * another process could get scheduled after the regs->msr | |
79 | * test but before we have finished saving the FP registers | |
80 | * to the thread_struct. That process could take over the | |
81 | * FPU, and then when we get scheduled again we would store | |
82 | * bogus values for the remaining FP registers. | |
83 | */ | |
84 | preempt_disable(); | |
85 | if (tsk->thread.regs->msr & MSR_FP) { | |
86 | #ifdef CONFIG_SMP | |
87 | /* | |
88 | * This should only ever be called for current or | |
89 | * for a stopped child process. Since we save away | |
90 | * the FP register state on context switch on SMP, | |
91 | * there is something wrong if a stopped child appears | |
92 | * to still have its FP state in the CPU registers. | |
93 | */ | |
94 | BUG_ON(tsk != current); | |
95 | #endif | |
0ee6c15e | 96 | giveup_fpu(tsk); |
14cf11af PM |
97 | } |
98 | preempt_enable(); | |
99 | } | |
100 | } | |
de56a948 | 101 | EXPORT_SYMBOL_GPL(flush_fp_to_thread); |
14cf11af PM |
102 | |
103 | void enable_kernel_fp(void) | |
104 | { | |
105 | WARN_ON(preemptible()); | |
106 | ||
107 | #ifdef CONFIG_SMP | |
108 | if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) | |
109 | giveup_fpu(current); | |
110 | else | |
111 | giveup_fpu(NULL); /* just enables FP for kernel */ | |
112 | #else | |
113 | giveup_fpu(last_task_used_math); | |
114 | #endif /* CONFIG_SMP */ | |
115 | } | |
116 | EXPORT_SYMBOL(enable_kernel_fp); | |
117 | ||
14cf11af PM |
118 | #ifdef CONFIG_ALTIVEC |
119 | void enable_kernel_altivec(void) | |
120 | { | |
121 | WARN_ON(preemptible()); | |
122 | ||
123 | #ifdef CONFIG_SMP | |
124 | if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) | |
125 | giveup_altivec(current); | |
126 | else | |
35000870 | 127 | giveup_altivec_notask(); |
14cf11af PM |
128 | #else |
129 | giveup_altivec(last_task_used_altivec); | |
130 | #endif /* CONFIG_SMP */ | |
131 | } | |
132 | EXPORT_SYMBOL(enable_kernel_altivec); | |
133 | ||
134 | /* | |
135 | * Make sure the VMX/Altivec register state in the | |
136 | * the thread_struct is up to date for task tsk. | |
137 | */ | |
138 | void flush_altivec_to_thread(struct task_struct *tsk) | |
139 | { | |
140 | if (tsk->thread.regs) { | |
141 | preempt_disable(); | |
142 | if (tsk->thread.regs->msr & MSR_VEC) { | |
143 | #ifdef CONFIG_SMP | |
144 | BUG_ON(tsk != current); | |
145 | #endif | |
0ee6c15e | 146 | giveup_altivec(tsk); |
14cf11af PM |
147 | } |
148 | preempt_enable(); | |
149 | } | |
150 | } | |
de56a948 | 151 | EXPORT_SYMBOL_GPL(flush_altivec_to_thread); |
14cf11af PM |
152 | #endif /* CONFIG_ALTIVEC */ |
153 | ||
ce48b210 MN |
154 | #ifdef CONFIG_VSX |
155 | #if 0 | |
156 | /* not currently used, but some crazy RAID module might want to later */ | |
157 | void enable_kernel_vsx(void) | |
158 | { | |
159 | WARN_ON(preemptible()); | |
160 | ||
161 | #ifdef CONFIG_SMP | |
162 | if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) | |
163 | giveup_vsx(current); | |
164 | else | |
165 | giveup_vsx(NULL); /* just enable vsx for kernel - force */ | |
166 | #else | |
167 | giveup_vsx(last_task_used_vsx); | |
168 | #endif /* CONFIG_SMP */ | |
169 | } | |
170 | EXPORT_SYMBOL(enable_kernel_vsx); | |
171 | #endif | |
172 | ||
7c292170 MN |
173 | void giveup_vsx(struct task_struct *tsk) |
174 | { | |
175 | giveup_fpu(tsk); | |
176 | giveup_altivec(tsk); | |
177 | __giveup_vsx(tsk); | |
178 | } | |
179 | ||
ce48b210 MN |
180 | void flush_vsx_to_thread(struct task_struct *tsk) |
181 | { | |
182 | if (tsk->thread.regs) { | |
183 | preempt_disable(); | |
184 | if (tsk->thread.regs->msr & MSR_VSX) { | |
185 | #ifdef CONFIG_SMP | |
186 | BUG_ON(tsk != current); | |
187 | #endif | |
188 | giveup_vsx(tsk); | |
189 | } | |
190 | preempt_enable(); | |
191 | } | |
192 | } | |
de56a948 | 193 | EXPORT_SYMBOL_GPL(flush_vsx_to_thread); |
ce48b210 MN |
194 | #endif /* CONFIG_VSX */ |
195 | ||
14cf11af PM |
196 | #ifdef CONFIG_SPE |
197 | ||
198 | void enable_kernel_spe(void) | |
199 | { | |
200 | WARN_ON(preemptible()); | |
201 | ||
202 | #ifdef CONFIG_SMP | |
203 | if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) | |
204 | giveup_spe(current); | |
205 | else | |
206 | giveup_spe(NULL); /* just enable SPE for kernel - force */ | |
207 | #else | |
208 | giveup_spe(last_task_used_spe); | |
209 | #endif /* __SMP __ */ | |
210 | } | |
211 | EXPORT_SYMBOL(enable_kernel_spe); | |
212 | ||
213 | void flush_spe_to_thread(struct task_struct *tsk) | |
214 | { | |
215 | if (tsk->thread.regs) { | |
216 | preempt_disable(); | |
217 | if (tsk->thread.regs->msr & MSR_SPE) { | |
218 | #ifdef CONFIG_SMP | |
219 | BUG_ON(tsk != current); | |
220 | #endif | |
685659ee | 221 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); |
0ee6c15e | 222 | giveup_spe(tsk); |
14cf11af PM |
223 | } |
224 | preempt_enable(); | |
225 | } | |
226 | } | |
14cf11af PM |
227 | #endif /* CONFIG_SPE */ |
228 | ||
5388fb10 | 229 | #ifndef CONFIG_SMP |
48abec07 PM |
230 | /* |
231 | * If we are doing lazy switching of CPU state (FP, altivec or SPE), | |
232 | * and the current task has some state, discard it. | |
233 | */ | |
5388fb10 | 234 | void discard_lazy_cpu_state(void) |
48abec07 | 235 | { |
48abec07 PM |
236 | preempt_disable(); |
237 | if (last_task_used_math == current) | |
238 | last_task_used_math = NULL; | |
239 | #ifdef CONFIG_ALTIVEC | |
240 | if (last_task_used_altivec == current) | |
241 | last_task_used_altivec = NULL; | |
242 | #endif /* CONFIG_ALTIVEC */ | |
ce48b210 MN |
243 | #ifdef CONFIG_VSX |
244 | if (last_task_used_vsx == current) | |
245 | last_task_used_vsx = NULL; | |
246 | #endif /* CONFIG_VSX */ | |
48abec07 PM |
247 | #ifdef CONFIG_SPE |
248 | if (last_task_used_spe == current) | |
249 | last_task_used_spe = NULL; | |
250 | #endif | |
251 | preempt_enable(); | |
48abec07 | 252 | } |
5388fb10 | 253 | #endif /* CONFIG_SMP */ |
48abec07 | 254 | |
3bffb652 DK |
255 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
256 | void do_send_trap(struct pt_regs *regs, unsigned long address, | |
257 | unsigned long error_code, int signal_code, int breakpt) | |
258 | { | |
259 | siginfo_t info; | |
260 | ||
41ab5266 | 261 | current->thread.trap_nr = signal_code; |
3bffb652 DK |
262 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
263 | 11, SIGSEGV) == NOTIFY_STOP) | |
264 | return; | |
265 | ||
266 | /* Deliver the signal to userspace */ | |
267 | info.si_signo = SIGTRAP; | |
268 | info.si_errno = breakpt; /* breakpoint or watchpoint id */ | |
269 | info.si_code = signal_code; | |
270 | info.si_addr = (void __user *)address; | |
271 | force_sig_info(SIGTRAP, &info, current); | |
272 | } | |
273 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
9422de3e | 274 | void do_break (struct pt_regs *regs, unsigned long address, |
d6a61bfc LM |
275 | unsigned long error_code) |
276 | { | |
277 | siginfo_t info; | |
278 | ||
41ab5266 | 279 | current->thread.trap_nr = TRAP_HWBKPT; |
d6a61bfc LM |
280 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
281 | 11, SIGSEGV) == NOTIFY_STOP) | |
282 | return; | |
283 | ||
9422de3e | 284 | if (debugger_break_match(regs)) |
d6a61bfc LM |
285 | return; |
286 | ||
9422de3e MN |
287 | /* Clear the breakpoint */ |
288 | hw_breakpoint_disable(); | |
d6a61bfc LM |
289 | |
290 | /* Deliver the signal to userspace */ | |
291 | info.si_signo = SIGTRAP; | |
292 | info.si_errno = 0; | |
293 | info.si_code = TRAP_HWBKPT; | |
294 | info.si_addr = (void __user *)address; | |
295 | force_sig_info(SIGTRAP, &info, current); | |
296 | } | |
3bffb652 | 297 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc | 298 | |
9422de3e | 299 | static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); |
a2ceff5e | 300 | |
3bffb652 DK |
301 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
302 | /* | |
303 | * Set the debug registers back to their default "safe" values. | |
304 | */ | |
305 | static void set_debug_reg_defaults(struct thread_struct *thread) | |
306 | { | |
307 | thread->iac1 = thread->iac2 = 0; | |
308 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
309 | thread->iac3 = thread->iac4 = 0; | |
310 | #endif | |
311 | thread->dac1 = thread->dac2 = 0; | |
312 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
313 | thread->dvc1 = thread->dvc2 = 0; | |
314 | #endif | |
315 | thread->dbcr0 = 0; | |
316 | #ifdef CONFIG_BOOKE | |
317 | /* | |
318 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | |
319 | */ | |
320 | thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \ | |
321 | DBCR1_IAC3US | DBCR1_IAC4US; | |
322 | /* | |
323 | * Force Data Address Compare User/Supervisor bits to be User-only | |
324 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | |
325 | */ | |
326 | thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; | |
327 | #else | |
328 | thread->dbcr1 = 0; | |
329 | #endif | |
330 | } | |
331 | ||
332 | static void prime_debug_regs(struct thread_struct *thread) | |
333 | { | |
334 | mtspr(SPRN_IAC1, thread->iac1); | |
335 | mtspr(SPRN_IAC2, thread->iac2); | |
336 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
337 | mtspr(SPRN_IAC3, thread->iac3); | |
338 | mtspr(SPRN_IAC4, thread->iac4); | |
339 | #endif | |
340 | mtspr(SPRN_DAC1, thread->dac1); | |
341 | mtspr(SPRN_DAC2, thread->dac2); | |
342 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
343 | mtspr(SPRN_DVC1, thread->dvc1); | |
344 | mtspr(SPRN_DVC2, thread->dvc2); | |
345 | #endif | |
346 | mtspr(SPRN_DBCR0, thread->dbcr0); | |
347 | mtspr(SPRN_DBCR1, thread->dbcr1); | |
348 | #ifdef CONFIG_BOOKE | |
349 | mtspr(SPRN_DBCR2, thread->dbcr2); | |
350 | #endif | |
351 | } | |
352 | /* | |
353 | * Unless neither the old or new thread are making use of the | |
354 | * debug registers, set the debug registers from the values | |
355 | * stored in the new thread. | |
356 | */ | |
357 | static void switch_booke_debug_regs(struct thread_struct *new_thread) | |
358 | { | |
359 | if ((current->thread.dbcr0 & DBCR0_IDM) | |
360 | || (new_thread->dbcr0 & DBCR0_IDM)) | |
361 | prime_debug_regs(new_thread); | |
362 | } | |
363 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
e0780b72 | 364 | #ifndef CONFIG_HAVE_HW_BREAKPOINT |
3bffb652 DK |
365 | static void set_debug_reg_defaults(struct thread_struct *thread) |
366 | { | |
9422de3e MN |
367 | thread->hw_brk.address = 0; |
368 | thread->hw_brk.type = 0; | |
369 | set_break(&thread->hw_brk); | |
3bffb652 | 370 | } |
e0780b72 | 371 | #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 DK |
372 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
373 | ||
172ae2e7 | 374 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e MN |
375 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
376 | { | |
d6a61bfc | 377 | mtspr(SPRN_DAC1, dabr); |
221c185d DK |
378 | #ifdef CONFIG_PPC_47x |
379 | isync(); | |
380 | #endif | |
9422de3e MN |
381 | return 0; |
382 | } | |
c6c9eace | 383 | #elif defined(CONFIG_PPC_BOOK3S) |
9422de3e MN |
384 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
385 | { | |
c6c9eace | 386 | mtspr(SPRN_DABR, dabr); |
4474ef05 | 387 | mtspr(SPRN_DABRX, dabrx); |
cab0af98 | 388 | return 0; |
14cf11af | 389 | } |
9422de3e MN |
390 | #else |
391 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | |
392 | { | |
393 | return -EINVAL; | |
394 | } | |
395 | #endif | |
396 | ||
397 | static inline int set_dabr(struct arch_hw_breakpoint *brk) | |
398 | { | |
399 | unsigned long dabr, dabrx; | |
400 | ||
401 | dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); | |
402 | dabrx = ((brk->type >> 3) & 0x7); | |
403 | ||
404 | if (ppc_md.set_dabr) | |
405 | return ppc_md.set_dabr(dabr, dabrx); | |
406 | ||
407 | return __set_dabr(dabr, dabrx); | |
408 | } | |
409 | ||
410 | int set_break(struct arch_hw_breakpoint *brk) | |
411 | { | |
412 | __get_cpu_var(current_brk) = *brk; | |
413 | ||
414 | return set_dabr(brk); | |
415 | } | |
14cf11af | 416 | |
06d67d54 PM |
417 | #ifdef CONFIG_PPC64 |
418 | DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); | |
06d67d54 | 419 | #endif |
14cf11af | 420 | |
9422de3e MN |
421 | static inline bool hw_brk_match(struct arch_hw_breakpoint *a, |
422 | struct arch_hw_breakpoint *b) | |
423 | { | |
424 | if (a->address != b->address) | |
425 | return false; | |
426 | if (a->type != b->type) | |
427 | return false; | |
428 | if (a->len != b->len) | |
429 | return false; | |
430 | return true; | |
431 | } | |
432 | ||
14cf11af PM |
433 | struct task_struct *__switch_to(struct task_struct *prev, |
434 | struct task_struct *new) | |
435 | { | |
436 | struct thread_struct *new_thread, *old_thread; | |
437 | unsigned long flags; | |
438 | struct task_struct *last; | |
d6bf29b4 PZ |
439 | #ifdef CONFIG_PPC_BOOK3S_64 |
440 | struct ppc64_tlb_batch *batch; | |
441 | #endif | |
14cf11af PM |
442 | |
443 | #ifdef CONFIG_SMP | |
444 | /* avoid complexity of lazy save/restore of fpu | |
445 | * by just saving it every time we switch out if | |
446 | * this task used the fpu during the last quantum. | |
447 | * | |
448 | * If it tries to use the fpu again, it'll trap and | |
449 | * reload its fp regs. So we don't have to do a restore | |
450 | * every switch, just a save. | |
451 | * -- Cort | |
452 | */ | |
453 | if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP)) | |
454 | giveup_fpu(prev); | |
455 | #ifdef CONFIG_ALTIVEC | |
456 | /* | |
457 | * If the previous thread used altivec in the last quantum | |
458 | * (thus changing altivec regs) then save them. | |
459 | * We used to check the VRSAVE register but not all apps | |
460 | * set it, so we don't rely on it now (and in fact we need | |
461 | * to save & restore VSCR even if VRSAVE == 0). -- paulus | |
462 | * | |
463 | * On SMP we always save/restore altivec regs just to avoid the | |
464 | * complexity of changing processors. | |
465 | * -- Cort | |
466 | */ | |
467 | if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC)) | |
468 | giveup_altivec(prev); | |
14cf11af | 469 | #endif /* CONFIG_ALTIVEC */ |
ce48b210 MN |
470 | #ifdef CONFIG_VSX |
471 | if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX)) | |
7c292170 MN |
472 | /* VMX and FPU registers are already save here */ |
473 | __giveup_vsx(prev); | |
ce48b210 | 474 | #endif /* CONFIG_VSX */ |
14cf11af PM |
475 | #ifdef CONFIG_SPE |
476 | /* | |
477 | * If the previous thread used spe in the last quantum | |
478 | * (thus changing spe regs) then save them. | |
479 | * | |
480 | * On SMP we always save/restore spe regs just to avoid the | |
481 | * complexity of changing processors. | |
482 | */ | |
483 | if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE))) | |
484 | giveup_spe(prev); | |
c0c0d996 PM |
485 | #endif /* CONFIG_SPE */ |
486 | ||
487 | #else /* CONFIG_SMP */ | |
488 | #ifdef CONFIG_ALTIVEC | |
489 | /* Avoid the trap. On smp this this never happens since | |
490 | * we don't set last_task_used_altivec -- Cort | |
491 | */ | |
492 | if (new->thread.regs && last_task_used_altivec == new) | |
493 | new->thread.regs->msr |= MSR_VEC; | |
494 | #endif /* CONFIG_ALTIVEC */ | |
ce48b210 MN |
495 | #ifdef CONFIG_VSX |
496 | if (new->thread.regs && last_task_used_vsx == new) | |
497 | new->thread.regs->msr |= MSR_VSX; | |
498 | #endif /* CONFIG_VSX */ | |
c0c0d996 | 499 | #ifdef CONFIG_SPE |
14cf11af PM |
500 | /* Avoid the trap. On smp this this never happens since |
501 | * we don't set last_task_used_spe | |
502 | */ | |
503 | if (new->thread.regs && last_task_used_spe == new) | |
504 | new->thread.regs->msr |= MSR_SPE; | |
505 | #endif /* CONFIG_SPE */ | |
c0c0d996 | 506 | |
14cf11af PM |
507 | #endif /* CONFIG_SMP */ |
508 | ||
172ae2e7 | 509 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 | 510 | switch_booke_debug_regs(&new->thread); |
c6c9eace | 511 | #else |
5aae8a53 P |
512 | /* |
513 | * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would | |
514 | * schedule DABR | |
515 | */ | |
516 | #ifndef CONFIG_HAVE_HW_BREAKPOINT | |
9422de3e MN |
517 | if (unlikely(hw_brk_match(&__get_cpu_var(current_brk), &new->thread.hw_brk))) |
518 | set_break(&new->thread.hw_brk); | |
5aae8a53 | 519 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
d6a61bfc LM |
520 | #endif |
521 | ||
c6c9eace | 522 | |
14cf11af PM |
523 | new_thread = &new->thread; |
524 | old_thread = ¤t->thread; | |
06d67d54 PM |
525 | |
526 | #ifdef CONFIG_PPC64 | |
527 | /* | |
528 | * Collect processor utilization data per process | |
529 | */ | |
530 | if (firmware_has_feature(FW_FEATURE_SPLPAR)) { | |
531 | struct cpu_usage *cu = &__get_cpu_var(cpu_usage_array); | |
532 | long unsigned start_tb, current_tb; | |
533 | start_tb = old_thread->start_tb; | |
534 | cu->current_tb = current_tb = mfspr(SPRN_PURR); | |
535 | old_thread->accum_tb += (current_tb - start_tb); | |
536 | new_thread->start_tb = current_tb; | |
537 | } | |
d6bf29b4 PZ |
538 | #endif /* CONFIG_PPC64 */ |
539 | ||
540 | #ifdef CONFIG_PPC_BOOK3S_64 | |
541 | batch = &__get_cpu_var(ppc64_tlb_batch); | |
542 | if (batch->active) { | |
543 | current_thread_info()->local_flags |= _TLF_LAZY_MMU; | |
544 | if (batch->index) | |
545 | __flush_tlb_pending(batch); | |
546 | batch->active = 0; | |
547 | } | |
548 | #endif /* CONFIG_PPC_BOOK3S_64 */ | |
06d67d54 | 549 | |
14cf11af | 550 | local_irq_save(flags); |
c6622f63 | 551 | |
44387e9f AB |
552 | /* |
553 | * We can't take a PMU exception inside _switch() since there is a | |
554 | * window where the kernel stack SLB and the kernel stack are out | |
555 | * of sync. Hard disable here. | |
556 | */ | |
557 | hard_irq_disable(); | |
14cf11af PM |
558 | last = _switch(old_thread, new_thread); |
559 | ||
d6bf29b4 PZ |
560 | #ifdef CONFIG_PPC_BOOK3S_64 |
561 | if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { | |
562 | current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; | |
563 | batch = &__get_cpu_var(ppc64_tlb_batch); | |
564 | batch->active = 1; | |
565 | } | |
566 | #endif /* CONFIG_PPC_BOOK3S_64 */ | |
567 | ||
14cf11af PM |
568 | local_irq_restore(flags); |
569 | ||
570 | return last; | |
571 | } | |
572 | ||
06d67d54 PM |
573 | static int instructions_to_print = 16; |
574 | ||
06d67d54 PM |
575 | static void show_instructions(struct pt_regs *regs) |
576 | { | |
577 | int i; | |
578 | unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * | |
579 | sizeof(int)); | |
580 | ||
581 | printk("Instruction dump:"); | |
582 | ||
583 | for (i = 0; i < instructions_to_print; i++) { | |
584 | int instr; | |
585 | ||
586 | if (!(i % 8)) | |
587 | printk("\n"); | |
588 | ||
0de2d820 SW |
589 | #if !defined(CONFIG_BOOKE) |
590 | /* If executing with the IMMU off, adjust pc rather | |
591 | * than print XXXXXXXX. | |
592 | */ | |
593 | if (!(regs->msr & MSR_IR)) | |
594 | pc = (unsigned long)phys_to_virt(pc); | |
595 | #endif | |
596 | ||
af308377 SR |
597 | /* We use __get_user here *only* to avoid an OOPS on a |
598 | * bad address because the pc *should* only be a | |
599 | * kernel address. | |
600 | */ | |
00ae36de AB |
601 | if (!__kernel_text_address(pc) || |
602 | __get_user(instr, (unsigned int __user *)pc)) { | |
40c8cefa | 603 | printk(KERN_CONT "XXXXXXXX "); |
06d67d54 PM |
604 | } else { |
605 | if (regs->nip == pc) | |
40c8cefa | 606 | printk(KERN_CONT "<%08x> ", instr); |
06d67d54 | 607 | else |
40c8cefa | 608 | printk(KERN_CONT "%08x ", instr); |
06d67d54 PM |
609 | } |
610 | ||
611 | pc += sizeof(int); | |
612 | } | |
613 | ||
614 | printk("\n"); | |
615 | } | |
616 | ||
617 | static struct regbit { | |
618 | unsigned long bit; | |
619 | const char *name; | |
620 | } msr_bits[] = { | |
3bfd0c9c AB |
621 | #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) |
622 | {MSR_SF, "SF"}, | |
623 | {MSR_HV, "HV"}, | |
624 | #endif | |
625 | {MSR_VEC, "VEC"}, | |
626 | {MSR_VSX, "VSX"}, | |
627 | #ifdef CONFIG_BOOKE | |
628 | {MSR_CE, "CE"}, | |
629 | #endif | |
06d67d54 PM |
630 | {MSR_EE, "EE"}, |
631 | {MSR_PR, "PR"}, | |
632 | {MSR_FP, "FP"}, | |
633 | {MSR_ME, "ME"}, | |
3bfd0c9c | 634 | #ifdef CONFIG_BOOKE |
1b98326b | 635 | {MSR_DE, "DE"}, |
3bfd0c9c AB |
636 | #else |
637 | {MSR_SE, "SE"}, | |
638 | {MSR_BE, "BE"}, | |
639 | #endif | |
06d67d54 PM |
640 | {MSR_IR, "IR"}, |
641 | {MSR_DR, "DR"}, | |
3bfd0c9c AB |
642 | {MSR_PMM, "PMM"}, |
643 | #ifndef CONFIG_BOOKE | |
644 | {MSR_RI, "RI"}, | |
645 | {MSR_LE, "LE"}, | |
646 | #endif | |
06d67d54 PM |
647 | {0, NULL} |
648 | }; | |
649 | ||
650 | static void printbits(unsigned long val, struct regbit *bits) | |
651 | { | |
652 | const char *sep = ""; | |
653 | ||
654 | printk("<"); | |
655 | for (; bits->bit; ++bits) | |
656 | if (val & bits->bit) { | |
657 | printk("%s%s", sep, bits->name); | |
658 | sep = ","; | |
659 | } | |
660 | printk(">"); | |
661 | } | |
662 | ||
663 | #ifdef CONFIG_PPC64 | |
f6f7dde3 | 664 | #define REG "%016lx" |
06d67d54 PM |
665 | #define REGS_PER_LINE 4 |
666 | #define LAST_VOLATILE 13 | |
667 | #else | |
f6f7dde3 | 668 | #define REG "%08lx" |
06d67d54 PM |
669 | #define REGS_PER_LINE 8 |
670 | #define LAST_VOLATILE 12 | |
671 | #endif | |
672 | ||
14cf11af PM |
673 | void show_regs(struct pt_regs * regs) |
674 | { | |
675 | int i, trap; | |
676 | ||
06d67d54 PM |
677 | printk("NIP: "REG" LR: "REG" CTR: "REG"\n", |
678 | regs->nip, regs->link, regs->ctr); | |
679 | printk("REGS: %p TRAP: %04lx %s (%s)\n", | |
96b644bd | 680 | regs, regs->trap, print_tainted(), init_utsname()->release); |
06d67d54 PM |
681 | printk("MSR: "REG" ", regs->msr); |
682 | printbits(regs->msr, msr_bits); | |
f6f7dde3 | 683 | printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); |
7230c564 BH |
684 | #ifdef CONFIG_PPC64 |
685 | printk("SOFTE: %ld\n", regs->softe); | |
686 | #endif | |
14cf11af | 687 | trap = TRAP(regs); |
5115a026 MN |
688 | if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) |
689 | printk("CFAR: "REG"\n", regs->orig_gpr3); | |
14cf11af | 690 | if (trap == 0x300 || trap == 0x600) |
ba28c9aa | 691 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
14170789 KG |
692 | printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr); |
693 | #else | |
7071854b | 694 | printk("DAR: "REG", DSISR: %08lx\n", regs->dar, regs->dsisr); |
14170789 | 695 | #endif |
06d67d54 | 696 | printk("TASK = %p[%d] '%s' THREAD: %p", |
19c5870c | 697 | current, task_pid_nr(current), current->comm, task_thread_info(current)); |
14cf11af PM |
698 | |
699 | #ifdef CONFIG_SMP | |
79ccd1be | 700 | printk(" CPU: %d", raw_smp_processor_id()); |
14cf11af PM |
701 | #endif /* CONFIG_SMP */ |
702 | ||
703 | for (i = 0; i < 32; i++) { | |
06d67d54 | 704 | if ((i % REGS_PER_LINE) == 0) |
a2367194 | 705 | printk("\nGPR%02d: ", i); |
06d67d54 PM |
706 | printk(REG " ", regs->gpr[i]); |
707 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) | |
14cf11af PM |
708 | break; |
709 | } | |
710 | printk("\n"); | |
711 | #ifdef CONFIG_KALLSYMS | |
712 | /* | |
713 | * Lookup NIP late so we have the best change of getting the | |
714 | * above info out without failing | |
715 | */ | |
058c78f4 BH |
716 | printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); |
717 | printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); | |
14cf11af PM |
718 | #endif |
719 | show_stack(current, (unsigned long *) regs->gpr[1]); | |
06d67d54 PM |
720 | if (!user_mode(regs)) |
721 | show_instructions(regs); | |
14cf11af PM |
722 | } |
723 | ||
724 | void exit_thread(void) | |
725 | { | |
48abec07 | 726 | discard_lazy_cpu_state(); |
14cf11af PM |
727 | } |
728 | ||
729 | void flush_thread(void) | |
730 | { | |
48abec07 | 731 | discard_lazy_cpu_state(); |
14cf11af | 732 | |
e0780b72 | 733 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
5aae8a53 | 734 | flush_ptrace_hw_breakpoint(current); |
e0780b72 | 735 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 736 | set_debug_reg_defaults(¤t->thread); |
e0780b72 | 737 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
14cf11af PM |
738 | } |
739 | ||
740 | void | |
741 | release_thread(struct task_struct *t) | |
742 | { | |
743 | } | |
744 | ||
745 | /* | |
55ccf3fe SS |
746 | * this gets called so that we can store coprocessor state into memory and |
747 | * copy the current task into the new thread. | |
14cf11af | 748 | */ |
55ccf3fe | 749 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
14cf11af | 750 | { |
55ccf3fe SS |
751 | flush_fp_to_thread(src); |
752 | flush_altivec_to_thread(src); | |
753 | flush_vsx_to_thread(src); | |
754 | flush_spe_to_thread(src); | |
5aae8a53 | 755 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
55ccf3fe | 756 | flush_ptrace_hw_breakpoint(src); |
5aae8a53 | 757 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
55ccf3fe SS |
758 | |
759 | *dst = *src; | |
760 | return 0; | |
14cf11af PM |
761 | } |
762 | ||
763 | /* | |
764 | * Copy a thread.. | |
765 | */ | |
efcac658 AK |
766 | extern unsigned long dscr_default; /* defined in arch/powerpc/kernel/sysfs.c */ |
767 | ||
6f2c55b8 | 768 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
afa86fc4 | 769 | unsigned long arg, struct task_struct *p) |
14cf11af PM |
770 | { |
771 | struct pt_regs *childregs, *kregs; | |
772 | extern void ret_from_fork(void); | |
58254e10 AV |
773 | extern void ret_from_kernel_thread(void); |
774 | void (*f)(void); | |
0cec6fd1 | 775 | unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
14cf11af | 776 | |
14cf11af PM |
777 | /* Copy registers */ |
778 | sp -= sizeof(struct pt_regs); | |
779 | childregs = (struct pt_regs *) sp; | |
ab75819d | 780 | if (unlikely(p->flags & PF_KTHREAD)) { |
138d1ce8 | 781 | struct thread_info *ti = (void *)task_stack_page(p); |
58254e10 | 782 | memset(childregs, 0, sizeof(struct pt_regs)); |
14cf11af | 783 | childregs->gpr[1] = sp + sizeof(struct pt_regs); |
53b50f94 | 784 | childregs->gpr[14] = usp; /* function */ |
58254e10 | 785 | #ifdef CONFIG_PPC64 |
b5e2fc1c | 786 | clear_tsk_thread_flag(p, TIF_32BIT); |
138d1ce8 | 787 | childregs->softe = 1; |
06d67d54 | 788 | #endif |
58254e10 | 789 | childregs->gpr[15] = arg; |
14cf11af | 790 | p->thread.regs = NULL; /* no user register state */ |
138d1ce8 | 791 | ti->flags |= _TIF_RESTOREALL; |
58254e10 | 792 | f = ret_from_kernel_thread; |
14cf11af | 793 | } else { |
afa86fc4 | 794 | struct pt_regs *regs = current_pt_regs(); |
58254e10 AV |
795 | CHECK_FULL_REGS(regs); |
796 | *childregs = *regs; | |
ea516b11 AV |
797 | if (usp) |
798 | childregs->gpr[1] = usp; | |
14cf11af | 799 | p->thread.regs = childregs; |
58254e10 | 800 | childregs->gpr[3] = 0; /* Result from fork() */ |
06d67d54 PM |
801 | if (clone_flags & CLONE_SETTLS) { |
802 | #ifdef CONFIG_PPC64 | |
9904b005 | 803 | if (!is_32bit_task()) |
06d67d54 PM |
804 | childregs->gpr[13] = childregs->gpr[6]; |
805 | else | |
806 | #endif | |
807 | childregs->gpr[2] = childregs->gpr[6]; | |
808 | } | |
58254e10 AV |
809 | |
810 | f = ret_from_fork; | |
14cf11af | 811 | } |
14cf11af | 812 | sp -= STACK_FRAME_OVERHEAD; |
14cf11af PM |
813 | |
814 | /* | |
815 | * The way this works is that at some point in the future | |
816 | * some task will call _switch to switch to the new task. | |
817 | * That will pop off the stack frame created below and start | |
818 | * the new task running at ret_from_fork. The new task will | |
819 | * do some house keeping and then return from the fork or clone | |
820 | * system call, using the stack frame created above. | |
821 | */ | |
822 | sp -= sizeof(struct pt_regs); | |
823 | kregs = (struct pt_regs *) sp; | |
824 | sp -= STACK_FRAME_OVERHEAD; | |
825 | p->thread.ksp = sp; | |
85218827 KG |
826 | p->thread.ksp_limit = (unsigned long)task_stack_page(p) + |
827 | _ALIGN_UP(sizeof(struct thread_info), 16); | |
14cf11af | 828 | |
94491685 | 829 | #ifdef CONFIG_PPC_STD_MMU_64 |
44ae3ab3 | 830 | if (mmu_has_feature(MMU_FTR_SLB)) { |
1189be65 | 831 | unsigned long sp_vsid; |
3c726f8d | 832 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; |
06d67d54 | 833 | |
44ae3ab3 | 834 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) |
1189be65 PM |
835 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) |
836 | << SLB_VSID_SHIFT_1T; | |
837 | else | |
838 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) | |
839 | << SLB_VSID_SHIFT; | |
3c726f8d | 840 | sp_vsid |= SLB_VSID_KERNEL | llp; |
06d67d54 PM |
841 | p->thread.ksp_vsid = sp_vsid; |
842 | } | |
747bea91 | 843 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
efcac658 AK |
844 | #ifdef CONFIG_PPC64 |
845 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1021cb26 AB |
846 | p->thread.dscr_inherit = current->thread.dscr_inherit; |
847 | p->thread.dscr = current->thread.dscr; | |
efcac658 | 848 | } |
92779245 HM |
849 | if (cpu_has_feature(CPU_FTR_HAS_PPR)) |
850 | p->thread.ppr = INIT_PPR; | |
efcac658 | 851 | #endif |
06d67d54 PM |
852 | /* |
853 | * The PPC64 ABI makes use of a TOC to contain function | |
854 | * pointers. The function (ret_from_except) is actually a pointer | |
855 | * to the TOC entry. The first entry is a pointer to the actual | |
856 | * function. | |
58254e10 | 857 | */ |
747bea91 | 858 | #ifdef CONFIG_PPC64 |
58254e10 | 859 | kregs->nip = *((unsigned long *)f); |
06d67d54 | 860 | #else |
58254e10 | 861 | kregs->nip = (unsigned long)f; |
06d67d54 | 862 | #endif |
14cf11af PM |
863 | return 0; |
864 | } | |
865 | ||
866 | /* | |
867 | * Set up a thread for executing a new program | |
868 | */ | |
06d67d54 | 869 | void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) |
14cf11af | 870 | { |
90eac727 ME |
871 | #ifdef CONFIG_PPC64 |
872 | unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ | |
873 | #endif | |
874 | ||
06d67d54 PM |
875 | /* |
876 | * If we exec out of a kernel thread then thread.regs will not be | |
877 | * set. Do it now. | |
878 | */ | |
879 | if (!current->thread.regs) { | |
0cec6fd1 AV |
880 | struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; |
881 | current->thread.regs = regs - 1; | |
06d67d54 PM |
882 | } |
883 | ||
14cf11af PM |
884 | memset(regs->gpr, 0, sizeof(regs->gpr)); |
885 | regs->ctr = 0; | |
886 | regs->link = 0; | |
887 | regs->xer = 0; | |
888 | regs->ccr = 0; | |
14cf11af | 889 | regs->gpr[1] = sp; |
06d67d54 | 890 | |
474f8196 RM |
891 | /* |
892 | * We have just cleared all the nonvolatile GPRs, so make | |
893 | * FULL_REGS(regs) return true. This is necessary to allow | |
894 | * ptrace to examine the thread immediately after exec. | |
895 | */ | |
896 | regs->trap &= ~1UL; | |
897 | ||
06d67d54 PM |
898 | #ifdef CONFIG_PPC32 |
899 | regs->mq = 0; | |
900 | regs->nip = start; | |
14cf11af | 901 | regs->msr = MSR_USER; |
06d67d54 | 902 | #else |
9904b005 | 903 | if (!is_32bit_task()) { |
90eac727 | 904 | unsigned long entry, toc; |
06d67d54 PM |
905 | |
906 | /* start is a relocated pointer to the function descriptor for | |
907 | * the elf _start routine. The first entry in the function | |
908 | * descriptor is the entry address of _start and the second | |
909 | * entry is the TOC value we need to use. | |
910 | */ | |
911 | __get_user(entry, (unsigned long __user *)start); | |
912 | __get_user(toc, (unsigned long __user *)start+1); | |
913 | ||
914 | /* Check whether the e_entry function descriptor entries | |
915 | * need to be relocated before we can use them. | |
916 | */ | |
917 | if (load_addr != 0) { | |
918 | entry += load_addr; | |
919 | toc += load_addr; | |
920 | } | |
921 | regs->nip = entry; | |
922 | regs->gpr[2] = toc; | |
923 | regs->msr = MSR_USER64; | |
d4bf9a78 SR |
924 | } else { |
925 | regs->nip = start; | |
926 | regs->gpr[2] = 0; | |
927 | regs->msr = MSR_USER32; | |
06d67d54 PM |
928 | } |
929 | #endif | |
930 | ||
48abec07 | 931 | discard_lazy_cpu_state(); |
ce48b210 MN |
932 | #ifdef CONFIG_VSX |
933 | current->thread.used_vsr = 0; | |
934 | #endif | |
14cf11af | 935 | memset(current->thread.fpr, 0, sizeof(current->thread.fpr)); |
25c8a78b | 936 | current->thread.fpscr.val = 0; |
14cf11af PM |
937 | #ifdef CONFIG_ALTIVEC |
938 | memset(current->thread.vr, 0, sizeof(current->thread.vr)); | |
939 | memset(¤t->thread.vscr, 0, sizeof(current->thread.vscr)); | |
06d67d54 | 940 | current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */ |
14cf11af PM |
941 | current->thread.vrsave = 0; |
942 | current->thread.used_vr = 0; | |
943 | #endif /* CONFIG_ALTIVEC */ | |
944 | #ifdef CONFIG_SPE | |
945 | memset(current->thread.evr, 0, sizeof(current->thread.evr)); | |
946 | current->thread.acc = 0; | |
947 | current->thread.spefscr = 0; | |
948 | current->thread.used_spe = 0; | |
949 | #endif /* CONFIG_SPE */ | |
950 | } | |
951 | ||
952 | #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ | |
953 | | PR_FP_EXC_RES | PR_FP_EXC_INV) | |
954 | ||
955 | int set_fpexc_mode(struct task_struct *tsk, unsigned int val) | |
956 | { | |
957 | struct pt_regs *regs = tsk->thread.regs; | |
958 | ||
959 | /* This is a bit hairy. If we are an SPE enabled processor | |
960 | * (have embedded fp) we store the IEEE exception enable flags in | |
961 | * fpexc_mode. fpexc_mode is also used for setting FP exception | |
962 | * mode (asyn, precise, disabled) for 'Classic' FP. */ | |
963 | if (val & PR_FP_EXC_SW_ENABLE) { | |
964 | #ifdef CONFIG_SPE | |
5e14d21e KG |
965 | if (cpu_has_feature(CPU_FTR_SPE)) { |
966 | tsk->thread.fpexc_mode = val & | |
967 | (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); | |
968 | return 0; | |
969 | } else { | |
970 | return -EINVAL; | |
971 | } | |
14cf11af PM |
972 | #else |
973 | return -EINVAL; | |
974 | #endif | |
14cf11af | 975 | } |
06d67d54 PM |
976 | |
977 | /* on a CONFIG_SPE this does not hurt us. The bits that | |
978 | * __pack_fe01 use do not overlap with bits used for | |
979 | * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits | |
980 | * on CONFIG_SPE implementations are reserved so writing to | |
981 | * them does not change anything */ | |
982 | if (val > PR_FP_EXC_PRECISE) | |
983 | return -EINVAL; | |
984 | tsk->thread.fpexc_mode = __pack_fe01(val); | |
985 | if (regs != NULL && (regs->msr & MSR_FP) != 0) | |
986 | regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) | |
987 | | tsk->thread.fpexc_mode; | |
14cf11af PM |
988 | return 0; |
989 | } | |
990 | ||
991 | int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) | |
992 | { | |
993 | unsigned int val; | |
994 | ||
995 | if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) | |
996 | #ifdef CONFIG_SPE | |
5e14d21e KG |
997 | if (cpu_has_feature(CPU_FTR_SPE)) |
998 | val = tsk->thread.fpexc_mode; | |
999 | else | |
1000 | return -EINVAL; | |
14cf11af PM |
1001 | #else |
1002 | return -EINVAL; | |
1003 | #endif | |
1004 | else | |
1005 | val = __unpack_fe01(tsk->thread.fpexc_mode); | |
1006 | return put_user(val, (unsigned int __user *) adr); | |
1007 | } | |
1008 | ||
fab5db97 PM |
1009 | int set_endian(struct task_struct *tsk, unsigned int val) |
1010 | { | |
1011 | struct pt_regs *regs = tsk->thread.regs; | |
1012 | ||
1013 | if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || | |
1014 | (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) | |
1015 | return -EINVAL; | |
1016 | ||
1017 | if (regs == NULL) | |
1018 | return -EINVAL; | |
1019 | ||
1020 | if (val == PR_ENDIAN_BIG) | |
1021 | regs->msr &= ~MSR_LE; | |
1022 | else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) | |
1023 | regs->msr |= MSR_LE; | |
1024 | else | |
1025 | return -EINVAL; | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | int get_endian(struct task_struct *tsk, unsigned long adr) | |
1031 | { | |
1032 | struct pt_regs *regs = tsk->thread.regs; | |
1033 | unsigned int val; | |
1034 | ||
1035 | if (!cpu_has_feature(CPU_FTR_PPC_LE) && | |
1036 | !cpu_has_feature(CPU_FTR_REAL_LE)) | |
1037 | return -EINVAL; | |
1038 | ||
1039 | if (regs == NULL) | |
1040 | return -EINVAL; | |
1041 | ||
1042 | if (regs->msr & MSR_LE) { | |
1043 | if (cpu_has_feature(CPU_FTR_REAL_LE)) | |
1044 | val = PR_ENDIAN_LITTLE; | |
1045 | else | |
1046 | val = PR_ENDIAN_PPC_LITTLE; | |
1047 | } else | |
1048 | val = PR_ENDIAN_BIG; | |
1049 | ||
1050 | return put_user(val, (unsigned int __user *)adr); | |
1051 | } | |
1052 | ||
e9370ae1 PM |
1053 | int set_unalign_ctl(struct task_struct *tsk, unsigned int val) |
1054 | { | |
1055 | tsk->thread.align_ctl = val; | |
1056 | return 0; | |
1057 | } | |
1058 | ||
1059 | int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) | |
1060 | { | |
1061 | return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); | |
1062 | } | |
1063 | ||
bb72c481 PM |
1064 | static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, |
1065 | unsigned long nbytes) | |
1066 | { | |
1067 | unsigned long stack_page; | |
1068 | unsigned long cpu = task_cpu(p); | |
1069 | ||
1070 | /* | |
1071 | * Avoid crashing if the stack has overflowed and corrupted | |
1072 | * task_cpu(p), which is in the thread_info struct. | |
1073 | */ | |
1074 | if (cpu < NR_CPUS && cpu_possible(cpu)) { | |
1075 | stack_page = (unsigned long) hardirq_ctx[cpu]; | |
1076 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1077 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1078 | return 1; | |
1079 | ||
1080 | stack_page = (unsigned long) softirq_ctx[cpu]; | |
1081 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1082 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1083 | return 1; | |
1084 | } | |
1085 | return 0; | |
1086 | } | |
1087 | ||
2f25194d | 1088 | int validate_sp(unsigned long sp, struct task_struct *p, |
14cf11af PM |
1089 | unsigned long nbytes) |
1090 | { | |
0cec6fd1 | 1091 | unsigned long stack_page = (unsigned long)task_stack_page(p); |
14cf11af PM |
1092 | |
1093 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1094 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1095 | return 1; | |
1096 | ||
bb72c481 | 1097 | return valid_irq_stack(sp, p, nbytes); |
14cf11af PM |
1098 | } |
1099 | ||
2f25194d AB |
1100 | EXPORT_SYMBOL(validate_sp); |
1101 | ||
14cf11af PM |
1102 | unsigned long get_wchan(struct task_struct *p) |
1103 | { | |
1104 | unsigned long ip, sp; | |
1105 | int count = 0; | |
1106 | ||
1107 | if (!p || p == current || p->state == TASK_RUNNING) | |
1108 | return 0; | |
1109 | ||
1110 | sp = p->thread.ksp; | |
ec2b36b9 | 1111 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1112 | return 0; |
1113 | ||
1114 | do { | |
1115 | sp = *(unsigned long *)sp; | |
ec2b36b9 | 1116 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1117 | return 0; |
1118 | if (count > 0) { | |
ec2b36b9 | 1119 | ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; |
14cf11af PM |
1120 | if (!in_sched_functions(ip)) |
1121 | return ip; | |
1122 | } | |
1123 | } while (count++ < 16); | |
1124 | return 0; | |
1125 | } | |
06d67d54 | 1126 | |
c4d04be1 | 1127 | static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; |
06d67d54 PM |
1128 | |
1129 | void show_stack(struct task_struct *tsk, unsigned long *stack) | |
1130 | { | |
1131 | unsigned long sp, ip, lr, newsp; | |
1132 | int count = 0; | |
1133 | int firstframe = 1; | |
6794c782 SR |
1134 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1135 | int curr_frame = current->curr_ret_stack; | |
1136 | extern void return_to_handler(void); | |
9135c3cc SR |
1137 | unsigned long rth = (unsigned long)return_to_handler; |
1138 | unsigned long mrth = -1; | |
6794c782 | 1139 | #ifdef CONFIG_PPC64 |
9135c3cc SR |
1140 | extern void mod_return_to_handler(void); |
1141 | rth = *(unsigned long *)rth; | |
1142 | mrth = (unsigned long)mod_return_to_handler; | |
1143 | mrth = *(unsigned long *)mrth; | |
6794c782 SR |
1144 | #endif |
1145 | #endif | |
06d67d54 PM |
1146 | |
1147 | sp = (unsigned long) stack; | |
1148 | if (tsk == NULL) | |
1149 | tsk = current; | |
1150 | if (sp == 0) { | |
1151 | if (tsk == current) | |
1152 | asm("mr %0,1" : "=r" (sp)); | |
1153 | else | |
1154 | sp = tsk->thread.ksp; | |
1155 | } | |
1156 | ||
1157 | lr = 0; | |
1158 | printk("Call Trace:\n"); | |
1159 | do { | |
ec2b36b9 | 1160 | if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) |
06d67d54 PM |
1161 | return; |
1162 | ||
1163 | stack = (unsigned long *) sp; | |
1164 | newsp = stack[0]; | |
ec2b36b9 | 1165 | ip = stack[STACK_FRAME_LR_SAVE]; |
06d67d54 | 1166 | if (!firstframe || ip != lr) { |
058c78f4 | 1167 | printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); |
6794c782 | 1168 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
9135c3cc | 1169 | if ((ip == rth || ip == mrth) && curr_frame >= 0) { |
6794c782 SR |
1170 | printk(" (%pS)", |
1171 | (void *)current->ret_stack[curr_frame].ret); | |
1172 | curr_frame--; | |
1173 | } | |
1174 | #endif | |
06d67d54 PM |
1175 | if (firstframe) |
1176 | printk(" (unreliable)"); | |
1177 | printk("\n"); | |
1178 | } | |
1179 | firstframe = 0; | |
1180 | ||
1181 | /* | |
1182 | * See if this is an exception frame. | |
1183 | * We look for the "regshere" marker in the current frame. | |
1184 | */ | |
ec2b36b9 BH |
1185 | if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) |
1186 | && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { | |
06d67d54 PM |
1187 | struct pt_regs *regs = (struct pt_regs *) |
1188 | (sp + STACK_FRAME_OVERHEAD); | |
06d67d54 | 1189 | lr = regs->link; |
058c78f4 BH |
1190 | printk("--- Exception: %lx at %pS\n LR = %pS\n", |
1191 | regs->trap, (void *)regs->nip, (void *)lr); | |
06d67d54 PM |
1192 | firstframe = 1; |
1193 | } | |
1194 | ||
1195 | sp = newsp; | |
1196 | } while (count++ < kstack_depth_to_print); | |
1197 | } | |
1198 | ||
1199 | void dump_stack(void) | |
1200 | { | |
1201 | show_stack(current, NULL); | |
1202 | } | |
1203 | EXPORT_SYMBOL(dump_stack); | |
cb2c9b27 AB |
1204 | |
1205 | #ifdef CONFIG_PPC64 | |
fe1952fc BH |
1206 | /* Called with hard IRQs off */ |
1207 | void __ppc64_runlatch_on(void) | |
cb2c9b27 | 1208 | { |
fe1952fc | 1209 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1210 | unsigned long ctrl; |
1211 | ||
fe1952fc BH |
1212 | ctrl = mfspr(SPRN_CTRLF); |
1213 | ctrl |= CTRL_RUNLATCH; | |
1214 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1215 | |
fae2e0fb | 1216 | ti->local_flags |= _TLF_RUNLATCH; |
cb2c9b27 AB |
1217 | } |
1218 | ||
fe1952fc | 1219 | /* Called with hard IRQs off */ |
4138d653 | 1220 | void __ppc64_runlatch_off(void) |
cb2c9b27 | 1221 | { |
fe1952fc | 1222 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1223 | unsigned long ctrl; |
1224 | ||
fae2e0fb | 1225 | ti->local_flags &= ~_TLF_RUNLATCH; |
cb2c9b27 | 1226 | |
4138d653 AB |
1227 | ctrl = mfspr(SPRN_CTRLF); |
1228 | ctrl &= ~CTRL_RUNLATCH; | |
1229 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1230 | } |
fe1952fc | 1231 | #endif /* CONFIG_PPC64 */ |
f6a61680 | 1232 | |
d839088c AB |
1233 | unsigned long arch_align_stack(unsigned long sp) |
1234 | { | |
1235 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
1236 | sp -= get_random_int() & ~PAGE_MASK; | |
1237 | return sp & ~0xf; | |
1238 | } | |
912f9ee2 AB |
1239 | |
1240 | static inline unsigned long brk_rnd(void) | |
1241 | { | |
1242 | unsigned long rnd = 0; | |
1243 | ||
1244 | /* 8MB for 32bit, 1GB for 64bit */ | |
1245 | if (is_32bit_task()) | |
1246 | rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT))); | |
1247 | else | |
1248 | rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT))); | |
1249 | ||
1250 | return rnd << PAGE_SHIFT; | |
1251 | } | |
1252 | ||
1253 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
1254 | { | |
8bbde7a7 AB |
1255 | unsigned long base = mm->brk; |
1256 | unsigned long ret; | |
1257 | ||
ce7a35c7 | 1258 | #ifdef CONFIG_PPC_STD_MMU_64 |
8bbde7a7 AB |
1259 | /* |
1260 | * If we are using 1TB segments and we are allowed to randomise | |
1261 | * the heap, we can put it above 1TB so it is backed by a 1TB | |
1262 | * segment. Otherwise the heap will be in the bottom 1TB | |
1263 | * which always uses 256MB segments and this may result in a | |
1264 | * performance penalty. | |
1265 | */ | |
1266 | if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) | |
1267 | base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); | |
1268 | #endif | |
1269 | ||
1270 | ret = PAGE_ALIGN(base + brk_rnd()); | |
912f9ee2 AB |
1271 | |
1272 | if (ret < mm->brk) | |
1273 | return mm->brk; | |
1274 | ||
1275 | return ret; | |
1276 | } | |
501cb16d AB |
1277 | |
1278 | unsigned long randomize_et_dyn(unsigned long base) | |
1279 | { | |
1280 | unsigned long ret = PAGE_ALIGN(base + brk_rnd()); | |
1281 | ||
1282 | if (ret < base) | |
1283 | return base; | |
1284 | ||
1285 | return ret; | |
1286 | } |