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Commit | Line | Data |
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14cf11af | 1 | /* |
14cf11af PM |
2 | * Derived from "arch/i386/kernel/process.c" |
3 | * Copyright (C) 1995 Linus Torvalds | |
4 | * | |
5 | * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and | |
6 | * Paul Mackerras (paulus@cs.anu.edu.au) | |
7 | * | |
8 | * PowerPC version | |
9 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | */ | |
16 | ||
14cf11af PM |
17 | #include <linux/errno.h> |
18 | #include <linux/sched.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
14cf11af PM |
22 | #include <linux/stddef.h> |
23 | #include <linux/unistd.h> | |
24 | #include <linux/ptrace.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/user.h> | |
27 | #include <linux/elf.h> | |
14cf11af PM |
28 | #include <linux/prctl.h> |
29 | #include <linux/init_task.h> | |
4b16f8e2 | 30 | #include <linux/export.h> |
14cf11af PM |
31 | #include <linux/kallsyms.h> |
32 | #include <linux/mqueue.h> | |
33 | #include <linux/hardirq.h> | |
06d67d54 | 34 | #include <linux/utsname.h> |
6794c782 | 35 | #include <linux/ftrace.h> |
79741dd3 | 36 | #include <linux/kernel_stat.h> |
d839088c AB |
37 | #include <linux/personality.h> |
38 | #include <linux/random.h> | |
5aae8a53 | 39 | #include <linux/hw_breakpoint.h> |
7b051f66 | 40 | #include <linux/uaccess.h> |
7f92bc56 | 41 | #include <linux/elf-randomize.h> |
14cf11af PM |
42 | |
43 | #include <asm/pgtable.h> | |
14cf11af PM |
44 | #include <asm/io.h> |
45 | #include <asm/processor.h> | |
46 | #include <asm/mmu.h> | |
47 | #include <asm/prom.h> | |
76032de8 | 48 | #include <asm/machdep.h> |
c6622f63 | 49 | #include <asm/time.h> |
ae3a197e | 50 | #include <asm/runlatch.h> |
a7f31841 | 51 | #include <asm/syscalls.h> |
ae3a197e | 52 | #include <asm/switch_to.h> |
fb09692e | 53 | #include <asm/tm.h> |
ae3a197e | 54 | #include <asm/debug.h> |
06d67d54 PM |
55 | #ifdef CONFIG_PPC64 |
56 | #include <asm/firmware.h> | |
06d67d54 | 57 | #endif |
7cedd601 | 58 | #include <asm/code-patching.h> |
7f92bc56 | 59 | #include <asm/exec.h> |
5d31a96e ME |
60 | #include <asm/livepatch.h> |
61 | ||
d6a61bfc LM |
62 | #include <linux/kprobes.h> |
63 | #include <linux/kdebug.h> | |
14cf11af | 64 | |
8b3c34cf MN |
65 | /* Transactional Memory debug */ |
66 | #ifdef TM_DEBUG_SW | |
67 | #define TM_DEBUG(x...) printk(KERN_INFO x) | |
68 | #else | |
69 | #define TM_DEBUG(x...) do { } while(0) | |
70 | #endif | |
71 | ||
14cf11af PM |
72 | extern unsigned long _get_SP(void); |
73 | ||
d31626f7 | 74 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
b86fd2bd | 75 | static void check_if_tm_restore_required(struct task_struct *tsk) |
d31626f7 PM |
76 | { |
77 | /* | |
78 | * If we are saving the current thread's registers, and the | |
79 | * thread is in a transactional state, set the TIF_RESTORE_TM | |
80 | * bit so that we know to restore the registers before | |
81 | * returning to userspace. | |
82 | */ | |
83 | if (tsk == current && tsk->thread.regs && | |
84 | MSR_TM_ACTIVE(tsk->thread.regs->msr) && | |
85 | !test_thread_flag(TIF_RESTORE_TM)) { | |
829023df | 86 | tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr; |
d31626f7 PM |
87 | set_thread_flag(TIF_RESTORE_TM); |
88 | } | |
d31626f7 | 89 | } |
d31626f7 | 90 | #else |
b86fd2bd | 91 | static inline void check_if_tm_restore_required(struct task_struct *tsk) { } |
d31626f7 PM |
92 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ |
93 | ||
3eb5d588 AB |
94 | bool strict_msr_control; |
95 | EXPORT_SYMBOL(strict_msr_control); | |
96 | ||
97 | static int __init enable_strict_msr_control(char *str) | |
98 | { | |
99 | strict_msr_control = true; | |
100 | pr_info("Enabling strict facility control\n"); | |
101 | ||
102 | return 0; | |
103 | } | |
104 | early_param("ppc_strict_facility_enable", enable_strict_msr_control); | |
105 | ||
106 | void msr_check_and_set(unsigned long bits) | |
98da581e | 107 | { |
a0e72cf1 AB |
108 | unsigned long oldmsr = mfmsr(); |
109 | unsigned long newmsr; | |
98da581e | 110 | |
a0e72cf1 | 111 | newmsr = oldmsr | bits; |
98da581e | 112 | |
98da581e | 113 | #ifdef CONFIG_VSX |
a0e72cf1 | 114 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) |
98da581e AB |
115 | newmsr |= MSR_VSX; |
116 | #endif | |
a0e72cf1 | 117 | |
98da581e AB |
118 | if (oldmsr != newmsr) |
119 | mtmsr_isync(newmsr); | |
a0e72cf1 | 120 | } |
98da581e | 121 | |
3eb5d588 | 122 | void __msr_check_and_clear(unsigned long bits) |
a0e72cf1 AB |
123 | { |
124 | unsigned long oldmsr = mfmsr(); | |
125 | unsigned long newmsr; | |
126 | ||
127 | newmsr = oldmsr & ~bits; | |
128 | ||
129 | #ifdef CONFIG_VSX | |
130 | if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP)) | |
131 | newmsr &= ~MSR_VSX; | |
132 | #endif | |
133 | ||
134 | if (oldmsr != newmsr) | |
135 | mtmsr_isync(newmsr); | |
136 | } | |
3eb5d588 | 137 | EXPORT_SYMBOL(__msr_check_and_clear); |
a0e72cf1 AB |
138 | |
139 | #ifdef CONFIG_PPC_FPU | |
8792468d CB |
140 | void __giveup_fpu(struct task_struct *tsk) |
141 | { | |
142 | save_fpu(tsk); | |
143 | tsk->thread.regs->msr &= ~MSR_FP; | |
144 | #ifdef CONFIG_VSX | |
145 | if (cpu_has_feature(CPU_FTR_VSX)) | |
146 | tsk->thread.regs->msr &= ~MSR_VSX; | |
147 | #endif | |
148 | } | |
149 | ||
a0e72cf1 AB |
150 | void giveup_fpu(struct task_struct *tsk) |
151 | { | |
152 | check_if_tm_restore_required(tsk); | |
153 | ||
154 | msr_check_and_set(MSR_FP); | |
98da581e | 155 | __giveup_fpu(tsk); |
a0e72cf1 | 156 | msr_check_and_clear(MSR_FP); |
98da581e AB |
157 | } |
158 | EXPORT_SYMBOL(giveup_fpu); | |
159 | ||
14cf11af PM |
160 | /* |
161 | * Make sure the floating-point register state in the | |
162 | * the thread_struct is up to date for task tsk. | |
163 | */ | |
164 | void flush_fp_to_thread(struct task_struct *tsk) | |
165 | { | |
166 | if (tsk->thread.regs) { | |
167 | /* | |
168 | * We need to disable preemption here because if we didn't, | |
169 | * another process could get scheduled after the regs->msr | |
170 | * test but before we have finished saving the FP registers | |
171 | * to the thread_struct. That process could take over the | |
172 | * FPU, and then when we get scheduled again we would store | |
173 | * bogus values for the remaining FP registers. | |
174 | */ | |
175 | preempt_disable(); | |
176 | if (tsk->thread.regs->msr & MSR_FP) { | |
14cf11af PM |
177 | /* |
178 | * This should only ever be called for current or | |
179 | * for a stopped child process. Since we save away | |
af1bbc3d | 180 | * the FP register state on context switch, |
14cf11af PM |
181 | * there is something wrong if a stopped child appears |
182 | * to still have its FP state in the CPU registers. | |
183 | */ | |
184 | BUG_ON(tsk != current); | |
b86fd2bd | 185 | giveup_fpu(tsk); |
14cf11af PM |
186 | } |
187 | preempt_enable(); | |
188 | } | |
189 | } | |
de56a948 | 190 | EXPORT_SYMBOL_GPL(flush_fp_to_thread); |
14cf11af PM |
191 | |
192 | void enable_kernel_fp(void) | |
193 | { | |
194 | WARN_ON(preemptible()); | |
195 | ||
a0e72cf1 | 196 | msr_check_and_set(MSR_FP); |
611b0e5c | 197 | |
d64d02ce AB |
198 | if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) { |
199 | check_if_tm_restore_required(current); | |
a0e72cf1 | 200 | __giveup_fpu(current); |
d64d02ce | 201 | } |
14cf11af PM |
202 | } |
203 | EXPORT_SYMBOL(enable_kernel_fp); | |
70fe3d98 CB |
204 | |
205 | static int restore_fp(struct task_struct *tsk) { | |
206 | if (tsk->thread.load_fp) { | |
207 | load_fp_state(¤t->thread.fp_state); | |
208 | current->thread.load_fp++; | |
209 | return 1; | |
210 | } | |
211 | return 0; | |
212 | } | |
213 | #else | |
214 | static int restore_fp(struct task_struct *tsk) { return 0; } | |
d1e1cf2e | 215 | #endif /* CONFIG_PPC_FPU */ |
14cf11af | 216 | |
14cf11af | 217 | #ifdef CONFIG_ALTIVEC |
70fe3d98 CB |
218 | #define loadvec(thr) ((thr).load_vec) |
219 | ||
6f515d84 CB |
220 | static void __giveup_altivec(struct task_struct *tsk) |
221 | { | |
222 | save_altivec(tsk); | |
223 | tsk->thread.regs->msr &= ~MSR_VEC; | |
224 | #ifdef CONFIG_VSX | |
225 | if (cpu_has_feature(CPU_FTR_VSX)) | |
226 | tsk->thread.regs->msr &= ~MSR_VSX; | |
227 | #endif | |
228 | } | |
229 | ||
98da581e AB |
230 | void giveup_altivec(struct task_struct *tsk) |
231 | { | |
98da581e AB |
232 | check_if_tm_restore_required(tsk); |
233 | ||
a0e72cf1 | 234 | msr_check_and_set(MSR_VEC); |
98da581e | 235 | __giveup_altivec(tsk); |
a0e72cf1 | 236 | msr_check_and_clear(MSR_VEC); |
98da581e AB |
237 | } |
238 | EXPORT_SYMBOL(giveup_altivec); | |
239 | ||
14cf11af PM |
240 | void enable_kernel_altivec(void) |
241 | { | |
242 | WARN_ON(preemptible()); | |
243 | ||
a0e72cf1 | 244 | msr_check_and_set(MSR_VEC); |
611b0e5c | 245 | |
d64d02ce AB |
246 | if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) { |
247 | check_if_tm_restore_required(current); | |
a0e72cf1 | 248 | __giveup_altivec(current); |
d64d02ce | 249 | } |
14cf11af PM |
250 | } |
251 | EXPORT_SYMBOL(enable_kernel_altivec); | |
252 | ||
253 | /* | |
254 | * Make sure the VMX/Altivec register state in the | |
255 | * the thread_struct is up to date for task tsk. | |
256 | */ | |
257 | void flush_altivec_to_thread(struct task_struct *tsk) | |
258 | { | |
259 | if (tsk->thread.regs) { | |
260 | preempt_disable(); | |
261 | if (tsk->thread.regs->msr & MSR_VEC) { | |
14cf11af | 262 | BUG_ON(tsk != current); |
b86fd2bd | 263 | giveup_altivec(tsk); |
14cf11af PM |
264 | } |
265 | preempt_enable(); | |
266 | } | |
267 | } | |
de56a948 | 268 | EXPORT_SYMBOL_GPL(flush_altivec_to_thread); |
70fe3d98 CB |
269 | |
270 | static int restore_altivec(struct task_struct *tsk) | |
271 | { | |
272 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && tsk->thread.load_vec) { | |
273 | load_vr_state(&tsk->thread.vr_state); | |
274 | tsk->thread.used_vr = 1; | |
275 | tsk->thread.load_vec++; | |
276 | ||
277 | return 1; | |
278 | } | |
279 | return 0; | |
280 | } | |
281 | #else | |
282 | #define loadvec(thr) 0 | |
283 | static inline int restore_altivec(struct task_struct *tsk) { return 0; } | |
14cf11af PM |
284 | #endif /* CONFIG_ALTIVEC */ |
285 | ||
ce48b210 | 286 | #ifdef CONFIG_VSX |
bf6a4d5b | 287 | static void __giveup_vsx(struct task_struct *tsk) |
a7d623d4 | 288 | { |
a7d623d4 AB |
289 | if (tsk->thread.regs->msr & MSR_FP) |
290 | __giveup_fpu(tsk); | |
291 | if (tsk->thread.regs->msr & MSR_VEC) | |
292 | __giveup_altivec(tsk); | |
bf6a4d5b CB |
293 | tsk->thread.regs->msr &= ~MSR_VSX; |
294 | } | |
295 | ||
296 | static void giveup_vsx(struct task_struct *tsk) | |
297 | { | |
298 | check_if_tm_restore_required(tsk); | |
299 | ||
300 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); | |
a7d623d4 | 301 | __giveup_vsx(tsk); |
a0e72cf1 | 302 | msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX); |
a7d623d4 | 303 | } |
bf6a4d5b CB |
304 | |
305 | static void save_vsx(struct task_struct *tsk) | |
306 | { | |
307 | if (tsk->thread.regs->msr & MSR_FP) | |
308 | save_fpu(tsk); | |
309 | if (tsk->thread.regs->msr & MSR_VEC) | |
310 | save_altivec(tsk); | |
311 | } | |
a7d623d4 | 312 | |
ce48b210 MN |
313 | void enable_kernel_vsx(void) |
314 | { | |
315 | WARN_ON(preemptible()); | |
316 | ||
a0e72cf1 | 317 | msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX); |
611b0e5c | 318 | |
a0e72cf1 | 319 | if (current->thread.regs && (current->thread.regs->msr & MSR_VSX)) { |
d64d02ce | 320 | check_if_tm_restore_required(current); |
a0e72cf1 AB |
321 | if (current->thread.regs->msr & MSR_FP) |
322 | __giveup_fpu(current); | |
323 | if (current->thread.regs->msr & MSR_VEC) | |
324 | __giveup_altivec(current); | |
325 | __giveup_vsx(current); | |
611b0e5c | 326 | } |
ce48b210 MN |
327 | } |
328 | EXPORT_SYMBOL(enable_kernel_vsx); | |
ce48b210 MN |
329 | |
330 | void flush_vsx_to_thread(struct task_struct *tsk) | |
331 | { | |
332 | if (tsk->thread.regs) { | |
333 | preempt_disable(); | |
334 | if (tsk->thread.regs->msr & MSR_VSX) { | |
ce48b210 | 335 | BUG_ON(tsk != current); |
ce48b210 MN |
336 | giveup_vsx(tsk); |
337 | } | |
338 | preempt_enable(); | |
339 | } | |
340 | } | |
de56a948 | 341 | EXPORT_SYMBOL_GPL(flush_vsx_to_thread); |
70fe3d98 CB |
342 | |
343 | static int restore_vsx(struct task_struct *tsk) | |
344 | { | |
345 | if (cpu_has_feature(CPU_FTR_VSX)) { | |
346 | tsk->thread.used_vsr = 1; | |
347 | return 1; | |
348 | } | |
349 | ||
350 | return 0; | |
351 | } | |
352 | #else | |
353 | static inline int restore_vsx(struct task_struct *tsk) { return 0; } | |
bf6a4d5b | 354 | static inline void save_vsx(struct task_struct *tsk) { } |
ce48b210 MN |
355 | #endif /* CONFIG_VSX */ |
356 | ||
14cf11af | 357 | #ifdef CONFIG_SPE |
98da581e AB |
358 | void giveup_spe(struct task_struct *tsk) |
359 | { | |
98da581e AB |
360 | check_if_tm_restore_required(tsk); |
361 | ||
a0e72cf1 | 362 | msr_check_and_set(MSR_SPE); |
98da581e | 363 | __giveup_spe(tsk); |
a0e72cf1 | 364 | msr_check_and_clear(MSR_SPE); |
98da581e AB |
365 | } |
366 | EXPORT_SYMBOL(giveup_spe); | |
14cf11af PM |
367 | |
368 | void enable_kernel_spe(void) | |
369 | { | |
370 | WARN_ON(preemptible()); | |
371 | ||
a0e72cf1 | 372 | msr_check_and_set(MSR_SPE); |
611b0e5c | 373 | |
d64d02ce AB |
374 | if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) { |
375 | check_if_tm_restore_required(current); | |
a0e72cf1 | 376 | __giveup_spe(current); |
d64d02ce | 377 | } |
14cf11af PM |
378 | } |
379 | EXPORT_SYMBOL(enable_kernel_spe); | |
380 | ||
381 | void flush_spe_to_thread(struct task_struct *tsk) | |
382 | { | |
383 | if (tsk->thread.regs) { | |
384 | preempt_disable(); | |
385 | if (tsk->thread.regs->msr & MSR_SPE) { | |
14cf11af | 386 | BUG_ON(tsk != current); |
685659ee | 387 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); |
0ee6c15e | 388 | giveup_spe(tsk); |
14cf11af PM |
389 | } |
390 | preempt_enable(); | |
391 | } | |
392 | } | |
14cf11af PM |
393 | #endif /* CONFIG_SPE */ |
394 | ||
c2085059 AB |
395 | static unsigned long msr_all_available; |
396 | ||
397 | static int __init init_msr_all_available(void) | |
398 | { | |
399 | #ifdef CONFIG_PPC_FPU | |
400 | msr_all_available |= MSR_FP; | |
401 | #endif | |
402 | #ifdef CONFIG_ALTIVEC | |
403 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) | |
404 | msr_all_available |= MSR_VEC; | |
405 | #endif | |
406 | #ifdef CONFIG_VSX | |
407 | if (cpu_has_feature(CPU_FTR_VSX)) | |
408 | msr_all_available |= MSR_VSX; | |
409 | #endif | |
410 | #ifdef CONFIG_SPE | |
411 | if (cpu_has_feature(CPU_FTR_SPE)) | |
412 | msr_all_available |= MSR_SPE; | |
413 | #endif | |
414 | ||
415 | return 0; | |
416 | } | |
417 | early_initcall(init_msr_all_available); | |
418 | ||
419 | void giveup_all(struct task_struct *tsk) | |
420 | { | |
421 | unsigned long usermsr; | |
422 | ||
423 | if (!tsk->thread.regs) | |
424 | return; | |
425 | ||
426 | usermsr = tsk->thread.regs->msr; | |
427 | ||
428 | if ((usermsr & msr_all_available) == 0) | |
429 | return; | |
430 | ||
431 | msr_check_and_set(msr_all_available); | |
432 | ||
433 | #ifdef CONFIG_PPC_FPU | |
434 | if (usermsr & MSR_FP) | |
435 | __giveup_fpu(tsk); | |
436 | #endif | |
437 | #ifdef CONFIG_ALTIVEC | |
438 | if (usermsr & MSR_VEC) | |
439 | __giveup_altivec(tsk); | |
440 | #endif | |
441 | #ifdef CONFIG_VSX | |
442 | if (usermsr & MSR_VSX) | |
443 | __giveup_vsx(tsk); | |
444 | #endif | |
445 | #ifdef CONFIG_SPE | |
446 | if (usermsr & MSR_SPE) | |
447 | __giveup_spe(tsk); | |
448 | #endif | |
449 | ||
450 | msr_check_and_clear(msr_all_available); | |
451 | } | |
452 | EXPORT_SYMBOL(giveup_all); | |
453 | ||
70fe3d98 CB |
454 | void restore_math(struct pt_regs *regs) |
455 | { | |
456 | unsigned long msr; | |
457 | ||
458 | if (!current->thread.load_fp && !loadvec(current->thread)) | |
459 | return; | |
460 | ||
461 | msr = regs->msr; | |
462 | msr_check_and_set(msr_all_available); | |
463 | ||
464 | /* | |
465 | * Only reload if the bit is not set in the user MSR, the bit BEING set | |
466 | * indicates that the registers are hot | |
467 | */ | |
468 | if ((!(msr & MSR_FP)) && restore_fp(current)) | |
469 | msr |= MSR_FP | current->thread.fpexc_mode; | |
470 | ||
471 | if ((!(msr & MSR_VEC)) && restore_altivec(current)) | |
472 | msr |= MSR_VEC; | |
473 | ||
474 | if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) && | |
475 | restore_vsx(current)) { | |
476 | msr |= MSR_VSX; | |
477 | } | |
478 | ||
479 | msr_check_and_clear(msr_all_available); | |
480 | ||
481 | regs->msr = msr; | |
482 | } | |
483 | ||
de2a20aa CB |
484 | void save_all(struct task_struct *tsk) |
485 | { | |
486 | unsigned long usermsr; | |
487 | ||
488 | if (!tsk->thread.regs) | |
489 | return; | |
490 | ||
491 | usermsr = tsk->thread.regs->msr; | |
492 | ||
493 | if ((usermsr & msr_all_available) == 0) | |
494 | return; | |
495 | ||
496 | msr_check_and_set(msr_all_available); | |
497 | ||
bf6a4d5b CB |
498 | /* |
499 | * Saving the way the register space is in hardware, save_vsx boils | |
500 | * down to a save_fpu() and save_altivec() | |
501 | */ | |
502 | if (usermsr & MSR_VSX) { | |
503 | save_vsx(tsk); | |
504 | } else { | |
505 | if (usermsr & MSR_FP) | |
506 | save_fpu(tsk); | |
507 | ||
508 | if (usermsr & MSR_VEC) | |
509 | save_altivec(tsk); | |
510 | } | |
de2a20aa CB |
511 | |
512 | if (usermsr & MSR_SPE) | |
513 | __giveup_spe(tsk); | |
514 | ||
515 | msr_check_and_clear(msr_all_available); | |
516 | } | |
517 | ||
579e633e AB |
518 | void flush_all_to_thread(struct task_struct *tsk) |
519 | { | |
520 | if (tsk->thread.regs) { | |
521 | preempt_disable(); | |
522 | BUG_ON(tsk != current); | |
de2a20aa | 523 | save_all(tsk); |
579e633e AB |
524 | |
525 | #ifdef CONFIG_SPE | |
526 | if (tsk->thread.regs->msr & MSR_SPE) | |
527 | tsk->thread.spefscr = mfspr(SPRN_SPEFSCR); | |
528 | #endif | |
529 | ||
530 | preempt_enable(); | |
531 | } | |
532 | } | |
533 | EXPORT_SYMBOL(flush_all_to_thread); | |
534 | ||
3bffb652 DK |
535 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
536 | void do_send_trap(struct pt_regs *regs, unsigned long address, | |
537 | unsigned long error_code, int signal_code, int breakpt) | |
538 | { | |
539 | siginfo_t info; | |
540 | ||
41ab5266 | 541 | current->thread.trap_nr = signal_code; |
3bffb652 DK |
542 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
543 | 11, SIGSEGV) == NOTIFY_STOP) | |
544 | return; | |
545 | ||
546 | /* Deliver the signal to userspace */ | |
547 | info.si_signo = SIGTRAP; | |
548 | info.si_errno = breakpt; /* breakpoint or watchpoint id */ | |
549 | info.si_code = signal_code; | |
550 | info.si_addr = (void __user *)address; | |
551 | force_sig_info(SIGTRAP, &info, current); | |
552 | } | |
553 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
9422de3e | 554 | void do_break (struct pt_regs *regs, unsigned long address, |
d6a61bfc LM |
555 | unsigned long error_code) |
556 | { | |
557 | siginfo_t info; | |
558 | ||
41ab5266 | 559 | current->thread.trap_nr = TRAP_HWBKPT; |
d6a61bfc LM |
560 | if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code, |
561 | 11, SIGSEGV) == NOTIFY_STOP) | |
562 | return; | |
563 | ||
9422de3e | 564 | if (debugger_break_match(regs)) |
d6a61bfc LM |
565 | return; |
566 | ||
9422de3e MN |
567 | /* Clear the breakpoint */ |
568 | hw_breakpoint_disable(); | |
d6a61bfc LM |
569 | |
570 | /* Deliver the signal to userspace */ | |
571 | info.si_signo = SIGTRAP; | |
572 | info.si_errno = 0; | |
573 | info.si_code = TRAP_HWBKPT; | |
574 | info.si_addr = (void __user *)address; | |
575 | force_sig_info(SIGTRAP, &info, current); | |
576 | } | |
3bffb652 | 577 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc | 578 | |
9422de3e | 579 | static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk); |
a2ceff5e | 580 | |
3bffb652 DK |
581 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
582 | /* | |
583 | * Set the debug registers back to their default "safe" values. | |
584 | */ | |
585 | static void set_debug_reg_defaults(struct thread_struct *thread) | |
586 | { | |
51ae8d4a | 587 | thread->debug.iac1 = thread->debug.iac2 = 0; |
3bffb652 | 588 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
51ae8d4a | 589 | thread->debug.iac3 = thread->debug.iac4 = 0; |
3bffb652 | 590 | #endif |
51ae8d4a | 591 | thread->debug.dac1 = thread->debug.dac2 = 0; |
3bffb652 | 592 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
51ae8d4a | 593 | thread->debug.dvc1 = thread->debug.dvc2 = 0; |
3bffb652 | 594 | #endif |
51ae8d4a | 595 | thread->debug.dbcr0 = 0; |
3bffb652 DK |
596 | #ifdef CONFIG_BOOKE |
597 | /* | |
598 | * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) | |
599 | */ | |
51ae8d4a | 600 | thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | |
3bffb652 DK |
601 | DBCR1_IAC3US | DBCR1_IAC4US; |
602 | /* | |
603 | * Force Data Address Compare User/Supervisor bits to be User-only | |
604 | * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. | |
605 | */ | |
51ae8d4a | 606 | thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; |
3bffb652 | 607 | #else |
51ae8d4a | 608 | thread->debug.dbcr1 = 0; |
3bffb652 DK |
609 | #endif |
610 | } | |
611 | ||
f5f97210 | 612 | static void prime_debug_regs(struct debug_reg *debug) |
3bffb652 | 613 | { |
6cecf76b SW |
614 | /* |
615 | * We could have inherited MSR_DE from userspace, since | |
616 | * it doesn't get cleared on exception entry. Make sure | |
617 | * MSR_DE is clear before we enable any debug events. | |
618 | */ | |
619 | mtmsr(mfmsr() & ~MSR_DE); | |
620 | ||
f5f97210 SW |
621 | mtspr(SPRN_IAC1, debug->iac1); |
622 | mtspr(SPRN_IAC2, debug->iac2); | |
3bffb652 | 623 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
f5f97210 SW |
624 | mtspr(SPRN_IAC3, debug->iac3); |
625 | mtspr(SPRN_IAC4, debug->iac4); | |
3bffb652 | 626 | #endif |
f5f97210 SW |
627 | mtspr(SPRN_DAC1, debug->dac1); |
628 | mtspr(SPRN_DAC2, debug->dac2); | |
3bffb652 | 629 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
f5f97210 SW |
630 | mtspr(SPRN_DVC1, debug->dvc1); |
631 | mtspr(SPRN_DVC2, debug->dvc2); | |
3bffb652 | 632 | #endif |
f5f97210 SW |
633 | mtspr(SPRN_DBCR0, debug->dbcr0); |
634 | mtspr(SPRN_DBCR1, debug->dbcr1); | |
3bffb652 | 635 | #ifdef CONFIG_BOOKE |
f5f97210 | 636 | mtspr(SPRN_DBCR2, debug->dbcr2); |
3bffb652 DK |
637 | #endif |
638 | } | |
639 | /* | |
640 | * Unless neither the old or new thread are making use of the | |
641 | * debug registers, set the debug registers from the values | |
642 | * stored in the new thread. | |
643 | */ | |
f5f97210 | 644 | void switch_booke_debug_regs(struct debug_reg *new_debug) |
3bffb652 | 645 | { |
51ae8d4a | 646 | if ((current->thread.debug.dbcr0 & DBCR0_IDM) |
f5f97210 SW |
647 | || (new_debug->dbcr0 & DBCR0_IDM)) |
648 | prime_debug_regs(new_debug); | |
3bffb652 | 649 | } |
3743c9b8 | 650 | EXPORT_SYMBOL_GPL(switch_booke_debug_regs); |
3bffb652 | 651 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ |
e0780b72 | 652 | #ifndef CONFIG_HAVE_HW_BREAKPOINT |
3bffb652 DK |
653 | static void set_debug_reg_defaults(struct thread_struct *thread) |
654 | { | |
9422de3e MN |
655 | thread->hw_brk.address = 0; |
656 | thread->hw_brk.type = 0; | |
b9818c33 | 657 | set_breakpoint(&thread->hw_brk); |
3bffb652 | 658 | } |
e0780b72 | 659 | #endif /* !CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 DK |
660 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
661 | ||
172ae2e7 | 662 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e MN |
663 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
664 | { | |
d6a61bfc | 665 | mtspr(SPRN_DAC1, dabr); |
221c185d DK |
666 | #ifdef CONFIG_PPC_47x |
667 | isync(); | |
668 | #endif | |
9422de3e MN |
669 | return 0; |
670 | } | |
c6c9eace | 671 | #elif defined(CONFIG_PPC_BOOK3S) |
9422de3e MN |
672 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) |
673 | { | |
c6c9eace | 674 | mtspr(SPRN_DABR, dabr); |
82a9f16a MN |
675 | if (cpu_has_feature(CPU_FTR_DABRX)) |
676 | mtspr(SPRN_DABRX, dabrx); | |
cab0af98 | 677 | return 0; |
14cf11af | 678 | } |
9422de3e MN |
679 | #else |
680 | static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) | |
681 | { | |
682 | return -EINVAL; | |
683 | } | |
684 | #endif | |
685 | ||
686 | static inline int set_dabr(struct arch_hw_breakpoint *brk) | |
687 | { | |
688 | unsigned long dabr, dabrx; | |
689 | ||
690 | dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR); | |
691 | dabrx = ((brk->type >> 3) & 0x7); | |
692 | ||
693 | if (ppc_md.set_dabr) | |
694 | return ppc_md.set_dabr(dabr, dabrx); | |
695 | ||
696 | return __set_dabr(dabr, dabrx); | |
697 | } | |
698 | ||
bf99de36 MN |
699 | static inline int set_dawr(struct arch_hw_breakpoint *brk) |
700 | { | |
05d694ea | 701 | unsigned long dawr, dawrx, mrd; |
bf99de36 MN |
702 | |
703 | dawr = brk->address; | |
704 | ||
705 | dawrx = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \ | |
706 | << (63 - 58); //* read/write bits */ | |
707 | dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \ | |
708 | << (63 - 59); //* translate */ | |
709 | dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \ | |
710 | >> 3; //* PRIM bits */ | |
05d694ea MN |
711 | /* dawr length is stored in field MDR bits 48:53. Matches range in |
712 | doublewords (64 bits) baised by -1 eg. 0b000000=1DW and | |
713 | 0b111111=64DW. | |
714 | brk->len is in bytes. | |
715 | This aligns up to double word size, shifts and does the bias. | |
716 | */ | |
717 | mrd = ((brk->len + 7) >> 3) - 1; | |
718 | dawrx |= (mrd & 0x3f) << (63 - 53); | |
bf99de36 MN |
719 | |
720 | if (ppc_md.set_dawr) | |
721 | return ppc_md.set_dawr(dawr, dawrx); | |
722 | mtspr(SPRN_DAWR, dawr); | |
723 | mtspr(SPRN_DAWRX, dawrx); | |
724 | return 0; | |
725 | } | |
726 | ||
21f58507 | 727 | void __set_breakpoint(struct arch_hw_breakpoint *brk) |
9422de3e | 728 | { |
69111bac | 729 | memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk)); |
9422de3e | 730 | |
bf99de36 | 731 | if (cpu_has_feature(CPU_FTR_DAWR)) |
04c32a51 PG |
732 | set_dawr(brk); |
733 | else | |
734 | set_dabr(brk); | |
9422de3e | 735 | } |
14cf11af | 736 | |
21f58507 PG |
737 | void set_breakpoint(struct arch_hw_breakpoint *brk) |
738 | { | |
739 | preempt_disable(); | |
740 | __set_breakpoint(brk); | |
741 | preempt_enable(); | |
742 | } | |
743 | ||
06d67d54 PM |
744 | #ifdef CONFIG_PPC64 |
745 | DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array); | |
06d67d54 | 746 | #endif |
14cf11af | 747 | |
9422de3e MN |
748 | static inline bool hw_brk_match(struct arch_hw_breakpoint *a, |
749 | struct arch_hw_breakpoint *b) | |
750 | { | |
751 | if (a->address != b->address) | |
752 | return false; | |
753 | if (a->type != b->type) | |
754 | return false; | |
755 | if (a->len != b->len) | |
756 | return false; | |
757 | return true; | |
758 | } | |
d31626f7 | 759 | |
fb09692e | 760 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
d31626f7 PM |
761 | static void tm_reclaim_thread(struct thread_struct *thr, |
762 | struct thread_info *ti, uint8_t cause) | |
763 | { | |
764 | unsigned long msr_diff = 0; | |
765 | ||
766 | /* | |
767 | * If FP/VSX registers have been already saved to the | |
768 | * thread_struct, move them to the transact_fp array. | |
769 | * We clear the TIF_RESTORE_TM bit since after the reclaim | |
770 | * the thread will no longer be transactional. | |
771 | */ | |
772 | if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) { | |
829023df | 773 | msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr; |
d31626f7 PM |
774 | if (msr_diff & MSR_FP) |
775 | memcpy(&thr->transact_fp, &thr->fp_state, | |
776 | sizeof(struct thread_fp_state)); | |
777 | if (msr_diff & MSR_VEC) | |
778 | memcpy(&thr->transact_vr, &thr->vr_state, | |
779 | sizeof(struct thread_vr_state)); | |
780 | clear_ti_thread_flag(ti, TIF_RESTORE_TM); | |
781 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1; | |
782 | } | |
783 | ||
7f821fc9 MN |
784 | /* |
785 | * Use the current MSR TM suspended bit to track if we have | |
786 | * checkpointed state outstanding. | |
787 | * On signal delivery, we'd normally reclaim the checkpointed | |
788 | * state to obtain stack pointer (see:get_tm_stackpointer()). | |
789 | * This will then directly return to userspace without going | |
790 | * through __switch_to(). However, if the stack frame is bad, | |
791 | * we need to exit this thread which calls __switch_to() which | |
792 | * will again attempt to reclaim the already saved tm state. | |
793 | * Hence we need to check that we've not already reclaimed | |
794 | * this state. | |
795 | * We do this using the current MSR, rather tracking it in | |
796 | * some specific thread_struct bit, as it has the additional | |
797 | * benifit of checking for a potential TM bad thing exception. | |
798 | */ | |
799 | if (!MSR_TM_SUSPENDED(mfmsr())) | |
800 | return; | |
801 | ||
d31626f7 PM |
802 | tm_reclaim(thr, thr->regs->msr, cause); |
803 | ||
804 | /* Having done the reclaim, we now have the checkpointed | |
805 | * FP/VSX values in the registers. These might be valid | |
806 | * even if we have previously called enable_kernel_fp() or | |
807 | * flush_fp_to_thread(), so update thr->regs->msr to | |
808 | * indicate their current validity. | |
809 | */ | |
810 | thr->regs->msr |= msr_diff; | |
811 | } | |
812 | ||
813 | void tm_reclaim_current(uint8_t cause) | |
814 | { | |
815 | tm_enable(); | |
816 | tm_reclaim_thread(¤t->thread, current_thread_info(), cause); | |
817 | } | |
818 | ||
fb09692e MN |
819 | static inline void tm_reclaim_task(struct task_struct *tsk) |
820 | { | |
821 | /* We have to work out if we're switching from/to a task that's in the | |
822 | * middle of a transaction. | |
823 | * | |
824 | * In switching we need to maintain a 2nd register state as | |
825 | * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the | |
826 | * checkpointed (tbegin) state in ckpt_regs and saves the transactional | |
827 | * (current) FPRs into oldtask->thread.transact_fpr[]. | |
828 | * | |
829 | * We also context switch (save) TFHAR/TEXASR/TFIAR in here. | |
830 | */ | |
831 | struct thread_struct *thr = &tsk->thread; | |
832 | ||
833 | if (!thr->regs) | |
834 | return; | |
835 | ||
836 | if (!MSR_TM_ACTIVE(thr->regs->msr)) | |
837 | goto out_and_saveregs; | |
838 | ||
839 | /* Stash the original thread MSR, as giveup_fpu et al will | |
840 | * modify it. We hold onto it to see whether the task used | |
d31626f7 | 841 | * FP & vector regs. If the TIF_RESTORE_TM flag is set, |
829023df | 842 | * ckpt_regs.msr is already set. |
fb09692e | 843 | */ |
d31626f7 | 844 | if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM)) |
829023df | 845 | thr->ckpt_regs.msr = thr->regs->msr; |
fb09692e MN |
846 | |
847 | TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, " | |
848 | "ccr=%lx, msr=%lx, trap=%lx)\n", | |
849 | tsk->pid, thr->regs->nip, | |
850 | thr->regs->ccr, thr->regs->msr, | |
851 | thr->regs->trap); | |
852 | ||
d31626f7 | 853 | tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED); |
fb09692e MN |
854 | |
855 | TM_DEBUG("--- tm_reclaim on pid %d complete\n", | |
856 | tsk->pid); | |
857 | ||
858 | out_and_saveregs: | |
859 | /* Always save the regs here, even if a transaction's not active. | |
860 | * This context-switches a thread's TM info SPRs. We do it here to | |
861 | * be consistent with the restore path (in recheckpoint) which | |
862 | * cannot happen later in _switch(). | |
863 | */ | |
864 | tm_save_sprs(thr); | |
865 | } | |
866 | ||
e6b8fd02 MN |
867 | extern void __tm_recheckpoint(struct thread_struct *thread, |
868 | unsigned long orig_msr); | |
869 | ||
870 | void tm_recheckpoint(struct thread_struct *thread, | |
871 | unsigned long orig_msr) | |
872 | { | |
873 | unsigned long flags; | |
874 | ||
875 | /* We really can't be interrupted here as the TEXASR registers can't | |
876 | * change and later in the trecheckpoint code, we have a userspace R1. | |
877 | * So let's hard disable over this region. | |
878 | */ | |
879 | local_irq_save(flags); | |
880 | hard_irq_disable(); | |
881 | ||
882 | /* The TM SPRs are restored here, so that TEXASR.FS can be set | |
883 | * before the trecheckpoint and no explosion occurs. | |
884 | */ | |
885 | tm_restore_sprs(thread); | |
886 | ||
887 | __tm_recheckpoint(thread, orig_msr); | |
888 | ||
889 | local_irq_restore(flags); | |
890 | } | |
891 | ||
bc2a9408 | 892 | static inline void tm_recheckpoint_new_task(struct task_struct *new) |
fb09692e MN |
893 | { |
894 | unsigned long msr; | |
895 | ||
896 | if (!cpu_has_feature(CPU_FTR_TM)) | |
897 | return; | |
898 | ||
899 | /* Recheckpoint the registers of the thread we're about to switch to. | |
900 | * | |
901 | * If the task was using FP, we non-lazily reload both the original and | |
902 | * the speculative FP register states. This is because the kernel | |
903 | * doesn't see if/when a TM rollback occurs, so if we take an FP | |
904 | * unavoidable later, we are unable to determine which set of FP regs | |
905 | * need to be restored. | |
906 | */ | |
907 | if (!new->thread.regs) | |
908 | return; | |
909 | ||
e6b8fd02 MN |
910 | if (!MSR_TM_ACTIVE(new->thread.regs->msr)){ |
911 | tm_restore_sprs(&new->thread); | |
fb09692e | 912 | return; |
e6b8fd02 | 913 | } |
829023df | 914 | msr = new->thread.ckpt_regs.msr; |
fb09692e MN |
915 | /* Recheckpoint to restore original checkpointed register state. */ |
916 | TM_DEBUG("*** tm_recheckpoint of pid %d " | |
917 | "(new->msr 0x%lx, new->origmsr 0x%lx)\n", | |
918 | new->pid, new->thread.regs->msr, msr); | |
919 | ||
920 | /* This loads the checkpointed FP/VEC state, if used */ | |
921 | tm_recheckpoint(&new->thread, msr); | |
922 | ||
923 | /* This loads the speculative FP/VEC state, if used */ | |
924 | if (msr & MSR_FP) { | |
925 | do_load_up_transact_fpu(&new->thread); | |
926 | new->thread.regs->msr |= | |
927 | (MSR_FP | new->thread.fpexc_mode); | |
928 | } | |
f110c0c1 | 929 | #ifdef CONFIG_ALTIVEC |
fb09692e MN |
930 | if (msr & MSR_VEC) { |
931 | do_load_up_transact_altivec(&new->thread); | |
932 | new->thread.regs->msr |= MSR_VEC; | |
933 | } | |
f110c0c1 | 934 | #endif |
fb09692e MN |
935 | /* We may as well turn on VSX too since all the state is restored now */ |
936 | if (msr & MSR_VSX) | |
937 | new->thread.regs->msr |= MSR_VSX; | |
938 | ||
939 | TM_DEBUG("*** tm_recheckpoint of pid %d complete " | |
940 | "(kernel msr 0x%lx)\n", | |
941 | new->pid, mfmsr()); | |
942 | } | |
943 | ||
944 | static inline void __switch_to_tm(struct task_struct *prev) | |
945 | { | |
946 | if (cpu_has_feature(CPU_FTR_TM)) { | |
947 | tm_enable(); | |
948 | tm_reclaim_task(prev); | |
949 | } | |
950 | } | |
d31626f7 PM |
951 | |
952 | /* | |
953 | * This is called if we are on the way out to userspace and the | |
954 | * TIF_RESTORE_TM flag is set. It checks if we need to reload | |
955 | * FP and/or vector state and does so if necessary. | |
956 | * If userspace is inside a transaction (whether active or | |
957 | * suspended) and FP/VMX/VSX instructions have ever been enabled | |
958 | * inside that transaction, then we have to keep them enabled | |
959 | * and keep the FP/VMX/VSX state loaded while ever the transaction | |
960 | * continues. The reason is that if we didn't, and subsequently | |
961 | * got a FP/VMX/VSX unavailable interrupt inside a transaction, | |
962 | * we don't know whether it's the same transaction, and thus we | |
963 | * don't know which of the checkpointed state and the transactional | |
964 | * state to use. | |
965 | */ | |
966 | void restore_tm_state(struct pt_regs *regs) | |
967 | { | |
968 | unsigned long msr_diff; | |
969 | ||
970 | clear_thread_flag(TIF_RESTORE_TM); | |
971 | if (!MSR_TM_ACTIVE(regs->msr)) | |
972 | return; | |
973 | ||
829023df | 974 | msr_diff = current->thread.ckpt_regs.msr & ~regs->msr; |
d31626f7 | 975 | msr_diff &= MSR_FP | MSR_VEC | MSR_VSX; |
70fe3d98 CB |
976 | |
977 | restore_math(regs); | |
978 | ||
d31626f7 PM |
979 | regs->msr |= msr_diff; |
980 | } | |
981 | ||
fb09692e MN |
982 | #else |
983 | #define tm_recheckpoint_new_task(new) | |
984 | #define __switch_to_tm(prev) | |
985 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
9422de3e | 986 | |
152d523e AB |
987 | static inline void save_sprs(struct thread_struct *t) |
988 | { | |
989 | #ifdef CONFIG_ALTIVEC | |
01d7c2a2 | 990 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
152d523e AB |
991 | t->vrsave = mfspr(SPRN_VRSAVE); |
992 | #endif | |
993 | #ifdef CONFIG_PPC_BOOK3S_64 | |
994 | if (cpu_has_feature(CPU_FTR_DSCR)) | |
995 | t->dscr = mfspr(SPRN_DSCR); | |
996 | ||
997 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
998 | t->bescr = mfspr(SPRN_BESCR); | |
999 | t->ebbhr = mfspr(SPRN_EBBHR); | |
1000 | t->ebbrr = mfspr(SPRN_EBBRR); | |
1001 | ||
1002 | t->fscr = mfspr(SPRN_FSCR); | |
1003 | ||
1004 | /* | |
1005 | * Note that the TAR is not available for use in the kernel. | |
1006 | * (To provide this, the TAR should be backed up/restored on | |
1007 | * exception entry/exit instead, and be in pt_regs. FIXME, | |
1008 | * this should be in pt_regs anyway (for debug).) | |
1009 | */ | |
1010 | t->tar = mfspr(SPRN_TAR); | |
1011 | } | |
1012 | #endif | |
1013 | } | |
1014 | ||
1015 | static inline void restore_sprs(struct thread_struct *old_thread, | |
1016 | struct thread_struct *new_thread) | |
1017 | { | |
1018 | #ifdef CONFIG_ALTIVEC | |
1019 | if (cpu_has_feature(CPU_FTR_ALTIVEC) && | |
1020 | old_thread->vrsave != new_thread->vrsave) | |
1021 | mtspr(SPRN_VRSAVE, new_thread->vrsave); | |
1022 | #endif | |
1023 | #ifdef CONFIG_PPC_BOOK3S_64 | |
1024 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1025 | u64 dscr = get_paca()->dscr_default; | |
1026 | u64 fscr = old_thread->fscr & ~FSCR_DSCR; | |
1027 | ||
1028 | if (new_thread->dscr_inherit) { | |
1029 | dscr = new_thread->dscr; | |
1030 | fscr |= FSCR_DSCR; | |
1031 | } | |
1032 | ||
1033 | if (old_thread->dscr != dscr) | |
1034 | mtspr(SPRN_DSCR, dscr); | |
1035 | ||
1036 | if (old_thread->fscr != fscr) | |
1037 | mtspr(SPRN_FSCR, fscr); | |
1038 | } | |
1039 | ||
1040 | if (cpu_has_feature(CPU_FTR_ARCH_207S)) { | |
1041 | if (old_thread->bescr != new_thread->bescr) | |
1042 | mtspr(SPRN_BESCR, new_thread->bescr); | |
1043 | if (old_thread->ebbhr != new_thread->ebbhr) | |
1044 | mtspr(SPRN_EBBHR, new_thread->ebbhr); | |
1045 | if (old_thread->ebbrr != new_thread->ebbrr) | |
1046 | mtspr(SPRN_EBBRR, new_thread->ebbrr); | |
1047 | ||
1048 | if (old_thread->tar != new_thread->tar) | |
1049 | mtspr(SPRN_TAR, new_thread->tar); | |
1050 | } | |
1051 | #endif | |
1052 | } | |
1053 | ||
14cf11af PM |
1054 | struct task_struct *__switch_to(struct task_struct *prev, |
1055 | struct task_struct *new) | |
1056 | { | |
1057 | struct thread_struct *new_thread, *old_thread; | |
14cf11af | 1058 | struct task_struct *last; |
d6bf29b4 PZ |
1059 | #ifdef CONFIG_PPC_BOOK3S_64 |
1060 | struct ppc64_tlb_batch *batch; | |
1061 | #endif | |
14cf11af | 1062 | |
152d523e AB |
1063 | new_thread = &new->thread; |
1064 | old_thread = ¤t->thread; | |
1065 | ||
7ba5fef7 MN |
1066 | WARN_ON(!irqs_disabled()); |
1067 | ||
06d67d54 PM |
1068 | #ifdef CONFIG_PPC64 |
1069 | /* | |
1070 | * Collect processor utilization data per process | |
1071 | */ | |
1072 | if (firmware_has_feature(FW_FEATURE_SPLPAR)) { | |
69111bac | 1073 | struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array); |
06d67d54 PM |
1074 | long unsigned start_tb, current_tb; |
1075 | start_tb = old_thread->start_tb; | |
1076 | cu->current_tb = current_tb = mfspr(SPRN_PURR); | |
1077 | old_thread->accum_tb += (current_tb - start_tb); | |
1078 | new_thread->start_tb = current_tb; | |
1079 | } | |
d6bf29b4 PZ |
1080 | #endif /* CONFIG_PPC64 */ |
1081 | ||
1082 | #ifdef CONFIG_PPC_BOOK3S_64 | |
69111bac | 1083 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1084 | if (batch->active) { |
1085 | current_thread_info()->local_flags |= _TLF_LAZY_MMU; | |
1086 | if (batch->index) | |
1087 | __flush_tlb_pending(batch); | |
1088 | batch->active = 0; | |
1089 | } | |
1090 | #endif /* CONFIG_PPC_BOOK3S_64 */ | |
06d67d54 | 1091 | |
f3d885cc AB |
1092 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1093 | switch_booke_debug_regs(&new->thread.debug); | |
1094 | #else | |
1095 | /* | |
1096 | * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would | |
1097 | * schedule DABR | |
1098 | */ | |
1099 | #ifndef CONFIG_HAVE_HW_BREAKPOINT | |
1100 | if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk))) | |
1101 | __set_breakpoint(&new->thread.hw_brk); | |
1102 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1103 | #endif | |
1104 | ||
1105 | /* | |
1106 | * We need to save SPRs before treclaim/trecheckpoint as these will | |
1107 | * change a number of them. | |
1108 | */ | |
1109 | save_sprs(&prev->thread); | |
1110 | ||
1111 | __switch_to_tm(prev); | |
1112 | ||
1113 | /* Save FPU, Altivec, VSX and SPE state */ | |
1114 | giveup_all(prev); | |
1115 | ||
44387e9f AB |
1116 | /* |
1117 | * We can't take a PMU exception inside _switch() since there is a | |
1118 | * window where the kernel stack SLB and the kernel stack are out | |
1119 | * of sync. Hard disable here. | |
1120 | */ | |
1121 | hard_irq_disable(); | |
bc2a9408 MN |
1122 | |
1123 | tm_recheckpoint_new_task(new); | |
1124 | ||
20dbe670 AB |
1125 | /* |
1126 | * Call restore_sprs() before calling _switch(). If we move it after | |
1127 | * _switch() then we miss out on calling it for new tasks. The reason | |
1128 | * for this is we manually create a stack frame for new tasks that | |
1129 | * directly returns through ret_from_fork() or | |
1130 | * ret_from_kernel_thread(). See copy_thread() for details. | |
1131 | */ | |
f3d885cc AB |
1132 | restore_sprs(old_thread, new_thread); |
1133 | ||
20dbe670 AB |
1134 | last = _switch(old_thread, new_thread); |
1135 | ||
d6bf29b4 PZ |
1136 | #ifdef CONFIG_PPC_BOOK3S_64 |
1137 | if (current_thread_info()->local_flags & _TLF_LAZY_MMU) { | |
1138 | current_thread_info()->local_flags &= ~_TLF_LAZY_MMU; | |
69111bac | 1139 | batch = this_cpu_ptr(&ppc64_tlb_batch); |
d6bf29b4 PZ |
1140 | batch->active = 1; |
1141 | } | |
70fe3d98 CB |
1142 | |
1143 | if (current_thread_info()->task->thread.regs) | |
1144 | restore_math(current_thread_info()->task->thread.regs); | |
1145 | ||
d6bf29b4 PZ |
1146 | #endif /* CONFIG_PPC_BOOK3S_64 */ |
1147 | ||
14cf11af PM |
1148 | return last; |
1149 | } | |
1150 | ||
06d67d54 PM |
1151 | static int instructions_to_print = 16; |
1152 | ||
06d67d54 PM |
1153 | static void show_instructions(struct pt_regs *regs) |
1154 | { | |
1155 | int i; | |
1156 | unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 * | |
1157 | sizeof(int)); | |
1158 | ||
1159 | printk("Instruction dump:"); | |
1160 | ||
1161 | for (i = 0; i < instructions_to_print; i++) { | |
1162 | int instr; | |
1163 | ||
1164 | if (!(i % 8)) | |
1165 | printk("\n"); | |
1166 | ||
0de2d820 SW |
1167 | #if !defined(CONFIG_BOOKE) |
1168 | /* If executing with the IMMU off, adjust pc rather | |
1169 | * than print XXXXXXXX. | |
1170 | */ | |
1171 | if (!(regs->msr & MSR_IR)) | |
1172 | pc = (unsigned long)phys_to_virt(pc); | |
1173 | #endif | |
1174 | ||
00ae36de | 1175 | if (!__kernel_text_address(pc) || |
7b051f66 | 1176 | probe_kernel_address((unsigned int __user *)pc, instr)) { |
40c8cefa | 1177 | printk(KERN_CONT "XXXXXXXX "); |
06d67d54 PM |
1178 | } else { |
1179 | if (regs->nip == pc) | |
40c8cefa | 1180 | printk(KERN_CONT "<%08x> ", instr); |
06d67d54 | 1181 | else |
40c8cefa | 1182 | printk(KERN_CONT "%08x ", instr); |
06d67d54 PM |
1183 | } |
1184 | ||
1185 | pc += sizeof(int); | |
1186 | } | |
1187 | ||
1188 | printk("\n"); | |
1189 | } | |
1190 | ||
801c0b2c | 1191 | struct regbit { |
06d67d54 PM |
1192 | unsigned long bit; |
1193 | const char *name; | |
801c0b2c MN |
1194 | }; |
1195 | ||
1196 | static struct regbit msr_bits[] = { | |
3bfd0c9c AB |
1197 | #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE) |
1198 | {MSR_SF, "SF"}, | |
1199 | {MSR_HV, "HV"}, | |
1200 | #endif | |
1201 | {MSR_VEC, "VEC"}, | |
1202 | {MSR_VSX, "VSX"}, | |
1203 | #ifdef CONFIG_BOOKE | |
1204 | {MSR_CE, "CE"}, | |
1205 | #endif | |
06d67d54 PM |
1206 | {MSR_EE, "EE"}, |
1207 | {MSR_PR, "PR"}, | |
1208 | {MSR_FP, "FP"}, | |
1209 | {MSR_ME, "ME"}, | |
3bfd0c9c | 1210 | #ifdef CONFIG_BOOKE |
1b98326b | 1211 | {MSR_DE, "DE"}, |
3bfd0c9c AB |
1212 | #else |
1213 | {MSR_SE, "SE"}, | |
1214 | {MSR_BE, "BE"}, | |
1215 | #endif | |
06d67d54 PM |
1216 | {MSR_IR, "IR"}, |
1217 | {MSR_DR, "DR"}, | |
3bfd0c9c AB |
1218 | {MSR_PMM, "PMM"}, |
1219 | #ifndef CONFIG_BOOKE | |
1220 | {MSR_RI, "RI"}, | |
1221 | {MSR_LE, "LE"}, | |
1222 | #endif | |
06d67d54 PM |
1223 | {0, NULL} |
1224 | }; | |
1225 | ||
801c0b2c | 1226 | static void print_bits(unsigned long val, struct regbit *bits, const char *sep) |
06d67d54 | 1227 | { |
801c0b2c | 1228 | const char *s = ""; |
06d67d54 | 1229 | |
06d67d54 PM |
1230 | for (; bits->bit; ++bits) |
1231 | if (val & bits->bit) { | |
801c0b2c MN |
1232 | printk("%s%s", s, bits->name); |
1233 | s = sep; | |
06d67d54 | 1234 | } |
801c0b2c MN |
1235 | } |
1236 | ||
1237 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1238 | static struct regbit msr_tm_bits[] = { | |
1239 | {MSR_TS_T, "T"}, | |
1240 | {MSR_TS_S, "S"}, | |
1241 | {MSR_TM, "E"}, | |
1242 | {0, NULL} | |
1243 | }; | |
1244 | ||
1245 | static void print_tm_bits(unsigned long val) | |
1246 | { | |
1247 | /* | |
1248 | * This only prints something if at least one of the TM bit is set. | |
1249 | * Inside the TM[], the output means: | |
1250 | * E: Enabled (bit 32) | |
1251 | * S: Suspended (bit 33) | |
1252 | * T: Transactional (bit 34) | |
1253 | */ | |
1254 | if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { | |
1255 | printk(",TM["); | |
1256 | print_bits(val, msr_tm_bits, ""); | |
1257 | printk("]"); | |
1258 | } | |
1259 | } | |
1260 | #else | |
1261 | static void print_tm_bits(unsigned long val) {} | |
1262 | #endif | |
1263 | ||
1264 | static void print_msr_bits(unsigned long val) | |
1265 | { | |
1266 | printk("<"); | |
1267 | print_bits(val, msr_bits, ","); | |
1268 | print_tm_bits(val); | |
06d67d54 PM |
1269 | printk(">"); |
1270 | } | |
1271 | ||
1272 | #ifdef CONFIG_PPC64 | |
f6f7dde3 | 1273 | #define REG "%016lx" |
06d67d54 PM |
1274 | #define REGS_PER_LINE 4 |
1275 | #define LAST_VOLATILE 13 | |
1276 | #else | |
f6f7dde3 | 1277 | #define REG "%08lx" |
06d67d54 PM |
1278 | #define REGS_PER_LINE 8 |
1279 | #define LAST_VOLATILE 12 | |
1280 | #endif | |
1281 | ||
14cf11af PM |
1282 | void show_regs(struct pt_regs * regs) |
1283 | { | |
1284 | int i, trap; | |
1285 | ||
a43cb95d TH |
1286 | show_regs_print_info(KERN_DEFAULT); |
1287 | ||
06d67d54 PM |
1288 | printk("NIP: "REG" LR: "REG" CTR: "REG"\n", |
1289 | regs->nip, regs->link, regs->ctr); | |
1290 | printk("REGS: %p TRAP: %04lx %s (%s)\n", | |
96b644bd | 1291 | regs, regs->trap, print_tainted(), init_utsname()->release); |
06d67d54 | 1292 | printk("MSR: "REG" ", regs->msr); |
801c0b2c | 1293 | print_msr_bits(regs->msr); |
f6f7dde3 | 1294 | printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); |
14cf11af | 1295 | trap = TRAP(regs); |
5115a026 | 1296 | if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR)) |
9db8bcfd | 1297 | printk("CFAR: "REG" ", regs->orig_gpr3); |
c5400649 | 1298 | if (trap == 0x200 || trap == 0x300 || trap == 0x600) |
ba28c9aa | 1299 | #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
9db8bcfd | 1300 | printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr); |
14170789 | 1301 | #else |
9db8bcfd AB |
1302 | printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr); |
1303 | #endif | |
1304 | #ifdef CONFIG_PPC64 | |
1305 | printk("SOFTE: %ld ", regs->softe); | |
1306 | #endif | |
1307 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
6d888d1a AB |
1308 | if (MSR_TM_ACTIVE(regs->msr)) |
1309 | printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch); | |
14170789 | 1310 | #endif |
14cf11af PM |
1311 | |
1312 | for (i = 0; i < 32; i++) { | |
06d67d54 | 1313 | if ((i % REGS_PER_LINE) == 0) |
a2367194 | 1314 | printk("\nGPR%02d: ", i); |
06d67d54 PM |
1315 | printk(REG " ", regs->gpr[i]); |
1316 | if (i == LAST_VOLATILE && !FULL_REGS(regs)) | |
14cf11af PM |
1317 | break; |
1318 | } | |
1319 | printk("\n"); | |
1320 | #ifdef CONFIG_KALLSYMS | |
1321 | /* | |
1322 | * Lookup NIP late so we have the best change of getting the | |
1323 | * above info out without failing | |
1324 | */ | |
058c78f4 BH |
1325 | printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip); |
1326 | printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link); | |
afc07701 | 1327 | #endif |
14cf11af | 1328 | show_stack(current, (unsigned long *) regs->gpr[1]); |
06d67d54 PM |
1329 | if (!user_mode(regs)) |
1330 | show_instructions(regs); | |
14cf11af PM |
1331 | } |
1332 | ||
1333 | void exit_thread(void) | |
1334 | { | |
14cf11af PM |
1335 | } |
1336 | ||
1337 | void flush_thread(void) | |
1338 | { | |
e0780b72 | 1339 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
5aae8a53 | 1340 | flush_ptrace_hw_breakpoint(current); |
e0780b72 | 1341 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1342 | set_debug_reg_defaults(¤t->thread); |
e0780b72 | 1343 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
14cf11af PM |
1344 | } |
1345 | ||
1346 | void | |
1347 | release_thread(struct task_struct *t) | |
1348 | { | |
1349 | } | |
1350 | ||
1351 | /* | |
55ccf3fe SS |
1352 | * this gets called so that we can store coprocessor state into memory and |
1353 | * copy the current task into the new thread. | |
14cf11af | 1354 | */ |
55ccf3fe | 1355 | int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) |
14cf11af | 1356 | { |
579e633e | 1357 | flush_all_to_thread(src); |
621b5060 MN |
1358 | /* |
1359 | * Flush TM state out so we can copy it. __switch_to_tm() does this | |
1360 | * flush but it removes the checkpointed state from the current CPU and | |
1361 | * transitions the CPU out of TM mode. Hence we need to call | |
1362 | * tm_recheckpoint_new_task() (on the same task) to restore the | |
1363 | * checkpointed state back and the TM mode. | |
1364 | */ | |
1365 | __switch_to_tm(src); | |
1366 | tm_recheckpoint_new_task(src); | |
330a1eb7 | 1367 | |
55ccf3fe | 1368 | *dst = *src; |
330a1eb7 ME |
1369 | |
1370 | clear_task_ebb(dst); | |
1371 | ||
55ccf3fe | 1372 | return 0; |
14cf11af PM |
1373 | } |
1374 | ||
cec15488 ME |
1375 | static void setup_ksp_vsid(struct task_struct *p, unsigned long sp) |
1376 | { | |
1377 | #ifdef CONFIG_PPC_STD_MMU_64 | |
1378 | unsigned long sp_vsid; | |
1379 | unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp; | |
1380 | ||
1381 | if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) | |
1382 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T) | |
1383 | << SLB_VSID_SHIFT_1T; | |
1384 | else | |
1385 | sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M) | |
1386 | << SLB_VSID_SHIFT; | |
1387 | sp_vsid |= SLB_VSID_KERNEL | llp; | |
1388 | p->thread.ksp_vsid = sp_vsid; | |
1389 | #endif | |
1390 | } | |
1391 | ||
14cf11af PM |
1392 | /* |
1393 | * Copy a thread.. | |
1394 | */ | |
efcac658 | 1395 | |
6eca8933 AD |
1396 | /* |
1397 | * Copy architecture-specific thread state | |
1398 | */ | |
6f2c55b8 | 1399 | int copy_thread(unsigned long clone_flags, unsigned long usp, |
6eca8933 | 1400 | unsigned long kthread_arg, struct task_struct *p) |
14cf11af PM |
1401 | { |
1402 | struct pt_regs *childregs, *kregs; | |
1403 | extern void ret_from_fork(void); | |
58254e10 AV |
1404 | extern void ret_from_kernel_thread(void); |
1405 | void (*f)(void); | |
0cec6fd1 | 1406 | unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE; |
5d31a96e ME |
1407 | struct thread_info *ti = task_thread_info(p); |
1408 | ||
1409 | klp_init_thread_info(ti); | |
14cf11af | 1410 | |
14cf11af PM |
1411 | /* Copy registers */ |
1412 | sp -= sizeof(struct pt_regs); | |
1413 | childregs = (struct pt_regs *) sp; | |
ab75819d | 1414 | if (unlikely(p->flags & PF_KTHREAD)) { |
6eca8933 | 1415 | /* kernel thread */ |
58254e10 | 1416 | memset(childregs, 0, sizeof(struct pt_regs)); |
14cf11af | 1417 | childregs->gpr[1] = sp + sizeof(struct pt_regs); |
7cedd601 AB |
1418 | /* function */ |
1419 | if (usp) | |
1420 | childregs->gpr[14] = ppc_function_entry((void *)usp); | |
58254e10 | 1421 | #ifdef CONFIG_PPC64 |
b5e2fc1c | 1422 | clear_tsk_thread_flag(p, TIF_32BIT); |
138d1ce8 | 1423 | childregs->softe = 1; |
06d67d54 | 1424 | #endif |
6eca8933 | 1425 | childregs->gpr[15] = kthread_arg; |
14cf11af | 1426 | p->thread.regs = NULL; /* no user register state */ |
138d1ce8 | 1427 | ti->flags |= _TIF_RESTOREALL; |
58254e10 | 1428 | f = ret_from_kernel_thread; |
14cf11af | 1429 | } else { |
6eca8933 | 1430 | /* user thread */ |
afa86fc4 | 1431 | struct pt_regs *regs = current_pt_regs(); |
58254e10 AV |
1432 | CHECK_FULL_REGS(regs); |
1433 | *childregs = *regs; | |
ea516b11 AV |
1434 | if (usp) |
1435 | childregs->gpr[1] = usp; | |
14cf11af | 1436 | p->thread.regs = childregs; |
58254e10 | 1437 | childregs->gpr[3] = 0; /* Result from fork() */ |
06d67d54 PM |
1438 | if (clone_flags & CLONE_SETTLS) { |
1439 | #ifdef CONFIG_PPC64 | |
9904b005 | 1440 | if (!is_32bit_task()) |
06d67d54 PM |
1441 | childregs->gpr[13] = childregs->gpr[6]; |
1442 | else | |
1443 | #endif | |
1444 | childregs->gpr[2] = childregs->gpr[6]; | |
1445 | } | |
58254e10 AV |
1446 | |
1447 | f = ret_from_fork; | |
14cf11af | 1448 | } |
d272f667 | 1449 | childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX); |
14cf11af | 1450 | sp -= STACK_FRAME_OVERHEAD; |
14cf11af PM |
1451 | |
1452 | /* | |
1453 | * The way this works is that at some point in the future | |
1454 | * some task will call _switch to switch to the new task. | |
1455 | * That will pop off the stack frame created below and start | |
1456 | * the new task running at ret_from_fork. The new task will | |
1457 | * do some house keeping and then return from the fork or clone | |
1458 | * system call, using the stack frame created above. | |
1459 | */ | |
af945cf4 | 1460 | ((unsigned long *)sp)[0] = 0; |
14cf11af PM |
1461 | sp -= sizeof(struct pt_regs); |
1462 | kregs = (struct pt_regs *) sp; | |
1463 | sp -= STACK_FRAME_OVERHEAD; | |
1464 | p->thread.ksp = sp; | |
cbc9565e | 1465 | #ifdef CONFIG_PPC32 |
85218827 KG |
1466 | p->thread.ksp_limit = (unsigned long)task_stack_page(p) + |
1467 | _ALIGN_UP(sizeof(struct thread_info), 16); | |
cbc9565e | 1468 | #endif |
28d170ab ON |
1469 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1470 | p->thread.ptrace_bps[0] = NULL; | |
1471 | #endif | |
1472 | ||
18461960 PM |
1473 | p->thread.fp_save_area = NULL; |
1474 | #ifdef CONFIG_ALTIVEC | |
1475 | p->thread.vr_save_area = NULL; | |
1476 | #endif | |
1477 | ||
cec15488 ME |
1478 | setup_ksp_vsid(p, sp); |
1479 | ||
efcac658 AK |
1480 | #ifdef CONFIG_PPC64 |
1481 | if (cpu_has_feature(CPU_FTR_DSCR)) { | |
1021cb26 | 1482 | p->thread.dscr_inherit = current->thread.dscr_inherit; |
db1231dc | 1483 | p->thread.dscr = mfspr(SPRN_DSCR); |
efcac658 | 1484 | } |
92779245 HM |
1485 | if (cpu_has_feature(CPU_FTR_HAS_PPR)) |
1486 | p->thread.ppr = INIT_PPR; | |
efcac658 | 1487 | #endif |
7cedd601 | 1488 | kregs->nip = ppc_function_entry(f); |
14cf11af PM |
1489 | return 0; |
1490 | } | |
1491 | ||
1492 | /* | |
1493 | * Set up a thread for executing a new program | |
1494 | */ | |
06d67d54 | 1495 | void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp) |
14cf11af | 1496 | { |
90eac727 ME |
1497 | #ifdef CONFIG_PPC64 |
1498 | unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */ | |
1499 | #endif | |
1500 | ||
06d67d54 PM |
1501 | /* |
1502 | * If we exec out of a kernel thread then thread.regs will not be | |
1503 | * set. Do it now. | |
1504 | */ | |
1505 | if (!current->thread.regs) { | |
0cec6fd1 AV |
1506 | struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE; |
1507 | current->thread.regs = regs - 1; | |
06d67d54 PM |
1508 | } |
1509 | ||
14cf11af PM |
1510 | memset(regs->gpr, 0, sizeof(regs->gpr)); |
1511 | regs->ctr = 0; | |
1512 | regs->link = 0; | |
1513 | regs->xer = 0; | |
1514 | regs->ccr = 0; | |
14cf11af | 1515 | regs->gpr[1] = sp; |
06d67d54 | 1516 | |
474f8196 RM |
1517 | /* |
1518 | * We have just cleared all the nonvolatile GPRs, so make | |
1519 | * FULL_REGS(regs) return true. This is necessary to allow | |
1520 | * ptrace to examine the thread immediately after exec. | |
1521 | */ | |
1522 | regs->trap &= ~1UL; | |
1523 | ||
06d67d54 PM |
1524 | #ifdef CONFIG_PPC32 |
1525 | regs->mq = 0; | |
1526 | regs->nip = start; | |
14cf11af | 1527 | regs->msr = MSR_USER; |
06d67d54 | 1528 | #else |
9904b005 | 1529 | if (!is_32bit_task()) { |
94af3abf | 1530 | unsigned long entry; |
06d67d54 | 1531 | |
94af3abf RR |
1532 | if (is_elf2_task()) { |
1533 | /* Look ma, no function descriptors! */ | |
1534 | entry = start; | |
06d67d54 | 1535 | |
94af3abf RR |
1536 | /* |
1537 | * Ulrich says: | |
1538 | * The latest iteration of the ABI requires that when | |
1539 | * calling a function (at its global entry point), | |
1540 | * the caller must ensure r12 holds the entry point | |
1541 | * address (so that the function can quickly | |
1542 | * establish addressability). | |
1543 | */ | |
1544 | regs->gpr[12] = start; | |
1545 | /* Make sure that's restored on entry to userspace. */ | |
1546 | set_thread_flag(TIF_RESTOREALL); | |
1547 | } else { | |
1548 | unsigned long toc; | |
1549 | ||
1550 | /* start is a relocated pointer to the function | |
1551 | * descriptor for the elf _start routine. The first | |
1552 | * entry in the function descriptor is the entry | |
1553 | * address of _start and the second entry is the TOC | |
1554 | * value we need to use. | |
1555 | */ | |
1556 | __get_user(entry, (unsigned long __user *)start); | |
1557 | __get_user(toc, (unsigned long __user *)start+1); | |
1558 | ||
1559 | /* Check whether the e_entry function descriptor entries | |
1560 | * need to be relocated before we can use them. | |
1561 | */ | |
1562 | if (load_addr != 0) { | |
1563 | entry += load_addr; | |
1564 | toc += load_addr; | |
1565 | } | |
1566 | regs->gpr[2] = toc; | |
06d67d54 PM |
1567 | } |
1568 | regs->nip = entry; | |
06d67d54 | 1569 | regs->msr = MSR_USER64; |
d4bf9a78 SR |
1570 | } else { |
1571 | regs->nip = start; | |
1572 | regs->gpr[2] = 0; | |
1573 | regs->msr = MSR_USER32; | |
06d67d54 PM |
1574 | } |
1575 | #endif | |
ce48b210 MN |
1576 | #ifdef CONFIG_VSX |
1577 | current->thread.used_vsr = 0; | |
1578 | #endif | |
de79f7b9 | 1579 | memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state)); |
18461960 | 1580 | current->thread.fp_save_area = NULL; |
14cf11af | 1581 | #ifdef CONFIG_ALTIVEC |
de79f7b9 PM |
1582 | memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state)); |
1583 | current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */ | |
18461960 | 1584 | current->thread.vr_save_area = NULL; |
14cf11af PM |
1585 | current->thread.vrsave = 0; |
1586 | current->thread.used_vr = 0; | |
1587 | #endif /* CONFIG_ALTIVEC */ | |
1588 | #ifdef CONFIG_SPE | |
1589 | memset(current->thread.evr, 0, sizeof(current->thread.evr)); | |
1590 | current->thread.acc = 0; | |
1591 | current->thread.spefscr = 0; | |
1592 | current->thread.used_spe = 0; | |
1593 | #endif /* CONFIG_SPE */ | |
bc2a9408 MN |
1594 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1595 | if (cpu_has_feature(CPU_FTR_TM)) | |
1596 | regs->msr |= MSR_TM; | |
1597 | current->thread.tm_tfhar = 0; | |
1598 | current->thread.tm_texasr = 0; | |
1599 | current->thread.tm_tfiar = 0; | |
1600 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
14cf11af | 1601 | } |
e1802b06 | 1602 | EXPORT_SYMBOL(start_thread); |
14cf11af PM |
1603 | |
1604 | #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \ | |
1605 | | PR_FP_EXC_RES | PR_FP_EXC_INV) | |
1606 | ||
1607 | int set_fpexc_mode(struct task_struct *tsk, unsigned int val) | |
1608 | { | |
1609 | struct pt_regs *regs = tsk->thread.regs; | |
1610 | ||
1611 | /* This is a bit hairy. If we are an SPE enabled processor | |
1612 | * (have embedded fp) we store the IEEE exception enable flags in | |
1613 | * fpexc_mode. fpexc_mode is also used for setting FP exception | |
1614 | * mode (asyn, precise, disabled) for 'Classic' FP. */ | |
1615 | if (val & PR_FP_EXC_SW_ENABLE) { | |
1616 | #ifdef CONFIG_SPE | |
5e14d21e | 1617 | if (cpu_has_feature(CPU_FTR_SPE)) { |
640e9225 JM |
1618 | /* |
1619 | * When the sticky exception bits are set | |
1620 | * directly by userspace, it must call prctl | |
1621 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1622 | * in the existing prctl settings) or | |
1623 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1624 | * the bits being set). <fenv.h> functions | |
1625 | * saving and restoring the whole | |
1626 | * floating-point environment need to do so | |
1627 | * anyway to restore the prctl settings from | |
1628 | * the saved environment. | |
1629 | */ | |
1630 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e KG |
1631 | tsk->thread.fpexc_mode = val & |
1632 | (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT); | |
1633 | return 0; | |
1634 | } else { | |
1635 | return -EINVAL; | |
1636 | } | |
14cf11af PM |
1637 | #else |
1638 | return -EINVAL; | |
1639 | #endif | |
14cf11af | 1640 | } |
06d67d54 PM |
1641 | |
1642 | /* on a CONFIG_SPE this does not hurt us. The bits that | |
1643 | * __pack_fe01 use do not overlap with bits used for | |
1644 | * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits | |
1645 | * on CONFIG_SPE implementations are reserved so writing to | |
1646 | * them does not change anything */ | |
1647 | if (val > PR_FP_EXC_PRECISE) | |
1648 | return -EINVAL; | |
1649 | tsk->thread.fpexc_mode = __pack_fe01(val); | |
1650 | if (regs != NULL && (regs->msr & MSR_FP) != 0) | |
1651 | regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1)) | |
1652 | | tsk->thread.fpexc_mode; | |
14cf11af PM |
1653 | return 0; |
1654 | } | |
1655 | ||
1656 | int get_fpexc_mode(struct task_struct *tsk, unsigned long adr) | |
1657 | { | |
1658 | unsigned int val; | |
1659 | ||
1660 | if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) | |
1661 | #ifdef CONFIG_SPE | |
640e9225 JM |
1662 | if (cpu_has_feature(CPU_FTR_SPE)) { |
1663 | /* | |
1664 | * When the sticky exception bits are set | |
1665 | * directly by userspace, it must call prctl | |
1666 | * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE | |
1667 | * in the existing prctl settings) or | |
1668 | * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in | |
1669 | * the bits being set). <fenv.h> functions | |
1670 | * saving and restoring the whole | |
1671 | * floating-point environment need to do so | |
1672 | * anyway to restore the prctl settings from | |
1673 | * the saved environment. | |
1674 | */ | |
1675 | tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR); | |
5e14d21e | 1676 | val = tsk->thread.fpexc_mode; |
640e9225 | 1677 | } else |
5e14d21e | 1678 | return -EINVAL; |
14cf11af PM |
1679 | #else |
1680 | return -EINVAL; | |
1681 | #endif | |
1682 | else | |
1683 | val = __unpack_fe01(tsk->thread.fpexc_mode); | |
1684 | return put_user(val, (unsigned int __user *) adr); | |
1685 | } | |
1686 | ||
fab5db97 PM |
1687 | int set_endian(struct task_struct *tsk, unsigned int val) |
1688 | { | |
1689 | struct pt_regs *regs = tsk->thread.regs; | |
1690 | ||
1691 | if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) || | |
1692 | (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE))) | |
1693 | return -EINVAL; | |
1694 | ||
1695 | if (regs == NULL) | |
1696 | return -EINVAL; | |
1697 | ||
1698 | if (val == PR_ENDIAN_BIG) | |
1699 | regs->msr &= ~MSR_LE; | |
1700 | else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE) | |
1701 | regs->msr |= MSR_LE; | |
1702 | else | |
1703 | return -EINVAL; | |
1704 | ||
1705 | return 0; | |
1706 | } | |
1707 | ||
1708 | int get_endian(struct task_struct *tsk, unsigned long adr) | |
1709 | { | |
1710 | struct pt_regs *regs = tsk->thread.regs; | |
1711 | unsigned int val; | |
1712 | ||
1713 | if (!cpu_has_feature(CPU_FTR_PPC_LE) && | |
1714 | !cpu_has_feature(CPU_FTR_REAL_LE)) | |
1715 | return -EINVAL; | |
1716 | ||
1717 | if (regs == NULL) | |
1718 | return -EINVAL; | |
1719 | ||
1720 | if (regs->msr & MSR_LE) { | |
1721 | if (cpu_has_feature(CPU_FTR_REAL_LE)) | |
1722 | val = PR_ENDIAN_LITTLE; | |
1723 | else | |
1724 | val = PR_ENDIAN_PPC_LITTLE; | |
1725 | } else | |
1726 | val = PR_ENDIAN_BIG; | |
1727 | ||
1728 | return put_user(val, (unsigned int __user *)adr); | |
1729 | } | |
1730 | ||
e9370ae1 PM |
1731 | int set_unalign_ctl(struct task_struct *tsk, unsigned int val) |
1732 | { | |
1733 | tsk->thread.align_ctl = val; | |
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) | |
1738 | { | |
1739 | return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr); | |
1740 | } | |
1741 | ||
bb72c481 PM |
1742 | static inline int valid_irq_stack(unsigned long sp, struct task_struct *p, |
1743 | unsigned long nbytes) | |
1744 | { | |
1745 | unsigned long stack_page; | |
1746 | unsigned long cpu = task_cpu(p); | |
1747 | ||
1748 | /* | |
1749 | * Avoid crashing if the stack has overflowed and corrupted | |
1750 | * task_cpu(p), which is in the thread_info struct. | |
1751 | */ | |
1752 | if (cpu < NR_CPUS && cpu_possible(cpu)) { | |
1753 | stack_page = (unsigned long) hardirq_ctx[cpu]; | |
1754 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1755 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1756 | return 1; | |
1757 | ||
1758 | stack_page = (unsigned long) softirq_ctx[cpu]; | |
1759 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1760 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1761 | return 1; | |
1762 | } | |
1763 | return 0; | |
1764 | } | |
1765 | ||
2f25194d | 1766 | int validate_sp(unsigned long sp, struct task_struct *p, |
14cf11af PM |
1767 | unsigned long nbytes) |
1768 | { | |
0cec6fd1 | 1769 | unsigned long stack_page = (unsigned long)task_stack_page(p); |
14cf11af PM |
1770 | |
1771 | if (sp >= stack_page + sizeof(struct thread_struct) | |
1772 | && sp <= stack_page + THREAD_SIZE - nbytes) | |
1773 | return 1; | |
1774 | ||
bb72c481 | 1775 | return valid_irq_stack(sp, p, nbytes); |
14cf11af PM |
1776 | } |
1777 | ||
2f25194d AB |
1778 | EXPORT_SYMBOL(validate_sp); |
1779 | ||
14cf11af PM |
1780 | unsigned long get_wchan(struct task_struct *p) |
1781 | { | |
1782 | unsigned long ip, sp; | |
1783 | int count = 0; | |
1784 | ||
1785 | if (!p || p == current || p->state == TASK_RUNNING) | |
1786 | return 0; | |
1787 | ||
1788 | sp = p->thread.ksp; | |
ec2b36b9 | 1789 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1790 | return 0; |
1791 | ||
1792 | do { | |
1793 | sp = *(unsigned long *)sp; | |
ec2b36b9 | 1794 | if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD)) |
14cf11af PM |
1795 | return 0; |
1796 | if (count > 0) { | |
ec2b36b9 | 1797 | ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE]; |
14cf11af PM |
1798 | if (!in_sched_functions(ip)) |
1799 | return ip; | |
1800 | } | |
1801 | } while (count++ < 16); | |
1802 | return 0; | |
1803 | } | |
06d67d54 | 1804 | |
c4d04be1 | 1805 | static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH; |
06d67d54 PM |
1806 | |
1807 | void show_stack(struct task_struct *tsk, unsigned long *stack) | |
1808 | { | |
1809 | unsigned long sp, ip, lr, newsp; | |
1810 | int count = 0; | |
1811 | int firstframe = 1; | |
6794c782 SR |
1812 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1813 | int curr_frame = current->curr_ret_stack; | |
1814 | extern void return_to_handler(void); | |
9135c3cc | 1815 | unsigned long rth = (unsigned long)return_to_handler; |
6794c782 | 1816 | #endif |
06d67d54 PM |
1817 | |
1818 | sp = (unsigned long) stack; | |
1819 | if (tsk == NULL) | |
1820 | tsk = current; | |
1821 | if (sp == 0) { | |
1822 | if (tsk == current) | |
acf620ec | 1823 | sp = current_stack_pointer(); |
06d67d54 PM |
1824 | else |
1825 | sp = tsk->thread.ksp; | |
1826 | } | |
1827 | ||
1828 | lr = 0; | |
1829 | printk("Call Trace:\n"); | |
1830 | do { | |
ec2b36b9 | 1831 | if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD)) |
06d67d54 PM |
1832 | return; |
1833 | ||
1834 | stack = (unsigned long *) sp; | |
1835 | newsp = stack[0]; | |
ec2b36b9 | 1836 | ip = stack[STACK_FRAME_LR_SAVE]; |
06d67d54 | 1837 | if (!firstframe || ip != lr) { |
058c78f4 | 1838 | printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip); |
6794c782 | 1839 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
7d56c65a | 1840 | if ((ip == rth) && curr_frame >= 0) { |
6794c782 SR |
1841 | printk(" (%pS)", |
1842 | (void *)current->ret_stack[curr_frame].ret); | |
1843 | curr_frame--; | |
1844 | } | |
1845 | #endif | |
06d67d54 PM |
1846 | if (firstframe) |
1847 | printk(" (unreliable)"); | |
1848 | printk("\n"); | |
1849 | } | |
1850 | firstframe = 0; | |
1851 | ||
1852 | /* | |
1853 | * See if this is an exception frame. | |
1854 | * We look for the "regshere" marker in the current frame. | |
1855 | */ | |
ec2b36b9 BH |
1856 | if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE) |
1857 | && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) { | |
06d67d54 PM |
1858 | struct pt_regs *regs = (struct pt_regs *) |
1859 | (sp + STACK_FRAME_OVERHEAD); | |
06d67d54 | 1860 | lr = regs->link; |
9be9be2e | 1861 | printk("--- interrupt: %lx at %pS\n LR = %pS\n", |
058c78f4 | 1862 | regs->trap, (void *)regs->nip, (void *)lr); |
06d67d54 PM |
1863 | firstframe = 1; |
1864 | } | |
1865 | ||
1866 | sp = newsp; | |
1867 | } while (count++ < kstack_depth_to_print); | |
1868 | } | |
1869 | ||
cb2c9b27 | 1870 | #ifdef CONFIG_PPC64 |
fe1952fc | 1871 | /* Called with hard IRQs off */ |
0e37739b | 1872 | void notrace __ppc64_runlatch_on(void) |
cb2c9b27 | 1873 | { |
fe1952fc | 1874 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1875 | unsigned long ctrl; |
1876 | ||
fe1952fc BH |
1877 | ctrl = mfspr(SPRN_CTRLF); |
1878 | ctrl |= CTRL_RUNLATCH; | |
1879 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1880 | |
fae2e0fb | 1881 | ti->local_flags |= _TLF_RUNLATCH; |
cb2c9b27 AB |
1882 | } |
1883 | ||
fe1952fc | 1884 | /* Called with hard IRQs off */ |
0e37739b | 1885 | void notrace __ppc64_runlatch_off(void) |
cb2c9b27 | 1886 | { |
fe1952fc | 1887 | struct thread_info *ti = current_thread_info(); |
cb2c9b27 AB |
1888 | unsigned long ctrl; |
1889 | ||
fae2e0fb | 1890 | ti->local_flags &= ~_TLF_RUNLATCH; |
cb2c9b27 | 1891 | |
4138d653 AB |
1892 | ctrl = mfspr(SPRN_CTRLF); |
1893 | ctrl &= ~CTRL_RUNLATCH; | |
1894 | mtspr(SPRN_CTRLT, ctrl); | |
cb2c9b27 | 1895 | } |
fe1952fc | 1896 | #endif /* CONFIG_PPC64 */ |
f6a61680 | 1897 | |
d839088c AB |
1898 | unsigned long arch_align_stack(unsigned long sp) |
1899 | { | |
1900 | if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space) | |
1901 | sp -= get_random_int() & ~PAGE_MASK; | |
1902 | return sp & ~0xf; | |
1903 | } | |
912f9ee2 AB |
1904 | |
1905 | static inline unsigned long brk_rnd(void) | |
1906 | { | |
1907 | unsigned long rnd = 0; | |
1908 | ||
1909 | /* 8MB for 32bit, 1GB for 64bit */ | |
1910 | if (is_32bit_task()) | |
5ef11c35 | 1911 | rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT))); |
912f9ee2 | 1912 | else |
5ef11c35 | 1913 | rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT))); |
912f9ee2 AB |
1914 | |
1915 | return rnd << PAGE_SHIFT; | |
1916 | } | |
1917 | ||
1918 | unsigned long arch_randomize_brk(struct mm_struct *mm) | |
1919 | { | |
8bbde7a7 AB |
1920 | unsigned long base = mm->brk; |
1921 | unsigned long ret; | |
1922 | ||
ce7a35c7 | 1923 | #ifdef CONFIG_PPC_STD_MMU_64 |
8bbde7a7 AB |
1924 | /* |
1925 | * If we are using 1TB segments and we are allowed to randomise | |
1926 | * the heap, we can put it above 1TB so it is backed by a 1TB | |
1927 | * segment. Otherwise the heap will be in the bottom 1TB | |
1928 | * which always uses 256MB segments and this may result in a | |
1929 | * performance penalty. | |
1930 | */ | |
1931 | if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T)) | |
1932 | base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T); | |
1933 | #endif | |
1934 | ||
1935 | ret = PAGE_ALIGN(base + brk_rnd()); | |
912f9ee2 AB |
1936 | |
1937 | if (ret < mm->brk) | |
1938 | return mm->brk; | |
1939 | ||
1940 | return ret; | |
1941 | } | |
501cb16d | 1942 |