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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
4f72c427 | 25 | #include <linux/tracehook.h> |
3caf06c6 | 26 | #include <linux/elf.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
ea9c102c DW |
30 | #include <linux/seccomp.h> |
31 | #include <linux/audit.h> | |
02424d89 | 32 | #include <trace/syscall.h> |
5aae8a53 P |
33 | #include <linux/hw_breakpoint.h> |
34 | #include <linux/perf_event.h> | |
22ecbe8d | 35 | #include <linux/context_tracking.h> |
1da177e4 LT |
36 | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
ae3a197e | 40 | #include <asm/switch_to.h> |
21a62902 | 41 | |
02424d89 IM |
42 | #define CREATE_TRACE_POINTS |
43 | #include <trace/events/syscalls.h> | |
44 | ||
359e4284 MS |
45 | /* |
46 | * The parameter save area on the stack is used to store arguments being passed | |
47 | * to callee function and is located at fixed offset from stack pointer. | |
48 | */ | |
49 | #ifdef CONFIG_PPC32 | |
50 | #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ | |
51 | #else /* CONFIG_PPC32 */ | |
52 | #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ | |
53 | #endif | |
54 | ||
55 | struct pt_regs_offset { | |
56 | const char *name; | |
57 | int offset; | |
58 | }; | |
59 | ||
60 | #define STR(s) #s /* convert to string */ | |
61 | #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} | |
62 | #define GPR_OFFSET_NAME(num) \ | |
343c3327 | 63 | {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \ |
359e4284 MS |
64 | {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} |
65 | #define REG_OFFSET_END {.name = NULL, .offset = 0} | |
66 | ||
67 | static const struct pt_regs_offset regoffset_table[] = { | |
68 | GPR_OFFSET_NAME(0), | |
69 | GPR_OFFSET_NAME(1), | |
70 | GPR_OFFSET_NAME(2), | |
71 | GPR_OFFSET_NAME(3), | |
72 | GPR_OFFSET_NAME(4), | |
73 | GPR_OFFSET_NAME(5), | |
74 | GPR_OFFSET_NAME(6), | |
75 | GPR_OFFSET_NAME(7), | |
76 | GPR_OFFSET_NAME(8), | |
77 | GPR_OFFSET_NAME(9), | |
78 | GPR_OFFSET_NAME(10), | |
79 | GPR_OFFSET_NAME(11), | |
80 | GPR_OFFSET_NAME(12), | |
81 | GPR_OFFSET_NAME(13), | |
82 | GPR_OFFSET_NAME(14), | |
83 | GPR_OFFSET_NAME(15), | |
84 | GPR_OFFSET_NAME(16), | |
85 | GPR_OFFSET_NAME(17), | |
86 | GPR_OFFSET_NAME(18), | |
87 | GPR_OFFSET_NAME(19), | |
88 | GPR_OFFSET_NAME(20), | |
89 | GPR_OFFSET_NAME(21), | |
90 | GPR_OFFSET_NAME(22), | |
91 | GPR_OFFSET_NAME(23), | |
92 | GPR_OFFSET_NAME(24), | |
93 | GPR_OFFSET_NAME(25), | |
94 | GPR_OFFSET_NAME(26), | |
95 | GPR_OFFSET_NAME(27), | |
96 | GPR_OFFSET_NAME(28), | |
97 | GPR_OFFSET_NAME(29), | |
98 | GPR_OFFSET_NAME(30), | |
99 | GPR_OFFSET_NAME(31), | |
100 | REG_OFFSET_NAME(nip), | |
101 | REG_OFFSET_NAME(msr), | |
102 | REG_OFFSET_NAME(ctr), | |
103 | REG_OFFSET_NAME(link), | |
104 | REG_OFFSET_NAME(xer), | |
105 | REG_OFFSET_NAME(ccr), | |
106 | #ifdef CONFIG_PPC64 | |
107 | REG_OFFSET_NAME(softe), | |
108 | #else | |
109 | REG_OFFSET_NAME(mq), | |
110 | #endif | |
111 | REG_OFFSET_NAME(trap), | |
112 | REG_OFFSET_NAME(dar), | |
113 | REG_OFFSET_NAME(dsisr), | |
114 | REG_OFFSET_END, | |
115 | }; | |
116 | ||
117 | /** | |
118 | * regs_query_register_offset() - query register offset from its name | |
119 | * @name: the name of a register | |
120 | * | |
121 | * regs_query_register_offset() returns the offset of a register in struct | |
122 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
123 | */ | |
124 | int regs_query_register_offset(const char *name) | |
125 | { | |
126 | const struct pt_regs_offset *roff; | |
127 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
128 | if (!strcmp(roff->name, name)) | |
129 | return roff->offset; | |
130 | return -EINVAL; | |
131 | } | |
132 | ||
133 | /** | |
134 | * regs_query_register_name() - query register name from its offset | |
135 | * @offset: the offset of a register in struct pt_regs. | |
136 | * | |
137 | * regs_query_register_name() returns the name of a register from its | |
138 | * offset in struct pt_regs. If the @offset is invalid, this returns NULL; | |
139 | */ | |
140 | const char *regs_query_register_name(unsigned int offset) | |
141 | { | |
142 | const struct pt_regs_offset *roff; | |
143 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
144 | if (roff->offset == offset) | |
145 | return roff->name; | |
146 | return NULL; | |
147 | } | |
148 | ||
abd06505 BH |
149 | /* |
150 | * does not yet catch signals sent when the child dies. | |
151 | * in exit.c or in signal.c. | |
152 | */ | |
153 | ||
154 | /* | |
155 | * Set of msr bits that gdb can change on behalf of a process. | |
156 | */ | |
172ae2e7 | 157 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
abd06505 | 158 | #define MSR_DEBUGCHANGE 0 |
1da177e4 | 159 | #else |
abd06505 | 160 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 161 | #endif |
acd89828 | 162 | |
1da177e4 | 163 | /* |
abd06505 | 164 | * Max register writeable via put_reg |
1da177e4 | 165 | */ |
abd06505 BH |
166 | #ifdef CONFIG_PPC32 |
167 | #define PT_MAX_PUT_REG PT_MQ | |
168 | #else | |
169 | #define PT_MAX_PUT_REG PT_CCR | |
170 | #endif | |
1da177e4 | 171 | |
26f77130 RM |
172 | static unsigned long get_user_msr(struct task_struct *task) |
173 | { | |
174 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
175 | } | |
176 | ||
177 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
178 | { | |
179 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
180 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
181 | return 0; | |
182 | } | |
183 | ||
1715a826 | 184 | #ifdef CONFIG_PPC64 |
ee4a3916 | 185 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 | 186 | { |
ee4a3916 AK |
187 | *data = task->thread.dscr; |
188 | return 0; | |
1715a826 AK |
189 | } |
190 | ||
191 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
192 | { | |
193 | task->thread.dscr = dscr; | |
194 | task->thread.dscr_inherit = 1; | |
195 | return 0; | |
196 | } | |
197 | #else | |
ee4a3916 | 198 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 AK |
199 | { |
200 | return -EIO; | |
201 | } | |
202 | ||
203 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
204 | { | |
205 | return -EIO; | |
206 | } | |
207 | #endif | |
208 | ||
26f77130 RM |
209 | /* |
210 | * We prevent mucking around with the reserved area of trap | |
211 | * which are used internally by the kernel. | |
212 | */ | |
213 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
214 | { | |
215 | task->thread.regs->trap = trap & 0xfff0; | |
216 | return 0; | |
217 | } | |
218 | ||
865418d8 BH |
219 | /* |
220 | * Get contents of register REGNO in task TASK. | |
221 | */ | |
ee4a3916 | 222 | int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data) |
865418d8 | 223 | { |
ee4a3916 | 224 | if ((task->thread.regs == NULL) || !data) |
865418d8 BH |
225 | return -EIO; |
226 | ||
ee4a3916 AK |
227 | if (regno == PT_MSR) { |
228 | *data = get_user_msr(task); | |
229 | return 0; | |
230 | } | |
865418d8 | 231 | |
1715a826 | 232 | if (regno == PT_DSCR) |
ee4a3916 | 233 | return get_user_dscr(task, data); |
1715a826 | 234 | |
ee4a3916 AK |
235 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) { |
236 | *data = ((unsigned long *)task->thread.regs)[regno]; | |
237 | return 0; | |
238 | } | |
865418d8 BH |
239 | |
240 | return -EIO; | |
241 | } | |
242 | ||
243 | /* | |
244 | * Write contents of register REGNO in task TASK. | |
245 | */ | |
246 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
247 | { | |
248 | if (task->thread.regs == NULL) | |
249 | return -EIO; | |
250 | ||
26f77130 RM |
251 | if (regno == PT_MSR) |
252 | return set_user_msr(task, data); | |
253 | if (regno == PT_TRAP) | |
254 | return set_user_trap(task, data); | |
1715a826 AK |
255 | if (regno == PT_DSCR) |
256 | return set_user_dscr(task, data); | |
26f77130 RM |
257 | |
258 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
259 | ((unsigned long *)task->thread.regs)[regno] = data; |
260 | return 0; | |
261 | } | |
262 | return -EIO; | |
263 | } | |
264 | ||
44dd3f50 RM |
265 | static int gpr_get(struct task_struct *target, const struct user_regset *regset, |
266 | unsigned int pos, unsigned int count, | |
267 | void *kbuf, void __user *ubuf) | |
268 | { | |
a71f5d5d | 269 | int i, ret; |
44dd3f50 RM |
270 | |
271 | if (target->thread.regs == NULL) | |
272 | return -EIO; | |
273 | ||
a71f5d5d MW |
274 | if (!FULL_REGS(target->thread.regs)) { |
275 | /* We have a partial register set. Fill 14-31 with bogus values */ | |
276 | for (i = 14; i < 32; i++) | |
277 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
278 | } | |
44dd3f50 RM |
279 | |
280 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
281 | target->thread.regs, | |
282 | 0, offsetof(struct pt_regs, msr)); | |
283 | if (!ret) { | |
284 | unsigned long msr = get_user_msr(target); | |
285 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
286 | offsetof(struct pt_regs, msr), | |
287 | offsetof(struct pt_regs, msr) + | |
288 | sizeof(msr)); | |
289 | } | |
290 | ||
291 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
292 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
293 | ||
294 | if (!ret) | |
295 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
296 | &target->thread.regs->orig_gpr3, | |
297 | offsetof(struct pt_regs, orig_gpr3), | |
298 | sizeof(struct pt_regs)); | |
299 | if (!ret) | |
300 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
301 | sizeof(struct pt_regs), -1); | |
302 | ||
303 | return ret; | |
304 | } | |
305 | ||
306 | static int gpr_set(struct task_struct *target, const struct user_regset *regset, | |
307 | unsigned int pos, unsigned int count, | |
308 | const void *kbuf, const void __user *ubuf) | |
309 | { | |
310 | unsigned long reg; | |
311 | int ret; | |
312 | ||
313 | if (target->thread.regs == NULL) | |
314 | return -EIO; | |
315 | ||
316 | CHECK_FULL_REGS(target->thread.regs); | |
317 | ||
318 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
319 | target->thread.regs, | |
320 | 0, PT_MSR * sizeof(reg)); | |
321 | ||
322 | if (!ret && count > 0) { | |
323 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
324 | PT_MSR * sizeof(reg), | |
325 | (PT_MSR + 1) * sizeof(reg)); | |
326 | if (!ret) | |
327 | ret = set_user_msr(target, reg); | |
328 | } | |
329 | ||
330 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
331 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
332 | ||
333 | if (!ret) | |
334 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
335 | &target->thread.regs->orig_gpr3, | |
336 | PT_ORIG_R3 * sizeof(reg), | |
337 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
338 | ||
339 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
340 | ret = user_regset_copyin_ignore( | |
341 | &pos, &count, &kbuf, &ubuf, | |
342 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
343 | PT_TRAP * sizeof(reg)); | |
344 | ||
345 | if (!ret && count > 0) { | |
346 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
347 | PT_TRAP * sizeof(reg), | |
348 | (PT_TRAP + 1) * sizeof(reg)); | |
349 | if (!ret) | |
350 | ret = set_user_trap(target, reg); | |
351 | } | |
352 | ||
353 | if (!ret) | |
354 | ret = user_regset_copyin_ignore( | |
355 | &pos, &count, &kbuf, &ubuf, | |
356 | (PT_TRAP + 1) * sizeof(reg), -1); | |
357 | ||
358 | return ret; | |
359 | } | |
865418d8 | 360 | |
f65255e8 RM |
361 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
362 | unsigned int pos, unsigned int count, | |
363 | void *kbuf, void __user *ubuf) | |
364 | { | |
c6e6771b | 365 | #ifdef CONFIG_VSX |
de79f7b9 | 366 | u64 buf[33]; |
c6e6771b MN |
367 | int i; |
368 | #endif | |
f65255e8 RM |
369 | flush_fp_to_thread(target); |
370 | ||
c6e6771b MN |
371 | #ifdef CONFIG_VSX |
372 | /* copy to local buffer then write that out */ | |
373 | for (i = 0; i < 32 ; i++) | |
374 | buf[i] = target->thread.TS_FPR(i); | |
de79f7b9 | 375 | buf[32] = target->thread.fp_state.fpscr; |
c6e6771b MN |
376 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); |
377 | ||
378 | #else | |
de79f7b9 | 379 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 380 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
381 | |
382 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 383 | &target->thread.fp_state, 0, -1); |
c6e6771b | 384 | #endif |
f65255e8 RM |
385 | } |
386 | ||
387 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, | |
388 | unsigned int pos, unsigned int count, | |
389 | const void *kbuf, const void __user *ubuf) | |
390 | { | |
c6e6771b | 391 | #ifdef CONFIG_VSX |
de79f7b9 | 392 | u64 buf[33]; |
c6e6771b MN |
393 | int i; |
394 | #endif | |
f65255e8 RM |
395 | flush_fp_to_thread(target); |
396 | ||
c6e6771b MN |
397 | #ifdef CONFIG_VSX |
398 | /* copy to local buffer then write that out */ | |
399 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
400 | if (i) | |
401 | return i; | |
402 | for (i = 0; i < 32 ; i++) | |
403 | target->thread.TS_FPR(i) = buf[i]; | |
de79f7b9 | 404 | target->thread.fp_state.fpscr = buf[32]; |
c6e6771b MN |
405 | return 0; |
406 | #else | |
de79f7b9 | 407 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 408 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
409 | |
410 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 411 | &target->thread.fp_state, 0, -1); |
c6e6771b | 412 | #endif |
f65255e8 RM |
413 | } |
414 | ||
865418d8 BH |
415 | #ifdef CONFIG_ALTIVEC |
416 | /* | |
417 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
418 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
419 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
420 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
421 | * vrsave as the first word (offset 0) within the quadword. | |
422 | * | |
423 | * This definition of the VMX state is compatible with the current PPC32 | |
424 | * ptrace interface. This allows signal handling and ptrace to use the | |
425 | * same structures. This also simplifies the implementation of a bi-arch | |
426 | * (combined (32- and 64-bit) gdb. | |
427 | */ | |
428 | ||
3caf06c6 RM |
429 | static int vr_active(struct task_struct *target, |
430 | const struct user_regset *regset) | |
431 | { | |
432 | flush_altivec_to_thread(target); | |
433 | return target->thread.used_vr ? regset->n : 0; | |
434 | } | |
435 | ||
436 | static int vr_get(struct task_struct *target, const struct user_regset *regset, | |
437 | unsigned int pos, unsigned int count, | |
438 | void *kbuf, void __user *ubuf) | |
439 | { | |
440 | int ret; | |
441 | ||
442 | flush_altivec_to_thread(target); | |
443 | ||
de79f7b9 PM |
444 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
445 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 RM |
446 | |
447 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 448 | &target->thread.vr_state, 0, |
3caf06c6 RM |
449 | 33 * sizeof(vector128)); |
450 | if (!ret) { | |
451 | /* | |
452 | * Copy out only the low-order word of vrsave. | |
453 | */ | |
454 | union { | |
455 | elf_vrreg_t reg; | |
456 | u32 word; | |
457 | } vrsave; | |
458 | memset(&vrsave, 0, sizeof(vrsave)); | |
459 | vrsave.word = target->thread.vrsave; | |
460 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, | |
461 | 33 * sizeof(vector128), -1); | |
462 | } | |
463 | ||
464 | return ret; | |
465 | } | |
466 | ||
467 | static int vr_set(struct task_struct *target, const struct user_regset *regset, | |
468 | unsigned int pos, unsigned int count, | |
469 | const void *kbuf, const void __user *ubuf) | |
470 | { | |
471 | int ret; | |
472 | ||
473 | flush_altivec_to_thread(target); | |
474 | ||
de79f7b9 PM |
475 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
476 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 RM |
477 | |
478 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 PM |
479 | &target->thread.vr_state, 0, |
480 | 33 * sizeof(vector128)); | |
3caf06c6 RM |
481 | if (!ret && count > 0) { |
482 | /* | |
483 | * We use only the first word of vrsave. | |
484 | */ | |
485 | union { | |
486 | elf_vrreg_t reg; | |
487 | u32 word; | |
488 | } vrsave; | |
489 | memset(&vrsave, 0, sizeof(vrsave)); | |
490 | vrsave.word = target->thread.vrsave; | |
491 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, | |
492 | 33 * sizeof(vector128), -1); | |
493 | if (!ret) | |
494 | target->thread.vrsave = vrsave.word; | |
495 | } | |
496 | ||
497 | return ret; | |
498 | } | |
865418d8 BH |
499 | #endif /* CONFIG_ALTIVEC */ |
500 | ||
ce48b210 MN |
501 | #ifdef CONFIG_VSX |
502 | /* | |
503 | * Currently to set and and get all the vsx state, you need to call | |
25985edc | 504 | * the fp and VMX calls as well. This only get/sets the lower 32 |
ce48b210 MN |
505 | * 128bit VSX registers. |
506 | */ | |
507 | ||
508 | static int vsr_active(struct task_struct *target, | |
509 | const struct user_regset *regset) | |
510 | { | |
511 | flush_vsx_to_thread(target); | |
512 | return target->thread.used_vsr ? regset->n : 0; | |
513 | } | |
514 | ||
515 | static int vsr_get(struct task_struct *target, const struct user_regset *regset, | |
516 | unsigned int pos, unsigned int count, | |
517 | void *kbuf, void __user *ubuf) | |
518 | { | |
de79f7b9 | 519 | u64 buf[32]; |
f3e909c2 | 520 | int ret, i; |
ce48b210 MN |
521 | |
522 | flush_vsx_to_thread(target); | |
523 | ||
f3e909c2 | 524 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 525 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; |
ce48b210 | 526 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
f3e909c2 | 527 | buf, 0, 32 * sizeof(double)); |
ce48b210 MN |
528 | |
529 | return ret; | |
530 | } | |
531 | ||
532 | static int vsr_set(struct task_struct *target, const struct user_regset *regset, | |
533 | unsigned int pos, unsigned int count, | |
534 | const void *kbuf, const void __user *ubuf) | |
535 | { | |
de79f7b9 | 536 | u64 buf[32]; |
f3e909c2 | 537 | int ret,i; |
ce48b210 MN |
538 | |
539 | flush_vsx_to_thread(target); | |
540 | ||
541 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
f3e909c2 MN |
542 | buf, 0, 32 * sizeof(double)); |
543 | for (i = 0; i < 32 ; i++) | |
de79f7b9 | 544 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
f3e909c2 | 545 | |
ce48b210 MN |
546 | |
547 | return ret; | |
548 | } | |
549 | #endif /* CONFIG_VSX */ | |
550 | ||
865418d8 BH |
551 | #ifdef CONFIG_SPE |
552 | ||
553 | /* | |
554 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
555 | * | |
556 | * struct { | |
557 | * u32 evr[32]; | |
558 | * u64 acc; | |
559 | * u32 spefscr; | |
560 | * } | |
561 | */ | |
562 | ||
a4e4b175 RM |
563 | static int evr_active(struct task_struct *target, |
564 | const struct user_regset *regset) | |
865418d8 | 565 | { |
a4e4b175 RM |
566 | flush_spe_to_thread(target); |
567 | return target->thread.used_spe ? regset->n : 0; | |
568 | } | |
865418d8 | 569 | |
a4e4b175 RM |
570 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
571 | unsigned int pos, unsigned int count, | |
572 | void *kbuf, void __user *ubuf) | |
573 | { | |
574 | int ret; | |
865418d8 | 575 | |
a4e4b175 | 576 | flush_spe_to_thread(target); |
865418d8 | 577 | |
a4e4b175 RM |
578 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
579 | &target->thread.evr, | |
580 | 0, sizeof(target->thread.evr)); | |
865418d8 | 581 | |
a4e4b175 RM |
582 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
583 | offsetof(struct thread_struct, spefscr)); | |
584 | ||
585 | if (!ret) | |
586 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
587 | &target->thread.acc, | |
588 | sizeof(target->thread.evr), -1); | |
589 | ||
590 | return ret; | |
591 | } | |
592 | ||
593 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
594 | unsigned int pos, unsigned int count, | |
595 | const void *kbuf, const void __user *ubuf) | |
596 | { | |
597 | int ret; | |
598 | ||
599 | flush_spe_to_thread(target); | |
600 | ||
601 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
602 | &target->thread.evr, | |
603 | 0, sizeof(target->thread.evr)); | |
865418d8 | 604 | |
a4e4b175 RM |
605 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
606 | offsetof(struct thread_struct, spefscr)); | |
607 | ||
608 | if (!ret) | |
609 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
610 | &target->thread.acc, | |
611 | sizeof(target->thread.evr), -1); | |
612 | ||
613 | return ret; | |
865418d8 | 614 | } |
865418d8 BH |
615 | #endif /* CONFIG_SPE */ |
616 | ||
617 | ||
80fdf470 RM |
618 | /* |
619 | * These are our native regset flavors. | |
620 | */ | |
621 | enum powerpc_regset { | |
622 | REGSET_GPR, | |
623 | REGSET_FPR, | |
624 | #ifdef CONFIG_ALTIVEC | |
625 | REGSET_VMX, | |
626 | #endif | |
ce48b210 MN |
627 | #ifdef CONFIG_VSX |
628 | REGSET_VSX, | |
629 | #endif | |
80fdf470 RM |
630 | #ifdef CONFIG_SPE |
631 | REGSET_SPE, | |
632 | #endif | |
633 | }; | |
634 | ||
635 | static const struct user_regset native_regsets[] = { | |
636 | [REGSET_GPR] = { | |
637 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
638 | .size = sizeof(long), .align = sizeof(long), | |
639 | .get = gpr_get, .set = gpr_set | |
640 | }, | |
641 | [REGSET_FPR] = { | |
642 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
643 | .size = sizeof(double), .align = sizeof(double), | |
644 | .get = fpr_get, .set = fpr_set | |
645 | }, | |
646 | #ifdef CONFIG_ALTIVEC | |
647 | [REGSET_VMX] = { | |
648 | .core_note_type = NT_PPC_VMX, .n = 34, | |
649 | .size = sizeof(vector128), .align = sizeof(vector128), | |
650 | .active = vr_active, .get = vr_get, .set = vr_set | |
651 | }, | |
652 | #endif | |
ce48b210 MN |
653 | #ifdef CONFIG_VSX |
654 | [REGSET_VSX] = { | |
f3e909c2 MN |
655 | .core_note_type = NT_PPC_VSX, .n = 32, |
656 | .size = sizeof(double), .align = sizeof(double), | |
ce48b210 MN |
657 | .active = vsr_active, .get = vsr_get, .set = vsr_set |
658 | }, | |
659 | #endif | |
80fdf470 RM |
660 | #ifdef CONFIG_SPE |
661 | [REGSET_SPE] = { | |
a0b38b4e | 662 | .core_note_type = NT_PPC_SPE, .n = 35, |
80fdf470 RM |
663 | .size = sizeof(u32), .align = sizeof(u32), |
664 | .active = evr_active, .get = evr_get, .set = evr_set | |
665 | }, | |
666 | #endif | |
667 | }; | |
668 | ||
669 | static const struct user_regset_view user_ppc_native_view = { | |
670 | .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, | |
671 | .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) | |
672 | }; | |
673 | ||
fa8f5cb0 RM |
674 | #ifdef CONFIG_PPC64 |
675 | #include <linux/compat.h> | |
676 | ||
677 | static int gpr32_get(struct task_struct *target, | |
678 | const struct user_regset *regset, | |
679 | unsigned int pos, unsigned int count, | |
680 | void *kbuf, void __user *ubuf) | |
681 | { | |
682 | const unsigned long *regs = &target->thread.regs->gpr[0]; | |
683 | compat_ulong_t *k = kbuf; | |
684 | compat_ulong_t __user *u = ubuf; | |
685 | compat_ulong_t reg; | |
a71f5d5d | 686 | int i; |
fa8f5cb0 RM |
687 | |
688 | if (target->thread.regs == NULL) | |
689 | return -EIO; | |
690 | ||
a71f5d5d MW |
691 | if (!FULL_REGS(target->thread.regs)) { |
692 | /* We have a partial register set. Fill 14-31 with bogus values */ | |
693 | for (i = 14; i < 32; i++) | |
694 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
695 | } | |
fa8f5cb0 RM |
696 | |
697 | pos /= sizeof(reg); | |
698 | count /= sizeof(reg); | |
699 | ||
700 | if (kbuf) | |
701 | for (; count > 0 && pos < PT_MSR; --count) | |
702 | *k++ = regs[pos++]; | |
703 | else | |
704 | for (; count > 0 && pos < PT_MSR; --count) | |
705 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
706 | return -EFAULT; | |
707 | ||
708 | if (count > 0 && pos == PT_MSR) { | |
709 | reg = get_user_msr(target); | |
710 | if (kbuf) | |
711 | *k++ = reg; | |
712 | else if (__put_user(reg, u++)) | |
713 | return -EFAULT; | |
714 | ++pos; | |
715 | --count; | |
716 | } | |
717 | ||
718 | if (kbuf) | |
719 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
720 | *k++ = regs[pos++]; | |
721 | else | |
722 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
723 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
724 | return -EFAULT; | |
725 | ||
726 | kbuf = k; | |
727 | ubuf = u; | |
728 | pos *= sizeof(reg); | |
729 | count *= sizeof(reg); | |
730 | return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
731 | PT_REGS_COUNT * sizeof(reg), -1); | |
732 | } | |
733 | ||
734 | static int gpr32_set(struct task_struct *target, | |
735 | const struct user_regset *regset, | |
736 | unsigned int pos, unsigned int count, | |
737 | const void *kbuf, const void __user *ubuf) | |
738 | { | |
739 | unsigned long *regs = &target->thread.regs->gpr[0]; | |
740 | const compat_ulong_t *k = kbuf; | |
741 | const compat_ulong_t __user *u = ubuf; | |
742 | compat_ulong_t reg; | |
743 | ||
744 | if (target->thread.regs == NULL) | |
745 | return -EIO; | |
746 | ||
747 | CHECK_FULL_REGS(target->thread.regs); | |
748 | ||
749 | pos /= sizeof(reg); | |
750 | count /= sizeof(reg); | |
751 | ||
752 | if (kbuf) | |
753 | for (; count > 0 && pos < PT_MSR; --count) | |
754 | regs[pos++] = *k++; | |
755 | else | |
756 | for (; count > 0 && pos < PT_MSR; --count) { | |
757 | if (__get_user(reg, u++)) | |
758 | return -EFAULT; | |
759 | regs[pos++] = reg; | |
760 | } | |
761 | ||
762 | ||
763 | if (count > 0 && pos == PT_MSR) { | |
764 | if (kbuf) | |
765 | reg = *k++; | |
766 | else if (__get_user(reg, u++)) | |
767 | return -EFAULT; | |
768 | set_user_msr(target, reg); | |
769 | ++pos; | |
770 | --count; | |
771 | } | |
772 | ||
c2372eb9 | 773 | if (kbuf) { |
fa8f5cb0 RM |
774 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) |
775 | regs[pos++] = *k++; | |
c2372eb9 RM |
776 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
777 | ++k; | |
778 | } else { | |
fa8f5cb0 RM |
779 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { |
780 | if (__get_user(reg, u++)) | |
781 | return -EFAULT; | |
782 | regs[pos++] = reg; | |
783 | } | |
c2372eb9 RM |
784 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
785 | if (__get_user(reg, u++)) | |
786 | return -EFAULT; | |
787 | } | |
fa8f5cb0 RM |
788 | |
789 | if (count > 0 && pos == PT_TRAP) { | |
790 | if (kbuf) | |
791 | reg = *k++; | |
792 | else if (__get_user(reg, u++)) | |
793 | return -EFAULT; | |
794 | set_user_trap(target, reg); | |
795 | ++pos; | |
796 | --count; | |
797 | } | |
798 | ||
799 | kbuf = k; | |
800 | ubuf = u; | |
801 | pos *= sizeof(reg); | |
802 | count *= sizeof(reg); | |
803 | return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, | |
804 | (PT_TRAP + 1) * sizeof(reg), -1); | |
805 | } | |
806 | ||
807 | /* | |
808 | * These are the regset flavors matching the CONFIG_PPC32 native set. | |
809 | */ | |
810 | static const struct user_regset compat_regsets[] = { | |
811 | [REGSET_GPR] = { | |
812 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
813 | .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), | |
814 | .get = gpr32_get, .set = gpr32_set | |
815 | }, | |
816 | [REGSET_FPR] = { | |
817 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
818 | .size = sizeof(double), .align = sizeof(double), | |
819 | .get = fpr_get, .set = fpr_set | |
820 | }, | |
821 | #ifdef CONFIG_ALTIVEC | |
822 | [REGSET_VMX] = { | |
823 | .core_note_type = NT_PPC_VMX, .n = 34, | |
824 | .size = sizeof(vector128), .align = sizeof(vector128), | |
825 | .active = vr_active, .get = vr_get, .set = vr_set | |
826 | }, | |
827 | #endif | |
828 | #ifdef CONFIG_SPE | |
829 | [REGSET_SPE] = { | |
24f1a849 | 830 | .core_note_type = NT_PPC_SPE, .n = 35, |
fa8f5cb0 RM |
831 | .size = sizeof(u32), .align = sizeof(u32), |
832 | .active = evr_active, .get = evr_get, .set = evr_set | |
833 | }, | |
834 | #endif | |
835 | }; | |
836 | ||
837 | static const struct user_regset_view user_ppc_compat_view = { | |
838 | .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, | |
839 | .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) | |
840 | }; | |
841 | #endif /* CONFIG_PPC64 */ | |
842 | ||
80fdf470 RM |
843 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
844 | { | |
fa8f5cb0 RM |
845 | #ifdef CONFIG_PPC64 |
846 | if (test_tsk_thread_flag(task, TIF_32BIT)) | |
847 | return &user_ppc_compat_view; | |
848 | #endif | |
80fdf470 RM |
849 | return &user_ppc_native_view; |
850 | } | |
851 | ||
852 | ||
2a84b0d7 | 853 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
854 | { |
855 | struct pt_regs *regs = task->thread.regs; | |
856 | ||
857 | if (regs != NULL) { | |
172ae2e7 | 858 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
859 | task->thread.debug.dbcr0 &= ~DBCR0_BT; |
860 | task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
865418d8 BH |
861 | regs->msr |= MSR_DE; |
862 | #else | |
ec097c84 | 863 | regs->msr &= ~MSR_BE; |
865418d8 BH |
864 | regs->msr |= MSR_SE; |
865 | #endif | |
866 | } | |
867 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
868 | } | |
869 | ||
ec097c84 RM |
870 | void user_enable_block_step(struct task_struct *task) |
871 | { | |
872 | struct pt_regs *regs = task->thread.regs; | |
873 | ||
874 | if (regs != NULL) { | |
172ae2e7 | 875 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
876 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
877 | task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; | |
ec097c84 RM |
878 | regs->msr |= MSR_DE; |
879 | #else | |
880 | regs->msr &= ~MSR_SE; | |
881 | regs->msr |= MSR_BE; | |
882 | #endif | |
883 | } | |
884 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
885 | } | |
886 | ||
2a84b0d7 | 887 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
888 | { |
889 | struct pt_regs *regs = task->thread.regs; | |
890 | ||
891 | if (regs != NULL) { | |
172ae2e7 | 892 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
893 | /* |
894 | * The logic to disable single stepping should be as | |
895 | * simple as turning off the Instruction Complete flag. | |
896 | * And, after doing so, if all debug flags are off, turn | |
897 | * off DBCR0(IDM) and MSR(DE) .... Torez | |
898 | */ | |
682775b8 | 899 | task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT); |
3bffb652 DK |
900 | /* |
901 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | |
902 | */ | |
51ae8d4a BB |
903 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
904 | task->thread.debug.dbcr1)) { | |
3bffb652 DK |
905 | /* |
906 | * All debug events were off..... | |
907 | */ | |
51ae8d4a | 908 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
28477fb1 DK |
909 | regs->msr &= ~MSR_DE; |
910 | } | |
865418d8 | 911 | #else |
ec097c84 | 912 | regs->msr &= ~(MSR_SE | MSR_BE); |
865418d8 BH |
913 | #endif |
914 | } | |
915 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
916 | } | |
917 | ||
5aae8a53 | 918 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
a8b0ca17 | 919 | void ptrace_triggered(struct perf_event *bp, |
5aae8a53 P |
920 | struct perf_sample_data *data, struct pt_regs *regs) |
921 | { | |
922 | struct perf_event_attr attr; | |
923 | ||
924 | /* | |
925 | * Disable the breakpoint request here since ptrace has defined a | |
926 | * one-shot behaviour for breakpoint exceptions in PPC64. | |
927 | * The SIGTRAP signal is generated automatically for us in do_dabr(). | |
928 | * We don't have to do anything about that here | |
929 | */ | |
930 | attr = bp->attr; | |
931 | attr.disabled = true; | |
932 | modify_user_hw_breakpoint(bp, &attr); | |
933 | } | |
934 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
935 | ||
e51df2c1 | 936 | static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
abd06505 BH |
937 | unsigned long data) |
938 | { | |
5aae8a53 P |
939 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
940 | int ret; | |
941 | struct thread_struct *thread = &(task->thread); | |
942 | struct perf_event *bp; | |
943 | struct perf_event_attr attr; | |
944 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e MN |
945 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
946 | struct arch_hw_breakpoint hw_brk; | |
947 | #endif | |
5aae8a53 | 948 | |
d6a61bfc LM |
949 | /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
950 | * For embedded processors we support one DAC and no IAC's at the | |
951 | * moment. | |
952 | */ | |
abd06505 BH |
953 | if (addr > 0) |
954 | return -EINVAL; | |
955 | ||
2325f0a0 | 956 | /* The bottom 3 bits in dabr are flags */ |
abd06505 BH |
957 | if ((data & ~0x7UL) >= TASK_SIZE) |
958 | return -EIO; | |
959 | ||
172ae2e7 | 960 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
d6a61bfc LM |
961 | /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. |
962 | * It was assumed, on previous implementations, that 3 bits were | |
963 | * passed together with the data address, fitting the design of the | |
964 | * DABR register, as follows: | |
965 | * | |
966 | * bit 0: Read flag | |
967 | * bit 1: Write flag | |
968 | * bit 2: Breakpoint translation | |
969 | * | |
970 | * Thus, we use them here as so. | |
971 | */ | |
972 | ||
973 | /* Ensure breakpoint translation bit is set */ | |
9422de3e | 974 | if (data && !(data & HW_BRK_TYPE_TRANSLATE)) |
abd06505 | 975 | return -EIO; |
9422de3e MN |
976 | hw_brk.address = data & (~HW_BRK_TYPE_DABR); |
977 | hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL; | |
978 | hw_brk.len = 8; | |
5aae8a53 P |
979 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
980 | bp = thread->ptrace_bps[0]; | |
9422de3e | 981 | if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) { |
5aae8a53 P |
982 | if (bp) { |
983 | unregister_hw_breakpoint(bp); | |
984 | thread->ptrace_bps[0] = NULL; | |
985 | } | |
986 | return 0; | |
987 | } | |
988 | if (bp) { | |
989 | attr = bp->attr; | |
9422de3e MN |
990 | attr.bp_addr = hw_brk.address; |
991 | arch_bp_generic_fields(hw_brk.type, &attr.bp_type); | |
a53fd61a AP |
992 | |
993 | /* Enable breakpoint */ | |
994 | attr.disabled = false; | |
995 | ||
5aae8a53 | 996 | ret = modify_user_hw_breakpoint(bp, &attr); |
925f83c0 | 997 | if (ret) { |
5aae8a53 | 998 | return ret; |
925f83c0 | 999 | } |
5aae8a53 | 1000 | thread->ptrace_bps[0] = bp; |
9422de3e | 1001 | thread->hw_brk = hw_brk; |
5aae8a53 P |
1002 | return 0; |
1003 | } | |
1004 | ||
1005 | /* Create a new breakpoint request if one doesn't exist already */ | |
1006 | hw_breakpoint_init(&attr); | |
9422de3e MN |
1007 | attr.bp_addr = hw_brk.address; |
1008 | arch_bp_generic_fields(hw_brk.type, | |
1009 | &attr.bp_type); | |
5aae8a53 P |
1010 | |
1011 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
4dc0da86 | 1012 | ptrace_triggered, NULL, task); |
5aae8a53 P |
1013 | if (IS_ERR(bp)) { |
1014 | thread->ptrace_bps[0] = NULL; | |
1015 | return PTR_ERR(bp); | |
1016 | } | |
1017 | ||
1018 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 1019 | task->thread.hw_brk = hw_brk; |
172ae2e7 | 1020 | #else /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc LM |
1021 | /* As described above, it was assumed 3 bits were passed with the data |
1022 | * address, but we will assume only the mode bits will be passed | |
1023 | * as to not cause alignment restrictions for DAC-based processors. | |
1024 | */ | |
1025 | ||
1026 | /* DAC's hold the whole address without any mode flags */ | |
51ae8d4a | 1027 | task->thread.debug.dac1 = data & ~0x3UL; |
3bffb652 | 1028 | |
51ae8d4a | 1029 | if (task->thread.debug.dac1 == 0) { |
3bffb652 | 1030 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
51ae8d4a BB |
1031 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1032 | task->thread.debug.dbcr1)) { | |
3bffb652 | 1033 | task->thread.regs->msr &= ~MSR_DE; |
51ae8d4a | 1034 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 | 1035 | } |
d6a61bfc LM |
1036 | return 0; |
1037 | } | |
1038 | ||
1039 | /* Read or Write bits must be set */ | |
1040 | ||
1041 | if (!(data & 0x3UL)) | |
1042 | return -EINVAL; | |
1043 | ||
1044 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | |
1045 | register */ | |
51ae8d4a | 1046 | task->thread.debug.dbcr0 |= DBCR0_IDM; |
d6a61bfc LM |
1047 | |
1048 | /* Check for write and read flags and set DBCR0 | |
1049 | accordingly */ | |
3bffb652 | 1050 | dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); |
d6a61bfc | 1051 | if (data & 0x1UL) |
3bffb652 | 1052 | dbcr_dac(task) |= DBCR_DAC1R; |
d6a61bfc | 1053 | if (data & 0x2UL) |
3bffb652 | 1054 | dbcr_dac(task) |= DBCR_DAC1W; |
d6a61bfc | 1055 | task->thread.regs->msr |= MSR_DE; |
172ae2e7 | 1056 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
abd06505 BH |
1057 | return 0; |
1058 | } | |
abd06505 | 1059 | |
1da177e4 LT |
1060 | /* |
1061 | * Called by kernel/ptrace.c when detaching.. | |
1062 | * | |
1063 | * Make sure single step bits etc are not set. | |
1064 | */ | |
1065 | void ptrace_disable(struct task_struct *child) | |
1066 | { | |
1067 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 1068 | user_disable_single_step(child); |
1da177e4 LT |
1069 | } |
1070 | ||
3bffb652 | 1071 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
84295dfc | 1072 | static long set_instruction_bp(struct task_struct *child, |
3bffb652 DK |
1073 | struct ppc_hw_breakpoint *bp_info) |
1074 | { | |
1075 | int slot; | |
51ae8d4a BB |
1076 | int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
1077 | int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); | |
1078 | int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); | |
1079 | int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); | |
3bffb652 DK |
1080 | |
1081 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1082 | slot2_in_use = 1; | |
1083 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1084 | slot4_in_use = 1; | |
1085 | ||
1086 | if (bp_info->addr >= TASK_SIZE) | |
1087 | return -EIO; | |
1088 | ||
1089 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { | |
1090 | ||
1091 | /* Make sure range is valid. */ | |
1092 | if (bp_info->addr2 >= TASK_SIZE) | |
1093 | return -EIO; | |
1094 | ||
1095 | /* We need a pair of IAC regsisters */ | |
1096 | if ((!slot1_in_use) && (!slot2_in_use)) { | |
1097 | slot = 1; | |
51ae8d4a BB |
1098 | child->thread.debug.iac1 = bp_info->addr; |
1099 | child->thread.debug.iac2 = bp_info->addr2; | |
1100 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
1101 | if (bp_info->addr_mode == |
1102 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1103 | dbcr_iac_range(child) |= DBCR_IAC12X; | |
1104 | else | |
1105 | dbcr_iac_range(child) |= DBCR_IAC12I; | |
1106 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1107 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | |
1108 | slot = 3; | |
51ae8d4a BB |
1109 | child->thread.debug.iac3 = bp_info->addr; |
1110 | child->thread.debug.iac4 = bp_info->addr2; | |
1111 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
1112 | if (bp_info->addr_mode == |
1113 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1114 | dbcr_iac_range(child) |= DBCR_IAC34X; | |
1115 | else | |
1116 | dbcr_iac_range(child) |= DBCR_IAC34I; | |
1117 | #endif | |
1118 | } else | |
1119 | return -ENOSPC; | |
1120 | } else { | |
1121 | /* We only need one. If possible leave a pair free in | |
1122 | * case a range is needed later | |
1123 | */ | |
1124 | if (!slot1_in_use) { | |
1125 | /* | |
1126 | * Don't use iac1 if iac1-iac2 are free and either | |
1127 | * iac3 or iac4 (but not both) are free | |
1128 | */ | |
1129 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | |
1130 | slot = 1; | |
51ae8d4a BB |
1131 | child->thread.debug.iac1 = bp_info->addr; |
1132 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
1133 | goto out; |
1134 | } | |
1135 | } | |
1136 | if (!slot2_in_use) { | |
1137 | slot = 2; | |
51ae8d4a BB |
1138 | child->thread.debug.iac2 = bp_info->addr; |
1139 | child->thread.debug.dbcr0 |= DBCR0_IAC2; | |
3bffb652 DK |
1140 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
1141 | } else if (!slot3_in_use) { | |
1142 | slot = 3; | |
51ae8d4a BB |
1143 | child->thread.debug.iac3 = bp_info->addr; |
1144 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
1145 | } else if (!slot4_in_use) { |
1146 | slot = 4; | |
51ae8d4a BB |
1147 | child->thread.debug.iac4 = bp_info->addr; |
1148 | child->thread.debug.dbcr0 |= DBCR0_IAC4; | |
3bffb652 DK |
1149 | #endif |
1150 | } else | |
1151 | return -ENOSPC; | |
1152 | } | |
1153 | out: | |
51ae8d4a | 1154 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
1155 | child->thread.regs->msr |= MSR_DE; |
1156 | ||
1157 | return slot; | |
1158 | } | |
1159 | ||
1160 | static int del_instruction_bp(struct task_struct *child, int slot) | |
1161 | { | |
1162 | switch (slot) { | |
1163 | case 1: | |
51ae8d4a | 1164 | if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
3bffb652 DK |
1165 | return -ENOENT; |
1166 | ||
1167 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | |
1168 | /* address range - clear slots 1 & 2 */ | |
51ae8d4a | 1169 | child->thread.debug.iac2 = 0; |
3bffb652 DK |
1170 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
1171 | } | |
51ae8d4a BB |
1172 | child->thread.debug.iac1 = 0; |
1173 | child->thread.debug.dbcr0 &= ~DBCR0_IAC1; | |
3bffb652 DK |
1174 | break; |
1175 | case 2: | |
51ae8d4a | 1176 | if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
3bffb652 DK |
1177 | return -ENOENT; |
1178 | ||
1179 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1180 | /* used in a range */ | |
1181 | return -EINVAL; | |
51ae8d4a BB |
1182 | child->thread.debug.iac2 = 0; |
1183 | child->thread.debug.dbcr0 &= ~DBCR0_IAC2; | |
3bffb652 DK |
1184 | break; |
1185 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1186 | case 3: | |
51ae8d4a | 1187 | if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
3bffb652 DK |
1188 | return -ENOENT; |
1189 | ||
1190 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | |
1191 | /* address range - clear slots 3 & 4 */ | |
51ae8d4a | 1192 | child->thread.debug.iac4 = 0; |
3bffb652 DK |
1193 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
1194 | } | |
51ae8d4a BB |
1195 | child->thread.debug.iac3 = 0; |
1196 | child->thread.debug.dbcr0 &= ~DBCR0_IAC3; | |
3bffb652 DK |
1197 | break; |
1198 | case 4: | |
51ae8d4a | 1199 | if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
3bffb652 DK |
1200 | return -ENOENT; |
1201 | ||
1202 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1203 | /* Used in a range */ | |
1204 | return -EINVAL; | |
51ae8d4a BB |
1205 | child->thread.debug.iac4 = 0; |
1206 | child->thread.debug.dbcr0 &= ~DBCR0_IAC4; | |
3bffb652 DK |
1207 | break; |
1208 | #endif | |
1209 | default: | |
1210 | return -EINVAL; | |
1211 | } | |
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |
1216 | { | |
1217 | int byte_enable = | |
1218 | (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) | |
1219 | & 0xf; | |
1220 | int condition_mode = | |
1221 | bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; | |
1222 | int slot; | |
1223 | ||
1224 | if (byte_enable && (condition_mode == 0)) | |
1225 | return -EINVAL; | |
1226 | ||
1227 | if (bp_info->addr >= TASK_SIZE) | |
1228 | return -EIO; | |
1229 | ||
1230 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { | |
1231 | slot = 1; | |
1232 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1233 | dbcr_dac(child) |= DBCR_DAC1R; | |
1234 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1235 | dbcr_dac(child) |= DBCR_DAC1W; | |
51ae8d4a | 1236 | child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
3bffb652 DK |
1237 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1238 | if (byte_enable) { | |
51ae8d4a | 1239 | child->thread.debug.dvc1 = |
3bffb652 | 1240 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 1241 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
1242 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | |
1243 | (condition_mode << DBCR2_DVC1M_SHIFT)); | |
1244 | } | |
1245 | #endif | |
1246 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1247 | } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
3bffb652 DK |
1248 | /* Both dac1 and dac2 are part of a range */ |
1249 | return -ENOSPC; | |
1250 | #endif | |
1251 | } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { | |
1252 | slot = 2; | |
1253 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1254 | dbcr_dac(child) |= DBCR_DAC2R; | |
1255 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1256 | dbcr_dac(child) |= DBCR_DAC2W; | |
51ae8d4a | 1257 | child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
3bffb652 DK |
1258 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1259 | if (byte_enable) { | |
51ae8d4a | 1260 | child->thread.debug.dvc2 = |
3bffb652 | 1261 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 1262 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
1263 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | |
1264 | (condition_mode << DBCR2_DVC2M_SHIFT)); | |
1265 | } | |
1266 | #endif | |
1267 | } else | |
1268 | return -ENOSPC; | |
51ae8d4a | 1269 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
1270 | child->thread.regs->msr |= MSR_DE; |
1271 | ||
1272 | return slot + 4; | |
1273 | } | |
1274 | ||
1275 | static int del_dac(struct task_struct *child, int slot) | |
1276 | { | |
1277 | if (slot == 1) { | |
30124d11 | 1278 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
3bffb652 DK |
1279 | return -ENOENT; |
1280 | ||
51ae8d4a | 1281 | child->thread.debug.dac1 = 0; |
3bffb652 DK |
1282 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
1283 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a BB |
1284 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
1285 | child->thread.debug.dac2 = 0; | |
1286 | child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; | |
3bffb652 | 1287 | } |
51ae8d4a | 1288 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
3bffb652 DK |
1289 | #endif |
1290 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 1291 | child->thread.debug.dvc1 = 0; |
3bffb652 DK |
1292 | #endif |
1293 | } else if (slot == 2) { | |
30124d11 | 1294 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
3bffb652 DK |
1295 | return -ENOENT; |
1296 | ||
1297 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1298 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
3bffb652 DK |
1299 | /* Part of a range */ |
1300 | return -EINVAL; | |
51ae8d4a | 1301 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
3bffb652 DK |
1302 | #endif |
1303 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 1304 | child->thread.debug.dvc2 = 0; |
3bffb652 | 1305 | #endif |
51ae8d4a | 1306 | child->thread.debug.dac2 = 0; |
3bffb652 DK |
1307 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
1308 | } else | |
1309 | return -EINVAL; | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ | |
1314 | ||
1315 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1316 | static int set_dac_range(struct task_struct *child, | |
1317 | struct ppc_hw_breakpoint *bp_info) | |
1318 | { | |
1319 | int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; | |
1320 | ||
1321 | /* We don't allow range watchpoints to be used with DVC */ | |
1322 | if (bp_info->condition_mode) | |
1323 | return -EINVAL; | |
1324 | ||
1325 | /* | |
1326 | * Best effort to verify the address range. The user/supervisor bits | |
1327 | * prevent trapping in kernel space, but let's fail on an obvious bad | |
1328 | * range. The simple test on the mask is not fool-proof, and any | |
1329 | * exclusive range will spill over into kernel space. | |
1330 | */ | |
1331 | if (bp_info->addr >= TASK_SIZE) | |
1332 | return -EIO; | |
1333 | if (mode == PPC_BREAKPOINT_MODE_MASK) { | |
1334 | /* | |
1335 | * dac2 is a bitmask. Don't allow a mask that makes a | |
1336 | * kernel space address from a valid dac1 value | |
1337 | */ | |
1338 | if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) | |
1339 | return -EIO; | |
1340 | } else { | |
1341 | /* | |
1342 | * For range breakpoints, addr2 must also be a valid address | |
1343 | */ | |
1344 | if (bp_info->addr2 >= TASK_SIZE) | |
1345 | return -EIO; | |
1346 | } | |
1347 | ||
51ae8d4a | 1348 | if (child->thread.debug.dbcr0 & |
3bffb652 DK |
1349 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
1350 | return -ENOSPC; | |
1351 | ||
1352 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
51ae8d4a | 1353 | child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
3bffb652 | 1354 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
51ae8d4a BB |
1355 | child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
1356 | child->thread.debug.dac1 = bp_info->addr; | |
1357 | child->thread.debug.dac2 = bp_info->addr2; | |
3bffb652 | 1358 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
51ae8d4a | 1359 | child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
3bffb652 | 1360 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
51ae8d4a | 1361 | child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
3bffb652 | 1362 | else /* PPC_BREAKPOINT_MODE_MASK */ |
51ae8d4a | 1363 | child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
3bffb652 DK |
1364 | child->thread.regs->msr |= MSR_DE; |
1365 | ||
1366 | return 5; | |
1367 | } | |
1368 | #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ | |
1369 | ||
3162d92d DK |
1370 | static long ppc_set_hwdebug(struct task_struct *child, |
1371 | struct ppc_hw_breakpoint *bp_info) | |
1372 | { | |
6c7a2856 P |
1373 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1374 | int len = 0; | |
1375 | struct thread_struct *thread = &(child->thread); | |
1376 | struct perf_event *bp; | |
1377 | struct perf_event_attr attr; | |
1378 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
4dfbf290 | 1379 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e | 1380 | struct arch_hw_breakpoint brk; |
4dfbf290 AS |
1381 | #endif |
1382 | ||
3bffb652 DK |
1383 | if (bp_info->version != 1) |
1384 | return -ENOTSUPP; | |
1385 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
1386 | /* | |
1387 | * Check for invalid flags and combinations | |
1388 | */ | |
1389 | if ((bp_info->trigger_type == 0) || | |
1390 | (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | | |
1391 | PPC_BREAKPOINT_TRIGGER_RW)) || | |
1392 | (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || | |
1393 | (bp_info->condition_mode & | |
1394 | ~(PPC_BREAKPOINT_CONDITION_MODE | | |
1395 | PPC_BREAKPOINT_CONDITION_BE_ALL))) | |
1396 | return -EINVAL; | |
1397 | #if CONFIG_PPC_ADV_DEBUG_DVCS == 0 | |
1398 | if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
1399 | return -EINVAL; | |
1400 | #endif | |
1401 | ||
1402 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { | |
1403 | if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || | |
1404 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
1405 | return -EINVAL; | |
84295dfc | 1406 | return set_instruction_bp(child, bp_info); |
3bffb652 DK |
1407 | } |
1408 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) | |
1409 | return set_dac(child, bp_info); | |
1410 | ||
1411 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1412 | return set_dac_range(child, bp_info); | |
1413 | #else | |
1414 | return -EINVAL; | |
1415 | #endif | |
1416 | #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ | |
3162d92d | 1417 | /* |
3bffb652 | 1418 | * We only support one data breakpoint |
3162d92d | 1419 | */ |
4dfbf290 AS |
1420 | if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || |
1421 | (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || | |
4dfbf290 | 1422 | bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
3162d92d DK |
1423 | return -EINVAL; |
1424 | ||
3162d92d DK |
1425 | if ((unsigned long)bp_info->addr >= TASK_SIZE) |
1426 | return -EIO; | |
1427 | ||
9422de3e MN |
1428 | brk.address = bp_info->addr & ~7UL; |
1429 | brk.type = HW_BRK_TYPE_TRANSLATE; | |
2bb78efa | 1430 | brk.len = 8; |
4dfbf290 | 1431 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
9422de3e | 1432 | brk.type |= HW_BRK_TYPE_READ; |
4dfbf290 | 1433 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
9422de3e | 1434 | brk.type |= HW_BRK_TYPE_WRITE; |
6c7a2856 | 1435 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6c7a2856 P |
1436 | /* |
1437 | * Check if the request is for 'range' breakpoints. We can | |
1438 | * support it if range < 8 bytes. | |
1439 | */ | |
6961ed96 | 1440 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
6c7a2856 | 1441 | len = bp_info->addr2 - bp_info->addr; |
6961ed96 | 1442 | else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) |
b0b0aa9c | 1443 | len = 1; |
6961ed96 | 1444 | else |
6c7a2856 | 1445 | return -EINVAL; |
6c7a2856 | 1446 | bp = thread->ptrace_bps[0]; |
6961ed96 | 1447 | if (bp) |
6c7a2856 | 1448 | return -ENOSPC; |
6c7a2856 P |
1449 | |
1450 | /* Create a new breakpoint request if one doesn't exist already */ | |
1451 | hw_breakpoint_init(&attr); | |
1452 | attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN; | |
1453 | attr.bp_len = len; | |
9422de3e | 1454 | arch_bp_generic_fields(brk.type, &attr.bp_type); |
6c7a2856 P |
1455 | |
1456 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
1457 | ptrace_triggered, NULL, child); | |
1458 | if (IS_ERR(bp)) { | |
1459 | thread->ptrace_bps[0] = NULL; | |
6c7a2856 P |
1460 | return PTR_ERR(bp); |
1461 | } | |
1462 | ||
6c7a2856 P |
1463 | return 1; |
1464 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1465 | ||
1466 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) | |
1467 | return -EINVAL; | |
1468 | ||
9422de3e | 1469 | if (child->thread.hw_brk.address) |
6c7a2856 | 1470 | return -ENOSPC; |
4dfbf290 | 1471 | |
9422de3e | 1472 | child->thread.hw_brk = brk; |
3bffb652 | 1473 | |
3162d92d | 1474 | return 1; |
3bffb652 | 1475 | #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ |
3162d92d DK |
1476 | } |
1477 | ||
ec1b33dc | 1478 | static long ppc_del_hwdebug(struct task_struct *child, long data) |
3162d92d | 1479 | { |
6c7a2856 P |
1480 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1481 | int ret = 0; | |
1482 | struct thread_struct *thread = &(child->thread); | |
1483 | struct perf_event *bp; | |
1484 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
3bffb652 DK |
1485 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1486 | int rc; | |
1487 | ||
1488 | if (data <= 4) | |
1489 | rc = del_instruction_bp(child, (int)data); | |
1490 | else | |
1491 | rc = del_dac(child, (int)data - 4); | |
1492 | ||
1493 | if (!rc) { | |
51ae8d4a BB |
1494 | if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
1495 | child->thread.debug.dbcr1)) { | |
1496 | child->thread.debug.dbcr0 &= ~DBCR0_IDM; | |
3bffb652 DK |
1497 | child->thread.regs->msr &= ~MSR_DE; |
1498 | } | |
1499 | } | |
1500 | return rc; | |
1501 | #else | |
3162d92d DK |
1502 | if (data != 1) |
1503 | return -EINVAL; | |
6c7a2856 P |
1504 | |
1505 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
6c7a2856 P |
1506 | bp = thread->ptrace_bps[0]; |
1507 | if (bp) { | |
1508 | unregister_hw_breakpoint(bp); | |
1509 | thread->ptrace_bps[0] = NULL; | |
1510 | } else | |
1511 | ret = -ENOENT; | |
6c7a2856 P |
1512 | return ret; |
1513 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 1514 | if (child->thread.hw_brk.address == 0) |
3162d92d DK |
1515 | return -ENOENT; |
1516 | ||
9422de3e MN |
1517 | child->thread.hw_brk.address = 0; |
1518 | child->thread.hw_brk.type = 0; | |
6c7a2856 | 1519 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1520 | |
3162d92d | 1521 | return 0; |
3bffb652 | 1522 | #endif |
3162d92d DK |
1523 | } |
1524 | ||
9b05a69e NK |
1525 | long arch_ptrace(struct task_struct *child, long request, |
1526 | unsigned long addr, unsigned long data) | |
1da177e4 | 1527 | { |
1da177e4 | 1528 | int ret = -EPERM; |
f68d2048 NK |
1529 | void __user *datavp = (void __user *) data; |
1530 | unsigned long __user *datalp = datavp; | |
1da177e4 | 1531 | |
1da177e4 | 1532 | switch (request) { |
1da177e4 | 1533 | /* read the word at location addr in the USER area. */ |
1da177e4 LT |
1534 | case PTRACE_PEEKUSR: { |
1535 | unsigned long index, tmp; | |
1536 | ||
1537 | ret = -EIO; | |
1538 | /* convert to index and check */ | |
e8a30302 | 1539 | #ifdef CONFIG_PPC32 |
9b05a69e | 1540 | index = addr >> 2; |
e8a30302 SR |
1541 | if ((addr & 3) || (index > PT_FPSCR) |
1542 | || (child->thread.regs == NULL)) | |
1543 | #else | |
9b05a69e | 1544 | index = addr >> 3; |
e8a30302 SR |
1545 | if ((addr & 7) || (index > PT_FPSCR)) |
1546 | #endif | |
1da177e4 LT |
1547 | break; |
1548 | ||
1549 | CHECK_FULL_REGS(child->thread.regs); | |
1550 | if (index < PT_FPR0) { | |
ee4a3916 AK |
1551 | ret = ptrace_get_reg(child, (int) index, &tmp); |
1552 | if (ret) | |
1553 | break; | |
1da177e4 | 1554 | } else { |
e69b742a BH |
1555 | unsigned int fpidx = index - PT_FPR0; |
1556 | ||
e8a30302 | 1557 | flush_fp_to_thread(child); |
e69b742a | 1558 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 1559 | memcpy(&tmp, &child->thread.TS_FPR(fpidx), |
87fec051 | 1560 | sizeof(long)); |
e69b742a | 1561 | else |
de79f7b9 | 1562 | tmp = child->thread.fp_state.fpscr; |
1da177e4 | 1563 | } |
f68d2048 | 1564 | ret = put_user(tmp, datalp); |
1da177e4 LT |
1565 | break; |
1566 | } | |
1567 | ||
1da177e4 LT |
1568 | /* write the word at location addr in the USER area */ |
1569 | case PTRACE_POKEUSR: { | |
1570 | unsigned long index; | |
1571 | ||
1572 | ret = -EIO; | |
1573 | /* convert to index and check */ | |
e8a30302 | 1574 | #ifdef CONFIG_PPC32 |
9b05a69e | 1575 | index = addr >> 2; |
e8a30302 SR |
1576 | if ((addr & 3) || (index > PT_FPSCR) |
1577 | || (child->thread.regs == NULL)) | |
1578 | #else | |
9b05a69e | 1579 | index = addr >> 3; |
e8a30302 SR |
1580 | if ((addr & 7) || (index > PT_FPSCR)) |
1581 | #endif | |
1da177e4 LT |
1582 | break; |
1583 | ||
1584 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 1585 | if (index < PT_FPR0) { |
865418d8 | 1586 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 1587 | } else { |
e69b742a BH |
1588 | unsigned int fpidx = index - PT_FPR0; |
1589 | ||
e8a30302 | 1590 | flush_fp_to_thread(child); |
e69b742a | 1591 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 1592 | memcpy(&child->thread.TS_FPR(fpidx), &data, |
87fec051 | 1593 | sizeof(long)); |
e69b742a | 1594 | else |
de79f7b9 | 1595 | child->thread.fp_state.fpscr = data; |
1da177e4 LT |
1596 | ret = 0; |
1597 | } | |
1598 | break; | |
1599 | } | |
1600 | ||
3162d92d DK |
1601 | case PPC_PTRACE_GETHWDBGINFO: { |
1602 | struct ppc_debug_info dbginfo; | |
1603 | ||
1604 | dbginfo.version = 1; | |
3bffb652 DK |
1605 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1606 | dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; | |
1607 | dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; | |
1608 | dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; | |
1609 | dbginfo.data_bp_alignment = 4; | |
1610 | dbginfo.sizeof_condition = 4; | |
1611 | dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | | |
1612 | PPC_DEBUG_FEATURE_INSN_BP_MASK; | |
1613 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1614 | dbginfo.features |= | |
1615 | PPC_DEBUG_FEATURE_DATA_BP_RANGE | | |
1616 | PPC_DEBUG_FEATURE_DATA_BP_MASK; | |
1617 | #endif | |
1618 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
3162d92d DK |
1619 | dbginfo.num_instruction_bps = 0; |
1620 | dbginfo.num_data_bps = 1; | |
1621 | dbginfo.num_condition_regs = 0; | |
1622 | #ifdef CONFIG_PPC64 | |
1623 | dbginfo.data_bp_alignment = 8; | |
1624 | #else | |
1625 | dbginfo.data_bp_alignment = 4; | |
1626 | #endif | |
1627 | dbginfo.sizeof_condition = 0; | |
6c7a2856 P |
1628 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1629 | dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE; | |
517b7314 MN |
1630 | if (cpu_has_feature(CPU_FTR_DAWR)) |
1631 | dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR; | |
6c7a2856 | 1632 | #else |
3162d92d | 1633 | dbginfo.features = 0; |
6c7a2856 | 1634 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1635 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
3162d92d | 1636 | |
f68d2048 | 1637 | if (!access_ok(VERIFY_WRITE, datavp, |
3162d92d DK |
1638 | sizeof(struct ppc_debug_info))) |
1639 | return -EFAULT; | |
f68d2048 NK |
1640 | ret = __copy_to_user(datavp, &dbginfo, |
1641 | sizeof(struct ppc_debug_info)) ? | |
3162d92d DK |
1642 | -EFAULT : 0; |
1643 | break; | |
1644 | } | |
1645 | ||
1646 | case PPC_PTRACE_SETHWDEBUG: { | |
1647 | struct ppc_hw_breakpoint bp_info; | |
1648 | ||
f68d2048 | 1649 | if (!access_ok(VERIFY_READ, datavp, |
3162d92d DK |
1650 | sizeof(struct ppc_hw_breakpoint))) |
1651 | return -EFAULT; | |
f68d2048 | 1652 | ret = __copy_from_user(&bp_info, datavp, |
3162d92d DK |
1653 | sizeof(struct ppc_hw_breakpoint)) ? |
1654 | -EFAULT : 0; | |
1655 | if (!ret) | |
1656 | ret = ppc_set_hwdebug(child, &bp_info); | |
1657 | break; | |
1658 | } | |
1659 | ||
1660 | case PPC_PTRACE_DELHWDEBUG: { | |
ec1b33dc | 1661 | ret = ppc_del_hwdebug(child, data); |
3162d92d DK |
1662 | break; |
1663 | } | |
1664 | ||
e8a30302 | 1665 | case PTRACE_GET_DEBUGREG: { |
9422de3e MN |
1666 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
1667 | unsigned long dabr_fake; | |
1668 | #endif | |
e8a30302 SR |
1669 | ret = -EINVAL; |
1670 | /* We only support one DABR and no IABRS at the moment */ | |
1671 | if (addr > 0) | |
1672 | break; | |
3bffb652 | 1673 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a | 1674 | ret = put_user(child->thread.debug.dac1, datalp); |
3bffb652 | 1675 | #else |
9422de3e MN |
1676 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
1677 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); | |
1678 | ret = put_user(dabr_fake, datalp); | |
3bffb652 | 1679 | #endif |
e8a30302 SR |
1680 | break; |
1681 | } | |
1682 | ||
1683 | case PTRACE_SET_DEBUGREG: | |
1684 | ret = ptrace_set_debugreg(child, addr, data); | |
1685 | break; | |
e8a30302 | 1686 | |
e17666ba BH |
1687 | #ifdef CONFIG_PPC64 |
1688 | case PTRACE_GETREGS64: | |
1689 | #endif | |
c391cd00 RM |
1690 | case PTRACE_GETREGS: /* Get all pt_regs from the child. */ |
1691 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1692 | REGSET_GPR, | |
1693 | 0, sizeof(struct pt_regs), | |
f68d2048 | 1694 | datavp); |
e8a30302 | 1695 | |
e17666ba BH |
1696 | #ifdef CONFIG_PPC64 |
1697 | case PTRACE_SETREGS64: | |
1698 | #endif | |
c391cd00 RM |
1699 | case PTRACE_SETREGS: /* Set all gp regs in the child. */ |
1700 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1701 | REGSET_GPR, | |
1702 | 0, sizeof(struct pt_regs), | |
f68d2048 | 1703 | datavp); |
c391cd00 RM |
1704 | |
1705 | case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ | |
1706 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1707 | REGSET_FPR, | |
1708 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 1709 | datavp); |
c391cd00 RM |
1710 | |
1711 | case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ | |
1712 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1713 | REGSET_FPR, | |
1714 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 1715 | datavp); |
e8a30302 | 1716 | |
1da177e4 LT |
1717 | #ifdef CONFIG_ALTIVEC |
1718 | case PTRACE_GETVRREGS: | |
c391cd00 RM |
1719 | return copy_regset_to_user(child, &user_ppc_native_view, |
1720 | REGSET_VMX, | |
1721 | 0, (33 * sizeof(vector128) + | |
1722 | sizeof(u32)), | |
f68d2048 | 1723 | datavp); |
1da177e4 LT |
1724 | |
1725 | case PTRACE_SETVRREGS: | |
c391cd00 RM |
1726 | return copy_regset_from_user(child, &user_ppc_native_view, |
1727 | REGSET_VMX, | |
1728 | 0, (33 * sizeof(vector128) + | |
1729 | sizeof(u32)), | |
f68d2048 | 1730 | datavp); |
1da177e4 | 1731 | #endif |
ce48b210 MN |
1732 | #ifdef CONFIG_VSX |
1733 | case PTRACE_GETVSRREGS: | |
1734 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1735 | REGSET_VSX, | |
1ac42ef8 | 1736 | 0, 32 * sizeof(double), |
f68d2048 | 1737 | datavp); |
ce48b210 MN |
1738 | |
1739 | case PTRACE_SETVSRREGS: | |
1740 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1741 | REGSET_VSX, | |
1ac42ef8 | 1742 | 0, 32 * sizeof(double), |
f68d2048 | 1743 | datavp); |
ce48b210 | 1744 | #endif |
1da177e4 LT |
1745 | #ifdef CONFIG_SPE |
1746 | case PTRACE_GETEVRREGS: | |
1747 | /* Get the child spe register state. */ | |
c391cd00 RM |
1748 | return copy_regset_to_user(child, &user_ppc_native_view, |
1749 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 1750 | datavp); |
1da177e4 LT |
1751 | |
1752 | case PTRACE_SETEVRREGS: | |
1753 | /* Set the child spe register state. */ | |
c391cd00 RM |
1754 | return copy_regset_from_user(child, &user_ppc_native_view, |
1755 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 1756 | datavp); |
1da177e4 LT |
1757 | #endif |
1758 | ||
1759 | default: | |
1760 | ret = ptrace_request(child, request, addr, data); | |
1761 | break; | |
1762 | } | |
1da177e4 LT |
1763 | return ret; |
1764 | } | |
1765 | ||
2449acc5 ME |
1766 | #ifdef CONFIG_SECCOMP |
1767 | static int do_seccomp(struct pt_regs *regs) | |
1768 | { | |
1769 | if (!test_thread_flag(TIF_SECCOMP)) | |
1770 | return 0; | |
1771 | ||
1772 | /* | |
1773 | * The ABI we present to seccomp tracers is that r3 contains | |
1774 | * the syscall return value and orig_gpr3 contains the first | |
1775 | * syscall parameter. This is different to the ptrace ABI where | |
1776 | * both r3 and orig_gpr3 contain the first syscall parameter. | |
1777 | */ | |
1778 | regs->gpr[3] = -ENOSYS; | |
1779 | ||
1780 | /* | |
1781 | * We use the __ version here because we have already checked | |
1782 | * TIF_SECCOMP. If this fails, there is nothing left to do, we | |
1783 | * have already loaded -ENOSYS into r3, or seccomp has put | |
1784 | * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). | |
1785 | */ | |
1786 | if (__secure_computing()) | |
1787 | return -1; | |
1788 | ||
1789 | /* | |
1790 | * The syscall was allowed by seccomp, restore the register | |
1791 | * state to what ptrace and audit expect. | |
1792 | * Note that we use orig_gpr3, which means a seccomp tracer can | |
1793 | * modify the first syscall parameter (in orig_gpr3) and also | |
1794 | * allow the syscall to proceed. | |
1795 | */ | |
1796 | regs->gpr[3] = regs->orig_gpr3; | |
1797 | ||
1798 | return 0; | |
1799 | } | |
1800 | #else | |
1801 | static inline int do_seccomp(struct pt_regs *regs) { return 0; } | |
1802 | #endif /* CONFIG_SECCOMP */ | |
1803 | ||
d3837414 ME |
1804 | /** |
1805 | * do_syscall_trace_enter() - Do syscall tracing on kernel entry. | |
1806 | * @regs: the pt_regs of the task to trace (current) | |
1807 | * | |
1808 | * Performs various types of tracing on syscall entry. This includes seccomp, | |
1809 | * ptrace, syscall tracepoints and audit. | |
1810 | * | |
1811 | * The pt_regs are potentially visible to userspace via ptrace, so their | |
1812 | * contents is ABI. | |
1813 | * | |
1814 | * One or more of the tracers may modify the contents of pt_regs, in particular | |
1815 | * to modify arguments or even the syscall number itself. | |
1816 | * | |
1817 | * It's also possible that a tracer can choose to reject the system call. In | |
1818 | * that case this function will return an illegal syscall number, and will put | |
1819 | * an appropriate return value in regs->r3. | |
1820 | * | |
1821 | * Return: the (possibly changed) syscall number. | |
4f72c427 RM |
1822 | */ |
1823 | long do_syscall_trace_enter(struct pt_regs *regs) | |
1da177e4 | 1824 | { |
d3837414 | 1825 | bool abort = false; |
ea9c102c | 1826 | |
22ecbe8d LZ |
1827 | user_exit(); |
1828 | ||
2449acc5 ME |
1829 | if (do_seccomp(regs)) |
1830 | return -1; | |
e8a30302 | 1831 | |
d3837414 | 1832 | if (test_thread_flag(TIF_SYSCALL_TRACE)) { |
4f72c427 | 1833 | /* |
d3837414 ME |
1834 | * The tracer may decide to abort the syscall, if so tracehook |
1835 | * will return !0. Note that the tracer may also just change | |
1836 | * regs->gpr[0] to an invalid syscall number, that is handled | |
1837 | * below on the exit path. | |
4f72c427 | 1838 | */ |
d3837414 ME |
1839 | abort = tracehook_report_syscall_entry(regs) != 0; |
1840 | } | |
ea9c102c | 1841 | |
02424d89 IM |
1842 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
1843 | trace_sys_enter(regs, regs->gpr[0]); | |
1844 | ||
cfcd1705 | 1845 | #ifdef CONFIG_PPC64 |
b05d8447 | 1846 | if (!is_32bit_task()) |
91397401 | 1847 | audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], |
b05d8447 EP |
1848 | regs->gpr[5], regs->gpr[6]); |
1849 | else | |
e8a30302 | 1850 | #endif |
91397401 | 1851 | audit_syscall_entry(regs->gpr[0], |
b05d8447 EP |
1852 | regs->gpr[3] & 0xffffffff, |
1853 | regs->gpr[4] & 0xffffffff, | |
1854 | regs->gpr[5] & 0xffffffff, | |
1855 | regs->gpr[6] & 0xffffffff); | |
4f72c427 | 1856 | |
d3837414 ME |
1857 | if (abort || regs->gpr[0] >= NR_syscalls) { |
1858 | /* | |
1859 | * If we are aborting explicitly, or if the syscall number is | |
1860 | * now invalid, set the return value to -ENOSYS. | |
1861 | */ | |
1862 | regs->gpr[3] = -ENOSYS; | |
1863 | return -1; | |
1864 | } | |
1865 | ||
1866 | /* Return the possibly modified but valid syscall number */ | |
1867 | return regs->gpr[0]; | |
ea9c102c DW |
1868 | } |
1869 | ||
1870 | void do_syscall_trace_leave(struct pt_regs *regs) | |
1871 | { | |
4f72c427 RM |
1872 | int step; |
1873 | ||
d7e7528b | 1874 | audit_syscall_exit(regs); |
ea9c102c | 1875 | |
02424d89 IM |
1876 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
1877 | trace_sys_exit(regs, regs->result); | |
1878 | ||
4f72c427 RM |
1879 | step = test_thread_flag(TIF_SINGLESTEP); |
1880 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) | |
1881 | tracehook_report_syscall_exit(regs, step); | |
22ecbe8d LZ |
1882 | |
1883 | user_enter(); | |
ea9c102c | 1884 | } |