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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
4f72c427 | 25 | #include <linux/tracehook.h> |
3caf06c6 | 26 | #include <linux/elf.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
ea9c102c DW |
30 | #include <linux/seccomp.h> |
31 | #include <linux/audit.h> | |
02424d89 | 32 | #include <trace/syscall.h> |
5aae8a53 P |
33 | #include <linux/hw_breakpoint.h> |
34 | #include <linux/perf_event.h> | |
22ecbe8d | 35 | #include <linux/context_tracking.h> |
1da177e4 LT |
36 | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
ae3a197e | 40 | #include <asm/switch_to.h> |
21a62902 | 41 | |
02424d89 IM |
42 | #define CREATE_TRACE_POINTS |
43 | #include <trace/events/syscalls.h> | |
44 | ||
359e4284 MS |
45 | /* |
46 | * The parameter save area on the stack is used to store arguments being passed | |
47 | * to callee function and is located at fixed offset from stack pointer. | |
48 | */ | |
49 | #ifdef CONFIG_PPC32 | |
50 | #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ | |
51 | #else /* CONFIG_PPC32 */ | |
52 | #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ | |
53 | #endif | |
54 | ||
55 | struct pt_regs_offset { | |
56 | const char *name; | |
57 | int offset; | |
58 | }; | |
59 | ||
60 | #define STR(s) #s /* convert to string */ | |
61 | #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} | |
62 | #define GPR_OFFSET_NAME(num) \ | |
343c3327 | 63 | {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \ |
359e4284 MS |
64 | {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} |
65 | #define REG_OFFSET_END {.name = NULL, .offset = 0} | |
66 | ||
67 | static const struct pt_regs_offset regoffset_table[] = { | |
68 | GPR_OFFSET_NAME(0), | |
69 | GPR_OFFSET_NAME(1), | |
70 | GPR_OFFSET_NAME(2), | |
71 | GPR_OFFSET_NAME(3), | |
72 | GPR_OFFSET_NAME(4), | |
73 | GPR_OFFSET_NAME(5), | |
74 | GPR_OFFSET_NAME(6), | |
75 | GPR_OFFSET_NAME(7), | |
76 | GPR_OFFSET_NAME(8), | |
77 | GPR_OFFSET_NAME(9), | |
78 | GPR_OFFSET_NAME(10), | |
79 | GPR_OFFSET_NAME(11), | |
80 | GPR_OFFSET_NAME(12), | |
81 | GPR_OFFSET_NAME(13), | |
82 | GPR_OFFSET_NAME(14), | |
83 | GPR_OFFSET_NAME(15), | |
84 | GPR_OFFSET_NAME(16), | |
85 | GPR_OFFSET_NAME(17), | |
86 | GPR_OFFSET_NAME(18), | |
87 | GPR_OFFSET_NAME(19), | |
88 | GPR_OFFSET_NAME(20), | |
89 | GPR_OFFSET_NAME(21), | |
90 | GPR_OFFSET_NAME(22), | |
91 | GPR_OFFSET_NAME(23), | |
92 | GPR_OFFSET_NAME(24), | |
93 | GPR_OFFSET_NAME(25), | |
94 | GPR_OFFSET_NAME(26), | |
95 | GPR_OFFSET_NAME(27), | |
96 | GPR_OFFSET_NAME(28), | |
97 | GPR_OFFSET_NAME(29), | |
98 | GPR_OFFSET_NAME(30), | |
99 | GPR_OFFSET_NAME(31), | |
100 | REG_OFFSET_NAME(nip), | |
101 | REG_OFFSET_NAME(msr), | |
102 | REG_OFFSET_NAME(ctr), | |
103 | REG_OFFSET_NAME(link), | |
104 | REG_OFFSET_NAME(xer), | |
105 | REG_OFFSET_NAME(ccr), | |
106 | #ifdef CONFIG_PPC64 | |
107 | REG_OFFSET_NAME(softe), | |
108 | #else | |
109 | REG_OFFSET_NAME(mq), | |
110 | #endif | |
111 | REG_OFFSET_NAME(trap), | |
112 | REG_OFFSET_NAME(dar), | |
113 | REG_OFFSET_NAME(dsisr), | |
114 | REG_OFFSET_END, | |
115 | }; | |
116 | ||
117 | /** | |
118 | * regs_query_register_offset() - query register offset from its name | |
119 | * @name: the name of a register | |
120 | * | |
121 | * regs_query_register_offset() returns the offset of a register in struct | |
122 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
123 | */ | |
124 | int regs_query_register_offset(const char *name) | |
125 | { | |
126 | const struct pt_regs_offset *roff; | |
127 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
128 | if (!strcmp(roff->name, name)) | |
129 | return roff->offset; | |
130 | return -EINVAL; | |
131 | } | |
132 | ||
133 | /** | |
134 | * regs_query_register_name() - query register name from its offset | |
135 | * @offset: the offset of a register in struct pt_regs. | |
136 | * | |
137 | * regs_query_register_name() returns the name of a register from its | |
138 | * offset in struct pt_regs. If the @offset is invalid, this returns NULL; | |
139 | */ | |
140 | const char *regs_query_register_name(unsigned int offset) | |
141 | { | |
142 | const struct pt_regs_offset *roff; | |
143 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
144 | if (roff->offset == offset) | |
145 | return roff->name; | |
146 | return NULL; | |
147 | } | |
148 | ||
abd06505 BH |
149 | /* |
150 | * does not yet catch signals sent when the child dies. | |
151 | * in exit.c or in signal.c. | |
152 | */ | |
153 | ||
154 | /* | |
155 | * Set of msr bits that gdb can change on behalf of a process. | |
156 | */ | |
172ae2e7 | 157 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
abd06505 | 158 | #define MSR_DEBUGCHANGE 0 |
1da177e4 | 159 | #else |
abd06505 | 160 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 161 | #endif |
acd89828 | 162 | |
1da177e4 | 163 | /* |
abd06505 | 164 | * Max register writeable via put_reg |
1da177e4 | 165 | */ |
abd06505 BH |
166 | #ifdef CONFIG_PPC32 |
167 | #define PT_MAX_PUT_REG PT_MQ | |
168 | #else | |
169 | #define PT_MAX_PUT_REG PT_CCR | |
170 | #endif | |
1da177e4 | 171 | |
26f77130 RM |
172 | static unsigned long get_user_msr(struct task_struct *task) |
173 | { | |
174 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
175 | } | |
176 | ||
177 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
178 | { | |
179 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
180 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
181 | return 0; | |
182 | } | |
183 | ||
1715a826 | 184 | #ifdef CONFIG_PPC64 |
ee4a3916 | 185 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 | 186 | { |
ee4a3916 AK |
187 | *data = task->thread.dscr; |
188 | return 0; | |
1715a826 AK |
189 | } |
190 | ||
191 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
192 | { | |
193 | task->thread.dscr = dscr; | |
194 | task->thread.dscr_inherit = 1; | |
195 | return 0; | |
196 | } | |
197 | #else | |
ee4a3916 | 198 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 AK |
199 | { |
200 | return -EIO; | |
201 | } | |
202 | ||
203 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
204 | { | |
205 | return -EIO; | |
206 | } | |
207 | #endif | |
208 | ||
26f77130 RM |
209 | /* |
210 | * We prevent mucking around with the reserved area of trap | |
211 | * which are used internally by the kernel. | |
212 | */ | |
213 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
214 | { | |
215 | task->thread.regs->trap = trap & 0xfff0; | |
216 | return 0; | |
217 | } | |
218 | ||
865418d8 BH |
219 | /* |
220 | * Get contents of register REGNO in task TASK. | |
221 | */ | |
ee4a3916 | 222 | int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data) |
865418d8 | 223 | { |
ee4a3916 | 224 | if ((task->thread.regs == NULL) || !data) |
865418d8 BH |
225 | return -EIO; |
226 | ||
ee4a3916 AK |
227 | if (regno == PT_MSR) { |
228 | *data = get_user_msr(task); | |
229 | return 0; | |
230 | } | |
865418d8 | 231 | |
1715a826 | 232 | if (regno == PT_DSCR) |
ee4a3916 | 233 | return get_user_dscr(task, data); |
1715a826 | 234 | |
ee4a3916 AK |
235 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) { |
236 | *data = ((unsigned long *)task->thread.regs)[regno]; | |
237 | return 0; | |
238 | } | |
865418d8 BH |
239 | |
240 | return -EIO; | |
241 | } | |
242 | ||
243 | /* | |
244 | * Write contents of register REGNO in task TASK. | |
245 | */ | |
246 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
247 | { | |
248 | if (task->thread.regs == NULL) | |
249 | return -EIO; | |
250 | ||
26f77130 RM |
251 | if (regno == PT_MSR) |
252 | return set_user_msr(task, data); | |
253 | if (regno == PT_TRAP) | |
254 | return set_user_trap(task, data); | |
1715a826 AK |
255 | if (regno == PT_DSCR) |
256 | return set_user_dscr(task, data); | |
26f77130 RM |
257 | |
258 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
259 | ((unsigned long *)task->thread.regs)[regno] = data; |
260 | return 0; | |
261 | } | |
262 | return -EIO; | |
263 | } | |
264 | ||
44dd3f50 RM |
265 | static int gpr_get(struct task_struct *target, const struct user_regset *regset, |
266 | unsigned int pos, unsigned int count, | |
267 | void *kbuf, void __user *ubuf) | |
268 | { | |
a71f5d5d | 269 | int i, ret; |
44dd3f50 RM |
270 | |
271 | if (target->thread.regs == NULL) | |
272 | return -EIO; | |
273 | ||
a71f5d5d MW |
274 | if (!FULL_REGS(target->thread.regs)) { |
275 | /* We have a partial register set. Fill 14-31 with bogus values */ | |
276 | for (i = 14; i < 32; i++) | |
277 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
278 | } | |
44dd3f50 RM |
279 | |
280 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
281 | target->thread.regs, | |
282 | 0, offsetof(struct pt_regs, msr)); | |
283 | if (!ret) { | |
284 | unsigned long msr = get_user_msr(target); | |
285 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
286 | offsetof(struct pt_regs, msr), | |
287 | offsetof(struct pt_regs, msr) + | |
288 | sizeof(msr)); | |
289 | } | |
290 | ||
291 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
292 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
293 | ||
294 | if (!ret) | |
295 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
296 | &target->thread.regs->orig_gpr3, | |
297 | offsetof(struct pt_regs, orig_gpr3), | |
298 | sizeof(struct pt_regs)); | |
299 | if (!ret) | |
300 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
301 | sizeof(struct pt_regs), -1); | |
302 | ||
303 | return ret; | |
304 | } | |
305 | ||
306 | static int gpr_set(struct task_struct *target, const struct user_regset *regset, | |
307 | unsigned int pos, unsigned int count, | |
308 | const void *kbuf, const void __user *ubuf) | |
309 | { | |
310 | unsigned long reg; | |
311 | int ret; | |
312 | ||
313 | if (target->thread.regs == NULL) | |
314 | return -EIO; | |
315 | ||
316 | CHECK_FULL_REGS(target->thread.regs); | |
317 | ||
318 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
319 | target->thread.regs, | |
320 | 0, PT_MSR * sizeof(reg)); | |
321 | ||
322 | if (!ret && count > 0) { | |
323 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
324 | PT_MSR * sizeof(reg), | |
325 | (PT_MSR + 1) * sizeof(reg)); | |
326 | if (!ret) | |
327 | ret = set_user_msr(target, reg); | |
328 | } | |
329 | ||
330 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
331 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
332 | ||
333 | if (!ret) | |
334 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
335 | &target->thread.regs->orig_gpr3, | |
336 | PT_ORIG_R3 * sizeof(reg), | |
337 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
338 | ||
339 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
340 | ret = user_regset_copyin_ignore( | |
341 | &pos, &count, &kbuf, &ubuf, | |
342 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
343 | PT_TRAP * sizeof(reg)); | |
344 | ||
345 | if (!ret && count > 0) { | |
346 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
347 | PT_TRAP * sizeof(reg), | |
348 | (PT_TRAP + 1) * sizeof(reg)); | |
349 | if (!ret) | |
350 | ret = set_user_trap(target, reg); | |
351 | } | |
352 | ||
353 | if (!ret) | |
354 | ret = user_regset_copyin_ignore( | |
355 | &pos, &count, &kbuf, &ubuf, | |
356 | (PT_TRAP + 1) * sizeof(reg), -1); | |
357 | ||
358 | return ret; | |
359 | } | |
865418d8 | 360 | |
1ec8549d AK |
361 | /* |
362 | * When the transaction is active, 'transact_fp' holds the current running | |
363 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
364 | * value of all FPR registers for the current transaction. When transaction | |
365 | * is not active 'fp_state' holds the current running state of all the FPR | |
366 | * registers. So this function which returns the current running values of | |
367 | * all the FPR registers, needs to know whether any transaction is active | |
368 | * or not. | |
369 | * | |
370 | * Userspace interface buffer layout: | |
371 | * | |
372 | * struct data { | |
373 | * u64 fpr[32]; | |
374 | * u64 fpscr; | |
375 | * }; | |
376 | * | |
377 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
378 | * which determines the final code in this function. All the combinations of | |
379 | * these two config options are possible except the one below as transactional | |
380 | * memory config pulls in CONFIG_VSX automatically. | |
381 | * | |
382 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
383 | */ | |
f65255e8 RM |
384 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
385 | unsigned int pos, unsigned int count, | |
386 | void *kbuf, void __user *ubuf) | |
387 | { | |
c6e6771b | 388 | #ifdef CONFIG_VSX |
de79f7b9 | 389 | u64 buf[33]; |
c6e6771b MN |
390 | int i; |
391 | #endif | |
f65255e8 RM |
392 | flush_fp_to_thread(target); |
393 | ||
1ec8549d AK |
394 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
395 | /* copy to local buffer then write that out */ | |
396 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
397 | flush_altivec_to_thread(target); | |
398 | flush_tmregs_to_thread(target); | |
399 | for (i = 0; i < 32 ; i++) | |
400 | buf[i] = target->thread.TS_TRANS_FPR(i); | |
401 | buf[32] = target->thread.transact_fp.fpscr; | |
402 | } else { | |
403 | for (i = 0; i < 32 ; i++) | |
404 | buf[i] = target->thread.TS_FPR(i); | |
405 | buf[32] = target->thread.fp_state.fpscr; | |
406 | } | |
407 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
408 | #endif | |
409 | ||
410 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
411 | /* copy to local buffer then write that out */ |
412 | for (i = 0; i < 32 ; i++) | |
413 | buf[i] = target->thread.TS_FPR(i); | |
de79f7b9 | 414 | buf[32] = target->thread.fp_state.fpscr; |
c6e6771b | 415 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); |
1ec8549d | 416 | #endif |
c6e6771b | 417 | |
1ec8549d | 418 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
de79f7b9 | 419 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 420 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
421 | |
422 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 423 | &target->thread.fp_state, 0, -1); |
c6e6771b | 424 | #endif |
f65255e8 RM |
425 | } |
426 | ||
1ec8549d AK |
427 | /* |
428 | * When the transaction is active, 'transact_fp' holds the current running | |
429 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
430 | * value of all FPR registers for the current transaction. When transaction | |
431 | * is not active 'fp_state' holds the current running state of all the FPR | |
432 | * registers. So this function which setss the current running values of | |
433 | * all the FPR registers, needs to know whether any transaction is active | |
434 | * or not. | |
435 | * | |
436 | * Userspace interface buffer layout: | |
437 | * | |
438 | * struct data { | |
439 | * u64 fpr[32]; | |
440 | * u64 fpscr; | |
441 | * }; | |
442 | * | |
443 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
444 | * which determines the final code in this function. All the combinations of | |
445 | * these two config options are possible except the one below as transactional | |
446 | * memory config pulls in CONFIG_VSX automatically. | |
447 | * | |
448 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
449 | */ | |
f65255e8 RM |
450 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, |
451 | unsigned int pos, unsigned int count, | |
452 | const void *kbuf, const void __user *ubuf) | |
453 | { | |
c6e6771b | 454 | #ifdef CONFIG_VSX |
de79f7b9 | 455 | u64 buf[33]; |
c6e6771b MN |
456 | int i; |
457 | #endif | |
f65255e8 RM |
458 | flush_fp_to_thread(target); |
459 | ||
1ec8549d AK |
460 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
461 | /* copy to local buffer then write that out */ | |
462 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
463 | if (i) | |
464 | return i; | |
465 | ||
466 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
467 | flush_altivec_to_thread(target); | |
468 | flush_tmregs_to_thread(target); | |
469 | for (i = 0; i < 32 ; i++) | |
470 | target->thread.TS_TRANS_FPR(i) = buf[i]; | |
471 | target->thread.transact_fp.fpscr = buf[32]; | |
472 | } else { | |
473 | for (i = 0; i < 32 ; i++) | |
474 | target->thread.TS_FPR(i) = buf[i]; | |
475 | target->thread.fp_state.fpscr = buf[32]; | |
476 | } | |
477 | return 0; | |
478 | #endif | |
479 | ||
480 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
481 | /* copy to local buffer then write that out */ |
482 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
483 | if (i) | |
484 | return i; | |
485 | for (i = 0; i < 32 ; i++) | |
486 | target->thread.TS_FPR(i) = buf[i]; | |
de79f7b9 | 487 | target->thread.fp_state.fpscr = buf[32]; |
c6e6771b | 488 | return 0; |
1ec8549d AK |
489 | #endif |
490 | ||
491 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
de79f7b9 | 492 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 493 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
494 | |
495 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 496 | &target->thread.fp_state, 0, -1); |
c6e6771b | 497 | #endif |
f65255e8 RM |
498 | } |
499 | ||
865418d8 BH |
500 | #ifdef CONFIG_ALTIVEC |
501 | /* | |
502 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
503 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
504 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
505 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
506 | * vrsave as the first word (offset 0) within the quadword. | |
507 | * | |
508 | * This definition of the VMX state is compatible with the current PPC32 | |
509 | * ptrace interface. This allows signal handling and ptrace to use the | |
510 | * same structures. This also simplifies the implementation of a bi-arch | |
511 | * (combined (32- and 64-bit) gdb. | |
512 | */ | |
513 | ||
3caf06c6 RM |
514 | static int vr_active(struct task_struct *target, |
515 | const struct user_regset *regset) | |
516 | { | |
517 | flush_altivec_to_thread(target); | |
518 | return target->thread.used_vr ? regset->n : 0; | |
519 | } | |
520 | ||
d844e279 AK |
521 | /* |
522 | * When the transaction is active, 'transact_vr' holds the current running | |
523 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
524 | * value of all the VMX registers for the current transaction to fall back | |
525 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
526 | * the current running state of all the VMX registers. So this function which | |
527 | * gets the current running values of all the VMX registers, needs to know | |
528 | * whether any transaction is active or not. | |
529 | * | |
530 | * Userspace interface buffer layout: | |
531 | * | |
532 | * struct data { | |
533 | * vector128 vr[32]; | |
534 | * vector128 vscr; | |
535 | * vector128 vrsave; | |
536 | * }; | |
537 | */ | |
3caf06c6 RM |
538 | static int vr_get(struct task_struct *target, const struct user_regset *regset, |
539 | unsigned int pos, unsigned int count, | |
540 | void *kbuf, void __user *ubuf) | |
541 | { | |
d844e279 | 542 | struct thread_vr_state *addr; |
3caf06c6 RM |
543 | int ret; |
544 | ||
545 | flush_altivec_to_thread(target); | |
546 | ||
de79f7b9 PM |
547 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
548 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 549 | |
d844e279 AK |
550 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
551 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
552 | flush_fp_to_thread(target); | |
553 | flush_tmregs_to_thread(target); | |
554 | addr = &target->thread.transact_vr; | |
555 | } else { | |
556 | addr = &target->thread.vr_state; | |
557 | } | |
558 | #else | |
559 | addr = &target->thread.vr_state; | |
560 | #endif | |
3caf06c6 | 561 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
d844e279 | 562 | addr, 0, |
3caf06c6 RM |
563 | 33 * sizeof(vector128)); |
564 | if (!ret) { | |
565 | /* | |
566 | * Copy out only the low-order word of vrsave. | |
567 | */ | |
568 | union { | |
569 | elf_vrreg_t reg; | |
570 | u32 word; | |
571 | } vrsave; | |
572 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
573 | |
574 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
575 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
576 | vrsave.word = target->thread.transact_vrsave; | |
577 | else | |
578 | vrsave.word = target->thread.vrsave; | |
579 | #else | |
3caf06c6 | 580 | vrsave.word = target->thread.vrsave; |
d844e279 AK |
581 | #endif |
582 | ||
3caf06c6 RM |
583 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, |
584 | 33 * sizeof(vector128), -1); | |
585 | } | |
586 | ||
587 | return ret; | |
588 | } | |
589 | ||
d844e279 AK |
590 | /* |
591 | * When the transaction is active, 'transact_vr' holds the current running | |
592 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
593 | * value of all the VMX registers for the current transaction to fall back | |
594 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
595 | * the current running state of all the VMX registers. So this function which | |
596 | * sets the current running values of all the VMX registers, needs to know | |
597 | * whether any transaction is active or not. | |
598 | * | |
599 | * Userspace interface buffer layout: | |
600 | * | |
601 | * struct data { | |
602 | * vector128 vr[32]; | |
603 | * vector128 vscr; | |
604 | * vector128 vrsave; | |
605 | * }; | |
606 | */ | |
3caf06c6 RM |
607 | static int vr_set(struct task_struct *target, const struct user_regset *regset, |
608 | unsigned int pos, unsigned int count, | |
609 | const void *kbuf, const void __user *ubuf) | |
610 | { | |
d844e279 | 611 | struct thread_vr_state *addr; |
3caf06c6 RM |
612 | int ret; |
613 | ||
614 | flush_altivec_to_thread(target); | |
615 | ||
de79f7b9 PM |
616 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
617 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 618 | |
d844e279 AK |
619 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
620 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
621 | flush_fp_to_thread(target); | |
622 | flush_tmregs_to_thread(target); | |
623 | addr = &target->thread.transact_vr; | |
624 | } else { | |
625 | addr = &target->thread.vr_state; | |
626 | } | |
627 | #else | |
628 | addr = &target->thread.vr_state; | |
629 | #endif | |
3caf06c6 | 630 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
d844e279 | 631 | addr, 0, |
de79f7b9 | 632 | 33 * sizeof(vector128)); |
3caf06c6 RM |
633 | if (!ret && count > 0) { |
634 | /* | |
635 | * We use only the first word of vrsave. | |
636 | */ | |
637 | union { | |
638 | elf_vrreg_t reg; | |
639 | u32 word; | |
640 | } vrsave; | |
641 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
642 | |
643 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
644 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
645 | vrsave.word = target->thread.transact_vrsave; | |
646 | else | |
647 | vrsave.word = target->thread.vrsave; | |
648 | #else | |
3caf06c6 | 649 | vrsave.word = target->thread.vrsave; |
d844e279 | 650 | #endif |
3caf06c6 RM |
651 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, |
652 | 33 * sizeof(vector128), -1); | |
d844e279 AK |
653 | if (!ret) { |
654 | ||
655 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
656 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
657 | target->thread.transact_vrsave = vrsave.word; | |
658 | else | |
659 | target->thread.vrsave = vrsave.word; | |
660 | #else | |
3caf06c6 | 661 | target->thread.vrsave = vrsave.word; |
d844e279 AK |
662 | #endif |
663 | } | |
3caf06c6 RM |
664 | } |
665 | ||
666 | return ret; | |
667 | } | |
865418d8 BH |
668 | #endif /* CONFIG_ALTIVEC */ |
669 | ||
ce48b210 MN |
670 | #ifdef CONFIG_VSX |
671 | /* | |
672 | * Currently to set and and get all the vsx state, you need to call | |
25985edc | 673 | * the fp and VMX calls as well. This only get/sets the lower 32 |
ce48b210 MN |
674 | * 128bit VSX registers. |
675 | */ | |
676 | ||
677 | static int vsr_active(struct task_struct *target, | |
678 | const struct user_regset *regset) | |
679 | { | |
680 | flush_vsx_to_thread(target); | |
681 | return target->thread.used_vsr ? regset->n : 0; | |
682 | } | |
683 | ||
94b7d361 AK |
684 | /* |
685 | * When the transaction is active, 'transact_fp' holds the current running | |
686 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
687 | * value of all FPR registers for the current transaction. When transaction | |
688 | * is not active 'fp_state' holds the current running state of all the FPR | |
689 | * registers. So this function which returns the current running values of | |
690 | * all the FPR registers, needs to know whether any transaction is active | |
691 | * or not. | |
692 | * | |
693 | * Userspace interface buffer layout: | |
694 | * | |
695 | * struct data { | |
696 | * u64 vsx[32]; | |
697 | * }; | |
698 | */ | |
ce48b210 MN |
699 | static int vsr_get(struct task_struct *target, const struct user_regset *regset, |
700 | unsigned int pos, unsigned int count, | |
701 | void *kbuf, void __user *ubuf) | |
702 | { | |
de79f7b9 | 703 | u64 buf[32]; |
f3e909c2 | 704 | int ret, i; |
ce48b210 | 705 | |
94b7d361 AK |
706 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
707 | flush_fp_to_thread(target); | |
708 | flush_altivec_to_thread(target); | |
709 | flush_tmregs_to_thread(target); | |
710 | #endif | |
ce48b210 MN |
711 | flush_vsx_to_thread(target); |
712 | ||
94b7d361 AK |
713 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
714 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
715 | for (i = 0; i < 32 ; i++) | |
716 | buf[i] = target->thread. | |
717 | transact_fp.fpr[i][TS_VSRLOWOFFSET]; | |
718 | } else { | |
719 | for (i = 0; i < 32 ; i++) | |
720 | buf[i] = target->thread. | |
721 | fp_state.fpr[i][TS_VSRLOWOFFSET]; | |
722 | } | |
723 | #else | |
f3e909c2 | 724 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 725 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; |
94b7d361 | 726 | #endif |
ce48b210 | 727 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
f3e909c2 | 728 | buf, 0, 32 * sizeof(double)); |
ce48b210 MN |
729 | |
730 | return ret; | |
731 | } | |
732 | ||
94b7d361 AK |
733 | /* |
734 | * When the transaction is active, 'transact_fp' holds the current running | |
735 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
736 | * value of all FPR registers for the current transaction. When transaction | |
737 | * is not active 'fp_state' holds the current running state of all the FPR | |
738 | * registers. So this function which sets the current running values of all | |
739 | * the FPR registers, needs to know whether any transaction is active or not. | |
740 | * | |
741 | * Userspace interface buffer layout: | |
742 | * | |
743 | * struct data { | |
744 | * u64 vsx[32]; | |
745 | * }; | |
746 | */ | |
ce48b210 MN |
747 | static int vsr_set(struct task_struct *target, const struct user_regset *regset, |
748 | unsigned int pos, unsigned int count, | |
749 | const void *kbuf, const void __user *ubuf) | |
750 | { | |
de79f7b9 | 751 | u64 buf[32]; |
f3e909c2 | 752 | int ret,i; |
ce48b210 | 753 | |
94b7d361 AK |
754 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
755 | flush_fp_to_thread(target); | |
756 | flush_altivec_to_thread(target); | |
757 | flush_tmregs_to_thread(target); | |
758 | #endif | |
ce48b210 MN |
759 | flush_vsx_to_thread(target); |
760 | ||
761 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
f3e909c2 | 762 | buf, 0, 32 * sizeof(double)); |
94b7d361 AK |
763 | |
764 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
765 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
766 | for (i = 0; i < 32 ; i++) | |
767 | target->thread.transact_fp. | |
768 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
769 | } else { | |
770 | for (i = 0; i < 32 ; i++) | |
771 | target->thread.fp_state. | |
772 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
773 | } | |
774 | #else | |
f3e909c2 | 775 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 776 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
94b7d361 | 777 | #endif |
f3e909c2 | 778 | |
ce48b210 MN |
779 | |
780 | return ret; | |
781 | } | |
782 | #endif /* CONFIG_VSX */ | |
783 | ||
865418d8 BH |
784 | #ifdef CONFIG_SPE |
785 | ||
786 | /* | |
787 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
788 | * | |
789 | * struct { | |
790 | * u32 evr[32]; | |
791 | * u64 acc; | |
792 | * u32 spefscr; | |
793 | * } | |
794 | */ | |
795 | ||
a4e4b175 RM |
796 | static int evr_active(struct task_struct *target, |
797 | const struct user_regset *regset) | |
865418d8 | 798 | { |
a4e4b175 RM |
799 | flush_spe_to_thread(target); |
800 | return target->thread.used_spe ? regset->n : 0; | |
801 | } | |
865418d8 | 802 | |
a4e4b175 RM |
803 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
804 | unsigned int pos, unsigned int count, | |
805 | void *kbuf, void __user *ubuf) | |
806 | { | |
807 | int ret; | |
865418d8 | 808 | |
a4e4b175 | 809 | flush_spe_to_thread(target); |
865418d8 | 810 | |
a4e4b175 RM |
811 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
812 | &target->thread.evr, | |
813 | 0, sizeof(target->thread.evr)); | |
865418d8 | 814 | |
a4e4b175 RM |
815 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
816 | offsetof(struct thread_struct, spefscr)); | |
817 | ||
818 | if (!ret) | |
819 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
820 | &target->thread.acc, | |
821 | sizeof(target->thread.evr), -1); | |
822 | ||
823 | return ret; | |
824 | } | |
825 | ||
826 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
827 | unsigned int pos, unsigned int count, | |
828 | const void *kbuf, const void __user *ubuf) | |
829 | { | |
830 | int ret; | |
831 | ||
832 | flush_spe_to_thread(target); | |
833 | ||
834 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
835 | &target->thread.evr, | |
836 | 0, sizeof(target->thread.evr)); | |
865418d8 | 837 | |
a4e4b175 RM |
838 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
839 | offsetof(struct thread_struct, spefscr)); | |
840 | ||
841 | if (!ret) | |
842 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
843 | &target->thread.acc, | |
844 | sizeof(target->thread.evr), -1); | |
845 | ||
846 | return ret; | |
865418d8 | 847 | } |
865418d8 BH |
848 | #endif /* CONFIG_SPE */ |
849 | ||
850 | ||
80fdf470 RM |
851 | /* |
852 | * These are our native regset flavors. | |
853 | */ | |
854 | enum powerpc_regset { | |
855 | REGSET_GPR, | |
856 | REGSET_FPR, | |
857 | #ifdef CONFIG_ALTIVEC | |
858 | REGSET_VMX, | |
859 | #endif | |
ce48b210 MN |
860 | #ifdef CONFIG_VSX |
861 | REGSET_VSX, | |
862 | #endif | |
80fdf470 RM |
863 | #ifdef CONFIG_SPE |
864 | REGSET_SPE, | |
865 | #endif | |
866 | }; | |
867 | ||
868 | static const struct user_regset native_regsets[] = { | |
869 | [REGSET_GPR] = { | |
870 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
871 | .size = sizeof(long), .align = sizeof(long), | |
872 | .get = gpr_get, .set = gpr_set | |
873 | }, | |
874 | [REGSET_FPR] = { | |
875 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
876 | .size = sizeof(double), .align = sizeof(double), | |
877 | .get = fpr_get, .set = fpr_set | |
878 | }, | |
879 | #ifdef CONFIG_ALTIVEC | |
880 | [REGSET_VMX] = { | |
881 | .core_note_type = NT_PPC_VMX, .n = 34, | |
882 | .size = sizeof(vector128), .align = sizeof(vector128), | |
883 | .active = vr_active, .get = vr_get, .set = vr_set | |
884 | }, | |
885 | #endif | |
ce48b210 MN |
886 | #ifdef CONFIG_VSX |
887 | [REGSET_VSX] = { | |
f3e909c2 MN |
888 | .core_note_type = NT_PPC_VSX, .n = 32, |
889 | .size = sizeof(double), .align = sizeof(double), | |
ce48b210 MN |
890 | .active = vsr_active, .get = vsr_get, .set = vsr_set |
891 | }, | |
892 | #endif | |
80fdf470 RM |
893 | #ifdef CONFIG_SPE |
894 | [REGSET_SPE] = { | |
a0b38b4e | 895 | .core_note_type = NT_PPC_SPE, .n = 35, |
80fdf470 RM |
896 | .size = sizeof(u32), .align = sizeof(u32), |
897 | .active = evr_active, .get = evr_get, .set = evr_set | |
898 | }, | |
899 | #endif | |
900 | }; | |
901 | ||
902 | static const struct user_regset_view user_ppc_native_view = { | |
903 | .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, | |
904 | .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) | |
905 | }; | |
906 | ||
fa8f5cb0 RM |
907 | #ifdef CONFIG_PPC64 |
908 | #include <linux/compat.h> | |
909 | ||
04fcadce | 910 | static int gpr32_get_common(struct task_struct *target, |
fa8f5cb0 RM |
911 | const struct user_regset *regset, |
912 | unsigned int pos, unsigned int count, | |
04fcadce | 913 | void *kbuf, void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
914 | { |
915 | const unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 916 | const unsigned long *ckpt_regs; |
fa8f5cb0 RM |
917 | compat_ulong_t *k = kbuf; |
918 | compat_ulong_t __user *u = ubuf; | |
919 | compat_ulong_t reg; | |
a71f5d5d | 920 | int i; |
fa8f5cb0 | 921 | |
04fcadce AK |
922 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
923 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
924 | #endif | |
925 | if (tm_active) { | |
926 | regs = ckpt_regs; | |
927 | } else { | |
928 | if (target->thread.regs == NULL) | |
929 | return -EIO; | |
930 | ||
931 | if (!FULL_REGS(target->thread.regs)) { | |
932 | /* | |
933 | * We have a partial register set. | |
934 | * Fill 14-31 with bogus values. | |
935 | */ | |
936 | for (i = 14; i < 32; i++) | |
937 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
938 | } | |
a71f5d5d | 939 | } |
fa8f5cb0 RM |
940 | |
941 | pos /= sizeof(reg); | |
942 | count /= sizeof(reg); | |
943 | ||
944 | if (kbuf) | |
945 | for (; count > 0 && pos < PT_MSR; --count) | |
946 | *k++ = regs[pos++]; | |
947 | else | |
948 | for (; count > 0 && pos < PT_MSR; --count) | |
949 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
950 | return -EFAULT; | |
951 | ||
952 | if (count > 0 && pos == PT_MSR) { | |
953 | reg = get_user_msr(target); | |
954 | if (kbuf) | |
955 | *k++ = reg; | |
956 | else if (__put_user(reg, u++)) | |
957 | return -EFAULT; | |
958 | ++pos; | |
959 | --count; | |
960 | } | |
961 | ||
962 | if (kbuf) | |
963 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
964 | *k++ = regs[pos++]; | |
965 | else | |
966 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
967 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
968 | return -EFAULT; | |
969 | ||
970 | kbuf = k; | |
971 | ubuf = u; | |
972 | pos *= sizeof(reg); | |
973 | count *= sizeof(reg); | |
974 | return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
975 | PT_REGS_COUNT * sizeof(reg), -1); | |
976 | } | |
977 | ||
04fcadce | 978 | static int gpr32_set_common(struct task_struct *target, |
fa8f5cb0 RM |
979 | const struct user_regset *regset, |
980 | unsigned int pos, unsigned int count, | |
04fcadce | 981 | const void *kbuf, const void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
982 | { |
983 | unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 984 | unsigned long *ckpt_regs; |
fa8f5cb0 RM |
985 | const compat_ulong_t *k = kbuf; |
986 | const compat_ulong_t __user *u = ubuf; | |
987 | compat_ulong_t reg; | |
988 | ||
04fcadce AK |
989 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
990 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
991 | #endif | |
fa8f5cb0 | 992 | |
04fcadce AK |
993 | if (tm_active) { |
994 | regs = ckpt_regs; | |
995 | } else { | |
996 | regs = &target->thread.regs->gpr[0]; | |
997 | ||
998 | if (target->thread.regs == NULL) | |
999 | return -EIO; | |
1000 | ||
1001 | CHECK_FULL_REGS(target->thread.regs); | |
1002 | } | |
fa8f5cb0 RM |
1003 | |
1004 | pos /= sizeof(reg); | |
1005 | count /= sizeof(reg); | |
1006 | ||
1007 | if (kbuf) | |
1008 | for (; count > 0 && pos < PT_MSR; --count) | |
1009 | regs[pos++] = *k++; | |
1010 | else | |
1011 | for (; count > 0 && pos < PT_MSR; --count) { | |
1012 | if (__get_user(reg, u++)) | |
1013 | return -EFAULT; | |
1014 | regs[pos++] = reg; | |
1015 | } | |
1016 | ||
1017 | ||
1018 | if (count > 0 && pos == PT_MSR) { | |
1019 | if (kbuf) | |
1020 | reg = *k++; | |
1021 | else if (__get_user(reg, u++)) | |
1022 | return -EFAULT; | |
1023 | set_user_msr(target, reg); | |
1024 | ++pos; | |
1025 | --count; | |
1026 | } | |
1027 | ||
c2372eb9 | 1028 | if (kbuf) { |
fa8f5cb0 RM |
1029 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) |
1030 | regs[pos++] = *k++; | |
c2372eb9 RM |
1031 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
1032 | ++k; | |
1033 | } else { | |
fa8f5cb0 RM |
1034 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { |
1035 | if (__get_user(reg, u++)) | |
1036 | return -EFAULT; | |
1037 | regs[pos++] = reg; | |
1038 | } | |
c2372eb9 RM |
1039 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
1040 | if (__get_user(reg, u++)) | |
1041 | return -EFAULT; | |
1042 | } | |
fa8f5cb0 RM |
1043 | |
1044 | if (count > 0 && pos == PT_TRAP) { | |
1045 | if (kbuf) | |
1046 | reg = *k++; | |
1047 | else if (__get_user(reg, u++)) | |
1048 | return -EFAULT; | |
1049 | set_user_trap(target, reg); | |
1050 | ++pos; | |
1051 | --count; | |
1052 | } | |
1053 | ||
1054 | kbuf = k; | |
1055 | ubuf = u; | |
1056 | pos *= sizeof(reg); | |
1057 | count *= sizeof(reg); | |
1058 | return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, | |
1059 | (PT_TRAP + 1) * sizeof(reg), -1); | |
1060 | } | |
1061 | ||
04fcadce AK |
1062 | static int gpr32_get(struct task_struct *target, |
1063 | const struct user_regset *regset, | |
1064 | unsigned int pos, unsigned int count, | |
1065 | void *kbuf, void __user *ubuf) | |
1066 | { | |
1067 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 0); | |
1068 | } | |
1069 | ||
1070 | static int gpr32_set(struct task_struct *target, | |
1071 | const struct user_regset *regset, | |
1072 | unsigned int pos, unsigned int count, | |
1073 | const void *kbuf, const void __user *ubuf) | |
1074 | { | |
1075 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 0); | |
1076 | } | |
1077 | ||
fa8f5cb0 RM |
1078 | /* |
1079 | * These are the regset flavors matching the CONFIG_PPC32 native set. | |
1080 | */ | |
1081 | static const struct user_regset compat_regsets[] = { | |
1082 | [REGSET_GPR] = { | |
1083 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
1084 | .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), | |
1085 | .get = gpr32_get, .set = gpr32_set | |
1086 | }, | |
1087 | [REGSET_FPR] = { | |
1088 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
1089 | .size = sizeof(double), .align = sizeof(double), | |
1090 | .get = fpr_get, .set = fpr_set | |
1091 | }, | |
1092 | #ifdef CONFIG_ALTIVEC | |
1093 | [REGSET_VMX] = { | |
1094 | .core_note_type = NT_PPC_VMX, .n = 34, | |
1095 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1096 | .active = vr_active, .get = vr_get, .set = vr_set | |
1097 | }, | |
1098 | #endif | |
1099 | #ifdef CONFIG_SPE | |
1100 | [REGSET_SPE] = { | |
24f1a849 | 1101 | .core_note_type = NT_PPC_SPE, .n = 35, |
fa8f5cb0 RM |
1102 | .size = sizeof(u32), .align = sizeof(u32), |
1103 | .active = evr_active, .get = evr_get, .set = evr_set | |
1104 | }, | |
1105 | #endif | |
1106 | }; | |
1107 | ||
1108 | static const struct user_regset_view user_ppc_compat_view = { | |
1109 | .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, | |
1110 | .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) | |
1111 | }; | |
1112 | #endif /* CONFIG_PPC64 */ | |
1113 | ||
80fdf470 RM |
1114 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
1115 | { | |
fa8f5cb0 RM |
1116 | #ifdef CONFIG_PPC64 |
1117 | if (test_tsk_thread_flag(task, TIF_32BIT)) | |
1118 | return &user_ppc_compat_view; | |
1119 | #endif | |
80fdf470 RM |
1120 | return &user_ppc_native_view; |
1121 | } | |
1122 | ||
1123 | ||
2a84b0d7 | 1124 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
1125 | { |
1126 | struct pt_regs *regs = task->thread.regs; | |
1127 | ||
1128 | if (regs != NULL) { | |
172ae2e7 | 1129 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
1130 | task->thread.debug.dbcr0 &= ~DBCR0_BT; |
1131 | task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
865418d8 BH |
1132 | regs->msr |= MSR_DE; |
1133 | #else | |
ec097c84 | 1134 | regs->msr &= ~MSR_BE; |
865418d8 BH |
1135 | regs->msr |= MSR_SE; |
1136 | #endif | |
1137 | } | |
1138 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1139 | } | |
1140 | ||
ec097c84 RM |
1141 | void user_enable_block_step(struct task_struct *task) |
1142 | { | |
1143 | struct pt_regs *regs = task->thread.regs; | |
1144 | ||
1145 | if (regs != NULL) { | |
172ae2e7 | 1146 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
1147 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
1148 | task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; | |
ec097c84 RM |
1149 | regs->msr |= MSR_DE; |
1150 | #else | |
1151 | regs->msr &= ~MSR_SE; | |
1152 | regs->msr |= MSR_BE; | |
1153 | #endif | |
1154 | } | |
1155 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1156 | } | |
1157 | ||
2a84b0d7 | 1158 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
1159 | { |
1160 | struct pt_regs *regs = task->thread.regs; | |
1161 | ||
1162 | if (regs != NULL) { | |
172ae2e7 | 1163 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1164 | /* |
1165 | * The logic to disable single stepping should be as | |
1166 | * simple as turning off the Instruction Complete flag. | |
1167 | * And, after doing so, if all debug flags are off, turn | |
1168 | * off DBCR0(IDM) and MSR(DE) .... Torez | |
1169 | */ | |
682775b8 | 1170 | task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT); |
3bffb652 DK |
1171 | /* |
1172 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | |
1173 | */ | |
51ae8d4a BB |
1174 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1175 | task->thread.debug.dbcr1)) { | |
3bffb652 DK |
1176 | /* |
1177 | * All debug events were off..... | |
1178 | */ | |
51ae8d4a | 1179 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
28477fb1 DK |
1180 | regs->msr &= ~MSR_DE; |
1181 | } | |
865418d8 | 1182 | #else |
ec097c84 | 1183 | regs->msr &= ~(MSR_SE | MSR_BE); |
865418d8 BH |
1184 | #endif |
1185 | } | |
1186 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1187 | } | |
1188 | ||
5aae8a53 | 1189 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
a8b0ca17 | 1190 | void ptrace_triggered(struct perf_event *bp, |
5aae8a53 P |
1191 | struct perf_sample_data *data, struct pt_regs *regs) |
1192 | { | |
1193 | struct perf_event_attr attr; | |
1194 | ||
1195 | /* | |
1196 | * Disable the breakpoint request here since ptrace has defined a | |
1197 | * one-shot behaviour for breakpoint exceptions in PPC64. | |
1198 | * The SIGTRAP signal is generated automatically for us in do_dabr(). | |
1199 | * We don't have to do anything about that here | |
1200 | */ | |
1201 | attr = bp->attr; | |
1202 | attr.disabled = true; | |
1203 | modify_user_hw_breakpoint(bp, &attr); | |
1204 | } | |
1205 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1206 | ||
e51df2c1 | 1207 | static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
abd06505 BH |
1208 | unsigned long data) |
1209 | { | |
5aae8a53 P |
1210 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1211 | int ret; | |
1212 | struct thread_struct *thread = &(task->thread); | |
1213 | struct perf_event *bp; | |
1214 | struct perf_event_attr attr; | |
1215 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e MN |
1216 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
1217 | struct arch_hw_breakpoint hw_brk; | |
1218 | #endif | |
5aae8a53 | 1219 | |
d6a61bfc LM |
1220 | /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
1221 | * For embedded processors we support one DAC and no IAC's at the | |
1222 | * moment. | |
1223 | */ | |
abd06505 BH |
1224 | if (addr > 0) |
1225 | return -EINVAL; | |
1226 | ||
2325f0a0 | 1227 | /* The bottom 3 bits in dabr are flags */ |
abd06505 BH |
1228 | if ((data & ~0x7UL) >= TASK_SIZE) |
1229 | return -EIO; | |
1230 | ||
172ae2e7 | 1231 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
d6a61bfc LM |
1232 | /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. |
1233 | * It was assumed, on previous implementations, that 3 bits were | |
1234 | * passed together with the data address, fitting the design of the | |
1235 | * DABR register, as follows: | |
1236 | * | |
1237 | * bit 0: Read flag | |
1238 | * bit 1: Write flag | |
1239 | * bit 2: Breakpoint translation | |
1240 | * | |
1241 | * Thus, we use them here as so. | |
1242 | */ | |
1243 | ||
1244 | /* Ensure breakpoint translation bit is set */ | |
9422de3e | 1245 | if (data && !(data & HW_BRK_TYPE_TRANSLATE)) |
abd06505 | 1246 | return -EIO; |
9422de3e MN |
1247 | hw_brk.address = data & (~HW_BRK_TYPE_DABR); |
1248 | hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL; | |
1249 | hw_brk.len = 8; | |
5aae8a53 P |
1250 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1251 | bp = thread->ptrace_bps[0]; | |
9422de3e | 1252 | if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) { |
5aae8a53 P |
1253 | if (bp) { |
1254 | unregister_hw_breakpoint(bp); | |
1255 | thread->ptrace_bps[0] = NULL; | |
1256 | } | |
1257 | return 0; | |
1258 | } | |
1259 | if (bp) { | |
1260 | attr = bp->attr; | |
9422de3e MN |
1261 | attr.bp_addr = hw_brk.address; |
1262 | arch_bp_generic_fields(hw_brk.type, &attr.bp_type); | |
a53fd61a AP |
1263 | |
1264 | /* Enable breakpoint */ | |
1265 | attr.disabled = false; | |
1266 | ||
5aae8a53 | 1267 | ret = modify_user_hw_breakpoint(bp, &attr); |
925f83c0 | 1268 | if (ret) { |
5aae8a53 | 1269 | return ret; |
925f83c0 | 1270 | } |
5aae8a53 | 1271 | thread->ptrace_bps[0] = bp; |
9422de3e | 1272 | thread->hw_brk = hw_brk; |
5aae8a53 P |
1273 | return 0; |
1274 | } | |
1275 | ||
1276 | /* Create a new breakpoint request if one doesn't exist already */ | |
1277 | hw_breakpoint_init(&attr); | |
9422de3e MN |
1278 | attr.bp_addr = hw_brk.address; |
1279 | arch_bp_generic_fields(hw_brk.type, | |
1280 | &attr.bp_type); | |
5aae8a53 P |
1281 | |
1282 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
4dc0da86 | 1283 | ptrace_triggered, NULL, task); |
5aae8a53 P |
1284 | if (IS_ERR(bp)) { |
1285 | thread->ptrace_bps[0] = NULL; | |
1286 | return PTR_ERR(bp); | |
1287 | } | |
1288 | ||
1289 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 1290 | task->thread.hw_brk = hw_brk; |
172ae2e7 | 1291 | #else /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc LM |
1292 | /* As described above, it was assumed 3 bits were passed with the data |
1293 | * address, but we will assume only the mode bits will be passed | |
1294 | * as to not cause alignment restrictions for DAC-based processors. | |
1295 | */ | |
1296 | ||
1297 | /* DAC's hold the whole address without any mode flags */ | |
51ae8d4a | 1298 | task->thread.debug.dac1 = data & ~0x3UL; |
3bffb652 | 1299 | |
51ae8d4a | 1300 | if (task->thread.debug.dac1 == 0) { |
3bffb652 | 1301 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
51ae8d4a BB |
1302 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1303 | task->thread.debug.dbcr1)) { | |
3bffb652 | 1304 | task->thread.regs->msr &= ~MSR_DE; |
51ae8d4a | 1305 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 | 1306 | } |
d6a61bfc LM |
1307 | return 0; |
1308 | } | |
1309 | ||
1310 | /* Read or Write bits must be set */ | |
1311 | ||
1312 | if (!(data & 0x3UL)) | |
1313 | return -EINVAL; | |
1314 | ||
1315 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | |
1316 | register */ | |
51ae8d4a | 1317 | task->thread.debug.dbcr0 |= DBCR0_IDM; |
d6a61bfc LM |
1318 | |
1319 | /* Check for write and read flags and set DBCR0 | |
1320 | accordingly */ | |
3bffb652 | 1321 | dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); |
d6a61bfc | 1322 | if (data & 0x1UL) |
3bffb652 | 1323 | dbcr_dac(task) |= DBCR_DAC1R; |
d6a61bfc | 1324 | if (data & 0x2UL) |
3bffb652 | 1325 | dbcr_dac(task) |= DBCR_DAC1W; |
d6a61bfc | 1326 | task->thread.regs->msr |= MSR_DE; |
172ae2e7 | 1327 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
abd06505 BH |
1328 | return 0; |
1329 | } | |
abd06505 | 1330 | |
1da177e4 LT |
1331 | /* |
1332 | * Called by kernel/ptrace.c when detaching.. | |
1333 | * | |
1334 | * Make sure single step bits etc are not set. | |
1335 | */ | |
1336 | void ptrace_disable(struct task_struct *child) | |
1337 | { | |
1338 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 1339 | user_disable_single_step(child); |
1da177e4 LT |
1340 | } |
1341 | ||
3bffb652 | 1342 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
84295dfc | 1343 | static long set_instruction_bp(struct task_struct *child, |
3bffb652 DK |
1344 | struct ppc_hw_breakpoint *bp_info) |
1345 | { | |
1346 | int slot; | |
51ae8d4a BB |
1347 | int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
1348 | int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); | |
1349 | int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); | |
1350 | int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); | |
3bffb652 DK |
1351 | |
1352 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1353 | slot2_in_use = 1; | |
1354 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1355 | slot4_in_use = 1; | |
1356 | ||
1357 | if (bp_info->addr >= TASK_SIZE) | |
1358 | return -EIO; | |
1359 | ||
1360 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { | |
1361 | ||
1362 | /* Make sure range is valid. */ | |
1363 | if (bp_info->addr2 >= TASK_SIZE) | |
1364 | return -EIO; | |
1365 | ||
1366 | /* We need a pair of IAC regsisters */ | |
1367 | if ((!slot1_in_use) && (!slot2_in_use)) { | |
1368 | slot = 1; | |
51ae8d4a BB |
1369 | child->thread.debug.iac1 = bp_info->addr; |
1370 | child->thread.debug.iac2 = bp_info->addr2; | |
1371 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
1372 | if (bp_info->addr_mode == |
1373 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1374 | dbcr_iac_range(child) |= DBCR_IAC12X; | |
1375 | else | |
1376 | dbcr_iac_range(child) |= DBCR_IAC12I; | |
1377 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1378 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | |
1379 | slot = 3; | |
51ae8d4a BB |
1380 | child->thread.debug.iac3 = bp_info->addr; |
1381 | child->thread.debug.iac4 = bp_info->addr2; | |
1382 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
1383 | if (bp_info->addr_mode == |
1384 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
1385 | dbcr_iac_range(child) |= DBCR_IAC34X; | |
1386 | else | |
1387 | dbcr_iac_range(child) |= DBCR_IAC34I; | |
1388 | #endif | |
1389 | } else | |
1390 | return -ENOSPC; | |
1391 | } else { | |
1392 | /* We only need one. If possible leave a pair free in | |
1393 | * case a range is needed later | |
1394 | */ | |
1395 | if (!slot1_in_use) { | |
1396 | /* | |
1397 | * Don't use iac1 if iac1-iac2 are free and either | |
1398 | * iac3 or iac4 (but not both) are free | |
1399 | */ | |
1400 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | |
1401 | slot = 1; | |
51ae8d4a BB |
1402 | child->thread.debug.iac1 = bp_info->addr; |
1403 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
1404 | goto out; |
1405 | } | |
1406 | } | |
1407 | if (!slot2_in_use) { | |
1408 | slot = 2; | |
51ae8d4a BB |
1409 | child->thread.debug.iac2 = bp_info->addr; |
1410 | child->thread.debug.dbcr0 |= DBCR0_IAC2; | |
3bffb652 DK |
1411 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
1412 | } else if (!slot3_in_use) { | |
1413 | slot = 3; | |
51ae8d4a BB |
1414 | child->thread.debug.iac3 = bp_info->addr; |
1415 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
1416 | } else if (!slot4_in_use) { |
1417 | slot = 4; | |
51ae8d4a BB |
1418 | child->thread.debug.iac4 = bp_info->addr; |
1419 | child->thread.debug.dbcr0 |= DBCR0_IAC4; | |
3bffb652 DK |
1420 | #endif |
1421 | } else | |
1422 | return -ENOSPC; | |
1423 | } | |
1424 | out: | |
51ae8d4a | 1425 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
1426 | child->thread.regs->msr |= MSR_DE; |
1427 | ||
1428 | return slot; | |
1429 | } | |
1430 | ||
1431 | static int del_instruction_bp(struct task_struct *child, int slot) | |
1432 | { | |
1433 | switch (slot) { | |
1434 | case 1: | |
51ae8d4a | 1435 | if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
3bffb652 DK |
1436 | return -ENOENT; |
1437 | ||
1438 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | |
1439 | /* address range - clear slots 1 & 2 */ | |
51ae8d4a | 1440 | child->thread.debug.iac2 = 0; |
3bffb652 DK |
1441 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
1442 | } | |
51ae8d4a BB |
1443 | child->thread.debug.iac1 = 0; |
1444 | child->thread.debug.dbcr0 &= ~DBCR0_IAC1; | |
3bffb652 DK |
1445 | break; |
1446 | case 2: | |
51ae8d4a | 1447 | if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
3bffb652 DK |
1448 | return -ENOENT; |
1449 | ||
1450 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1451 | /* used in a range */ | |
1452 | return -EINVAL; | |
51ae8d4a BB |
1453 | child->thread.debug.iac2 = 0; |
1454 | child->thread.debug.dbcr0 &= ~DBCR0_IAC2; | |
3bffb652 DK |
1455 | break; |
1456 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
1457 | case 3: | |
51ae8d4a | 1458 | if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
3bffb652 DK |
1459 | return -ENOENT; |
1460 | ||
1461 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | |
1462 | /* address range - clear slots 3 & 4 */ | |
51ae8d4a | 1463 | child->thread.debug.iac4 = 0; |
3bffb652 DK |
1464 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
1465 | } | |
51ae8d4a BB |
1466 | child->thread.debug.iac3 = 0; |
1467 | child->thread.debug.dbcr0 &= ~DBCR0_IAC3; | |
3bffb652 DK |
1468 | break; |
1469 | case 4: | |
51ae8d4a | 1470 | if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
3bffb652 DK |
1471 | return -ENOENT; |
1472 | ||
1473 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1474 | /* Used in a range */ | |
1475 | return -EINVAL; | |
51ae8d4a BB |
1476 | child->thread.debug.iac4 = 0; |
1477 | child->thread.debug.dbcr0 &= ~DBCR0_IAC4; | |
3bffb652 DK |
1478 | break; |
1479 | #endif | |
1480 | default: | |
1481 | return -EINVAL; | |
1482 | } | |
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |
1487 | { | |
1488 | int byte_enable = | |
1489 | (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) | |
1490 | & 0xf; | |
1491 | int condition_mode = | |
1492 | bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; | |
1493 | int slot; | |
1494 | ||
1495 | if (byte_enable && (condition_mode == 0)) | |
1496 | return -EINVAL; | |
1497 | ||
1498 | if (bp_info->addr >= TASK_SIZE) | |
1499 | return -EIO; | |
1500 | ||
1501 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { | |
1502 | slot = 1; | |
1503 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1504 | dbcr_dac(child) |= DBCR_DAC1R; | |
1505 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1506 | dbcr_dac(child) |= DBCR_DAC1W; | |
51ae8d4a | 1507 | child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
3bffb652 DK |
1508 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1509 | if (byte_enable) { | |
51ae8d4a | 1510 | child->thread.debug.dvc1 = |
3bffb652 | 1511 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 1512 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
1513 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | |
1514 | (condition_mode << DBCR2_DVC1M_SHIFT)); | |
1515 | } | |
1516 | #endif | |
1517 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1518 | } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
3bffb652 DK |
1519 | /* Both dac1 and dac2 are part of a range */ |
1520 | return -ENOSPC; | |
1521 | #endif | |
1522 | } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { | |
1523 | slot = 2; | |
1524 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
1525 | dbcr_dac(child) |= DBCR_DAC2R; | |
1526 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
1527 | dbcr_dac(child) |= DBCR_DAC2W; | |
51ae8d4a | 1528 | child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
3bffb652 DK |
1529 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
1530 | if (byte_enable) { | |
51ae8d4a | 1531 | child->thread.debug.dvc2 = |
3bffb652 | 1532 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 1533 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
1534 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | |
1535 | (condition_mode << DBCR2_DVC2M_SHIFT)); | |
1536 | } | |
1537 | #endif | |
1538 | } else | |
1539 | return -ENOSPC; | |
51ae8d4a | 1540 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
1541 | child->thread.regs->msr |= MSR_DE; |
1542 | ||
1543 | return slot + 4; | |
1544 | } | |
1545 | ||
1546 | static int del_dac(struct task_struct *child, int slot) | |
1547 | { | |
1548 | if (slot == 1) { | |
30124d11 | 1549 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
3bffb652 DK |
1550 | return -ENOENT; |
1551 | ||
51ae8d4a | 1552 | child->thread.debug.dac1 = 0; |
3bffb652 DK |
1553 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
1554 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a BB |
1555 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
1556 | child->thread.debug.dac2 = 0; | |
1557 | child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; | |
3bffb652 | 1558 | } |
51ae8d4a | 1559 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
3bffb652 DK |
1560 | #endif |
1561 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 1562 | child->thread.debug.dvc1 = 0; |
3bffb652 DK |
1563 | #endif |
1564 | } else if (slot == 2) { | |
30124d11 | 1565 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
3bffb652 DK |
1566 | return -ENOENT; |
1567 | ||
1568 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 1569 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
3bffb652 DK |
1570 | /* Part of a range */ |
1571 | return -EINVAL; | |
51ae8d4a | 1572 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
3bffb652 DK |
1573 | #endif |
1574 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 1575 | child->thread.debug.dvc2 = 0; |
3bffb652 | 1576 | #endif |
51ae8d4a | 1577 | child->thread.debug.dac2 = 0; |
3bffb652 DK |
1578 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
1579 | } else | |
1580 | return -EINVAL; | |
1581 | ||
1582 | return 0; | |
1583 | } | |
1584 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ | |
1585 | ||
1586 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1587 | static int set_dac_range(struct task_struct *child, | |
1588 | struct ppc_hw_breakpoint *bp_info) | |
1589 | { | |
1590 | int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; | |
1591 | ||
1592 | /* We don't allow range watchpoints to be used with DVC */ | |
1593 | if (bp_info->condition_mode) | |
1594 | return -EINVAL; | |
1595 | ||
1596 | /* | |
1597 | * Best effort to verify the address range. The user/supervisor bits | |
1598 | * prevent trapping in kernel space, but let's fail on an obvious bad | |
1599 | * range. The simple test on the mask is not fool-proof, and any | |
1600 | * exclusive range will spill over into kernel space. | |
1601 | */ | |
1602 | if (bp_info->addr >= TASK_SIZE) | |
1603 | return -EIO; | |
1604 | if (mode == PPC_BREAKPOINT_MODE_MASK) { | |
1605 | /* | |
1606 | * dac2 is a bitmask. Don't allow a mask that makes a | |
1607 | * kernel space address from a valid dac1 value | |
1608 | */ | |
1609 | if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) | |
1610 | return -EIO; | |
1611 | } else { | |
1612 | /* | |
1613 | * For range breakpoints, addr2 must also be a valid address | |
1614 | */ | |
1615 | if (bp_info->addr2 >= TASK_SIZE) | |
1616 | return -EIO; | |
1617 | } | |
1618 | ||
51ae8d4a | 1619 | if (child->thread.debug.dbcr0 & |
3bffb652 DK |
1620 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
1621 | return -ENOSPC; | |
1622 | ||
1623 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
51ae8d4a | 1624 | child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
3bffb652 | 1625 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
51ae8d4a BB |
1626 | child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
1627 | child->thread.debug.dac1 = bp_info->addr; | |
1628 | child->thread.debug.dac2 = bp_info->addr2; | |
3bffb652 | 1629 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
51ae8d4a | 1630 | child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
3bffb652 | 1631 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
51ae8d4a | 1632 | child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
3bffb652 | 1633 | else /* PPC_BREAKPOINT_MODE_MASK */ |
51ae8d4a | 1634 | child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
3bffb652 DK |
1635 | child->thread.regs->msr |= MSR_DE; |
1636 | ||
1637 | return 5; | |
1638 | } | |
1639 | #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ | |
1640 | ||
3162d92d DK |
1641 | static long ppc_set_hwdebug(struct task_struct *child, |
1642 | struct ppc_hw_breakpoint *bp_info) | |
1643 | { | |
6c7a2856 P |
1644 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1645 | int len = 0; | |
1646 | struct thread_struct *thread = &(child->thread); | |
1647 | struct perf_event *bp; | |
1648 | struct perf_event_attr attr; | |
1649 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
4dfbf290 | 1650 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e | 1651 | struct arch_hw_breakpoint brk; |
4dfbf290 AS |
1652 | #endif |
1653 | ||
3bffb652 DK |
1654 | if (bp_info->version != 1) |
1655 | return -ENOTSUPP; | |
1656 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
1657 | /* | |
1658 | * Check for invalid flags and combinations | |
1659 | */ | |
1660 | if ((bp_info->trigger_type == 0) || | |
1661 | (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | | |
1662 | PPC_BREAKPOINT_TRIGGER_RW)) || | |
1663 | (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || | |
1664 | (bp_info->condition_mode & | |
1665 | ~(PPC_BREAKPOINT_CONDITION_MODE | | |
1666 | PPC_BREAKPOINT_CONDITION_BE_ALL))) | |
1667 | return -EINVAL; | |
1668 | #if CONFIG_PPC_ADV_DEBUG_DVCS == 0 | |
1669 | if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
1670 | return -EINVAL; | |
1671 | #endif | |
1672 | ||
1673 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { | |
1674 | if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || | |
1675 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
1676 | return -EINVAL; | |
84295dfc | 1677 | return set_instruction_bp(child, bp_info); |
3bffb652 DK |
1678 | } |
1679 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) | |
1680 | return set_dac(child, bp_info); | |
1681 | ||
1682 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1683 | return set_dac_range(child, bp_info); | |
1684 | #else | |
1685 | return -EINVAL; | |
1686 | #endif | |
1687 | #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ | |
3162d92d | 1688 | /* |
3bffb652 | 1689 | * We only support one data breakpoint |
3162d92d | 1690 | */ |
4dfbf290 AS |
1691 | if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || |
1692 | (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || | |
4dfbf290 | 1693 | bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
3162d92d DK |
1694 | return -EINVAL; |
1695 | ||
3162d92d DK |
1696 | if ((unsigned long)bp_info->addr >= TASK_SIZE) |
1697 | return -EIO; | |
1698 | ||
9422de3e MN |
1699 | brk.address = bp_info->addr & ~7UL; |
1700 | brk.type = HW_BRK_TYPE_TRANSLATE; | |
2bb78efa | 1701 | brk.len = 8; |
4dfbf290 | 1702 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
9422de3e | 1703 | brk.type |= HW_BRK_TYPE_READ; |
4dfbf290 | 1704 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
9422de3e | 1705 | brk.type |= HW_BRK_TYPE_WRITE; |
6c7a2856 | 1706 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6c7a2856 P |
1707 | /* |
1708 | * Check if the request is for 'range' breakpoints. We can | |
1709 | * support it if range < 8 bytes. | |
1710 | */ | |
6961ed96 | 1711 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
6c7a2856 | 1712 | len = bp_info->addr2 - bp_info->addr; |
6961ed96 | 1713 | else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) |
b0b0aa9c | 1714 | len = 1; |
6961ed96 | 1715 | else |
6c7a2856 | 1716 | return -EINVAL; |
6c7a2856 | 1717 | bp = thread->ptrace_bps[0]; |
6961ed96 | 1718 | if (bp) |
6c7a2856 | 1719 | return -ENOSPC; |
6c7a2856 P |
1720 | |
1721 | /* Create a new breakpoint request if one doesn't exist already */ | |
1722 | hw_breakpoint_init(&attr); | |
1723 | attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN; | |
1724 | attr.bp_len = len; | |
9422de3e | 1725 | arch_bp_generic_fields(brk.type, &attr.bp_type); |
6c7a2856 P |
1726 | |
1727 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
1728 | ptrace_triggered, NULL, child); | |
1729 | if (IS_ERR(bp)) { | |
1730 | thread->ptrace_bps[0] = NULL; | |
6c7a2856 P |
1731 | return PTR_ERR(bp); |
1732 | } | |
1733 | ||
6c7a2856 P |
1734 | return 1; |
1735 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1736 | ||
1737 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) | |
1738 | return -EINVAL; | |
1739 | ||
9422de3e | 1740 | if (child->thread.hw_brk.address) |
6c7a2856 | 1741 | return -ENOSPC; |
4dfbf290 | 1742 | |
9422de3e | 1743 | child->thread.hw_brk = brk; |
3bffb652 | 1744 | |
3162d92d | 1745 | return 1; |
3bffb652 | 1746 | #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ |
3162d92d DK |
1747 | } |
1748 | ||
ec1b33dc | 1749 | static long ppc_del_hwdebug(struct task_struct *child, long data) |
3162d92d | 1750 | { |
6c7a2856 P |
1751 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1752 | int ret = 0; | |
1753 | struct thread_struct *thread = &(child->thread); | |
1754 | struct perf_event *bp; | |
1755 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
3bffb652 DK |
1756 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1757 | int rc; | |
1758 | ||
1759 | if (data <= 4) | |
1760 | rc = del_instruction_bp(child, (int)data); | |
1761 | else | |
1762 | rc = del_dac(child, (int)data - 4); | |
1763 | ||
1764 | if (!rc) { | |
51ae8d4a BB |
1765 | if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
1766 | child->thread.debug.dbcr1)) { | |
1767 | child->thread.debug.dbcr0 &= ~DBCR0_IDM; | |
3bffb652 DK |
1768 | child->thread.regs->msr &= ~MSR_DE; |
1769 | } | |
1770 | } | |
1771 | return rc; | |
1772 | #else | |
3162d92d DK |
1773 | if (data != 1) |
1774 | return -EINVAL; | |
6c7a2856 P |
1775 | |
1776 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
6c7a2856 P |
1777 | bp = thread->ptrace_bps[0]; |
1778 | if (bp) { | |
1779 | unregister_hw_breakpoint(bp); | |
1780 | thread->ptrace_bps[0] = NULL; | |
1781 | } else | |
1782 | ret = -ENOENT; | |
6c7a2856 P |
1783 | return ret; |
1784 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 1785 | if (child->thread.hw_brk.address == 0) |
3162d92d DK |
1786 | return -ENOENT; |
1787 | ||
9422de3e MN |
1788 | child->thread.hw_brk.address = 0; |
1789 | child->thread.hw_brk.type = 0; | |
6c7a2856 | 1790 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1791 | |
3162d92d | 1792 | return 0; |
3bffb652 | 1793 | #endif |
3162d92d DK |
1794 | } |
1795 | ||
9b05a69e NK |
1796 | long arch_ptrace(struct task_struct *child, long request, |
1797 | unsigned long addr, unsigned long data) | |
1da177e4 | 1798 | { |
1da177e4 | 1799 | int ret = -EPERM; |
f68d2048 NK |
1800 | void __user *datavp = (void __user *) data; |
1801 | unsigned long __user *datalp = datavp; | |
1da177e4 | 1802 | |
1da177e4 | 1803 | switch (request) { |
1da177e4 | 1804 | /* read the word at location addr in the USER area. */ |
1da177e4 LT |
1805 | case PTRACE_PEEKUSR: { |
1806 | unsigned long index, tmp; | |
1807 | ||
1808 | ret = -EIO; | |
1809 | /* convert to index and check */ | |
e8a30302 | 1810 | #ifdef CONFIG_PPC32 |
9b05a69e | 1811 | index = addr >> 2; |
e8a30302 SR |
1812 | if ((addr & 3) || (index > PT_FPSCR) |
1813 | || (child->thread.regs == NULL)) | |
1814 | #else | |
9b05a69e | 1815 | index = addr >> 3; |
e8a30302 SR |
1816 | if ((addr & 7) || (index > PT_FPSCR)) |
1817 | #endif | |
1da177e4 LT |
1818 | break; |
1819 | ||
1820 | CHECK_FULL_REGS(child->thread.regs); | |
1821 | if (index < PT_FPR0) { | |
ee4a3916 AK |
1822 | ret = ptrace_get_reg(child, (int) index, &tmp); |
1823 | if (ret) | |
1824 | break; | |
1da177e4 | 1825 | } else { |
e69b742a BH |
1826 | unsigned int fpidx = index - PT_FPR0; |
1827 | ||
e8a30302 | 1828 | flush_fp_to_thread(child); |
e69b742a | 1829 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 1830 | memcpy(&tmp, &child->thread.TS_FPR(fpidx), |
87fec051 | 1831 | sizeof(long)); |
e69b742a | 1832 | else |
de79f7b9 | 1833 | tmp = child->thread.fp_state.fpscr; |
1da177e4 | 1834 | } |
f68d2048 | 1835 | ret = put_user(tmp, datalp); |
1da177e4 LT |
1836 | break; |
1837 | } | |
1838 | ||
1da177e4 LT |
1839 | /* write the word at location addr in the USER area */ |
1840 | case PTRACE_POKEUSR: { | |
1841 | unsigned long index; | |
1842 | ||
1843 | ret = -EIO; | |
1844 | /* convert to index and check */ | |
e8a30302 | 1845 | #ifdef CONFIG_PPC32 |
9b05a69e | 1846 | index = addr >> 2; |
e8a30302 SR |
1847 | if ((addr & 3) || (index > PT_FPSCR) |
1848 | || (child->thread.regs == NULL)) | |
1849 | #else | |
9b05a69e | 1850 | index = addr >> 3; |
e8a30302 SR |
1851 | if ((addr & 7) || (index > PT_FPSCR)) |
1852 | #endif | |
1da177e4 LT |
1853 | break; |
1854 | ||
1855 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 1856 | if (index < PT_FPR0) { |
865418d8 | 1857 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 1858 | } else { |
e69b742a BH |
1859 | unsigned int fpidx = index - PT_FPR0; |
1860 | ||
e8a30302 | 1861 | flush_fp_to_thread(child); |
e69b742a | 1862 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 1863 | memcpy(&child->thread.TS_FPR(fpidx), &data, |
87fec051 | 1864 | sizeof(long)); |
e69b742a | 1865 | else |
de79f7b9 | 1866 | child->thread.fp_state.fpscr = data; |
1da177e4 LT |
1867 | ret = 0; |
1868 | } | |
1869 | break; | |
1870 | } | |
1871 | ||
3162d92d DK |
1872 | case PPC_PTRACE_GETHWDBGINFO: { |
1873 | struct ppc_debug_info dbginfo; | |
1874 | ||
1875 | dbginfo.version = 1; | |
3bffb652 DK |
1876 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
1877 | dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; | |
1878 | dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; | |
1879 | dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; | |
1880 | dbginfo.data_bp_alignment = 4; | |
1881 | dbginfo.sizeof_condition = 4; | |
1882 | dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | | |
1883 | PPC_DEBUG_FEATURE_INSN_BP_MASK; | |
1884 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
1885 | dbginfo.features |= | |
1886 | PPC_DEBUG_FEATURE_DATA_BP_RANGE | | |
1887 | PPC_DEBUG_FEATURE_DATA_BP_MASK; | |
1888 | #endif | |
1889 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
3162d92d DK |
1890 | dbginfo.num_instruction_bps = 0; |
1891 | dbginfo.num_data_bps = 1; | |
1892 | dbginfo.num_condition_regs = 0; | |
1893 | #ifdef CONFIG_PPC64 | |
1894 | dbginfo.data_bp_alignment = 8; | |
1895 | #else | |
1896 | dbginfo.data_bp_alignment = 4; | |
1897 | #endif | |
1898 | dbginfo.sizeof_condition = 0; | |
6c7a2856 P |
1899 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1900 | dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE; | |
517b7314 MN |
1901 | if (cpu_has_feature(CPU_FTR_DAWR)) |
1902 | dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR; | |
6c7a2856 | 1903 | #else |
3162d92d | 1904 | dbginfo.features = 0; |
6c7a2856 | 1905 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 1906 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
3162d92d | 1907 | |
f68d2048 | 1908 | if (!access_ok(VERIFY_WRITE, datavp, |
3162d92d DK |
1909 | sizeof(struct ppc_debug_info))) |
1910 | return -EFAULT; | |
f68d2048 NK |
1911 | ret = __copy_to_user(datavp, &dbginfo, |
1912 | sizeof(struct ppc_debug_info)) ? | |
3162d92d DK |
1913 | -EFAULT : 0; |
1914 | break; | |
1915 | } | |
1916 | ||
1917 | case PPC_PTRACE_SETHWDEBUG: { | |
1918 | struct ppc_hw_breakpoint bp_info; | |
1919 | ||
f68d2048 | 1920 | if (!access_ok(VERIFY_READ, datavp, |
3162d92d DK |
1921 | sizeof(struct ppc_hw_breakpoint))) |
1922 | return -EFAULT; | |
f68d2048 | 1923 | ret = __copy_from_user(&bp_info, datavp, |
3162d92d DK |
1924 | sizeof(struct ppc_hw_breakpoint)) ? |
1925 | -EFAULT : 0; | |
1926 | if (!ret) | |
1927 | ret = ppc_set_hwdebug(child, &bp_info); | |
1928 | break; | |
1929 | } | |
1930 | ||
1931 | case PPC_PTRACE_DELHWDEBUG: { | |
ec1b33dc | 1932 | ret = ppc_del_hwdebug(child, data); |
3162d92d DK |
1933 | break; |
1934 | } | |
1935 | ||
e8a30302 | 1936 | case PTRACE_GET_DEBUGREG: { |
9422de3e MN |
1937 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
1938 | unsigned long dabr_fake; | |
1939 | #endif | |
e8a30302 SR |
1940 | ret = -EINVAL; |
1941 | /* We only support one DABR and no IABRS at the moment */ | |
1942 | if (addr > 0) | |
1943 | break; | |
3bffb652 | 1944 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a | 1945 | ret = put_user(child->thread.debug.dac1, datalp); |
3bffb652 | 1946 | #else |
9422de3e MN |
1947 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
1948 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); | |
1949 | ret = put_user(dabr_fake, datalp); | |
3bffb652 | 1950 | #endif |
e8a30302 SR |
1951 | break; |
1952 | } | |
1953 | ||
1954 | case PTRACE_SET_DEBUGREG: | |
1955 | ret = ptrace_set_debugreg(child, addr, data); | |
1956 | break; | |
e8a30302 | 1957 | |
e17666ba BH |
1958 | #ifdef CONFIG_PPC64 |
1959 | case PTRACE_GETREGS64: | |
1960 | #endif | |
c391cd00 RM |
1961 | case PTRACE_GETREGS: /* Get all pt_regs from the child. */ |
1962 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1963 | REGSET_GPR, | |
1964 | 0, sizeof(struct pt_regs), | |
f68d2048 | 1965 | datavp); |
e8a30302 | 1966 | |
e17666ba BH |
1967 | #ifdef CONFIG_PPC64 |
1968 | case PTRACE_SETREGS64: | |
1969 | #endif | |
c391cd00 RM |
1970 | case PTRACE_SETREGS: /* Set all gp regs in the child. */ |
1971 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1972 | REGSET_GPR, | |
1973 | 0, sizeof(struct pt_regs), | |
f68d2048 | 1974 | datavp); |
c391cd00 RM |
1975 | |
1976 | case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ | |
1977 | return copy_regset_to_user(child, &user_ppc_native_view, | |
1978 | REGSET_FPR, | |
1979 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 1980 | datavp); |
c391cd00 RM |
1981 | |
1982 | case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ | |
1983 | return copy_regset_from_user(child, &user_ppc_native_view, | |
1984 | REGSET_FPR, | |
1985 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 1986 | datavp); |
e8a30302 | 1987 | |
1da177e4 LT |
1988 | #ifdef CONFIG_ALTIVEC |
1989 | case PTRACE_GETVRREGS: | |
c391cd00 RM |
1990 | return copy_regset_to_user(child, &user_ppc_native_view, |
1991 | REGSET_VMX, | |
1992 | 0, (33 * sizeof(vector128) + | |
1993 | sizeof(u32)), | |
f68d2048 | 1994 | datavp); |
1da177e4 LT |
1995 | |
1996 | case PTRACE_SETVRREGS: | |
c391cd00 RM |
1997 | return copy_regset_from_user(child, &user_ppc_native_view, |
1998 | REGSET_VMX, | |
1999 | 0, (33 * sizeof(vector128) + | |
2000 | sizeof(u32)), | |
f68d2048 | 2001 | datavp); |
1da177e4 | 2002 | #endif |
ce48b210 MN |
2003 | #ifdef CONFIG_VSX |
2004 | case PTRACE_GETVSRREGS: | |
2005 | return copy_regset_to_user(child, &user_ppc_native_view, | |
2006 | REGSET_VSX, | |
1ac42ef8 | 2007 | 0, 32 * sizeof(double), |
f68d2048 | 2008 | datavp); |
ce48b210 MN |
2009 | |
2010 | case PTRACE_SETVSRREGS: | |
2011 | return copy_regset_from_user(child, &user_ppc_native_view, | |
2012 | REGSET_VSX, | |
1ac42ef8 | 2013 | 0, 32 * sizeof(double), |
f68d2048 | 2014 | datavp); |
ce48b210 | 2015 | #endif |
1da177e4 LT |
2016 | #ifdef CONFIG_SPE |
2017 | case PTRACE_GETEVRREGS: | |
2018 | /* Get the child spe register state. */ | |
c391cd00 RM |
2019 | return copy_regset_to_user(child, &user_ppc_native_view, |
2020 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 2021 | datavp); |
1da177e4 LT |
2022 | |
2023 | case PTRACE_SETEVRREGS: | |
2024 | /* Set the child spe register state. */ | |
c391cd00 RM |
2025 | return copy_regset_from_user(child, &user_ppc_native_view, |
2026 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 2027 | datavp); |
1da177e4 LT |
2028 | #endif |
2029 | ||
2030 | default: | |
2031 | ret = ptrace_request(child, request, addr, data); | |
2032 | break; | |
2033 | } | |
1da177e4 LT |
2034 | return ret; |
2035 | } | |
2036 | ||
2449acc5 ME |
2037 | #ifdef CONFIG_SECCOMP |
2038 | static int do_seccomp(struct pt_regs *regs) | |
2039 | { | |
2040 | if (!test_thread_flag(TIF_SECCOMP)) | |
2041 | return 0; | |
2042 | ||
2043 | /* | |
2044 | * The ABI we present to seccomp tracers is that r3 contains | |
2045 | * the syscall return value and orig_gpr3 contains the first | |
2046 | * syscall parameter. This is different to the ptrace ABI where | |
2047 | * both r3 and orig_gpr3 contain the first syscall parameter. | |
2048 | */ | |
2049 | regs->gpr[3] = -ENOSYS; | |
2050 | ||
2051 | /* | |
2052 | * We use the __ version here because we have already checked | |
2053 | * TIF_SECCOMP. If this fails, there is nothing left to do, we | |
2054 | * have already loaded -ENOSYS into r3, or seccomp has put | |
2055 | * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). | |
2056 | */ | |
2f275de5 | 2057 | if (__secure_computing(NULL)) |
2449acc5 ME |
2058 | return -1; |
2059 | ||
2060 | /* | |
2061 | * The syscall was allowed by seccomp, restore the register | |
1addc57e | 2062 | * state to what audit expects. |
2449acc5 ME |
2063 | * Note that we use orig_gpr3, which means a seccomp tracer can |
2064 | * modify the first syscall parameter (in orig_gpr3) and also | |
2065 | * allow the syscall to proceed. | |
2066 | */ | |
2067 | regs->gpr[3] = regs->orig_gpr3; | |
2068 | ||
2069 | return 0; | |
2070 | } | |
2071 | #else | |
2072 | static inline int do_seccomp(struct pt_regs *regs) { return 0; } | |
2073 | #endif /* CONFIG_SECCOMP */ | |
2074 | ||
d3837414 ME |
2075 | /** |
2076 | * do_syscall_trace_enter() - Do syscall tracing on kernel entry. | |
2077 | * @regs: the pt_regs of the task to trace (current) | |
2078 | * | |
2079 | * Performs various types of tracing on syscall entry. This includes seccomp, | |
2080 | * ptrace, syscall tracepoints and audit. | |
2081 | * | |
2082 | * The pt_regs are potentially visible to userspace via ptrace, so their | |
2083 | * contents is ABI. | |
2084 | * | |
2085 | * One or more of the tracers may modify the contents of pt_regs, in particular | |
2086 | * to modify arguments or even the syscall number itself. | |
2087 | * | |
2088 | * It's also possible that a tracer can choose to reject the system call. In | |
2089 | * that case this function will return an illegal syscall number, and will put | |
2090 | * an appropriate return value in regs->r3. | |
2091 | * | |
2092 | * Return: the (possibly changed) syscall number. | |
4f72c427 RM |
2093 | */ |
2094 | long do_syscall_trace_enter(struct pt_regs *regs) | |
1da177e4 | 2095 | { |
22ecbe8d LZ |
2096 | user_exit(); |
2097 | ||
1addc57e KC |
2098 | /* |
2099 | * The tracer may decide to abort the syscall, if so tracehook | |
2100 | * will return !0. Note that the tracer may also just change | |
2101 | * regs->gpr[0] to an invalid syscall number, that is handled | |
2102 | * below on the exit path. | |
2103 | */ | |
2104 | if (test_thread_flag(TIF_SYSCALL_TRACE) && | |
2105 | tracehook_report_syscall_entry(regs)) | |
2106 | goto skip; | |
2107 | ||
2108 | /* Run seccomp after ptrace; allow it to set gpr[3]. */ | |
2449acc5 ME |
2109 | if (do_seccomp(regs)) |
2110 | return -1; | |
e8a30302 | 2111 | |
1addc57e KC |
2112 | /* Avoid trace and audit when syscall is invalid. */ |
2113 | if (regs->gpr[0] >= NR_syscalls) | |
2114 | goto skip; | |
ea9c102c | 2115 | |
02424d89 IM |
2116 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
2117 | trace_sys_enter(regs, regs->gpr[0]); | |
2118 | ||
cfcd1705 | 2119 | #ifdef CONFIG_PPC64 |
b05d8447 | 2120 | if (!is_32bit_task()) |
91397401 | 2121 | audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], |
b05d8447 EP |
2122 | regs->gpr[5], regs->gpr[6]); |
2123 | else | |
e8a30302 | 2124 | #endif |
91397401 | 2125 | audit_syscall_entry(regs->gpr[0], |
b05d8447 EP |
2126 | regs->gpr[3] & 0xffffffff, |
2127 | regs->gpr[4] & 0xffffffff, | |
2128 | regs->gpr[5] & 0xffffffff, | |
2129 | regs->gpr[6] & 0xffffffff); | |
4f72c427 | 2130 | |
d3837414 ME |
2131 | /* Return the possibly modified but valid syscall number */ |
2132 | return regs->gpr[0]; | |
1addc57e KC |
2133 | |
2134 | skip: | |
2135 | /* | |
2136 | * If we are aborting explicitly, or if the syscall number is | |
2137 | * now invalid, set the return value to -ENOSYS. | |
2138 | */ | |
2139 | regs->gpr[3] = -ENOSYS; | |
2140 | return -1; | |
ea9c102c DW |
2141 | } |
2142 | ||
2143 | void do_syscall_trace_leave(struct pt_regs *regs) | |
2144 | { | |
4f72c427 RM |
2145 | int step; |
2146 | ||
d7e7528b | 2147 | audit_syscall_exit(regs); |
ea9c102c | 2148 | |
02424d89 IM |
2149 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
2150 | trace_sys_exit(regs, regs->result); | |
2151 | ||
4f72c427 RM |
2152 | step = test_thread_flag(TIF_SINGLESTEP); |
2153 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) | |
2154 | tracehook_report_syscall_exit(regs, step); | |
22ecbe8d LZ |
2155 | |
2156 | user_enter(); | |
ea9c102c | 2157 | } |