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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/smp.h> | |
1da177e4 LT |
22 | #include <linux/errno.h> |
23 | #include <linux/ptrace.h> | |
f65255e8 | 24 | #include <linux/regset.h> |
4f72c427 | 25 | #include <linux/tracehook.h> |
3caf06c6 | 26 | #include <linux/elf.h> |
1da177e4 LT |
27 | #include <linux/user.h> |
28 | #include <linux/security.h> | |
7ed20e1a | 29 | #include <linux/signal.h> |
ea9c102c DW |
30 | #include <linux/seccomp.h> |
31 | #include <linux/audit.h> | |
02424d89 | 32 | #include <trace/syscall.h> |
5aae8a53 P |
33 | #include <linux/hw_breakpoint.h> |
34 | #include <linux/perf_event.h> | |
22ecbe8d | 35 | #include <linux/context_tracking.h> |
1da177e4 LT |
36 | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
ae3a197e | 40 | #include <asm/switch_to.h> |
21a62902 | 41 | |
02424d89 IM |
42 | #define CREATE_TRACE_POINTS |
43 | #include <trace/events/syscalls.h> | |
44 | ||
359e4284 MS |
45 | /* |
46 | * The parameter save area on the stack is used to store arguments being passed | |
47 | * to callee function and is located at fixed offset from stack pointer. | |
48 | */ | |
49 | #ifdef CONFIG_PPC32 | |
50 | #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */ | |
51 | #else /* CONFIG_PPC32 */ | |
52 | #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */ | |
53 | #endif | |
54 | ||
55 | struct pt_regs_offset { | |
56 | const char *name; | |
57 | int offset; | |
58 | }; | |
59 | ||
60 | #define STR(s) #s /* convert to string */ | |
61 | #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)} | |
62 | #define GPR_OFFSET_NAME(num) \ | |
343c3327 | 63 | {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \ |
359e4284 MS |
64 | {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])} |
65 | #define REG_OFFSET_END {.name = NULL, .offset = 0} | |
66 | ||
8c13f599 | 67 | #define TVSO(f) (offsetof(struct thread_vr_state, f)) |
9d3918f7 | 68 | #define TFSO(f) (offsetof(struct thread_fp_state, f)) |
8c13f599 | 69 | |
359e4284 MS |
70 | static const struct pt_regs_offset regoffset_table[] = { |
71 | GPR_OFFSET_NAME(0), | |
72 | GPR_OFFSET_NAME(1), | |
73 | GPR_OFFSET_NAME(2), | |
74 | GPR_OFFSET_NAME(3), | |
75 | GPR_OFFSET_NAME(4), | |
76 | GPR_OFFSET_NAME(5), | |
77 | GPR_OFFSET_NAME(6), | |
78 | GPR_OFFSET_NAME(7), | |
79 | GPR_OFFSET_NAME(8), | |
80 | GPR_OFFSET_NAME(9), | |
81 | GPR_OFFSET_NAME(10), | |
82 | GPR_OFFSET_NAME(11), | |
83 | GPR_OFFSET_NAME(12), | |
84 | GPR_OFFSET_NAME(13), | |
85 | GPR_OFFSET_NAME(14), | |
86 | GPR_OFFSET_NAME(15), | |
87 | GPR_OFFSET_NAME(16), | |
88 | GPR_OFFSET_NAME(17), | |
89 | GPR_OFFSET_NAME(18), | |
90 | GPR_OFFSET_NAME(19), | |
91 | GPR_OFFSET_NAME(20), | |
92 | GPR_OFFSET_NAME(21), | |
93 | GPR_OFFSET_NAME(22), | |
94 | GPR_OFFSET_NAME(23), | |
95 | GPR_OFFSET_NAME(24), | |
96 | GPR_OFFSET_NAME(25), | |
97 | GPR_OFFSET_NAME(26), | |
98 | GPR_OFFSET_NAME(27), | |
99 | GPR_OFFSET_NAME(28), | |
100 | GPR_OFFSET_NAME(29), | |
101 | GPR_OFFSET_NAME(30), | |
102 | GPR_OFFSET_NAME(31), | |
103 | REG_OFFSET_NAME(nip), | |
104 | REG_OFFSET_NAME(msr), | |
105 | REG_OFFSET_NAME(ctr), | |
106 | REG_OFFSET_NAME(link), | |
107 | REG_OFFSET_NAME(xer), | |
108 | REG_OFFSET_NAME(ccr), | |
109 | #ifdef CONFIG_PPC64 | |
110 | REG_OFFSET_NAME(softe), | |
111 | #else | |
112 | REG_OFFSET_NAME(mq), | |
113 | #endif | |
114 | REG_OFFSET_NAME(trap), | |
115 | REG_OFFSET_NAME(dar), | |
116 | REG_OFFSET_NAME(dsisr), | |
117 | REG_OFFSET_END, | |
118 | }; | |
119 | ||
120 | /** | |
121 | * regs_query_register_offset() - query register offset from its name | |
122 | * @name: the name of a register | |
123 | * | |
124 | * regs_query_register_offset() returns the offset of a register in struct | |
125 | * pt_regs from its name. If the name is invalid, this returns -EINVAL; | |
126 | */ | |
127 | int regs_query_register_offset(const char *name) | |
128 | { | |
129 | const struct pt_regs_offset *roff; | |
130 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
131 | if (!strcmp(roff->name, name)) | |
132 | return roff->offset; | |
133 | return -EINVAL; | |
134 | } | |
135 | ||
136 | /** | |
137 | * regs_query_register_name() - query register name from its offset | |
138 | * @offset: the offset of a register in struct pt_regs. | |
139 | * | |
140 | * regs_query_register_name() returns the name of a register from its | |
141 | * offset in struct pt_regs. If the @offset is invalid, this returns NULL; | |
142 | */ | |
143 | const char *regs_query_register_name(unsigned int offset) | |
144 | { | |
145 | const struct pt_regs_offset *roff; | |
146 | for (roff = regoffset_table; roff->name != NULL; roff++) | |
147 | if (roff->offset == offset) | |
148 | return roff->name; | |
149 | return NULL; | |
150 | } | |
151 | ||
abd06505 BH |
152 | /* |
153 | * does not yet catch signals sent when the child dies. | |
154 | * in exit.c or in signal.c. | |
155 | */ | |
156 | ||
157 | /* | |
158 | * Set of msr bits that gdb can change on behalf of a process. | |
159 | */ | |
172ae2e7 | 160 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
abd06505 | 161 | #define MSR_DEBUGCHANGE 0 |
1da177e4 | 162 | #else |
abd06505 | 163 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) |
1da177e4 | 164 | #endif |
acd89828 | 165 | |
1da177e4 | 166 | /* |
abd06505 | 167 | * Max register writeable via put_reg |
1da177e4 | 168 | */ |
abd06505 BH |
169 | #ifdef CONFIG_PPC32 |
170 | #define PT_MAX_PUT_REG PT_MQ | |
171 | #else | |
172 | #define PT_MAX_PUT_REG PT_CCR | |
173 | #endif | |
1da177e4 | 174 | |
26f77130 RM |
175 | static unsigned long get_user_msr(struct task_struct *task) |
176 | { | |
177 | return task->thread.regs->msr | task->thread.fpexc_mode; | |
178 | } | |
179 | ||
180 | static int set_user_msr(struct task_struct *task, unsigned long msr) | |
181 | { | |
182 | task->thread.regs->msr &= ~MSR_DEBUGCHANGE; | |
183 | task->thread.regs->msr |= msr & MSR_DEBUGCHANGE; | |
184 | return 0; | |
185 | } | |
186 | ||
25847fb1 AK |
187 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
188 | static unsigned long get_user_ckpt_msr(struct task_struct *task) | |
189 | { | |
190 | return task->thread.ckpt_regs.msr | task->thread.fpexc_mode; | |
191 | } | |
192 | ||
193 | static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr) | |
194 | { | |
195 | task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE; | |
196 | task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE; | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap) | |
201 | { | |
202 | task->thread.ckpt_regs.trap = trap & 0xfff0; | |
203 | return 0; | |
204 | } | |
205 | #endif | |
206 | ||
1715a826 | 207 | #ifdef CONFIG_PPC64 |
ee4a3916 | 208 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 | 209 | { |
ee4a3916 AK |
210 | *data = task->thread.dscr; |
211 | return 0; | |
1715a826 AK |
212 | } |
213 | ||
214 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
215 | { | |
216 | task->thread.dscr = dscr; | |
217 | task->thread.dscr_inherit = 1; | |
218 | return 0; | |
219 | } | |
220 | #else | |
ee4a3916 | 221 | static int get_user_dscr(struct task_struct *task, unsigned long *data) |
1715a826 AK |
222 | { |
223 | return -EIO; | |
224 | } | |
225 | ||
226 | static int set_user_dscr(struct task_struct *task, unsigned long dscr) | |
227 | { | |
228 | return -EIO; | |
229 | } | |
230 | #endif | |
231 | ||
26f77130 RM |
232 | /* |
233 | * We prevent mucking around with the reserved area of trap | |
234 | * which are used internally by the kernel. | |
235 | */ | |
236 | static int set_user_trap(struct task_struct *task, unsigned long trap) | |
237 | { | |
238 | task->thread.regs->trap = trap & 0xfff0; | |
239 | return 0; | |
240 | } | |
241 | ||
865418d8 BH |
242 | /* |
243 | * Get contents of register REGNO in task TASK. | |
244 | */ | |
ee4a3916 | 245 | int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data) |
865418d8 | 246 | { |
ee4a3916 | 247 | if ((task->thread.regs == NULL) || !data) |
865418d8 BH |
248 | return -EIO; |
249 | ||
ee4a3916 AK |
250 | if (regno == PT_MSR) { |
251 | *data = get_user_msr(task); | |
252 | return 0; | |
253 | } | |
865418d8 | 254 | |
1715a826 | 255 | if (regno == PT_DSCR) |
ee4a3916 | 256 | return get_user_dscr(task, data); |
1715a826 | 257 | |
ee4a3916 AK |
258 | if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) { |
259 | *data = ((unsigned long *)task->thread.regs)[regno]; | |
260 | return 0; | |
261 | } | |
865418d8 BH |
262 | |
263 | return -EIO; | |
264 | } | |
265 | ||
266 | /* | |
267 | * Write contents of register REGNO in task TASK. | |
268 | */ | |
269 | int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data) | |
270 | { | |
271 | if (task->thread.regs == NULL) | |
272 | return -EIO; | |
273 | ||
26f77130 RM |
274 | if (regno == PT_MSR) |
275 | return set_user_msr(task, data); | |
276 | if (regno == PT_TRAP) | |
277 | return set_user_trap(task, data); | |
1715a826 AK |
278 | if (regno == PT_DSCR) |
279 | return set_user_dscr(task, data); | |
26f77130 RM |
280 | |
281 | if (regno <= PT_MAX_PUT_REG) { | |
865418d8 BH |
282 | ((unsigned long *)task->thread.regs)[regno] = data; |
283 | return 0; | |
284 | } | |
285 | return -EIO; | |
286 | } | |
287 | ||
44dd3f50 RM |
288 | static int gpr_get(struct task_struct *target, const struct user_regset *regset, |
289 | unsigned int pos, unsigned int count, | |
290 | void *kbuf, void __user *ubuf) | |
291 | { | |
a71f5d5d | 292 | int i, ret; |
44dd3f50 RM |
293 | |
294 | if (target->thread.regs == NULL) | |
295 | return -EIO; | |
296 | ||
a71f5d5d MW |
297 | if (!FULL_REGS(target->thread.regs)) { |
298 | /* We have a partial register set. Fill 14-31 with bogus values */ | |
299 | for (i = 14; i < 32; i++) | |
300 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
301 | } | |
44dd3f50 RM |
302 | |
303 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
304 | target->thread.regs, | |
305 | 0, offsetof(struct pt_regs, msr)); | |
306 | if (!ret) { | |
307 | unsigned long msr = get_user_msr(target); | |
308 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
309 | offsetof(struct pt_regs, msr), | |
310 | offsetof(struct pt_regs, msr) + | |
311 | sizeof(msr)); | |
312 | } | |
313 | ||
314 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
315 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
316 | ||
317 | if (!ret) | |
318 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
319 | &target->thread.regs->orig_gpr3, | |
320 | offsetof(struct pt_regs, orig_gpr3), | |
321 | sizeof(struct pt_regs)); | |
322 | if (!ret) | |
323 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
324 | sizeof(struct pt_regs), -1); | |
325 | ||
326 | return ret; | |
327 | } | |
328 | ||
329 | static int gpr_set(struct task_struct *target, const struct user_regset *regset, | |
330 | unsigned int pos, unsigned int count, | |
331 | const void *kbuf, const void __user *ubuf) | |
332 | { | |
333 | unsigned long reg; | |
334 | int ret; | |
335 | ||
336 | if (target->thread.regs == NULL) | |
337 | return -EIO; | |
338 | ||
339 | CHECK_FULL_REGS(target->thread.regs); | |
340 | ||
341 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
342 | target->thread.regs, | |
343 | 0, PT_MSR * sizeof(reg)); | |
344 | ||
345 | if (!ret && count > 0) { | |
346 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
347 | PT_MSR * sizeof(reg), | |
348 | (PT_MSR + 1) * sizeof(reg)); | |
349 | if (!ret) | |
350 | ret = set_user_msr(target, reg); | |
351 | } | |
352 | ||
353 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
354 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
355 | ||
356 | if (!ret) | |
357 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
358 | &target->thread.regs->orig_gpr3, | |
359 | PT_ORIG_R3 * sizeof(reg), | |
360 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
361 | ||
362 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
363 | ret = user_regset_copyin_ignore( | |
364 | &pos, &count, &kbuf, &ubuf, | |
365 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
366 | PT_TRAP * sizeof(reg)); | |
367 | ||
368 | if (!ret && count > 0) { | |
369 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
370 | PT_TRAP * sizeof(reg), | |
371 | (PT_TRAP + 1) * sizeof(reg)); | |
372 | if (!ret) | |
373 | ret = set_user_trap(target, reg); | |
374 | } | |
375 | ||
376 | if (!ret) | |
377 | ret = user_regset_copyin_ignore( | |
378 | &pos, &count, &kbuf, &ubuf, | |
379 | (PT_TRAP + 1) * sizeof(reg), -1); | |
380 | ||
381 | return ret; | |
382 | } | |
865418d8 | 383 | |
1ec8549d AK |
384 | /* |
385 | * When the transaction is active, 'transact_fp' holds the current running | |
386 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
387 | * value of all FPR registers for the current transaction. When transaction | |
388 | * is not active 'fp_state' holds the current running state of all the FPR | |
389 | * registers. So this function which returns the current running values of | |
390 | * all the FPR registers, needs to know whether any transaction is active | |
391 | * or not. | |
392 | * | |
393 | * Userspace interface buffer layout: | |
394 | * | |
395 | * struct data { | |
396 | * u64 fpr[32]; | |
397 | * u64 fpscr; | |
398 | * }; | |
399 | * | |
400 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
401 | * which determines the final code in this function. All the combinations of | |
402 | * these two config options are possible except the one below as transactional | |
403 | * memory config pulls in CONFIG_VSX automatically. | |
404 | * | |
405 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
406 | */ | |
f65255e8 RM |
407 | static int fpr_get(struct task_struct *target, const struct user_regset *regset, |
408 | unsigned int pos, unsigned int count, | |
409 | void *kbuf, void __user *ubuf) | |
410 | { | |
c6e6771b | 411 | #ifdef CONFIG_VSX |
de79f7b9 | 412 | u64 buf[33]; |
c6e6771b MN |
413 | int i; |
414 | #endif | |
f65255e8 RM |
415 | flush_fp_to_thread(target); |
416 | ||
1ec8549d AK |
417 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
418 | /* copy to local buffer then write that out */ | |
419 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
420 | flush_altivec_to_thread(target); | |
421 | flush_tmregs_to_thread(target); | |
422 | for (i = 0; i < 32 ; i++) | |
423 | buf[i] = target->thread.TS_TRANS_FPR(i); | |
424 | buf[32] = target->thread.transact_fp.fpscr; | |
425 | } else { | |
426 | for (i = 0; i < 32 ; i++) | |
427 | buf[i] = target->thread.TS_FPR(i); | |
428 | buf[32] = target->thread.fp_state.fpscr; | |
429 | } | |
430 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
431 | #endif | |
432 | ||
433 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
434 | /* copy to local buffer then write that out */ |
435 | for (i = 0; i < 32 ; i++) | |
436 | buf[i] = target->thread.TS_FPR(i); | |
de79f7b9 | 437 | buf[32] = target->thread.fp_state.fpscr; |
c6e6771b | 438 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); |
1ec8549d | 439 | #endif |
c6e6771b | 440 | |
1ec8549d | 441 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
de79f7b9 | 442 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 443 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
444 | |
445 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 446 | &target->thread.fp_state, 0, -1); |
c6e6771b | 447 | #endif |
f65255e8 RM |
448 | } |
449 | ||
1ec8549d AK |
450 | /* |
451 | * When the transaction is active, 'transact_fp' holds the current running | |
452 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
453 | * value of all FPR registers for the current transaction. When transaction | |
454 | * is not active 'fp_state' holds the current running state of all the FPR | |
455 | * registers. So this function which setss the current running values of | |
456 | * all the FPR registers, needs to know whether any transaction is active | |
457 | * or not. | |
458 | * | |
459 | * Userspace interface buffer layout: | |
460 | * | |
461 | * struct data { | |
462 | * u64 fpr[32]; | |
463 | * u64 fpscr; | |
464 | * }; | |
465 | * | |
466 | * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM | |
467 | * which determines the final code in this function. All the combinations of | |
468 | * these two config options are possible except the one below as transactional | |
469 | * memory config pulls in CONFIG_VSX automatically. | |
470 | * | |
471 | * !defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
472 | */ | |
f65255e8 RM |
473 | static int fpr_set(struct task_struct *target, const struct user_regset *regset, |
474 | unsigned int pos, unsigned int count, | |
475 | const void *kbuf, const void __user *ubuf) | |
476 | { | |
c6e6771b | 477 | #ifdef CONFIG_VSX |
de79f7b9 | 478 | u64 buf[33]; |
c6e6771b MN |
479 | int i; |
480 | #endif | |
f65255e8 RM |
481 | flush_fp_to_thread(target); |
482 | ||
1ec8549d AK |
483 | #if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM) |
484 | /* copy to local buffer then write that out */ | |
485 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
486 | if (i) | |
487 | return i; | |
488 | ||
489 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
490 | flush_altivec_to_thread(target); | |
491 | flush_tmregs_to_thread(target); | |
492 | for (i = 0; i < 32 ; i++) | |
493 | target->thread.TS_TRANS_FPR(i) = buf[i]; | |
494 | target->thread.transact_fp.fpscr = buf[32]; | |
495 | } else { | |
496 | for (i = 0; i < 32 ; i++) | |
497 | target->thread.TS_FPR(i) = buf[i]; | |
498 | target->thread.fp_state.fpscr = buf[32]; | |
499 | } | |
500 | return 0; | |
501 | #endif | |
502 | ||
503 | #if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
c6e6771b MN |
504 | /* copy to local buffer then write that out */ |
505 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
506 | if (i) | |
507 | return i; | |
508 | for (i = 0; i < 32 ; i++) | |
509 | target->thread.TS_FPR(i) = buf[i]; | |
de79f7b9 | 510 | target->thread.fp_state.fpscr = buf[32]; |
c6e6771b | 511 | return 0; |
1ec8549d AK |
512 | #endif |
513 | ||
514 | #if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM) | |
de79f7b9 | 515 | BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) != |
1e407ee3 | 516 | offsetof(struct thread_fp_state, fpr[32])); |
f65255e8 RM |
517 | |
518 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
de79f7b9 | 519 | &target->thread.fp_state, 0, -1); |
c6e6771b | 520 | #endif |
f65255e8 RM |
521 | } |
522 | ||
865418d8 BH |
523 | #ifdef CONFIG_ALTIVEC |
524 | /* | |
525 | * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. | |
526 | * The transfer totals 34 quadword. Quadwords 0-31 contain the | |
527 | * corresponding vector registers. Quadword 32 contains the vscr as the | |
528 | * last word (offset 12) within that quadword. Quadword 33 contains the | |
529 | * vrsave as the first word (offset 0) within the quadword. | |
530 | * | |
531 | * This definition of the VMX state is compatible with the current PPC32 | |
532 | * ptrace interface. This allows signal handling and ptrace to use the | |
533 | * same structures. This also simplifies the implementation of a bi-arch | |
534 | * (combined (32- and 64-bit) gdb. | |
535 | */ | |
536 | ||
3caf06c6 RM |
537 | static int vr_active(struct task_struct *target, |
538 | const struct user_regset *regset) | |
539 | { | |
540 | flush_altivec_to_thread(target); | |
541 | return target->thread.used_vr ? regset->n : 0; | |
542 | } | |
543 | ||
d844e279 AK |
544 | /* |
545 | * When the transaction is active, 'transact_vr' holds the current running | |
546 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
547 | * value of all the VMX registers for the current transaction to fall back | |
548 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
549 | * the current running state of all the VMX registers. So this function which | |
550 | * gets the current running values of all the VMX registers, needs to know | |
551 | * whether any transaction is active or not. | |
552 | * | |
553 | * Userspace interface buffer layout: | |
554 | * | |
555 | * struct data { | |
556 | * vector128 vr[32]; | |
557 | * vector128 vscr; | |
558 | * vector128 vrsave; | |
559 | * }; | |
560 | */ | |
3caf06c6 RM |
561 | static int vr_get(struct task_struct *target, const struct user_regset *regset, |
562 | unsigned int pos, unsigned int count, | |
563 | void *kbuf, void __user *ubuf) | |
564 | { | |
d844e279 | 565 | struct thread_vr_state *addr; |
3caf06c6 RM |
566 | int ret; |
567 | ||
568 | flush_altivec_to_thread(target); | |
569 | ||
de79f7b9 PM |
570 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
571 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 572 | |
d844e279 AK |
573 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
574 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
575 | flush_fp_to_thread(target); | |
576 | flush_tmregs_to_thread(target); | |
577 | addr = &target->thread.transact_vr; | |
578 | } else { | |
579 | addr = &target->thread.vr_state; | |
580 | } | |
581 | #else | |
582 | addr = &target->thread.vr_state; | |
583 | #endif | |
3caf06c6 | 584 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
d844e279 | 585 | addr, 0, |
3caf06c6 RM |
586 | 33 * sizeof(vector128)); |
587 | if (!ret) { | |
588 | /* | |
589 | * Copy out only the low-order word of vrsave. | |
590 | */ | |
591 | union { | |
592 | elf_vrreg_t reg; | |
593 | u32 word; | |
594 | } vrsave; | |
595 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
596 | |
597 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
598 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
599 | vrsave.word = target->thread.transact_vrsave; | |
600 | else | |
601 | vrsave.word = target->thread.vrsave; | |
602 | #else | |
3caf06c6 | 603 | vrsave.word = target->thread.vrsave; |
d844e279 AK |
604 | #endif |
605 | ||
3caf06c6 RM |
606 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, |
607 | 33 * sizeof(vector128), -1); | |
608 | } | |
609 | ||
610 | return ret; | |
611 | } | |
612 | ||
d844e279 AK |
613 | /* |
614 | * When the transaction is active, 'transact_vr' holds the current running | |
615 | * value of all the VMX registers and 'vr_state' holds the last checkpointed | |
616 | * value of all the VMX registers for the current transaction to fall back | |
617 | * on in case it aborts. When transaction is not active 'vr_state' holds | |
618 | * the current running state of all the VMX registers. So this function which | |
619 | * sets the current running values of all the VMX registers, needs to know | |
620 | * whether any transaction is active or not. | |
621 | * | |
622 | * Userspace interface buffer layout: | |
623 | * | |
624 | * struct data { | |
625 | * vector128 vr[32]; | |
626 | * vector128 vscr; | |
627 | * vector128 vrsave; | |
628 | * }; | |
629 | */ | |
3caf06c6 RM |
630 | static int vr_set(struct task_struct *target, const struct user_regset *regset, |
631 | unsigned int pos, unsigned int count, | |
632 | const void *kbuf, const void __user *ubuf) | |
633 | { | |
d844e279 | 634 | struct thread_vr_state *addr; |
3caf06c6 RM |
635 | int ret; |
636 | ||
637 | flush_altivec_to_thread(target); | |
638 | ||
de79f7b9 PM |
639 | BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != |
640 | offsetof(struct thread_vr_state, vr[32])); | |
3caf06c6 | 641 | |
d844e279 AK |
642 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
643 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
644 | flush_fp_to_thread(target); | |
645 | flush_tmregs_to_thread(target); | |
646 | addr = &target->thread.transact_vr; | |
647 | } else { | |
648 | addr = &target->thread.vr_state; | |
649 | } | |
650 | #else | |
651 | addr = &target->thread.vr_state; | |
652 | #endif | |
3caf06c6 | 653 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
d844e279 | 654 | addr, 0, |
de79f7b9 | 655 | 33 * sizeof(vector128)); |
3caf06c6 RM |
656 | if (!ret && count > 0) { |
657 | /* | |
658 | * We use only the first word of vrsave. | |
659 | */ | |
660 | union { | |
661 | elf_vrreg_t reg; | |
662 | u32 word; | |
663 | } vrsave; | |
664 | memset(&vrsave, 0, sizeof(vrsave)); | |
d844e279 AK |
665 | |
666 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
667 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
668 | vrsave.word = target->thread.transact_vrsave; | |
669 | else | |
670 | vrsave.word = target->thread.vrsave; | |
671 | #else | |
3caf06c6 | 672 | vrsave.word = target->thread.vrsave; |
d844e279 | 673 | #endif |
3caf06c6 RM |
674 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, |
675 | 33 * sizeof(vector128), -1); | |
d844e279 AK |
676 | if (!ret) { |
677 | ||
678 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
679 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) | |
680 | target->thread.transact_vrsave = vrsave.word; | |
681 | else | |
682 | target->thread.vrsave = vrsave.word; | |
683 | #else | |
3caf06c6 | 684 | target->thread.vrsave = vrsave.word; |
d844e279 AK |
685 | #endif |
686 | } | |
3caf06c6 RM |
687 | } |
688 | ||
689 | return ret; | |
690 | } | |
865418d8 BH |
691 | #endif /* CONFIG_ALTIVEC */ |
692 | ||
ce48b210 MN |
693 | #ifdef CONFIG_VSX |
694 | /* | |
695 | * Currently to set and and get all the vsx state, you need to call | |
25985edc | 696 | * the fp and VMX calls as well. This only get/sets the lower 32 |
ce48b210 MN |
697 | * 128bit VSX registers. |
698 | */ | |
699 | ||
700 | static int vsr_active(struct task_struct *target, | |
701 | const struct user_regset *regset) | |
702 | { | |
703 | flush_vsx_to_thread(target); | |
704 | return target->thread.used_vsr ? regset->n : 0; | |
705 | } | |
706 | ||
94b7d361 AK |
707 | /* |
708 | * When the transaction is active, 'transact_fp' holds the current running | |
709 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
710 | * value of all FPR registers for the current transaction. When transaction | |
711 | * is not active 'fp_state' holds the current running state of all the FPR | |
712 | * registers. So this function which returns the current running values of | |
713 | * all the FPR registers, needs to know whether any transaction is active | |
714 | * or not. | |
715 | * | |
716 | * Userspace interface buffer layout: | |
717 | * | |
718 | * struct data { | |
719 | * u64 vsx[32]; | |
720 | * }; | |
721 | */ | |
ce48b210 MN |
722 | static int vsr_get(struct task_struct *target, const struct user_regset *regset, |
723 | unsigned int pos, unsigned int count, | |
724 | void *kbuf, void __user *ubuf) | |
725 | { | |
de79f7b9 | 726 | u64 buf[32]; |
f3e909c2 | 727 | int ret, i; |
ce48b210 | 728 | |
94b7d361 AK |
729 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
730 | flush_fp_to_thread(target); | |
731 | flush_altivec_to_thread(target); | |
732 | flush_tmregs_to_thread(target); | |
733 | #endif | |
ce48b210 MN |
734 | flush_vsx_to_thread(target); |
735 | ||
94b7d361 AK |
736 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
737 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
738 | for (i = 0; i < 32 ; i++) | |
739 | buf[i] = target->thread. | |
740 | transact_fp.fpr[i][TS_VSRLOWOFFSET]; | |
741 | } else { | |
742 | for (i = 0; i < 32 ; i++) | |
743 | buf[i] = target->thread. | |
744 | fp_state.fpr[i][TS_VSRLOWOFFSET]; | |
745 | } | |
746 | #else | |
f3e909c2 | 747 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 748 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; |
94b7d361 | 749 | #endif |
ce48b210 | 750 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
f3e909c2 | 751 | buf, 0, 32 * sizeof(double)); |
ce48b210 MN |
752 | |
753 | return ret; | |
754 | } | |
755 | ||
94b7d361 AK |
756 | /* |
757 | * When the transaction is active, 'transact_fp' holds the current running | |
758 | * value of all FPR registers and 'fp_state' holds the last checkpointed | |
759 | * value of all FPR registers for the current transaction. When transaction | |
760 | * is not active 'fp_state' holds the current running state of all the FPR | |
761 | * registers. So this function which sets the current running values of all | |
762 | * the FPR registers, needs to know whether any transaction is active or not. | |
763 | * | |
764 | * Userspace interface buffer layout: | |
765 | * | |
766 | * struct data { | |
767 | * u64 vsx[32]; | |
768 | * }; | |
769 | */ | |
ce48b210 MN |
770 | static int vsr_set(struct task_struct *target, const struct user_regset *regset, |
771 | unsigned int pos, unsigned int count, | |
772 | const void *kbuf, const void __user *ubuf) | |
773 | { | |
de79f7b9 | 774 | u64 buf[32]; |
f3e909c2 | 775 | int ret,i; |
ce48b210 | 776 | |
94b7d361 AK |
777 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
778 | flush_fp_to_thread(target); | |
779 | flush_altivec_to_thread(target); | |
780 | flush_tmregs_to_thread(target); | |
781 | #endif | |
ce48b210 MN |
782 | flush_vsx_to_thread(target); |
783 | ||
784 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
f3e909c2 | 785 | buf, 0, 32 * sizeof(double)); |
94b7d361 AK |
786 | |
787 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
788 | if (MSR_TM_ACTIVE(target->thread.regs->msr)) { | |
789 | for (i = 0; i < 32 ; i++) | |
790 | target->thread.transact_fp. | |
791 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
792 | } else { | |
793 | for (i = 0; i < 32 ; i++) | |
794 | target->thread.fp_state. | |
795 | fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
796 | } | |
797 | #else | |
f3e909c2 | 798 | for (i = 0; i < 32 ; i++) |
de79f7b9 | 799 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; |
94b7d361 | 800 | #endif |
f3e909c2 | 801 | |
ce48b210 MN |
802 | |
803 | return ret; | |
804 | } | |
805 | #endif /* CONFIG_VSX */ | |
806 | ||
865418d8 BH |
807 | #ifdef CONFIG_SPE |
808 | ||
809 | /* | |
810 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
811 | * | |
812 | * struct { | |
813 | * u32 evr[32]; | |
814 | * u64 acc; | |
815 | * u32 spefscr; | |
816 | * } | |
817 | */ | |
818 | ||
a4e4b175 RM |
819 | static int evr_active(struct task_struct *target, |
820 | const struct user_regset *regset) | |
865418d8 | 821 | { |
a4e4b175 RM |
822 | flush_spe_to_thread(target); |
823 | return target->thread.used_spe ? regset->n : 0; | |
824 | } | |
865418d8 | 825 | |
a4e4b175 RM |
826 | static int evr_get(struct task_struct *target, const struct user_regset *regset, |
827 | unsigned int pos, unsigned int count, | |
828 | void *kbuf, void __user *ubuf) | |
829 | { | |
830 | int ret; | |
865418d8 | 831 | |
a4e4b175 | 832 | flush_spe_to_thread(target); |
865418d8 | 833 | |
a4e4b175 RM |
834 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
835 | &target->thread.evr, | |
836 | 0, sizeof(target->thread.evr)); | |
865418d8 | 837 | |
a4e4b175 RM |
838 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
839 | offsetof(struct thread_struct, spefscr)); | |
840 | ||
841 | if (!ret) | |
842 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
843 | &target->thread.acc, | |
844 | sizeof(target->thread.evr), -1); | |
845 | ||
846 | return ret; | |
847 | } | |
848 | ||
849 | static int evr_set(struct task_struct *target, const struct user_regset *regset, | |
850 | unsigned int pos, unsigned int count, | |
851 | const void *kbuf, const void __user *ubuf) | |
852 | { | |
853 | int ret; | |
854 | ||
855 | flush_spe_to_thread(target); | |
856 | ||
857 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
858 | &target->thread.evr, | |
859 | 0, sizeof(target->thread.evr)); | |
865418d8 | 860 | |
a4e4b175 RM |
861 | BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) != |
862 | offsetof(struct thread_struct, spefscr)); | |
863 | ||
864 | if (!ret) | |
865 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
866 | &target->thread.acc, | |
867 | sizeof(target->thread.evr), -1); | |
868 | ||
869 | return ret; | |
865418d8 | 870 | } |
865418d8 BH |
871 | #endif /* CONFIG_SPE */ |
872 | ||
25847fb1 AK |
873 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
874 | /** | |
875 | * tm_cgpr_active - get active number of registers in CGPR | |
876 | * @target: The target task. | |
877 | * @regset: The user regset structure. | |
878 | * | |
879 | * This function checks for the active number of available | |
880 | * regisers in transaction checkpointed GPR category. | |
881 | */ | |
882 | static int tm_cgpr_active(struct task_struct *target, | |
883 | const struct user_regset *regset) | |
884 | { | |
885 | if (!cpu_has_feature(CPU_FTR_TM)) | |
886 | return -ENODEV; | |
887 | ||
888 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
889 | return 0; | |
890 | ||
891 | return regset->n; | |
892 | } | |
893 | ||
894 | /** | |
895 | * tm_cgpr_get - get CGPR registers | |
896 | * @target: The target task. | |
897 | * @regset: The user regset structure. | |
898 | * @pos: The buffer position. | |
899 | * @count: Number of bytes to copy. | |
900 | * @kbuf: Kernel buffer to copy from. | |
901 | * @ubuf: User buffer to copy into. | |
902 | * | |
903 | * This function gets transaction checkpointed GPR registers. | |
904 | * | |
905 | * When the transaction is active, 'ckpt_regs' holds all the checkpointed | |
906 | * GPR register values for the current transaction to fall back on if it | |
907 | * aborts in between. This function gets those checkpointed GPR registers. | |
908 | * The userspace interface buffer layout is as follows. | |
909 | * | |
910 | * struct data { | |
911 | * struct pt_regs ckpt_regs; | |
912 | * }; | |
913 | */ | |
914 | static int tm_cgpr_get(struct task_struct *target, | |
915 | const struct user_regset *regset, | |
916 | unsigned int pos, unsigned int count, | |
917 | void *kbuf, void __user *ubuf) | |
918 | { | |
919 | int ret; | |
920 | ||
921 | if (!cpu_has_feature(CPU_FTR_TM)) | |
922 | return -ENODEV; | |
923 | ||
924 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
925 | return -ENODATA; | |
926 | ||
927 | flush_fp_to_thread(target); | |
928 | flush_altivec_to_thread(target); | |
929 | flush_tmregs_to_thread(target); | |
930 | ||
931 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
932 | &target->thread.ckpt_regs, | |
933 | 0, offsetof(struct pt_regs, msr)); | |
934 | if (!ret) { | |
935 | unsigned long msr = get_user_ckpt_msr(target); | |
936 | ||
937 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr, | |
938 | offsetof(struct pt_regs, msr), | |
939 | offsetof(struct pt_regs, msr) + | |
940 | sizeof(msr)); | |
941 | } | |
942 | ||
943 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
944 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
945 | ||
946 | if (!ret) | |
947 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
948 | &target->thread.ckpt_regs.orig_gpr3, | |
949 | offsetof(struct pt_regs, orig_gpr3), | |
950 | sizeof(struct pt_regs)); | |
951 | if (!ret) | |
952 | ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
953 | sizeof(struct pt_regs), -1); | |
954 | ||
955 | return ret; | |
956 | } | |
957 | ||
958 | /* | |
959 | * tm_cgpr_set - set the CGPR registers | |
960 | * @target: The target task. | |
961 | * @regset: The user regset structure. | |
962 | * @pos: The buffer position. | |
963 | * @count: Number of bytes to copy. | |
964 | * @kbuf: Kernel buffer to copy into. | |
965 | * @ubuf: User buffer to copy from. | |
966 | * | |
967 | * This function sets in transaction checkpointed GPR registers. | |
968 | * | |
969 | * When the transaction is active, 'ckpt_regs' holds the checkpointed | |
970 | * GPR register values for the current transaction to fall back on if it | |
971 | * aborts in between. This function sets those checkpointed GPR registers. | |
972 | * The userspace interface buffer layout is as follows. | |
973 | * | |
974 | * struct data { | |
975 | * struct pt_regs ckpt_regs; | |
976 | * }; | |
977 | */ | |
978 | static int tm_cgpr_set(struct task_struct *target, | |
979 | const struct user_regset *regset, | |
980 | unsigned int pos, unsigned int count, | |
981 | const void *kbuf, const void __user *ubuf) | |
982 | { | |
983 | unsigned long reg; | |
984 | int ret; | |
985 | ||
986 | if (!cpu_has_feature(CPU_FTR_TM)) | |
987 | return -ENODEV; | |
988 | ||
989 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
990 | return -ENODATA; | |
991 | ||
992 | flush_fp_to_thread(target); | |
993 | flush_altivec_to_thread(target); | |
994 | flush_tmregs_to_thread(target); | |
995 | ||
996 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
997 | &target->thread.ckpt_regs, | |
998 | 0, PT_MSR * sizeof(reg)); | |
999 | ||
1000 | if (!ret && count > 0) { | |
1001 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
1002 | PT_MSR * sizeof(reg), | |
1003 | (PT_MSR + 1) * sizeof(reg)); | |
1004 | if (!ret) | |
1005 | ret = set_user_ckpt_msr(target, reg); | |
1006 | } | |
1007 | ||
1008 | BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) != | |
1009 | offsetof(struct pt_regs, msr) + sizeof(long)); | |
1010 | ||
1011 | if (!ret) | |
1012 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1013 | &target->thread.ckpt_regs.orig_gpr3, | |
1014 | PT_ORIG_R3 * sizeof(reg), | |
1015 | (PT_MAX_PUT_REG + 1) * sizeof(reg)); | |
1016 | ||
1017 | if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret) | |
1018 | ret = user_regset_copyin_ignore( | |
1019 | &pos, &count, &kbuf, &ubuf, | |
1020 | (PT_MAX_PUT_REG + 1) * sizeof(reg), | |
1021 | PT_TRAP * sizeof(reg)); | |
1022 | ||
1023 | if (!ret && count > 0) { | |
1024 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®, | |
1025 | PT_TRAP * sizeof(reg), | |
1026 | (PT_TRAP + 1) * sizeof(reg)); | |
1027 | if (!ret) | |
1028 | ret = set_user_ckpt_trap(target, reg); | |
1029 | } | |
1030 | ||
1031 | if (!ret) | |
1032 | ret = user_regset_copyin_ignore( | |
1033 | &pos, &count, &kbuf, &ubuf, | |
1034 | (PT_TRAP + 1) * sizeof(reg), -1); | |
1035 | ||
1036 | return ret; | |
1037 | } | |
19cbcbf7 AK |
1038 | |
1039 | /** | |
1040 | * tm_cfpr_active - get active number of registers in CFPR | |
1041 | * @target: The target task. | |
1042 | * @regset: The user regset structure. | |
1043 | * | |
1044 | * This function checks for the active number of available | |
1045 | * regisers in transaction checkpointed FPR category. | |
1046 | */ | |
1047 | static int tm_cfpr_active(struct task_struct *target, | |
1048 | const struct user_regset *regset) | |
1049 | { | |
1050 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1051 | return -ENODEV; | |
1052 | ||
1053 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1054 | return 0; | |
1055 | ||
1056 | return regset->n; | |
1057 | } | |
1058 | ||
1059 | /** | |
1060 | * tm_cfpr_get - get CFPR registers | |
1061 | * @target: The target task. | |
1062 | * @regset: The user regset structure. | |
1063 | * @pos: The buffer position. | |
1064 | * @count: Number of bytes to copy. | |
1065 | * @kbuf: Kernel buffer to copy from. | |
1066 | * @ubuf: User buffer to copy into. | |
1067 | * | |
1068 | * This function gets in transaction checkpointed FPR registers. | |
1069 | * | |
1070 | * When the transaction is active 'fp_state' holds the checkpointed | |
1071 | * values for the current transaction to fall back on if it aborts | |
1072 | * in between. This function gets those checkpointed FPR registers. | |
1073 | * The userspace interface buffer layout is as follows. | |
1074 | * | |
1075 | * struct data { | |
1076 | * u64 fpr[32]; | |
1077 | * u64 fpscr; | |
1078 | *}; | |
1079 | */ | |
1080 | static int tm_cfpr_get(struct task_struct *target, | |
1081 | const struct user_regset *regset, | |
1082 | unsigned int pos, unsigned int count, | |
1083 | void *kbuf, void __user *ubuf) | |
1084 | { | |
1085 | u64 buf[33]; | |
1086 | int i; | |
1087 | ||
1088 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1089 | return -ENODEV; | |
1090 | ||
1091 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1092 | return -ENODATA; | |
1093 | ||
1094 | flush_fp_to_thread(target); | |
1095 | flush_altivec_to_thread(target); | |
1096 | flush_tmregs_to_thread(target); | |
1097 | ||
1098 | /* copy to local buffer then write that out */ | |
1099 | for (i = 0; i < 32 ; i++) | |
1100 | buf[i] = target->thread.TS_FPR(i); | |
1101 | buf[32] = target->thread.fp_state.fpscr; | |
1102 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
1103 | } | |
1104 | ||
1105 | /** | |
1106 | * tm_cfpr_set - set CFPR registers | |
1107 | * @target: The target task. | |
1108 | * @regset: The user regset structure. | |
1109 | * @pos: The buffer position. | |
1110 | * @count: Number of bytes to copy. | |
1111 | * @kbuf: Kernel buffer to copy into. | |
1112 | * @ubuf: User buffer to copy from. | |
1113 | * | |
1114 | * This function sets in transaction checkpointed FPR registers. | |
1115 | * | |
1116 | * When the transaction is active 'fp_state' holds the checkpointed | |
1117 | * FPR register values for the current transaction to fall back on | |
1118 | * if it aborts in between. This function sets these checkpointed | |
1119 | * FPR registers. The userspace interface buffer layout is as follows. | |
1120 | * | |
1121 | * struct data { | |
1122 | * u64 fpr[32]; | |
1123 | * u64 fpscr; | |
1124 | *}; | |
1125 | */ | |
1126 | static int tm_cfpr_set(struct task_struct *target, | |
1127 | const struct user_regset *regset, | |
1128 | unsigned int pos, unsigned int count, | |
1129 | const void *kbuf, const void __user *ubuf) | |
1130 | { | |
1131 | u64 buf[33]; | |
1132 | int i; | |
1133 | ||
1134 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1135 | return -ENODEV; | |
1136 | ||
1137 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1138 | return -ENODATA; | |
1139 | ||
1140 | flush_fp_to_thread(target); | |
1141 | flush_altivec_to_thread(target); | |
1142 | flush_tmregs_to_thread(target); | |
1143 | ||
1144 | /* copy to local buffer then write that out */ | |
1145 | i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1); | |
1146 | if (i) | |
1147 | return i; | |
1148 | for (i = 0; i < 32 ; i++) | |
1149 | target->thread.TS_FPR(i) = buf[i]; | |
1150 | target->thread.fp_state.fpscr = buf[32]; | |
1151 | return 0; | |
1152 | } | |
8c13f599 AK |
1153 | |
1154 | /** | |
1155 | * tm_cvmx_active - get active number of registers in CVMX | |
1156 | * @target: The target task. | |
1157 | * @regset: The user regset structure. | |
1158 | * | |
1159 | * This function checks for the active number of available | |
1160 | * regisers in checkpointed VMX category. | |
1161 | */ | |
1162 | static int tm_cvmx_active(struct task_struct *target, | |
1163 | const struct user_regset *regset) | |
1164 | { | |
1165 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1166 | return -ENODEV; | |
1167 | ||
1168 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1169 | return 0; | |
1170 | ||
1171 | return regset->n; | |
1172 | } | |
1173 | ||
1174 | /** | |
1175 | * tm_cvmx_get - get CMVX registers | |
1176 | * @target: The target task. | |
1177 | * @regset: The user regset structure. | |
1178 | * @pos: The buffer position. | |
1179 | * @count: Number of bytes to copy. | |
1180 | * @kbuf: Kernel buffer to copy from. | |
1181 | * @ubuf: User buffer to copy into. | |
1182 | * | |
1183 | * This function gets in transaction checkpointed VMX registers. | |
1184 | * | |
1185 | * When the transaction is active 'vr_state' and 'vr_save' hold | |
1186 | * the checkpointed values for the current transaction to fall | |
1187 | * back on if it aborts in between. The userspace interface buffer | |
1188 | * layout is as follows. | |
1189 | * | |
1190 | * struct data { | |
1191 | * vector128 vr[32]; | |
1192 | * vector128 vscr; | |
1193 | * vector128 vrsave; | |
1194 | *}; | |
1195 | */ | |
1196 | static int tm_cvmx_get(struct task_struct *target, | |
1197 | const struct user_regset *regset, | |
1198 | unsigned int pos, unsigned int count, | |
1199 | void *kbuf, void __user *ubuf) | |
1200 | { | |
1201 | int ret; | |
1202 | ||
1203 | BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); | |
1204 | ||
1205 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1206 | return -ENODEV; | |
1207 | ||
1208 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1209 | return -ENODATA; | |
1210 | ||
1211 | /* Flush the state */ | |
1212 | flush_fp_to_thread(target); | |
1213 | flush_altivec_to_thread(target); | |
1214 | flush_tmregs_to_thread(target); | |
1215 | ||
1216 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1217 | &target->thread.vr_state, 0, | |
1218 | 33 * sizeof(vector128)); | |
1219 | if (!ret) { | |
1220 | /* | |
1221 | * Copy out only the low-order word of vrsave. | |
1222 | */ | |
1223 | union { | |
1224 | elf_vrreg_t reg; | |
1225 | u32 word; | |
1226 | } vrsave; | |
1227 | memset(&vrsave, 0, sizeof(vrsave)); | |
1228 | vrsave.word = target->thread.vrsave; | |
1229 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave, | |
1230 | 33 * sizeof(vector128), -1); | |
1231 | } | |
1232 | ||
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | /** | |
1237 | * tm_cvmx_set - set CMVX registers | |
1238 | * @target: The target task. | |
1239 | * @regset: The user regset structure. | |
1240 | * @pos: The buffer position. | |
1241 | * @count: Number of bytes to copy. | |
1242 | * @kbuf: Kernel buffer to copy into. | |
1243 | * @ubuf: User buffer to copy from. | |
1244 | * | |
1245 | * This function sets in transaction checkpointed VMX registers. | |
1246 | * | |
1247 | * When the transaction is active 'vr_state' and 'vr_save' hold | |
1248 | * the checkpointed values for the current transaction to fall | |
1249 | * back on if it aborts in between. The userspace interface buffer | |
1250 | * layout is as follows. | |
1251 | * | |
1252 | * struct data { | |
1253 | * vector128 vr[32]; | |
1254 | * vector128 vscr; | |
1255 | * vector128 vrsave; | |
1256 | *}; | |
1257 | */ | |
1258 | static int tm_cvmx_set(struct task_struct *target, | |
1259 | const struct user_regset *regset, | |
1260 | unsigned int pos, unsigned int count, | |
1261 | const void *kbuf, const void __user *ubuf) | |
1262 | { | |
1263 | int ret; | |
1264 | ||
1265 | BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); | |
1266 | ||
1267 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1268 | return -ENODEV; | |
1269 | ||
1270 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1271 | return -ENODATA; | |
1272 | ||
1273 | flush_fp_to_thread(target); | |
1274 | flush_altivec_to_thread(target); | |
1275 | flush_tmregs_to_thread(target); | |
1276 | ||
1277 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1278 | &target->thread.vr_state, 0, | |
1279 | 33 * sizeof(vector128)); | |
1280 | if (!ret && count > 0) { | |
1281 | /* | |
1282 | * We use only the low-order word of vrsave. | |
1283 | */ | |
1284 | union { | |
1285 | elf_vrreg_t reg; | |
1286 | u32 word; | |
1287 | } vrsave; | |
1288 | memset(&vrsave, 0, sizeof(vrsave)); | |
1289 | vrsave.word = target->thread.vrsave; | |
1290 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave, | |
1291 | 33 * sizeof(vector128), -1); | |
1292 | if (!ret) | |
1293 | target->thread.vrsave = vrsave.word; | |
1294 | } | |
1295 | ||
1296 | return ret; | |
1297 | } | |
9d3918f7 AK |
1298 | |
1299 | /** | |
1300 | * tm_cvsx_active - get active number of registers in CVSX | |
1301 | * @target: The target task. | |
1302 | * @regset: The user regset structure. | |
1303 | * | |
1304 | * This function checks for the active number of available | |
1305 | * regisers in transaction checkpointed VSX category. | |
1306 | */ | |
1307 | static int tm_cvsx_active(struct task_struct *target, | |
1308 | const struct user_regset *regset) | |
1309 | { | |
1310 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1311 | return -ENODEV; | |
1312 | ||
1313 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1314 | return 0; | |
1315 | ||
1316 | flush_vsx_to_thread(target); | |
1317 | return target->thread.used_vsr ? regset->n : 0; | |
1318 | } | |
1319 | ||
1320 | /** | |
1321 | * tm_cvsx_get - get CVSX registers | |
1322 | * @target: The target task. | |
1323 | * @regset: The user regset structure. | |
1324 | * @pos: The buffer position. | |
1325 | * @count: Number of bytes to copy. | |
1326 | * @kbuf: Kernel buffer to copy from. | |
1327 | * @ubuf: User buffer to copy into. | |
1328 | * | |
1329 | * This function gets in transaction checkpointed VSX registers. | |
1330 | * | |
1331 | * When the transaction is active 'fp_state' holds the checkpointed | |
1332 | * values for the current transaction to fall back on if it aborts | |
1333 | * in between. This function gets those checkpointed VSX registers. | |
1334 | * The userspace interface buffer layout is as follows. | |
1335 | * | |
1336 | * struct data { | |
1337 | * u64 vsx[32]; | |
1338 | *}; | |
1339 | */ | |
1340 | static int tm_cvsx_get(struct task_struct *target, | |
1341 | const struct user_regset *regset, | |
1342 | unsigned int pos, unsigned int count, | |
1343 | void *kbuf, void __user *ubuf) | |
1344 | { | |
1345 | u64 buf[32]; | |
1346 | int ret, i; | |
1347 | ||
1348 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1349 | return -ENODEV; | |
1350 | ||
1351 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1352 | return -ENODATA; | |
1353 | ||
1354 | /* Flush the state */ | |
1355 | flush_fp_to_thread(target); | |
1356 | flush_altivec_to_thread(target); | |
1357 | flush_tmregs_to_thread(target); | |
1358 | flush_vsx_to_thread(target); | |
1359 | ||
1360 | for (i = 0; i < 32 ; i++) | |
1361 | buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET]; | |
1362 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, | |
1363 | buf, 0, 32 * sizeof(double)); | |
1364 | ||
1365 | return ret; | |
1366 | } | |
1367 | ||
1368 | /** | |
1369 | * tm_cvsx_set - set CFPR registers | |
1370 | * @target: The target task. | |
1371 | * @regset: The user regset structure. | |
1372 | * @pos: The buffer position. | |
1373 | * @count: Number of bytes to copy. | |
1374 | * @kbuf: Kernel buffer to copy into. | |
1375 | * @ubuf: User buffer to copy from. | |
1376 | * | |
1377 | * This function sets in transaction checkpointed VSX registers. | |
1378 | * | |
1379 | * When the transaction is active 'fp_state' holds the checkpointed | |
1380 | * VSX register values for the current transaction to fall back on | |
1381 | * if it aborts in between. This function sets these checkpointed | |
1382 | * FPR registers. The userspace interface buffer layout is as follows. | |
1383 | * | |
1384 | * struct data { | |
1385 | * u64 vsx[32]; | |
1386 | *}; | |
1387 | */ | |
1388 | static int tm_cvsx_set(struct task_struct *target, | |
1389 | const struct user_regset *regset, | |
1390 | unsigned int pos, unsigned int count, | |
1391 | const void *kbuf, const void __user *ubuf) | |
1392 | { | |
1393 | u64 buf[32]; | |
1394 | int ret, i; | |
1395 | ||
1396 | if (!cpu_has_feature(CPU_FTR_TM)) | |
1397 | return -ENODEV; | |
1398 | ||
1399 | if (!MSR_TM_ACTIVE(target->thread.regs->msr)) | |
1400 | return -ENODATA; | |
1401 | ||
1402 | /* Flush the state */ | |
1403 | flush_fp_to_thread(target); | |
1404 | flush_altivec_to_thread(target); | |
1405 | flush_tmregs_to_thread(target); | |
1406 | flush_vsx_to_thread(target); | |
1407 | ||
1408 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, | |
1409 | buf, 0, 32 * sizeof(double)); | |
1410 | for (i = 0; i < 32 ; i++) | |
1411 | target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i]; | |
1412 | ||
1413 | return ret; | |
1414 | } | |
25847fb1 | 1415 | #endif |
865418d8 | 1416 | |
80fdf470 RM |
1417 | /* |
1418 | * These are our native regset flavors. | |
1419 | */ | |
1420 | enum powerpc_regset { | |
1421 | REGSET_GPR, | |
1422 | REGSET_FPR, | |
1423 | #ifdef CONFIG_ALTIVEC | |
1424 | REGSET_VMX, | |
1425 | #endif | |
ce48b210 MN |
1426 | #ifdef CONFIG_VSX |
1427 | REGSET_VSX, | |
1428 | #endif | |
80fdf470 RM |
1429 | #ifdef CONFIG_SPE |
1430 | REGSET_SPE, | |
1431 | #endif | |
25847fb1 AK |
1432 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1433 | REGSET_TM_CGPR, /* TM checkpointed GPR registers */ | |
19cbcbf7 | 1434 | REGSET_TM_CFPR, /* TM checkpointed FPR registers */ |
8c13f599 | 1435 | REGSET_TM_CVMX, /* TM checkpointed VMX registers */ |
9d3918f7 | 1436 | REGSET_TM_CVSX, /* TM checkpointed VSX registers */ |
25847fb1 | 1437 | #endif |
80fdf470 RM |
1438 | }; |
1439 | ||
1440 | static const struct user_regset native_regsets[] = { | |
1441 | [REGSET_GPR] = { | |
1442 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
1443 | .size = sizeof(long), .align = sizeof(long), | |
1444 | .get = gpr_get, .set = gpr_set | |
1445 | }, | |
1446 | [REGSET_FPR] = { | |
1447 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
1448 | .size = sizeof(double), .align = sizeof(double), | |
1449 | .get = fpr_get, .set = fpr_set | |
1450 | }, | |
1451 | #ifdef CONFIG_ALTIVEC | |
1452 | [REGSET_VMX] = { | |
1453 | .core_note_type = NT_PPC_VMX, .n = 34, | |
1454 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1455 | .active = vr_active, .get = vr_get, .set = vr_set | |
1456 | }, | |
1457 | #endif | |
ce48b210 MN |
1458 | #ifdef CONFIG_VSX |
1459 | [REGSET_VSX] = { | |
f3e909c2 MN |
1460 | .core_note_type = NT_PPC_VSX, .n = 32, |
1461 | .size = sizeof(double), .align = sizeof(double), | |
ce48b210 MN |
1462 | .active = vsr_active, .get = vsr_get, .set = vsr_set |
1463 | }, | |
1464 | #endif | |
80fdf470 RM |
1465 | #ifdef CONFIG_SPE |
1466 | [REGSET_SPE] = { | |
a0b38b4e | 1467 | .core_note_type = NT_PPC_SPE, .n = 35, |
80fdf470 RM |
1468 | .size = sizeof(u32), .align = sizeof(u32), |
1469 | .active = evr_active, .get = evr_get, .set = evr_set | |
1470 | }, | |
1471 | #endif | |
25847fb1 AK |
1472 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1473 | [REGSET_TM_CGPR] = { | |
1474 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
1475 | .size = sizeof(long), .align = sizeof(long), | |
1476 | .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set | |
1477 | }, | |
19cbcbf7 AK |
1478 | [REGSET_TM_CFPR] = { |
1479 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
1480 | .size = sizeof(double), .align = sizeof(double), | |
1481 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
1482 | }, | |
8c13f599 AK |
1483 | [REGSET_TM_CVMX] = { |
1484 | .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX, | |
1485 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1486 | .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set | |
1487 | }, | |
9d3918f7 AK |
1488 | [REGSET_TM_CVSX] = { |
1489 | .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX, | |
1490 | .size = sizeof(double), .align = sizeof(double), | |
1491 | .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set | |
1492 | }, | |
25847fb1 | 1493 | #endif |
80fdf470 RM |
1494 | }; |
1495 | ||
1496 | static const struct user_regset_view user_ppc_native_view = { | |
1497 | .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI, | |
1498 | .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets) | |
1499 | }; | |
1500 | ||
fa8f5cb0 RM |
1501 | #ifdef CONFIG_PPC64 |
1502 | #include <linux/compat.h> | |
1503 | ||
04fcadce | 1504 | static int gpr32_get_common(struct task_struct *target, |
fa8f5cb0 RM |
1505 | const struct user_regset *regset, |
1506 | unsigned int pos, unsigned int count, | |
04fcadce | 1507 | void *kbuf, void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
1508 | { |
1509 | const unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 1510 | const unsigned long *ckpt_regs; |
fa8f5cb0 RM |
1511 | compat_ulong_t *k = kbuf; |
1512 | compat_ulong_t __user *u = ubuf; | |
1513 | compat_ulong_t reg; | |
a71f5d5d | 1514 | int i; |
fa8f5cb0 | 1515 | |
04fcadce AK |
1516 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1517 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
1518 | #endif | |
1519 | if (tm_active) { | |
1520 | regs = ckpt_regs; | |
1521 | } else { | |
1522 | if (target->thread.regs == NULL) | |
1523 | return -EIO; | |
1524 | ||
1525 | if (!FULL_REGS(target->thread.regs)) { | |
1526 | /* | |
1527 | * We have a partial register set. | |
1528 | * Fill 14-31 with bogus values. | |
1529 | */ | |
1530 | for (i = 14; i < 32; i++) | |
1531 | target->thread.regs->gpr[i] = NV_REG_POISON; | |
1532 | } | |
a71f5d5d | 1533 | } |
fa8f5cb0 RM |
1534 | |
1535 | pos /= sizeof(reg); | |
1536 | count /= sizeof(reg); | |
1537 | ||
1538 | if (kbuf) | |
1539 | for (; count > 0 && pos < PT_MSR; --count) | |
1540 | *k++ = regs[pos++]; | |
1541 | else | |
1542 | for (; count > 0 && pos < PT_MSR; --count) | |
1543 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
1544 | return -EFAULT; | |
1545 | ||
1546 | if (count > 0 && pos == PT_MSR) { | |
1547 | reg = get_user_msr(target); | |
1548 | if (kbuf) | |
1549 | *k++ = reg; | |
1550 | else if (__put_user(reg, u++)) | |
1551 | return -EFAULT; | |
1552 | ++pos; | |
1553 | --count; | |
1554 | } | |
1555 | ||
1556 | if (kbuf) | |
1557 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
1558 | *k++ = regs[pos++]; | |
1559 | else | |
1560 | for (; count > 0 && pos < PT_REGS_COUNT; --count) | |
1561 | if (__put_user((compat_ulong_t) regs[pos++], u++)) | |
1562 | return -EFAULT; | |
1563 | ||
1564 | kbuf = k; | |
1565 | ubuf = u; | |
1566 | pos *= sizeof(reg); | |
1567 | count *= sizeof(reg); | |
1568 | return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, | |
1569 | PT_REGS_COUNT * sizeof(reg), -1); | |
1570 | } | |
1571 | ||
04fcadce | 1572 | static int gpr32_set_common(struct task_struct *target, |
fa8f5cb0 RM |
1573 | const struct user_regset *regset, |
1574 | unsigned int pos, unsigned int count, | |
04fcadce | 1575 | const void *kbuf, const void __user *ubuf, bool tm_active) |
fa8f5cb0 RM |
1576 | { |
1577 | unsigned long *regs = &target->thread.regs->gpr[0]; | |
04fcadce | 1578 | unsigned long *ckpt_regs; |
fa8f5cb0 RM |
1579 | const compat_ulong_t *k = kbuf; |
1580 | const compat_ulong_t __user *u = ubuf; | |
1581 | compat_ulong_t reg; | |
1582 | ||
04fcadce AK |
1583 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1584 | ckpt_regs = &target->thread.ckpt_regs.gpr[0]; | |
1585 | #endif | |
fa8f5cb0 | 1586 | |
04fcadce AK |
1587 | if (tm_active) { |
1588 | regs = ckpt_regs; | |
1589 | } else { | |
1590 | regs = &target->thread.regs->gpr[0]; | |
1591 | ||
1592 | if (target->thread.regs == NULL) | |
1593 | return -EIO; | |
1594 | ||
1595 | CHECK_FULL_REGS(target->thread.regs); | |
1596 | } | |
fa8f5cb0 RM |
1597 | |
1598 | pos /= sizeof(reg); | |
1599 | count /= sizeof(reg); | |
1600 | ||
1601 | if (kbuf) | |
1602 | for (; count > 0 && pos < PT_MSR; --count) | |
1603 | regs[pos++] = *k++; | |
1604 | else | |
1605 | for (; count > 0 && pos < PT_MSR; --count) { | |
1606 | if (__get_user(reg, u++)) | |
1607 | return -EFAULT; | |
1608 | regs[pos++] = reg; | |
1609 | } | |
1610 | ||
1611 | ||
1612 | if (count > 0 && pos == PT_MSR) { | |
1613 | if (kbuf) | |
1614 | reg = *k++; | |
1615 | else if (__get_user(reg, u++)) | |
1616 | return -EFAULT; | |
1617 | set_user_msr(target, reg); | |
1618 | ++pos; | |
1619 | --count; | |
1620 | } | |
1621 | ||
c2372eb9 | 1622 | if (kbuf) { |
fa8f5cb0 RM |
1623 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) |
1624 | regs[pos++] = *k++; | |
c2372eb9 RM |
1625 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
1626 | ++k; | |
1627 | } else { | |
fa8f5cb0 RM |
1628 | for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) { |
1629 | if (__get_user(reg, u++)) | |
1630 | return -EFAULT; | |
1631 | regs[pos++] = reg; | |
1632 | } | |
c2372eb9 RM |
1633 | for (; count > 0 && pos < PT_TRAP; --count, ++pos) |
1634 | if (__get_user(reg, u++)) | |
1635 | return -EFAULT; | |
1636 | } | |
fa8f5cb0 RM |
1637 | |
1638 | if (count > 0 && pos == PT_TRAP) { | |
1639 | if (kbuf) | |
1640 | reg = *k++; | |
1641 | else if (__get_user(reg, u++)) | |
1642 | return -EFAULT; | |
1643 | set_user_trap(target, reg); | |
1644 | ++pos; | |
1645 | --count; | |
1646 | } | |
1647 | ||
1648 | kbuf = k; | |
1649 | ubuf = u; | |
1650 | pos *= sizeof(reg); | |
1651 | count *= sizeof(reg); | |
1652 | return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf, | |
1653 | (PT_TRAP + 1) * sizeof(reg), -1); | |
1654 | } | |
1655 | ||
25847fb1 AK |
1656 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1657 | static int tm_cgpr32_get(struct task_struct *target, | |
1658 | const struct user_regset *regset, | |
1659 | unsigned int pos, unsigned int count, | |
1660 | void *kbuf, void __user *ubuf) | |
1661 | { | |
1662 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 1); | |
1663 | } | |
1664 | ||
1665 | static int tm_cgpr32_set(struct task_struct *target, | |
1666 | const struct user_regset *regset, | |
1667 | unsigned int pos, unsigned int count, | |
1668 | const void *kbuf, const void __user *ubuf) | |
1669 | { | |
1670 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 1); | |
1671 | } | |
1672 | #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ | |
1673 | ||
04fcadce AK |
1674 | static int gpr32_get(struct task_struct *target, |
1675 | const struct user_regset *regset, | |
1676 | unsigned int pos, unsigned int count, | |
1677 | void *kbuf, void __user *ubuf) | |
1678 | { | |
1679 | return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 0); | |
1680 | } | |
1681 | ||
1682 | static int gpr32_set(struct task_struct *target, | |
1683 | const struct user_regset *regset, | |
1684 | unsigned int pos, unsigned int count, | |
1685 | const void *kbuf, const void __user *ubuf) | |
1686 | { | |
1687 | return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 0); | |
1688 | } | |
1689 | ||
fa8f5cb0 RM |
1690 | /* |
1691 | * These are the regset flavors matching the CONFIG_PPC32 native set. | |
1692 | */ | |
1693 | static const struct user_regset compat_regsets[] = { | |
1694 | [REGSET_GPR] = { | |
1695 | .core_note_type = NT_PRSTATUS, .n = ELF_NGREG, | |
1696 | .size = sizeof(compat_long_t), .align = sizeof(compat_long_t), | |
1697 | .get = gpr32_get, .set = gpr32_set | |
1698 | }, | |
1699 | [REGSET_FPR] = { | |
1700 | .core_note_type = NT_PRFPREG, .n = ELF_NFPREG, | |
1701 | .size = sizeof(double), .align = sizeof(double), | |
1702 | .get = fpr_get, .set = fpr_set | |
1703 | }, | |
1704 | #ifdef CONFIG_ALTIVEC | |
1705 | [REGSET_VMX] = { | |
1706 | .core_note_type = NT_PPC_VMX, .n = 34, | |
1707 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1708 | .active = vr_active, .get = vr_get, .set = vr_set | |
1709 | }, | |
1710 | #endif | |
1711 | #ifdef CONFIG_SPE | |
1712 | [REGSET_SPE] = { | |
24f1a849 | 1713 | .core_note_type = NT_PPC_SPE, .n = 35, |
fa8f5cb0 RM |
1714 | .size = sizeof(u32), .align = sizeof(u32), |
1715 | .active = evr_active, .get = evr_get, .set = evr_set | |
1716 | }, | |
1717 | #endif | |
25847fb1 AK |
1718 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1719 | [REGSET_TM_CGPR] = { | |
1720 | .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG, | |
1721 | .size = sizeof(long), .align = sizeof(long), | |
1722 | .active = tm_cgpr_active, | |
1723 | .get = tm_cgpr32_get, .set = tm_cgpr32_set | |
1724 | }, | |
19cbcbf7 AK |
1725 | [REGSET_TM_CFPR] = { |
1726 | .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG, | |
1727 | .size = sizeof(double), .align = sizeof(double), | |
1728 | .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set | |
1729 | }, | |
8c13f599 AK |
1730 | [REGSET_TM_CVMX] = { |
1731 | .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX, | |
1732 | .size = sizeof(vector128), .align = sizeof(vector128), | |
1733 | .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set | |
1734 | }, | |
9d3918f7 AK |
1735 | [REGSET_TM_CVSX] = { |
1736 | .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX, | |
1737 | .size = sizeof(double), .align = sizeof(double), | |
1738 | .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set | |
1739 | }, | |
25847fb1 | 1740 | #endif |
fa8f5cb0 RM |
1741 | }; |
1742 | ||
1743 | static const struct user_regset_view user_ppc_compat_view = { | |
1744 | .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI, | |
1745 | .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets) | |
1746 | }; | |
1747 | #endif /* CONFIG_PPC64 */ | |
1748 | ||
80fdf470 RM |
1749 | const struct user_regset_view *task_user_regset_view(struct task_struct *task) |
1750 | { | |
fa8f5cb0 RM |
1751 | #ifdef CONFIG_PPC64 |
1752 | if (test_tsk_thread_flag(task, TIF_32BIT)) | |
1753 | return &user_ppc_compat_view; | |
1754 | #endif | |
80fdf470 RM |
1755 | return &user_ppc_native_view; |
1756 | } | |
1757 | ||
1758 | ||
2a84b0d7 | 1759 | void user_enable_single_step(struct task_struct *task) |
865418d8 BH |
1760 | { |
1761 | struct pt_regs *regs = task->thread.regs; | |
1762 | ||
1763 | if (regs != NULL) { | |
172ae2e7 | 1764 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
1765 | task->thread.debug.dbcr0 &= ~DBCR0_BT; |
1766 | task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC; | |
865418d8 BH |
1767 | regs->msr |= MSR_DE; |
1768 | #else | |
ec097c84 | 1769 | regs->msr &= ~MSR_BE; |
865418d8 BH |
1770 | regs->msr |= MSR_SE; |
1771 | #endif | |
1772 | } | |
1773 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1774 | } | |
1775 | ||
ec097c84 RM |
1776 | void user_enable_block_step(struct task_struct *task) |
1777 | { | |
1778 | struct pt_regs *regs = task->thread.regs; | |
1779 | ||
1780 | if (regs != NULL) { | |
172ae2e7 | 1781 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a BB |
1782 | task->thread.debug.dbcr0 &= ~DBCR0_IC; |
1783 | task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT; | |
ec097c84 RM |
1784 | regs->msr |= MSR_DE; |
1785 | #else | |
1786 | regs->msr &= ~MSR_SE; | |
1787 | regs->msr |= MSR_BE; | |
1788 | #endif | |
1789 | } | |
1790 | set_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1791 | } | |
1792 | ||
2a84b0d7 | 1793 | void user_disable_single_step(struct task_struct *task) |
865418d8 BH |
1794 | { |
1795 | struct pt_regs *regs = task->thread.regs; | |
1796 | ||
1797 | if (regs != NULL) { | |
172ae2e7 | 1798 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
3bffb652 DK |
1799 | /* |
1800 | * The logic to disable single stepping should be as | |
1801 | * simple as turning off the Instruction Complete flag. | |
1802 | * And, after doing so, if all debug flags are off, turn | |
1803 | * off DBCR0(IDM) and MSR(DE) .... Torez | |
1804 | */ | |
682775b8 | 1805 | task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT); |
3bffb652 DK |
1806 | /* |
1807 | * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. | |
1808 | */ | |
51ae8d4a BB |
1809 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1810 | task->thread.debug.dbcr1)) { | |
3bffb652 DK |
1811 | /* |
1812 | * All debug events were off..... | |
1813 | */ | |
51ae8d4a | 1814 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
28477fb1 DK |
1815 | regs->msr &= ~MSR_DE; |
1816 | } | |
865418d8 | 1817 | #else |
ec097c84 | 1818 | regs->msr &= ~(MSR_SE | MSR_BE); |
865418d8 BH |
1819 | #endif |
1820 | } | |
1821 | clear_tsk_thread_flag(task, TIF_SINGLESTEP); | |
1822 | } | |
1823 | ||
5aae8a53 | 1824 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
a8b0ca17 | 1825 | void ptrace_triggered(struct perf_event *bp, |
5aae8a53 P |
1826 | struct perf_sample_data *data, struct pt_regs *regs) |
1827 | { | |
1828 | struct perf_event_attr attr; | |
1829 | ||
1830 | /* | |
1831 | * Disable the breakpoint request here since ptrace has defined a | |
1832 | * one-shot behaviour for breakpoint exceptions in PPC64. | |
1833 | * The SIGTRAP signal is generated automatically for us in do_dabr(). | |
1834 | * We don't have to do anything about that here | |
1835 | */ | |
1836 | attr = bp->attr; | |
1837 | attr.disabled = true; | |
1838 | modify_user_hw_breakpoint(bp, &attr); | |
1839 | } | |
1840 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
1841 | ||
e51df2c1 | 1842 | static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr, |
abd06505 BH |
1843 | unsigned long data) |
1844 | { | |
5aae8a53 P |
1845 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1846 | int ret; | |
1847 | struct thread_struct *thread = &(task->thread); | |
1848 | struct perf_event *bp; | |
1849 | struct perf_event_attr attr; | |
1850 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e MN |
1851 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
1852 | struct arch_hw_breakpoint hw_brk; | |
1853 | #endif | |
5aae8a53 | 1854 | |
d6a61bfc LM |
1855 | /* For ppc64 we support one DABR and no IABR's at the moment (ppc64). |
1856 | * For embedded processors we support one DAC and no IAC's at the | |
1857 | * moment. | |
1858 | */ | |
abd06505 BH |
1859 | if (addr > 0) |
1860 | return -EINVAL; | |
1861 | ||
2325f0a0 | 1862 | /* The bottom 3 bits in dabr are flags */ |
abd06505 BH |
1863 | if ((data & ~0x7UL) >= TASK_SIZE) |
1864 | return -EIO; | |
1865 | ||
172ae2e7 | 1866 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
d6a61bfc LM |
1867 | /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. |
1868 | * It was assumed, on previous implementations, that 3 bits were | |
1869 | * passed together with the data address, fitting the design of the | |
1870 | * DABR register, as follows: | |
1871 | * | |
1872 | * bit 0: Read flag | |
1873 | * bit 1: Write flag | |
1874 | * bit 2: Breakpoint translation | |
1875 | * | |
1876 | * Thus, we use them here as so. | |
1877 | */ | |
1878 | ||
1879 | /* Ensure breakpoint translation bit is set */ | |
9422de3e | 1880 | if (data && !(data & HW_BRK_TYPE_TRANSLATE)) |
abd06505 | 1881 | return -EIO; |
9422de3e MN |
1882 | hw_brk.address = data & (~HW_BRK_TYPE_DABR); |
1883 | hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL; | |
1884 | hw_brk.len = 8; | |
5aae8a53 P |
1885 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
1886 | bp = thread->ptrace_bps[0]; | |
9422de3e | 1887 | if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) { |
5aae8a53 P |
1888 | if (bp) { |
1889 | unregister_hw_breakpoint(bp); | |
1890 | thread->ptrace_bps[0] = NULL; | |
1891 | } | |
1892 | return 0; | |
1893 | } | |
1894 | if (bp) { | |
1895 | attr = bp->attr; | |
9422de3e MN |
1896 | attr.bp_addr = hw_brk.address; |
1897 | arch_bp_generic_fields(hw_brk.type, &attr.bp_type); | |
a53fd61a AP |
1898 | |
1899 | /* Enable breakpoint */ | |
1900 | attr.disabled = false; | |
1901 | ||
5aae8a53 | 1902 | ret = modify_user_hw_breakpoint(bp, &attr); |
925f83c0 | 1903 | if (ret) { |
5aae8a53 | 1904 | return ret; |
925f83c0 | 1905 | } |
5aae8a53 | 1906 | thread->ptrace_bps[0] = bp; |
9422de3e | 1907 | thread->hw_brk = hw_brk; |
5aae8a53 P |
1908 | return 0; |
1909 | } | |
1910 | ||
1911 | /* Create a new breakpoint request if one doesn't exist already */ | |
1912 | hw_breakpoint_init(&attr); | |
9422de3e MN |
1913 | attr.bp_addr = hw_brk.address; |
1914 | arch_bp_generic_fields(hw_brk.type, | |
1915 | &attr.bp_type); | |
5aae8a53 P |
1916 | |
1917 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
4dc0da86 | 1918 | ptrace_triggered, NULL, task); |
5aae8a53 P |
1919 | if (IS_ERR(bp)) { |
1920 | thread->ptrace_bps[0] = NULL; | |
1921 | return PTR_ERR(bp); | |
1922 | } | |
1923 | ||
1924 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 1925 | task->thread.hw_brk = hw_brk; |
172ae2e7 | 1926 | #else /* CONFIG_PPC_ADV_DEBUG_REGS */ |
d6a61bfc LM |
1927 | /* As described above, it was assumed 3 bits were passed with the data |
1928 | * address, but we will assume only the mode bits will be passed | |
1929 | * as to not cause alignment restrictions for DAC-based processors. | |
1930 | */ | |
1931 | ||
1932 | /* DAC's hold the whole address without any mode flags */ | |
51ae8d4a | 1933 | task->thread.debug.dac1 = data & ~0x3UL; |
3bffb652 | 1934 | |
51ae8d4a | 1935 | if (task->thread.debug.dac1 == 0) { |
3bffb652 | 1936 | dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
51ae8d4a BB |
1937 | if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0, |
1938 | task->thread.debug.dbcr1)) { | |
3bffb652 | 1939 | task->thread.regs->msr &= ~MSR_DE; |
51ae8d4a | 1940 | task->thread.debug.dbcr0 &= ~DBCR0_IDM; |
3bffb652 | 1941 | } |
d6a61bfc LM |
1942 | return 0; |
1943 | } | |
1944 | ||
1945 | /* Read or Write bits must be set */ | |
1946 | ||
1947 | if (!(data & 0x3UL)) | |
1948 | return -EINVAL; | |
1949 | ||
1950 | /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 | |
1951 | register */ | |
51ae8d4a | 1952 | task->thread.debug.dbcr0 |= DBCR0_IDM; |
d6a61bfc LM |
1953 | |
1954 | /* Check for write and read flags and set DBCR0 | |
1955 | accordingly */ | |
3bffb652 | 1956 | dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W); |
d6a61bfc | 1957 | if (data & 0x1UL) |
3bffb652 | 1958 | dbcr_dac(task) |= DBCR_DAC1R; |
d6a61bfc | 1959 | if (data & 0x2UL) |
3bffb652 | 1960 | dbcr_dac(task) |= DBCR_DAC1W; |
d6a61bfc | 1961 | task->thread.regs->msr |= MSR_DE; |
172ae2e7 | 1962 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
abd06505 BH |
1963 | return 0; |
1964 | } | |
abd06505 | 1965 | |
1da177e4 LT |
1966 | /* |
1967 | * Called by kernel/ptrace.c when detaching.. | |
1968 | * | |
1969 | * Make sure single step bits etc are not set. | |
1970 | */ | |
1971 | void ptrace_disable(struct task_struct *child) | |
1972 | { | |
1973 | /* make sure the single step bit is not set. */ | |
2a84b0d7 | 1974 | user_disable_single_step(child); |
1da177e4 LT |
1975 | } |
1976 | ||
3bffb652 | 1977 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
84295dfc | 1978 | static long set_instruction_bp(struct task_struct *child, |
3bffb652 DK |
1979 | struct ppc_hw_breakpoint *bp_info) |
1980 | { | |
1981 | int slot; | |
51ae8d4a BB |
1982 | int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0); |
1983 | int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0); | |
1984 | int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0); | |
1985 | int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0); | |
3bffb652 DK |
1986 | |
1987 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
1988 | slot2_in_use = 1; | |
1989 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
1990 | slot4_in_use = 1; | |
1991 | ||
1992 | if (bp_info->addr >= TASK_SIZE) | |
1993 | return -EIO; | |
1994 | ||
1995 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) { | |
1996 | ||
1997 | /* Make sure range is valid. */ | |
1998 | if (bp_info->addr2 >= TASK_SIZE) | |
1999 | return -EIO; | |
2000 | ||
2001 | /* We need a pair of IAC regsisters */ | |
2002 | if ((!slot1_in_use) && (!slot2_in_use)) { | |
2003 | slot = 1; | |
51ae8d4a BB |
2004 | child->thread.debug.iac1 = bp_info->addr; |
2005 | child->thread.debug.iac2 = bp_info->addr2; | |
2006 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
2007 | if (bp_info->addr_mode == |
2008 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
2009 | dbcr_iac_range(child) |= DBCR_IAC12X; | |
2010 | else | |
2011 | dbcr_iac_range(child) |= DBCR_IAC12I; | |
2012 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
2013 | } else if ((!slot3_in_use) && (!slot4_in_use)) { | |
2014 | slot = 3; | |
51ae8d4a BB |
2015 | child->thread.debug.iac3 = bp_info->addr; |
2016 | child->thread.debug.iac4 = bp_info->addr2; | |
2017 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
2018 | if (bp_info->addr_mode == |
2019 | PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) | |
2020 | dbcr_iac_range(child) |= DBCR_IAC34X; | |
2021 | else | |
2022 | dbcr_iac_range(child) |= DBCR_IAC34I; | |
2023 | #endif | |
2024 | } else | |
2025 | return -ENOSPC; | |
2026 | } else { | |
2027 | /* We only need one. If possible leave a pair free in | |
2028 | * case a range is needed later | |
2029 | */ | |
2030 | if (!slot1_in_use) { | |
2031 | /* | |
2032 | * Don't use iac1 if iac1-iac2 are free and either | |
2033 | * iac3 or iac4 (but not both) are free | |
2034 | */ | |
2035 | if (slot2_in_use || (slot3_in_use == slot4_in_use)) { | |
2036 | slot = 1; | |
51ae8d4a BB |
2037 | child->thread.debug.iac1 = bp_info->addr; |
2038 | child->thread.debug.dbcr0 |= DBCR0_IAC1; | |
3bffb652 DK |
2039 | goto out; |
2040 | } | |
2041 | } | |
2042 | if (!slot2_in_use) { | |
2043 | slot = 2; | |
51ae8d4a BB |
2044 | child->thread.debug.iac2 = bp_info->addr; |
2045 | child->thread.debug.dbcr0 |= DBCR0_IAC2; | |
3bffb652 DK |
2046 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 |
2047 | } else if (!slot3_in_use) { | |
2048 | slot = 3; | |
51ae8d4a BB |
2049 | child->thread.debug.iac3 = bp_info->addr; |
2050 | child->thread.debug.dbcr0 |= DBCR0_IAC3; | |
3bffb652 DK |
2051 | } else if (!slot4_in_use) { |
2052 | slot = 4; | |
51ae8d4a BB |
2053 | child->thread.debug.iac4 = bp_info->addr; |
2054 | child->thread.debug.dbcr0 |= DBCR0_IAC4; | |
3bffb652 DK |
2055 | #endif |
2056 | } else | |
2057 | return -ENOSPC; | |
2058 | } | |
2059 | out: | |
51ae8d4a | 2060 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
2061 | child->thread.regs->msr |= MSR_DE; |
2062 | ||
2063 | return slot; | |
2064 | } | |
2065 | ||
2066 | static int del_instruction_bp(struct task_struct *child, int slot) | |
2067 | { | |
2068 | switch (slot) { | |
2069 | case 1: | |
51ae8d4a | 2070 | if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0) |
3bffb652 DK |
2071 | return -ENOENT; |
2072 | ||
2073 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) { | |
2074 | /* address range - clear slots 1 & 2 */ | |
51ae8d4a | 2075 | child->thread.debug.iac2 = 0; |
3bffb652 DK |
2076 | dbcr_iac_range(child) &= ~DBCR_IAC12MODE; |
2077 | } | |
51ae8d4a BB |
2078 | child->thread.debug.iac1 = 0; |
2079 | child->thread.debug.dbcr0 &= ~DBCR0_IAC1; | |
3bffb652 DK |
2080 | break; |
2081 | case 2: | |
51ae8d4a | 2082 | if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0) |
3bffb652 DK |
2083 | return -ENOENT; |
2084 | ||
2085 | if (dbcr_iac_range(child) & DBCR_IAC12MODE) | |
2086 | /* used in a range */ | |
2087 | return -EINVAL; | |
51ae8d4a BB |
2088 | child->thread.debug.iac2 = 0; |
2089 | child->thread.debug.dbcr0 &= ~DBCR0_IAC2; | |
3bffb652 DK |
2090 | break; |
2091 | #if CONFIG_PPC_ADV_DEBUG_IACS > 2 | |
2092 | case 3: | |
51ae8d4a | 2093 | if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0) |
3bffb652 DK |
2094 | return -ENOENT; |
2095 | ||
2096 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) { | |
2097 | /* address range - clear slots 3 & 4 */ | |
51ae8d4a | 2098 | child->thread.debug.iac4 = 0; |
3bffb652 DK |
2099 | dbcr_iac_range(child) &= ~DBCR_IAC34MODE; |
2100 | } | |
51ae8d4a BB |
2101 | child->thread.debug.iac3 = 0; |
2102 | child->thread.debug.dbcr0 &= ~DBCR0_IAC3; | |
3bffb652 DK |
2103 | break; |
2104 | case 4: | |
51ae8d4a | 2105 | if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0) |
3bffb652 DK |
2106 | return -ENOENT; |
2107 | ||
2108 | if (dbcr_iac_range(child) & DBCR_IAC34MODE) | |
2109 | /* Used in a range */ | |
2110 | return -EINVAL; | |
51ae8d4a BB |
2111 | child->thread.debug.iac4 = 0; |
2112 | child->thread.debug.dbcr0 &= ~DBCR0_IAC4; | |
3bffb652 DK |
2113 | break; |
2114 | #endif | |
2115 | default: | |
2116 | return -EINVAL; | |
2117 | } | |
2118 | return 0; | |
2119 | } | |
2120 | ||
2121 | static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info) | |
2122 | { | |
2123 | int byte_enable = | |
2124 | (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT) | |
2125 | & 0xf; | |
2126 | int condition_mode = | |
2127 | bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE; | |
2128 | int slot; | |
2129 | ||
2130 | if (byte_enable && (condition_mode == 0)) | |
2131 | return -EINVAL; | |
2132 | ||
2133 | if (bp_info->addr >= TASK_SIZE) | |
2134 | return -EIO; | |
2135 | ||
2136 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) { | |
2137 | slot = 1; | |
2138 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
2139 | dbcr_dac(child) |= DBCR_DAC1R; | |
2140 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
2141 | dbcr_dac(child) |= DBCR_DAC1W; | |
51ae8d4a | 2142 | child->thread.debug.dac1 = (unsigned long)bp_info->addr; |
3bffb652 DK |
2143 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
2144 | if (byte_enable) { | |
51ae8d4a | 2145 | child->thread.debug.dvc1 = |
3bffb652 | 2146 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 2147 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
2148 | ((byte_enable << DBCR2_DVC1BE_SHIFT) | |
2149 | (condition_mode << DBCR2_DVC1M_SHIFT)); | |
2150 | } | |
2151 | #endif | |
2152 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 2153 | } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
3bffb652 DK |
2154 | /* Both dac1 and dac2 are part of a range */ |
2155 | return -ENOSPC; | |
2156 | #endif | |
2157 | } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) { | |
2158 | slot = 2; | |
2159 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
2160 | dbcr_dac(child) |= DBCR_DAC2R; | |
2161 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) | |
2162 | dbcr_dac(child) |= DBCR_DAC2W; | |
51ae8d4a | 2163 | child->thread.debug.dac2 = (unsigned long)bp_info->addr; |
3bffb652 DK |
2164 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 |
2165 | if (byte_enable) { | |
51ae8d4a | 2166 | child->thread.debug.dvc2 = |
3bffb652 | 2167 | (unsigned long)bp_info->condition_value; |
51ae8d4a | 2168 | child->thread.debug.dbcr2 |= |
3bffb652 DK |
2169 | ((byte_enable << DBCR2_DVC2BE_SHIFT) | |
2170 | (condition_mode << DBCR2_DVC2M_SHIFT)); | |
2171 | } | |
2172 | #endif | |
2173 | } else | |
2174 | return -ENOSPC; | |
51ae8d4a | 2175 | child->thread.debug.dbcr0 |= DBCR0_IDM; |
3bffb652 DK |
2176 | child->thread.regs->msr |= MSR_DE; |
2177 | ||
2178 | return slot + 4; | |
2179 | } | |
2180 | ||
2181 | static int del_dac(struct task_struct *child, int slot) | |
2182 | { | |
2183 | if (slot == 1) { | |
30124d11 | 2184 | if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) |
3bffb652 DK |
2185 | return -ENOENT; |
2186 | ||
51ae8d4a | 2187 | child->thread.debug.dac1 = 0; |
3bffb652 DK |
2188 | dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); |
2189 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a BB |
2190 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) { |
2191 | child->thread.debug.dac2 = 0; | |
2192 | child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE; | |
3bffb652 | 2193 | } |
51ae8d4a | 2194 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); |
3bffb652 DK |
2195 | #endif |
2196 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 2197 | child->thread.debug.dvc1 = 0; |
3bffb652 DK |
2198 | #endif |
2199 | } else if (slot == 2) { | |
30124d11 | 2200 | if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) |
3bffb652 DK |
2201 | return -ENOENT; |
2202 | ||
2203 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
51ae8d4a | 2204 | if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) |
3bffb652 DK |
2205 | /* Part of a range */ |
2206 | return -EINVAL; | |
51ae8d4a | 2207 | child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); |
3bffb652 DK |
2208 | #endif |
2209 | #if CONFIG_PPC_ADV_DEBUG_DVCS > 0 | |
51ae8d4a | 2210 | child->thread.debug.dvc2 = 0; |
3bffb652 | 2211 | #endif |
51ae8d4a | 2212 | child->thread.debug.dac2 = 0; |
3bffb652 DK |
2213 | dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); |
2214 | } else | |
2215 | return -EINVAL; | |
2216 | ||
2217 | return 0; | |
2218 | } | |
2219 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ | |
2220 | ||
2221 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2222 | static int set_dac_range(struct task_struct *child, | |
2223 | struct ppc_hw_breakpoint *bp_info) | |
2224 | { | |
2225 | int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK; | |
2226 | ||
2227 | /* We don't allow range watchpoints to be used with DVC */ | |
2228 | if (bp_info->condition_mode) | |
2229 | return -EINVAL; | |
2230 | ||
2231 | /* | |
2232 | * Best effort to verify the address range. The user/supervisor bits | |
2233 | * prevent trapping in kernel space, but let's fail on an obvious bad | |
2234 | * range. The simple test on the mask is not fool-proof, and any | |
2235 | * exclusive range will spill over into kernel space. | |
2236 | */ | |
2237 | if (bp_info->addr >= TASK_SIZE) | |
2238 | return -EIO; | |
2239 | if (mode == PPC_BREAKPOINT_MODE_MASK) { | |
2240 | /* | |
2241 | * dac2 is a bitmask. Don't allow a mask that makes a | |
2242 | * kernel space address from a valid dac1 value | |
2243 | */ | |
2244 | if (~((unsigned long)bp_info->addr2) >= TASK_SIZE) | |
2245 | return -EIO; | |
2246 | } else { | |
2247 | /* | |
2248 | * For range breakpoints, addr2 must also be a valid address | |
2249 | */ | |
2250 | if (bp_info->addr2 >= TASK_SIZE) | |
2251 | return -EIO; | |
2252 | } | |
2253 | ||
51ae8d4a | 2254 | if (child->thread.debug.dbcr0 & |
3bffb652 DK |
2255 | (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) |
2256 | return -ENOSPC; | |
2257 | ||
2258 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) | |
51ae8d4a | 2259 | child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); |
3bffb652 | 2260 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
51ae8d4a BB |
2261 | child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); |
2262 | child->thread.debug.dac1 = bp_info->addr; | |
2263 | child->thread.debug.dac2 = bp_info->addr2; | |
3bffb652 | 2264 | if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
51ae8d4a | 2265 | child->thread.debug.dbcr2 |= DBCR2_DAC12M; |
3bffb652 | 2266 | else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) |
51ae8d4a | 2267 | child->thread.debug.dbcr2 |= DBCR2_DAC12MX; |
3bffb652 | 2268 | else /* PPC_BREAKPOINT_MODE_MASK */ |
51ae8d4a | 2269 | child->thread.debug.dbcr2 |= DBCR2_DAC12MM; |
3bffb652 DK |
2270 | child->thread.regs->msr |= MSR_DE; |
2271 | ||
2272 | return 5; | |
2273 | } | |
2274 | #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */ | |
2275 | ||
3162d92d DK |
2276 | static long ppc_set_hwdebug(struct task_struct *child, |
2277 | struct ppc_hw_breakpoint *bp_info) | |
2278 | { | |
6c7a2856 P |
2279 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2280 | int len = 0; | |
2281 | struct thread_struct *thread = &(child->thread); | |
2282 | struct perf_event *bp; | |
2283 | struct perf_event_attr attr; | |
2284 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
4dfbf290 | 2285 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
9422de3e | 2286 | struct arch_hw_breakpoint brk; |
4dfbf290 AS |
2287 | #endif |
2288 | ||
3bffb652 DK |
2289 | if (bp_info->version != 1) |
2290 | return -ENOTSUPP; | |
2291 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS | |
2292 | /* | |
2293 | * Check for invalid flags and combinations | |
2294 | */ | |
2295 | if ((bp_info->trigger_type == 0) || | |
2296 | (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE | | |
2297 | PPC_BREAKPOINT_TRIGGER_RW)) || | |
2298 | (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) || | |
2299 | (bp_info->condition_mode & | |
2300 | ~(PPC_BREAKPOINT_CONDITION_MODE | | |
2301 | PPC_BREAKPOINT_CONDITION_BE_ALL))) | |
2302 | return -EINVAL; | |
2303 | #if CONFIG_PPC_ADV_DEBUG_DVCS == 0 | |
2304 | if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) | |
2305 | return -EINVAL; | |
2306 | #endif | |
2307 | ||
2308 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) { | |
2309 | if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) || | |
2310 | (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)) | |
2311 | return -EINVAL; | |
84295dfc | 2312 | return set_instruction_bp(child, bp_info); |
3bffb652 DK |
2313 | } |
2314 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) | |
2315 | return set_dac(child, bp_info); | |
2316 | ||
2317 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2318 | return set_dac_range(child, bp_info); | |
2319 | #else | |
2320 | return -EINVAL; | |
2321 | #endif | |
2322 | #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */ | |
3162d92d | 2323 | /* |
3bffb652 | 2324 | * We only support one data breakpoint |
3162d92d | 2325 | */ |
4dfbf290 AS |
2326 | if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 || |
2327 | (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 || | |
4dfbf290 | 2328 | bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE) |
3162d92d DK |
2329 | return -EINVAL; |
2330 | ||
3162d92d DK |
2331 | if ((unsigned long)bp_info->addr >= TASK_SIZE) |
2332 | return -EIO; | |
2333 | ||
9422de3e MN |
2334 | brk.address = bp_info->addr & ~7UL; |
2335 | brk.type = HW_BRK_TYPE_TRANSLATE; | |
2bb78efa | 2336 | brk.len = 8; |
4dfbf290 | 2337 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) |
9422de3e | 2338 | brk.type |= HW_BRK_TYPE_READ; |
4dfbf290 | 2339 | if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) |
9422de3e | 2340 | brk.type |= HW_BRK_TYPE_WRITE; |
6c7a2856 | 2341 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
6c7a2856 P |
2342 | /* |
2343 | * Check if the request is for 'range' breakpoints. We can | |
2344 | * support it if range < 8 bytes. | |
2345 | */ | |
6961ed96 | 2346 | if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) |
6c7a2856 | 2347 | len = bp_info->addr2 - bp_info->addr; |
6961ed96 | 2348 | else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT) |
b0b0aa9c | 2349 | len = 1; |
6961ed96 | 2350 | else |
6c7a2856 | 2351 | return -EINVAL; |
6c7a2856 | 2352 | bp = thread->ptrace_bps[0]; |
6961ed96 | 2353 | if (bp) |
6c7a2856 | 2354 | return -ENOSPC; |
6c7a2856 P |
2355 | |
2356 | /* Create a new breakpoint request if one doesn't exist already */ | |
2357 | hw_breakpoint_init(&attr); | |
2358 | attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN; | |
2359 | attr.bp_len = len; | |
9422de3e | 2360 | arch_bp_generic_fields(brk.type, &attr.bp_type); |
6c7a2856 P |
2361 | |
2362 | thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr, | |
2363 | ptrace_triggered, NULL, child); | |
2364 | if (IS_ERR(bp)) { | |
2365 | thread->ptrace_bps[0] = NULL; | |
6c7a2856 P |
2366 | return PTR_ERR(bp); |
2367 | } | |
2368 | ||
6c7a2856 P |
2369 | return 1; |
2370 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
2371 | ||
2372 | if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) | |
2373 | return -EINVAL; | |
2374 | ||
9422de3e | 2375 | if (child->thread.hw_brk.address) |
6c7a2856 | 2376 | return -ENOSPC; |
4dfbf290 | 2377 | |
9422de3e | 2378 | child->thread.hw_brk = brk; |
3bffb652 | 2379 | |
3162d92d | 2380 | return 1; |
3bffb652 | 2381 | #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */ |
3162d92d DK |
2382 | } |
2383 | ||
ec1b33dc | 2384 | static long ppc_del_hwdebug(struct task_struct *child, long data) |
3162d92d | 2385 | { |
6c7a2856 P |
2386 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2387 | int ret = 0; | |
2388 | struct thread_struct *thread = &(child->thread); | |
2389 | struct perf_event *bp; | |
2390 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ | |
3bffb652 DK |
2391 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
2392 | int rc; | |
2393 | ||
2394 | if (data <= 4) | |
2395 | rc = del_instruction_bp(child, (int)data); | |
2396 | else | |
2397 | rc = del_dac(child, (int)data - 4); | |
2398 | ||
2399 | if (!rc) { | |
51ae8d4a BB |
2400 | if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0, |
2401 | child->thread.debug.dbcr1)) { | |
2402 | child->thread.debug.dbcr0 &= ~DBCR0_IDM; | |
3bffb652 DK |
2403 | child->thread.regs->msr &= ~MSR_DE; |
2404 | } | |
2405 | } | |
2406 | return rc; | |
2407 | #else | |
3162d92d DK |
2408 | if (data != 1) |
2409 | return -EINVAL; | |
6c7a2856 P |
2410 | |
2411 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
6c7a2856 P |
2412 | bp = thread->ptrace_bps[0]; |
2413 | if (bp) { | |
2414 | unregister_hw_breakpoint(bp); | |
2415 | thread->ptrace_bps[0] = NULL; | |
2416 | } else | |
2417 | ret = -ENOENT; | |
6c7a2856 P |
2418 | return ret; |
2419 | #else /* CONFIG_HAVE_HW_BREAKPOINT */ | |
9422de3e | 2420 | if (child->thread.hw_brk.address == 0) |
3162d92d DK |
2421 | return -ENOENT; |
2422 | ||
9422de3e MN |
2423 | child->thread.hw_brk.address = 0; |
2424 | child->thread.hw_brk.type = 0; | |
6c7a2856 | 2425 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 2426 | |
3162d92d | 2427 | return 0; |
3bffb652 | 2428 | #endif |
3162d92d DK |
2429 | } |
2430 | ||
9b05a69e NK |
2431 | long arch_ptrace(struct task_struct *child, long request, |
2432 | unsigned long addr, unsigned long data) | |
1da177e4 | 2433 | { |
1da177e4 | 2434 | int ret = -EPERM; |
f68d2048 NK |
2435 | void __user *datavp = (void __user *) data; |
2436 | unsigned long __user *datalp = datavp; | |
1da177e4 | 2437 | |
1da177e4 | 2438 | switch (request) { |
1da177e4 | 2439 | /* read the word at location addr in the USER area. */ |
1da177e4 LT |
2440 | case PTRACE_PEEKUSR: { |
2441 | unsigned long index, tmp; | |
2442 | ||
2443 | ret = -EIO; | |
2444 | /* convert to index and check */ | |
e8a30302 | 2445 | #ifdef CONFIG_PPC32 |
9b05a69e | 2446 | index = addr >> 2; |
e8a30302 SR |
2447 | if ((addr & 3) || (index > PT_FPSCR) |
2448 | || (child->thread.regs == NULL)) | |
2449 | #else | |
9b05a69e | 2450 | index = addr >> 3; |
e8a30302 SR |
2451 | if ((addr & 7) || (index > PT_FPSCR)) |
2452 | #endif | |
1da177e4 LT |
2453 | break; |
2454 | ||
2455 | CHECK_FULL_REGS(child->thread.regs); | |
2456 | if (index < PT_FPR0) { | |
ee4a3916 AK |
2457 | ret = ptrace_get_reg(child, (int) index, &tmp); |
2458 | if (ret) | |
2459 | break; | |
1da177e4 | 2460 | } else { |
e69b742a BH |
2461 | unsigned int fpidx = index - PT_FPR0; |
2462 | ||
e8a30302 | 2463 | flush_fp_to_thread(child); |
e69b742a | 2464 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 2465 | memcpy(&tmp, &child->thread.TS_FPR(fpidx), |
87fec051 | 2466 | sizeof(long)); |
e69b742a | 2467 | else |
de79f7b9 | 2468 | tmp = child->thread.fp_state.fpscr; |
1da177e4 | 2469 | } |
f68d2048 | 2470 | ret = put_user(tmp, datalp); |
1da177e4 LT |
2471 | break; |
2472 | } | |
2473 | ||
1da177e4 LT |
2474 | /* write the word at location addr in the USER area */ |
2475 | case PTRACE_POKEUSR: { | |
2476 | unsigned long index; | |
2477 | ||
2478 | ret = -EIO; | |
2479 | /* convert to index and check */ | |
e8a30302 | 2480 | #ifdef CONFIG_PPC32 |
9b05a69e | 2481 | index = addr >> 2; |
e8a30302 SR |
2482 | if ((addr & 3) || (index > PT_FPSCR) |
2483 | || (child->thread.regs == NULL)) | |
2484 | #else | |
9b05a69e | 2485 | index = addr >> 3; |
e8a30302 SR |
2486 | if ((addr & 7) || (index > PT_FPSCR)) |
2487 | #endif | |
1da177e4 LT |
2488 | break; |
2489 | ||
2490 | CHECK_FULL_REGS(child->thread.regs); | |
1da177e4 | 2491 | if (index < PT_FPR0) { |
865418d8 | 2492 | ret = ptrace_put_reg(child, index, data); |
1da177e4 | 2493 | } else { |
e69b742a BH |
2494 | unsigned int fpidx = index - PT_FPR0; |
2495 | ||
e8a30302 | 2496 | flush_fp_to_thread(child); |
e69b742a | 2497 | if (fpidx < (PT_FPSCR - PT_FPR0)) |
36aa1b18 | 2498 | memcpy(&child->thread.TS_FPR(fpidx), &data, |
87fec051 | 2499 | sizeof(long)); |
e69b742a | 2500 | else |
de79f7b9 | 2501 | child->thread.fp_state.fpscr = data; |
1da177e4 LT |
2502 | ret = 0; |
2503 | } | |
2504 | break; | |
2505 | } | |
2506 | ||
3162d92d DK |
2507 | case PPC_PTRACE_GETHWDBGINFO: { |
2508 | struct ppc_debug_info dbginfo; | |
2509 | ||
2510 | dbginfo.version = 1; | |
3bffb652 DK |
2511 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
2512 | dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS; | |
2513 | dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS; | |
2514 | dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS; | |
2515 | dbginfo.data_bp_alignment = 4; | |
2516 | dbginfo.sizeof_condition = 4; | |
2517 | dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE | | |
2518 | PPC_DEBUG_FEATURE_INSN_BP_MASK; | |
2519 | #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE | |
2520 | dbginfo.features |= | |
2521 | PPC_DEBUG_FEATURE_DATA_BP_RANGE | | |
2522 | PPC_DEBUG_FEATURE_DATA_BP_MASK; | |
2523 | #endif | |
2524 | #else /* !CONFIG_PPC_ADV_DEBUG_REGS */ | |
3162d92d DK |
2525 | dbginfo.num_instruction_bps = 0; |
2526 | dbginfo.num_data_bps = 1; | |
2527 | dbginfo.num_condition_regs = 0; | |
2528 | #ifdef CONFIG_PPC64 | |
2529 | dbginfo.data_bp_alignment = 8; | |
2530 | #else | |
2531 | dbginfo.data_bp_alignment = 4; | |
2532 | #endif | |
2533 | dbginfo.sizeof_condition = 0; | |
6c7a2856 P |
2534 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
2535 | dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE; | |
517b7314 MN |
2536 | if (cpu_has_feature(CPU_FTR_DAWR)) |
2537 | dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR; | |
6c7a2856 | 2538 | #else |
3162d92d | 2539 | dbginfo.features = 0; |
6c7a2856 | 2540 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
3bffb652 | 2541 | #endif /* CONFIG_PPC_ADV_DEBUG_REGS */ |
3162d92d | 2542 | |
f68d2048 | 2543 | if (!access_ok(VERIFY_WRITE, datavp, |
3162d92d DK |
2544 | sizeof(struct ppc_debug_info))) |
2545 | return -EFAULT; | |
f68d2048 NK |
2546 | ret = __copy_to_user(datavp, &dbginfo, |
2547 | sizeof(struct ppc_debug_info)) ? | |
3162d92d DK |
2548 | -EFAULT : 0; |
2549 | break; | |
2550 | } | |
2551 | ||
2552 | case PPC_PTRACE_SETHWDEBUG: { | |
2553 | struct ppc_hw_breakpoint bp_info; | |
2554 | ||
f68d2048 | 2555 | if (!access_ok(VERIFY_READ, datavp, |
3162d92d DK |
2556 | sizeof(struct ppc_hw_breakpoint))) |
2557 | return -EFAULT; | |
f68d2048 | 2558 | ret = __copy_from_user(&bp_info, datavp, |
3162d92d DK |
2559 | sizeof(struct ppc_hw_breakpoint)) ? |
2560 | -EFAULT : 0; | |
2561 | if (!ret) | |
2562 | ret = ppc_set_hwdebug(child, &bp_info); | |
2563 | break; | |
2564 | } | |
2565 | ||
2566 | case PPC_PTRACE_DELHWDEBUG: { | |
ec1b33dc | 2567 | ret = ppc_del_hwdebug(child, data); |
3162d92d DK |
2568 | break; |
2569 | } | |
2570 | ||
e8a30302 | 2571 | case PTRACE_GET_DEBUGREG: { |
9422de3e MN |
2572 | #ifndef CONFIG_PPC_ADV_DEBUG_REGS |
2573 | unsigned long dabr_fake; | |
2574 | #endif | |
e8a30302 SR |
2575 | ret = -EINVAL; |
2576 | /* We only support one DABR and no IABRS at the moment */ | |
2577 | if (addr > 0) | |
2578 | break; | |
3bffb652 | 2579 | #ifdef CONFIG_PPC_ADV_DEBUG_REGS |
51ae8d4a | 2580 | ret = put_user(child->thread.debug.dac1, datalp); |
3bffb652 | 2581 | #else |
9422de3e MN |
2582 | dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | |
2583 | (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); | |
2584 | ret = put_user(dabr_fake, datalp); | |
3bffb652 | 2585 | #endif |
e8a30302 SR |
2586 | break; |
2587 | } | |
2588 | ||
2589 | case PTRACE_SET_DEBUGREG: | |
2590 | ret = ptrace_set_debugreg(child, addr, data); | |
2591 | break; | |
e8a30302 | 2592 | |
e17666ba BH |
2593 | #ifdef CONFIG_PPC64 |
2594 | case PTRACE_GETREGS64: | |
2595 | #endif | |
c391cd00 RM |
2596 | case PTRACE_GETREGS: /* Get all pt_regs from the child. */ |
2597 | return copy_regset_to_user(child, &user_ppc_native_view, | |
2598 | REGSET_GPR, | |
2599 | 0, sizeof(struct pt_regs), | |
f68d2048 | 2600 | datavp); |
e8a30302 | 2601 | |
e17666ba BH |
2602 | #ifdef CONFIG_PPC64 |
2603 | case PTRACE_SETREGS64: | |
2604 | #endif | |
c391cd00 RM |
2605 | case PTRACE_SETREGS: /* Set all gp regs in the child. */ |
2606 | return copy_regset_from_user(child, &user_ppc_native_view, | |
2607 | REGSET_GPR, | |
2608 | 0, sizeof(struct pt_regs), | |
f68d2048 | 2609 | datavp); |
c391cd00 RM |
2610 | |
2611 | case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */ | |
2612 | return copy_regset_to_user(child, &user_ppc_native_view, | |
2613 | REGSET_FPR, | |
2614 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 2615 | datavp); |
c391cd00 RM |
2616 | |
2617 | case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */ | |
2618 | return copy_regset_from_user(child, &user_ppc_native_view, | |
2619 | REGSET_FPR, | |
2620 | 0, sizeof(elf_fpregset_t), | |
f68d2048 | 2621 | datavp); |
e8a30302 | 2622 | |
1da177e4 LT |
2623 | #ifdef CONFIG_ALTIVEC |
2624 | case PTRACE_GETVRREGS: | |
c391cd00 RM |
2625 | return copy_regset_to_user(child, &user_ppc_native_view, |
2626 | REGSET_VMX, | |
2627 | 0, (33 * sizeof(vector128) + | |
2628 | sizeof(u32)), | |
f68d2048 | 2629 | datavp); |
1da177e4 LT |
2630 | |
2631 | case PTRACE_SETVRREGS: | |
c391cd00 RM |
2632 | return copy_regset_from_user(child, &user_ppc_native_view, |
2633 | REGSET_VMX, | |
2634 | 0, (33 * sizeof(vector128) + | |
2635 | sizeof(u32)), | |
f68d2048 | 2636 | datavp); |
1da177e4 | 2637 | #endif |
ce48b210 MN |
2638 | #ifdef CONFIG_VSX |
2639 | case PTRACE_GETVSRREGS: | |
2640 | return copy_regset_to_user(child, &user_ppc_native_view, | |
2641 | REGSET_VSX, | |
1ac42ef8 | 2642 | 0, 32 * sizeof(double), |
f68d2048 | 2643 | datavp); |
ce48b210 MN |
2644 | |
2645 | case PTRACE_SETVSRREGS: | |
2646 | return copy_regset_from_user(child, &user_ppc_native_view, | |
2647 | REGSET_VSX, | |
1ac42ef8 | 2648 | 0, 32 * sizeof(double), |
f68d2048 | 2649 | datavp); |
ce48b210 | 2650 | #endif |
1da177e4 LT |
2651 | #ifdef CONFIG_SPE |
2652 | case PTRACE_GETEVRREGS: | |
2653 | /* Get the child spe register state. */ | |
c391cd00 RM |
2654 | return copy_regset_to_user(child, &user_ppc_native_view, |
2655 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 2656 | datavp); |
1da177e4 LT |
2657 | |
2658 | case PTRACE_SETEVRREGS: | |
2659 | /* Set the child spe register state. */ | |
c391cd00 RM |
2660 | return copy_regset_from_user(child, &user_ppc_native_view, |
2661 | REGSET_SPE, 0, 35 * sizeof(u32), | |
f68d2048 | 2662 | datavp); |
1da177e4 LT |
2663 | #endif |
2664 | ||
2665 | default: | |
2666 | ret = ptrace_request(child, request, addr, data); | |
2667 | break; | |
2668 | } | |
1da177e4 LT |
2669 | return ret; |
2670 | } | |
2671 | ||
2449acc5 ME |
2672 | #ifdef CONFIG_SECCOMP |
2673 | static int do_seccomp(struct pt_regs *regs) | |
2674 | { | |
2675 | if (!test_thread_flag(TIF_SECCOMP)) | |
2676 | return 0; | |
2677 | ||
2678 | /* | |
2679 | * The ABI we present to seccomp tracers is that r3 contains | |
2680 | * the syscall return value and orig_gpr3 contains the first | |
2681 | * syscall parameter. This is different to the ptrace ABI where | |
2682 | * both r3 and orig_gpr3 contain the first syscall parameter. | |
2683 | */ | |
2684 | regs->gpr[3] = -ENOSYS; | |
2685 | ||
2686 | /* | |
2687 | * We use the __ version here because we have already checked | |
2688 | * TIF_SECCOMP. If this fails, there is nothing left to do, we | |
2689 | * have already loaded -ENOSYS into r3, or seccomp has put | |
2690 | * something else in r3 (via SECCOMP_RET_ERRNO/TRACE). | |
2691 | */ | |
2f275de5 | 2692 | if (__secure_computing(NULL)) |
2449acc5 ME |
2693 | return -1; |
2694 | ||
2695 | /* | |
2696 | * The syscall was allowed by seccomp, restore the register | |
1addc57e | 2697 | * state to what audit expects. |
2449acc5 ME |
2698 | * Note that we use orig_gpr3, which means a seccomp tracer can |
2699 | * modify the first syscall parameter (in orig_gpr3) and also | |
2700 | * allow the syscall to proceed. | |
2701 | */ | |
2702 | regs->gpr[3] = regs->orig_gpr3; | |
2703 | ||
2704 | return 0; | |
2705 | } | |
2706 | #else | |
2707 | static inline int do_seccomp(struct pt_regs *regs) { return 0; } | |
2708 | #endif /* CONFIG_SECCOMP */ | |
2709 | ||
d3837414 ME |
2710 | /** |
2711 | * do_syscall_trace_enter() - Do syscall tracing on kernel entry. | |
2712 | * @regs: the pt_regs of the task to trace (current) | |
2713 | * | |
2714 | * Performs various types of tracing on syscall entry. This includes seccomp, | |
2715 | * ptrace, syscall tracepoints and audit. | |
2716 | * | |
2717 | * The pt_regs are potentially visible to userspace via ptrace, so their | |
2718 | * contents is ABI. | |
2719 | * | |
2720 | * One or more of the tracers may modify the contents of pt_regs, in particular | |
2721 | * to modify arguments or even the syscall number itself. | |
2722 | * | |
2723 | * It's also possible that a tracer can choose to reject the system call. In | |
2724 | * that case this function will return an illegal syscall number, and will put | |
2725 | * an appropriate return value in regs->r3. | |
2726 | * | |
2727 | * Return: the (possibly changed) syscall number. | |
4f72c427 RM |
2728 | */ |
2729 | long do_syscall_trace_enter(struct pt_regs *regs) | |
1da177e4 | 2730 | { |
22ecbe8d LZ |
2731 | user_exit(); |
2732 | ||
1addc57e KC |
2733 | /* |
2734 | * The tracer may decide to abort the syscall, if so tracehook | |
2735 | * will return !0. Note that the tracer may also just change | |
2736 | * regs->gpr[0] to an invalid syscall number, that is handled | |
2737 | * below on the exit path. | |
2738 | */ | |
2739 | if (test_thread_flag(TIF_SYSCALL_TRACE) && | |
2740 | tracehook_report_syscall_entry(regs)) | |
2741 | goto skip; | |
2742 | ||
2743 | /* Run seccomp after ptrace; allow it to set gpr[3]. */ | |
2449acc5 ME |
2744 | if (do_seccomp(regs)) |
2745 | return -1; | |
e8a30302 | 2746 | |
1addc57e KC |
2747 | /* Avoid trace and audit when syscall is invalid. */ |
2748 | if (regs->gpr[0] >= NR_syscalls) | |
2749 | goto skip; | |
ea9c102c | 2750 | |
02424d89 IM |
2751 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
2752 | trace_sys_enter(regs, regs->gpr[0]); | |
2753 | ||
cfcd1705 | 2754 | #ifdef CONFIG_PPC64 |
b05d8447 | 2755 | if (!is_32bit_task()) |
91397401 | 2756 | audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4], |
b05d8447 EP |
2757 | regs->gpr[5], regs->gpr[6]); |
2758 | else | |
e8a30302 | 2759 | #endif |
91397401 | 2760 | audit_syscall_entry(regs->gpr[0], |
b05d8447 EP |
2761 | regs->gpr[3] & 0xffffffff, |
2762 | regs->gpr[4] & 0xffffffff, | |
2763 | regs->gpr[5] & 0xffffffff, | |
2764 | regs->gpr[6] & 0xffffffff); | |
4f72c427 | 2765 | |
d3837414 ME |
2766 | /* Return the possibly modified but valid syscall number */ |
2767 | return regs->gpr[0]; | |
1addc57e KC |
2768 | |
2769 | skip: | |
2770 | /* | |
2771 | * If we are aborting explicitly, or if the syscall number is | |
2772 | * now invalid, set the return value to -ENOSYS. | |
2773 | */ | |
2774 | regs->gpr[3] = -ENOSYS; | |
2775 | return -1; | |
ea9c102c DW |
2776 | } |
2777 | ||
2778 | void do_syscall_trace_leave(struct pt_regs *regs) | |
2779 | { | |
4f72c427 RM |
2780 | int step; |
2781 | ||
d7e7528b | 2782 | audit_syscall_exit(regs); |
ea9c102c | 2783 | |
02424d89 IM |
2784 | if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) |
2785 | trace_sys_exit(regs, regs->result); | |
2786 | ||
4f72c427 RM |
2787 | step = test_thread_flag(TIF_SINGLESTEP); |
2788 | if (step || test_thread_flag(TIF_SYSCALL_TRACE)) | |
2789 | tracehook_report_syscall_exit(regs, step); | |
22ecbe8d LZ |
2790 | |
2791 | user_enter(); | |
ea9c102c | 2792 | } |