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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * PowerPC version |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Derived from "arch/m68k/kernel/ptrace.c" | |
6 | * Copyright (C) 1994 by Hamish Macdonald | |
7 | * Taken from linux/kernel/ptrace.c and modified for M680x0. | |
8 | * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds | |
9 | * | |
10 | * Modified by Cort Dougan (cort@hq.fsmlabs.com) | |
b123923d | 11 | * and Paul Mackerras (paulus@samba.org). |
1da177e4 LT |
12 | * |
13 | * This file is subject to the terms and conditions of the GNU General | |
14 | * Public License. See the file README.legal in the main directory of | |
15 | * this archive for more details. | |
16 | */ | |
17 | ||
e8a30302 | 18 | #include <linux/config.h> |
1da177e4 LT |
19 | #include <linux/kernel.h> |
20 | #include <linux/sched.h> | |
21 | #include <linux/mm.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/smp_lock.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/ptrace.h> | |
26 | #include <linux/user.h> | |
27 | #include <linux/security.h> | |
7ed20e1a | 28 | #include <linux/signal.h> |
ea9c102c DW |
29 | #include <linux/seccomp.h> |
30 | #include <linux/audit.h> | |
e8a30302 | 31 | #ifdef CONFIG_PPC32 |
ea9c102c | 32 | #include <linux/module.h> |
e8a30302 | 33 | #endif |
1da177e4 LT |
34 | |
35 | #include <asm/uaccess.h> | |
36 | #include <asm/page.h> | |
37 | #include <asm/pgtable.h> | |
38 | #include <asm/system.h> | |
e8a30302 SR |
39 | #ifdef CONFIG_PPC64 |
40 | #include <asm/ptrace-common.h> | |
41 | #endif | |
1da177e4 | 42 | |
e8a30302 | 43 | #ifdef CONFIG_PPC32 |
1da177e4 LT |
44 | /* |
45 | * Set of msr bits that gdb can change on behalf of a process. | |
46 | */ | |
47 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
48 | #define MSR_DEBUGCHANGE 0 | |
49 | #else | |
50 | #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) | |
51 | #endif | |
e8a30302 | 52 | #endif /* CONFIG_PPC32 */ |
1da177e4 LT |
53 | |
54 | /* | |
55 | * does not yet catch signals sent when the child dies. | |
56 | * in exit.c or in signal.c. | |
57 | */ | |
58 | ||
e8a30302 | 59 | #ifdef CONFIG_PPC32 |
1da177e4 LT |
60 | /* |
61 | * Get contents of register REGNO in task TASK. | |
62 | */ | |
63 | static inline unsigned long get_reg(struct task_struct *task, int regno) | |
64 | { | |
65 | if (regno < sizeof(struct pt_regs) / sizeof(unsigned long) | |
66 | && task->thread.regs != NULL) | |
67 | return ((unsigned long *)task->thread.regs)[regno]; | |
68 | return (0); | |
69 | } | |
70 | ||
71 | /* | |
72 | * Write contents of register REGNO in task TASK. | |
73 | */ | |
74 | static inline int put_reg(struct task_struct *task, int regno, | |
75 | unsigned long data) | |
76 | { | |
77 | if (regno <= PT_MQ && task->thread.regs != NULL) { | |
78 | if (regno == PT_MSR) | |
79 | data = (data & MSR_DEBUGCHANGE) | |
80 | | (task->thread.regs->msr & ~MSR_DEBUGCHANGE); | |
81 | ((unsigned long *)task->thread.regs)[regno] = data; | |
82 | return 0; | |
83 | } | |
84 | return -EIO; | |
85 | } | |
86 | ||
87 | #ifdef CONFIG_ALTIVEC | |
88 | /* | |
89 | * Get contents of AltiVec register state in task TASK | |
90 | */ | |
91 | static inline int get_vrregs(unsigned long __user *data, struct task_struct *task) | |
92 | { | |
93 | int i, j; | |
94 | ||
95 | if (!access_ok(VERIFY_WRITE, data, 133 * sizeof(unsigned long))) | |
96 | return -EFAULT; | |
97 | ||
98 | /* copy AltiVec registers VR[0] .. VR[31] */ | |
99 | for (i = 0; i < 32; i++) | |
100 | for (j = 0; j < 4; j++, data++) | |
101 | if (__put_user(task->thread.vr[i].u[j], data)) | |
102 | return -EFAULT; | |
103 | ||
104 | /* copy VSCR */ | |
105 | for (i = 0; i < 4; i++, data++) | |
106 | if (__put_user(task->thread.vscr.u[i], data)) | |
107 | return -EFAULT; | |
108 | ||
109 | /* copy VRSAVE */ | |
110 | if (__put_user(task->thread.vrsave, data)) | |
111 | return -EFAULT; | |
112 | ||
113 | return 0; | |
114 | } | |
115 | ||
116 | /* | |
117 | * Write contents of AltiVec register state into task TASK. | |
118 | */ | |
119 | static inline int set_vrregs(struct task_struct *task, unsigned long __user *data) | |
120 | { | |
121 | int i, j; | |
122 | ||
123 | if (!access_ok(VERIFY_READ, data, 133 * sizeof(unsigned long))) | |
124 | return -EFAULT; | |
125 | ||
126 | /* copy AltiVec registers VR[0] .. VR[31] */ | |
127 | for (i = 0; i < 32; i++) | |
128 | for (j = 0; j < 4; j++, data++) | |
129 | if (__get_user(task->thread.vr[i].u[j], data)) | |
130 | return -EFAULT; | |
131 | ||
132 | /* copy VSCR */ | |
133 | for (i = 0; i < 4; i++, data++) | |
134 | if (__get_user(task->thread.vscr.u[i], data)) | |
135 | return -EFAULT; | |
136 | ||
137 | /* copy VRSAVE */ | |
138 | if (__get_user(task->thread.vrsave, data)) | |
139 | return -EFAULT; | |
140 | ||
141 | return 0; | |
142 | } | |
143 | #endif | |
144 | ||
145 | #ifdef CONFIG_SPE | |
146 | ||
147 | /* | |
148 | * For get_evrregs/set_evrregs functions 'data' has the following layout: | |
149 | * | |
150 | * struct { | |
151 | * u32 evr[32]; | |
152 | * u64 acc; | |
153 | * u32 spefscr; | |
154 | * } | |
155 | */ | |
156 | ||
157 | /* | |
158 | * Get contents of SPE register state in task TASK. | |
159 | */ | |
160 | static inline int get_evrregs(unsigned long *data, struct task_struct *task) | |
161 | { | |
162 | int i; | |
163 | ||
164 | if (!access_ok(VERIFY_WRITE, data, 35 * sizeof(unsigned long))) | |
165 | return -EFAULT; | |
166 | ||
167 | /* copy SPEFSCR */ | |
168 | if (__put_user(task->thread.spefscr, &data[34])) | |
169 | return -EFAULT; | |
170 | ||
171 | /* copy SPE registers EVR[0] .. EVR[31] */ | |
172 | for (i = 0; i < 32; i++, data++) | |
173 | if (__put_user(task->thread.evr[i], data)) | |
174 | return -EFAULT; | |
175 | ||
176 | /* copy ACC */ | |
177 | if (__put_user64(task->thread.acc, (unsigned long long *)data)) | |
178 | return -EFAULT; | |
179 | ||
180 | return 0; | |
181 | } | |
182 | ||
183 | /* | |
184 | * Write contents of SPE register state into task TASK. | |
185 | */ | |
186 | static inline int set_evrregs(struct task_struct *task, unsigned long *data) | |
187 | { | |
188 | int i; | |
189 | ||
190 | if (!access_ok(VERIFY_READ, data, 35 * sizeof(unsigned long))) | |
191 | return -EFAULT; | |
192 | ||
193 | /* copy SPEFSCR */ | |
194 | if (__get_user(task->thread.spefscr, &data[34])) | |
195 | return -EFAULT; | |
196 | ||
197 | /* copy SPE registers EVR[0] .. EVR[31] */ | |
198 | for (i = 0; i < 32; i++, data++) | |
199 | if (__get_user(task->thread.evr[i], data)) | |
200 | return -EFAULT; | |
201 | /* copy ACC */ | |
202 | if (__get_user64(task->thread.acc, (unsigned long long*)data)) | |
203 | return -EFAULT; | |
204 | ||
205 | return 0; | |
206 | } | |
207 | #endif /* CONFIG_SPE */ | |
208 | ||
209 | static inline void | |
210 | set_single_step(struct task_struct *task) | |
211 | { | |
212 | struct pt_regs *regs = task->thread.regs; | |
213 | ||
214 | if (regs != NULL) { | |
215 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
216 | task->thread.dbcr0 = DBCR0_IDM | DBCR0_IC; | |
217 | regs->msr |= MSR_DE; | |
218 | #else | |
219 | regs->msr |= MSR_SE; | |
220 | #endif | |
221 | } | |
222 | } | |
223 | ||
224 | static inline void | |
225 | clear_single_step(struct task_struct *task) | |
226 | { | |
227 | struct pt_regs *regs = task->thread.regs; | |
228 | ||
229 | if (regs != NULL) { | |
230 | #if defined(CONFIG_40x) || defined(CONFIG_BOOKE) | |
231 | task->thread.dbcr0 = 0; | |
232 | regs->msr &= ~MSR_DE; | |
233 | #else | |
234 | regs->msr &= ~MSR_SE; | |
235 | #endif | |
236 | } | |
237 | } | |
e8a30302 | 238 | #endif /* CONFIG_PPC32 */ |
1da177e4 LT |
239 | |
240 | /* | |
241 | * Called by kernel/ptrace.c when detaching.. | |
242 | * | |
243 | * Make sure single step bits etc are not set. | |
244 | */ | |
245 | void ptrace_disable(struct task_struct *child) | |
246 | { | |
247 | /* make sure the single step bit is not set. */ | |
248 | clear_single_step(child); | |
249 | } | |
250 | ||
481bed45 | 251 | long arch_ptrace(struct task_struct *child, long request, long addr, long data) |
1da177e4 | 252 | { |
1da177e4 LT |
253 | int ret = -EPERM; |
254 | ||
1da177e4 LT |
255 | switch (request) { |
256 | /* when I and D space are separate, these will need to be fixed. */ | |
257 | case PTRACE_PEEKTEXT: /* read word at location addr. */ | |
258 | case PTRACE_PEEKDATA: { | |
259 | unsigned long tmp; | |
260 | int copied; | |
261 | ||
262 | copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0); | |
263 | ret = -EIO; | |
264 | if (copied != sizeof(tmp)) | |
265 | break; | |
266 | ret = put_user(tmp,(unsigned long __user *) data); | |
267 | break; | |
268 | } | |
269 | ||
270 | /* read the word at location addr in the USER area. */ | |
1da177e4 LT |
271 | case PTRACE_PEEKUSR: { |
272 | unsigned long index, tmp; | |
273 | ||
274 | ret = -EIO; | |
275 | /* convert to index and check */ | |
e8a30302 | 276 | #ifdef CONFIG_PPC32 |
1da177e4 | 277 | index = (unsigned long) addr >> 2; |
e8a30302 SR |
278 | if ((addr & 3) || (index > PT_FPSCR) |
279 | || (child->thread.regs == NULL)) | |
280 | #else | |
281 | index = (unsigned long) addr >> 3; | |
282 | if ((addr & 7) || (index > PT_FPSCR)) | |
283 | #endif | |
1da177e4 LT |
284 | break; |
285 | ||
e8a30302 | 286 | #ifdef CONFIG_PPC32 |
1da177e4 | 287 | CHECK_FULL_REGS(child->thread.regs); |
e8a30302 | 288 | #endif |
1da177e4 LT |
289 | if (index < PT_FPR0) { |
290 | tmp = get_reg(child, (int) index); | |
291 | } else { | |
e8a30302 | 292 | flush_fp_to_thread(child); |
1da177e4 LT |
293 | tmp = ((unsigned long *)child->thread.fpr)[index - PT_FPR0]; |
294 | } | |
295 | ret = put_user(tmp,(unsigned long __user *) data); | |
296 | break; | |
297 | } | |
298 | ||
299 | /* If I and D space are separate, this will have to be fixed. */ | |
300 | case PTRACE_POKETEXT: /* write the word at location addr. */ | |
301 | case PTRACE_POKEDATA: | |
302 | ret = 0; | |
e8a30302 SR |
303 | if (access_process_vm(child, addr, &data, sizeof(data), 1) |
304 | == sizeof(data)) | |
1da177e4 LT |
305 | break; |
306 | ret = -EIO; | |
307 | break; | |
308 | ||
309 | /* write the word at location addr in the USER area */ | |
310 | case PTRACE_POKEUSR: { | |
311 | unsigned long index; | |
312 | ||
313 | ret = -EIO; | |
314 | /* convert to index and check */ | |
e8a30302 | 315 | #ifdef CONFIG_PPC32 |
1da177e4 | 316 | index = (unsigned long) addr >> 2; |
e8a30302 SR |
317 | if ((addr & 3) || (index > PT_FPSCR) |
318 | || (child->thread.regs == NULL)) | |
319 | #else | |
320 | index = (unsigned long) addr >> 3; | |
321 | if ((addr & 7) || (index > PT_FPSCR)) | |
322 | #endif | |
1da177e4 LT |
323 | break; |
324 | ||
e8a30302 | 325 | #ifdef CONFIG_PPC32 |
1da177e4 | 326 | CHECK_FULL_REGS(child->thread.regs); |
e8a30302 | 327 | #endif |
1da177e4 LT |
328 | if (index == PT_ORIG_R3) |
329 | break; | |
330 | if (index < PT_FPR0) { | |
331 | ret = put_reg(child, index, data); | |
332 | } else { | |
e8a30302 | 333 | flush_fp_to_thread(child); |
1da177e4 LT |
334 | ((unsigned long *)child->thread.fpr)[index - PT_FPR0] = data; |
335 | ret = 0; | |
336 | } | |
337 | break; | |
338 | } | |
339 | ||
340 | case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ | |
341 | case PTRACE_CONT: { /* restart after signal. */ | |
342 | ret = -EIO; | |
7ed20e1a | 343 | if (!valid_signal(data)) |
1da177e4 | 344 | break; |
e8a30302 | 345 | if (request == PTRACE_SYSCALL) |
1da177e4 | 346 | set_tsk_thread_flag(child, TIF_SYSCALL_TRACE); |
e8a30302 | 347 | else |
1da177e4 | 348 | clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); |
1da177e4 LT |
349 | child->exit_code = data; |
350 | /* make sure the single step bit is not set. */ | |
351 | clear_single_step(child); | |
352 | wake_up_process(child); | |
353 | ret = 0; | |
354 | break; | |
355 | } | |
356 | ||
357 | /* | |
358 | * make the child exit. Best I can do is send it a sigkill. | |
359 | * perhaps it should be put in the status that it wants to | |
360 | * exit. | |
361 | */ | |
362 | case PTRACE_KILL: { | |
363 | ret = 0; | |
364 | if (child->exit_state == EXIT_ZOMBIE) /* already dead */ | |
365 | break; | |
366 | child->exit_code = SIGKILL; | |
367 | /* make sure the single step bit is not set. */ | |
368 | clear_single_step(child); | |
369 | wake_up_process(child); | |
370 | break; | |
371 | } | |
372 | ||
373 | case PTRACE_SINGLESTEP: { /* set the trap flag. */ | |
374 | ret = -EIO; | |
7ed20e1a | 375 | if (!valid_signal(data)) |
1da177e4 LT |
376 | break; |
377 | clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE); | |
378 | set_single_step(child); | |
379 | child->exit_code = data; | |
380 | /* give it a chance to run. */ | |
381 | wake_up_process(child); | |
382 | ret = 0; | |
383 | break; | |
384 | } | |
385 | ||
e8a30302 SR |
386 | #ifdef CONFIG_PPC64 |
387 | case PTRACE_GET_DEBUGREG: { | |
388 | ret = -EINVAL; | |
389 | /* We only support one DABR and no IABRS at the moment */ | |
390 | if (addr > 0) | |
391 | break; | |
392 | ret = put_user(child->thread.dabr, | |
393 | (unsigned long __user *)data); | |
394 | break; | |
395 | } | |
396 | ||
397 | case PTRACE_SET_DEBUGREG: | |
398 | ret = ptrace_set_debugreg(child, addr, data); | |
399 | break; | |
400 | #endif | |
401 | ||
1da177e4 LT |
402 | case PTRACE_DETACH: |
403 | ret = ptrace_detach(child, data); | |
404 | break; | |
405 | ||
e8a30302 SR |
406 | #ifdef CONFIG_PPC64 |
407 | case PPC_PTRACE_GETREGS: { /* Get GPRs 0 - 31. */ | |
408 | int i; | |
409 | unsigned long *reg = &((unsigned long *)child->thread.regs)[0]; | |
410 | unsigned long __user *tmp = (unsigned long __user *)addr; | |
411 | ||
412 | for (i = 0; i < 32; i++) { | |
413 | ret = put_user(*reg, tmp); | |
414 | if (ret) | |
415 | break; | |
416 | reg++; | |
417 | tmp++; | |
418 | } | |
419 | break; | |
420 | } | |
421 | ||
422 | case PPC_PTRACE_SETREGS: { /* Set GPRs 0 - 31. */ | |
423 | int i; | |
424 | unsigned long *reg = &((unsigned long *)child->thread.regs)[0]; | |
425 | unsigned long __user *tmp = (unsigned long __user *)addr; | |
426 | ||
427 | for (i = 0; i < 32; i++) { | |
428 | ret = get_user(*reg, tmp); | |
429 | if (ret) | |
430 | break; | |
431 | reg++; | |
432 | tmp++; | |
433 | } | |
434 | break; | |
435 | } | |
436 | ||
437 | case PPC_PTRACE_GETFPREGS: { /* Get FPRs 0 - 31. */ | |
438 | int i; | |
439 | unsigned long *reg = &((unsigned long *)child->thread.fpr)[0]; | |
440 | unsigned long __user *tmp = (unsigned long __user *)addr; | |
441 | ||
442 | flush_fp_to_thread(child); | |
443 | ||
444 | for (i = 0; i < 32; i++) { | |
445 | ret = put_user(*reg, tmp); | |
446 | if (ret) | |
447 | break; | |
448 | reg++; | |
449 | tmp++; | |
450 | } | |
451 | break; | |
452 | } | |
453 | ||
454 | case PPC_PTRACE_SETFPREGS: { /* Get FPRs 0 - 31. */ | |
455 | int i; | |
456 | unsigned long *reg = &((unsigned long *)child->thread.fpr)[0]; | |
457 | unsigned long __user *tmp = (unsigned long __user *)addr; | |
458 | ||
459 | flush_fp_to_thread(child); | |
460 | ||
461 | for (i = 0; i < 32; i++) { | |
462 | ret = get_user(*reg, tmp); | |
463 | if (ret) | |
464 | break; | |
465 | reg++; | |
466 | tmp++; | |
467 | } | |
468 | break; | |
469 | } | |
470 | #endif /* CONFIG_PPC64 */ | |
471 | ||
1da177e4 LT |
472 | #ifdef CONFIG_ALTIVEC |
473 | case PTRACE_GETVRREGS: | |
474 | /* Get the child altivec register state. */ | |
e8a30302 | 475 | flush_altivec_to_thread(child); |
1da177e4 LT |
476 | ret = get_vrregs((unsigned long __user *)data, child); |
477 | break; | |
478 | ||
479 | case PTRACE_SETVRREGS: | |
480 | /* Set the child altivec register state. */ | |
e8a30302 | 481 | flush_altivec_to_thread(child); |
1da177e4 LT |
482 | ret = set_vrregs(child, (unsigned long __user *)data); |
483 | break; | |
484 | #endif | |
485 | #ifdef CONFIG_SPE | |
486 | case PTRACE_GETEVRREGS: | |
487 | /* Get the child spe register state. */ | |
488 | if (child->thread.regs->msr & MSR_SPE) | |
489 | giveup_spe(child); | |
490 | ret = get_evrregs((unsigned long __user *)data, child); | |
491 | break; | |
492 | ||
493 | case PTRACE_SETEVRREGS: | |
494 | /* Set the child spe register state. */ | |
495 | /* this is to clear the MSR_SPE bit to force a reload | |
496 | * of register state from memory */ | |
497 | if (child->thread.regs->msr & MSR_SPE) | |
498 | giveup_spe(child); | |
499 | ret = set_evrregs(child, (unsigned long __user *)data); | |
500 | break; | |
501 | #endif | |
502 | ||
503 | default: | |
504 | ret = ptrace_request(child, request, addr, data); | |
505 | break; | |
506 | } | |
481bed45 | 507 | |
1da177e4 LT |
508 | return ret; |
509 | } | |
510 | ||
ea9c102c | 511 | static void do_syscall_trace(void) |
1da177e4 | 512 | { |
ea9c102c DW |
513 | /* the 0x80 provides a way for the tracing parent to distinguish |
514 | between a syscall stop and SIGTRAP delivery */ | |
1da177e4 LT |
515 | ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) |
516 | ? 0x80 : 0)); | |
517 | ||
518 | /* | |
519 | * this isn't the same as continuing with a signal, but it will do | |
520 | * for normal use. strace only continues with a signal if the | |
521 | * stopping signal is not SIGTRAP. -brl | |
522 | */ | |
523 | if (current->exit_code) { | |
524 | send_sig(current->exit_code, current, 1); | |
525 | current->exit_code = 0; | |
526 | } | |
527 | } | |
ea9c102c DW |
528 | |
529 | void do_syscall_trace_enter(struct pt_regs *regs) | |
530 | { | |
e8a30302 SR |
531 | #ifdef CONFIG_PPC64 |
532 | secure_computing(regs->gpr[0]); | |
533 | #endif | |
534 | ||
ea9c102c DW |
535 | if (test_thread_flag(TIF_SYSCALL_TRACE) |
536 | && (current->ptrace & PT_PTRACED)) | |
537 | do_syscall_trace(); | |
538 | ||
539 | if (unlikely(current->audit_context)) | |
e8a30302 SR |
540 | audit_syscall_entry(current, |
541 | #ifdef CONFIG_PPC32 | |
542 | AUDIT_ARCH_PPC, | |
543 | #else | |
544 | test_thread_flag(TIF_32BIT)?AUDIT_ARCH_PPC:AUDIT_ARCH_PPC64, | |
545 | #endif | |
ea9c102c DW |
546 | regs->gpr[0], |
547 | regs->gpr[3], regs->gpr[4], | |
548 | regs->gpr[5], regs->gpr[6]); | |
549 | } | |
550 | ||
551 | void do_syscall_trace_leave(struct pt_regs *regs) | |
552 | { | |
e8a30302 | 553 | #ifdef CONFIG_PPC32 |
ea9c102c | 554 | secure_computing(regs->gpr[0]); |
e8a30302 | 555 | #endif |
ea9c102c DW |
556 | |
557 | if (unlikely(current->audit_context)) | |
558 | audit_syscall_exit(current, | |
559 | (regs->ccr&0x1000)?AUDITSC_FAILURE:AUDITSC_SUCCESS, | |
560 | regs->result); | |
561 | ||
e8a30302 SR |
562 | if ((test_thread_flag(TIF_SYSCALL_TRACE) |
563 | #ifdef CONFIG_PPC64 | |
564 | || test_thread_flag(TIF_SINGLESTEP) | |
565 | #endif | |
566 | ) | |
ea9c102c DW |
567 | && (current->ptrace & PT_PTRACED)) |
568 | do_syscall_trace(); | |
569 | } | |
570 | ||
e8a30302 | 571 | #ifdef CONFIG_PPC32 |
ea9c102c DW |
572 | EXPORT_SYMBOL(do_syscall_trace_enter); |
573 | EXPORT_SYMBOL(do_syscall_trace_leave); | |
e8a30302 | 574 | #endif |